diff options
Diffstat (limited to 'arch/m68k/include/asm/m5307sim.h')
-rw-r--r-- | arch/m68k/include/asm/m5307sim.h | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 0bf57397e7a9..4c94c01f36c4 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h | |||
@@ -16,6 +16,7 @@ | |||
16 | 16 | ||
17 | #define CPU_NAME "COLDFIRE(m5307)" | 17 | #define CPU_NAME "COLDFIRE(m5307)" |
18 | #define CPU_INSTR_PER_JIFFY 3 | 18 | #define CPU_INSTR_PER_JIFFY 3 |
19 | #define MCF_BUSCLK (MCF_CLK / 2) | ||
19 | 20 | ||
20 | #include <asm/m53xxacr.h> | 21 | #include <asm/m53xxacr.h> |
21 | 22 | ||
@@ -89,16 +90,30 @@ | |||
89 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ | 90 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ |
90 | #endif /* CONFIG_OLDMASK */ | 91 | #endif /* CONFIG_OLDMASK */ |
91 | 92 | ||
92 | #define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ | 93 | #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ |
93 | #define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ | 94 | #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */ |
94 | #define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ | 95 | #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */ |
95 | #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ | 96 | #define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */ |
96 | #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ | 97 | #define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */ |
98 | |||
99 | /* | ||
100 | * Timer module. | ||
101 | */ | ||
102 | #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ | ||
103 | #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ | ||
97 | 104 | ||
98 | #define MCFSIM_PADDR (MCF_MBAR + 0x244) | 105 | #define MCFSIM_PADDR (MCF_MBAR + 0x244) |
99 | #define MCFSIM_PADAT (MCF_MBAR + 0x248) | 106 | #define MCFSIM_PADAT (MCF_MBAR + 0x248) |
100 | 107 | ||
101 | /* | 108 | /* |
109 | * DMA unit base addresses. | ||
110 | */ | ||
111 | #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ | ||
112 | #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ | ||
113 | #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ | ||
114 | #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ | ||
115 | |||
116 | /* | ||
102 | * UART module. | 117 | * UART module. |
103 | */ | 118 | */ |
104 | #if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) | 119 | #if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) |