diff options
Diffstat (limited to 'arch/m68k/include/asm/m5272sim.h')
-rw-r--r-- | arch/m68k/include/asm/m5272sim.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index df3332c2317d..b7cc50abc831 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h | |||
@@ -12,6 +12,11 @@ | |||
12 | #define m5272sim_h | 12 | #define m5272sim_h |
13 | /****************************************************************************/ | 13 | /****************************************************************************/ |
14 | 14 | ||
15 | #define CPU_NAME "COLDFIRE(m5272)" | ||
16 | #define CPU_INSTR_PER_JIFFY 3 | ||
17 | |||
18 | #include <asm/m52xxacr.h> | ||
19 | |||
15 | /* | 20 | /* |
16 | * Define the 5272 SIM register set addresses. | 21 | * Define the 5272 SIM register set addresses. |
17 | */ | 22 | */ |
@@ -62,6 +67,9 @@ | |||
62 | #define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ | 67 | #define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ |
63 | #define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ | 68 | #define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ |
64 | 69 | ||
70 | #define MCFUART_BASE1 0x100 /* Base address of UART1 */ | ||
71 | #define MCFUART_BASE2 0x140 /* Base address of UART2 */ | ||
72 | |||
65 | #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ | 73 | #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ |
66 | #define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ | 74 | #define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ |
67 | #define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ | 75 | #define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ |