aboutsummaryrefslogtreecommitdiffstats
path: root/arch/m68k/include/asm/m5272sim.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/m68k/include/asm/m5272sim.h')
-rw-r--r--arch/m68k/include/asm/m5272sim.h17
1 files changed, 10 insertions, 7 deletions
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index 759c2b07a994..a58f1760d858 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -68,8 +68,8 @@
68#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ 68#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
69#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ 69#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
70 70
71#define MCFUART_BASE1 0x100 /* Base address of UART1 */ 71#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
72#define MCFUART_BASE2 0x140 /* Base address of UART2 */ 72#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
73 73
74#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ 74#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
75#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ 75#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
@@ -88,6 +88,9 @@
88#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */ 88#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
89#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */ 89#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
90 90
91#define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */
92#define MCFFEC_SIZE0 0x1d0
93
91/* 94/*
92 * Define system peripheral IRQ usage. 95 * Define system peripheral IRQ usage.
93 */ 96 */
@@ -101,8 +104,8 @@
101#define MCF_IRQ_TIMER2 70 /* Timer 2 */ 104#define MCF_IRQ_TIMER2 70 /* Timer 2 */
102#define MCF_IRQ_TIMER3 71 /* Timer 3 */ 105#define MCF_IRQ_TIMER3 71 /* Timer 3 */
103#define MCF_IRQ_TIMER4 72 /* Timer 4 */ 106#define MCF_IRQ_TIMER4 72 /* Timer 4 */
104#define MCF_IRQ_UART1 73 /* UART 1 */ 107#define MCF_IRQ_UART0 73 /* UART 0 */
105#define MCF_IRQ_UART2 74 /* UART 2 */ 108#define MCF_IRQ_UART1 74 /* UART 1 */
106#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */ 109#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
107#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */ 110#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
108#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */ 111#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */
@@ -114,9 +117,9 @@
114#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */ 117#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */
115#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */ 118#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */
116#define MCF_IRQ_DMA 85 /* DMA Controller */ 119#define MCF_IRQ_DMA 85 /* DMA Controller */
117#define MCF_IRQ_ERX 86 /* Ethernet Receiver */ 120#define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */
118#define MCF_IRQ_ETX 87 /* Ethernet Transmitter */ 121#define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */
119#define MCF_IRQ_ENTC 88 /* Ethernet Non-Time Critical */ 122#define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */
120#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */ 123#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */
121#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */ 124#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */
122#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */ 125#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */