1 files changed, 16 insertions, 1 deletions

diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index db824a4b136e..88ed8239fe4e 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -11,6 +11,11 @@
 #define m520xsim_h
 /****************************************************************************/
 
+#define CPU_NAME                "COLDFIRE(m520x)"
+#define CPU_INSTR_PER_JIFFY     3
+
+#include <asm/m52xxacr.h>
+
 /*
  *  Define the 520x SIM register set addresses.
  */
@@ -54,6 +59,9 @@
 #define MCFSIM_SDCS0        0x000a8110  /* SDRAM Chip Select 0 Configuration */
 #define MCFSIM_SDCS1        0x000a8114  /* SDRAM Chip Select 1 Configuration */
 
+/*
+ * EPORT and GPIO registers.
+ */
 #define MCFEPORT_EPDDR                  0xFC088002
 #define MCFEPORT_EPDR                   0xFC088004
 #define MCFEPORT_EPPDR                  0xFC088005
@@ -97,6 +105,7 @@
 #define MCFGPIO_PCLRR_UART              0xFC0A402A
 #define MCFGPIO_PCLRR_FECH              0xFC0A402B
 #define MCFGPIO_PCLRR_FECL              0xFC0A402C
+
 /*
  * Generic GPIO support
  */
@@ -109,7 +118,6 @@
 #define MCFGPIO_PIN_MAX                 80
 #define MCFGPIO_IRQ_MAX                 8
 #define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
-/****************************************************************************/
 
 #define MCF_GPIO_PAR_UART                   (0xA4036)
 #define MCF_GPIO_PAR_FECI2C                 (0xA4033)
@@ -126,6 +134,13 @@
 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2   (0x04)
 
 /*
+ *  UART module.
+ */
+#define MCFUART_BASE1           0x60000         /* Base address of UART1 */
+#define MCFUART_BASE2           0x64000         /* Base address of UART2 */
+#define MCFUART_BASE3           0x68000         /* Base address of UART2 */
+
+/*
  *  Reset Controll Unit.
  */
 #define MCF_RCR                 0xFC0A0000