diff options
Diffstat (limited to 'arch/m68k/include/asm/m5206sim.h')
| -rw-r--r-- | arch/m68k/include/asm/m5206sim.h | 98 |
1 files changed, 49 insertions, 49 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index 69722366b084..4cf864f5ea7a 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h | |||
| @@ -21,33 +21,33 @@ | |||
| 21 | /* | 21 | /* |
| 22 | * Define the 5206 SIM register set addresses. | 22 | * Define the 5206 SIM register set addresses. |
| 23 | */ | 23 | */ |
| 24 | #define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */ | 24 | #define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */ |
| 25 | #define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */ | 25 | #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */ |
| 26 | #define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */ | 26 | #define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */ |
| 27 | #define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */ | 27 | #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */ |
| 28 | #define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */ | 28 | #define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */ |
| 29 | #define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */ | 29 | #define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */ |
| 30 | #define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */ | 30 | #define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */ |
| 31 | #define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */ | 31 | #define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */ |
| 32 | #define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */ | 32 | #define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */ |
| 33 | #define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */ | 33 | #define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */ |
| 34 | #define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */ | 34 | #define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */ |
| 35 | #define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */ | 35 | #define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */ |
| 36 | #define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */ | 36 | #define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */ |
| 37 | #define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */ | 37 | #define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */ |
| 38 | #ifdef CONFIG_M5206e | 38 | #ifdef CONFIG_M5206e |
| 39 | #define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */ | 39 | #define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */ |
| 40 | #define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */ | 40 | #define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */ |
| 41 | #endif | 41 | #endif |
| 42 | 42 | ||
| 43 | #define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */ | 43 | #define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */ |
| 44 | #define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */ | 44 | #define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */ |
| 45 | 45 | ||
| 46 | #define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */ | 46 | #define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */ |
| 47 | #define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/ | 47 | #define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */ |
| 48 | 48 | ||
| 49 | #define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */ | 49 | #define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */ |
| 50 | #define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */ | 50 | #define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */ |
| 51 | 51 | ||
| 52 | #define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */ | 52 | #define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */ |
| 53 | #define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */ | 53 | #define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */ |
| @@ -58,36 +58,36 @@ | |||
| 58 | #define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */ | 58 | #define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */ |
| 59 | #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */ | 59 | #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */ |
| 60 | 60 | ||
| 61 | #define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */ | 61 | #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */ |
| 62 | #define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */ | 62 | #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */ |
| 63 | #define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */ | 63 | #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */ |
| 64 | #define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */ | 64 | #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */ |
| 65 | #define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */ | 65 | #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */ |
| 66 | #define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */ | 66 | #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */ |
| 67 | #define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */ | 67 | #define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */ |
| 68 | #define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */ | 68 | #define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */ |
| 69 | #define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */ | 69 | #define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */ |
| 70 | #define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */ | 70 | #define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */ |
| 71 | #define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */ | 71 | #define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */ |
| 72 | #define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */ | 72 | #define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */ |
| 73 | #define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */ | 73 | #define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */ |
| 74 | #define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */ | 74 | #define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */ |
| 75 | #define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */ | 75 | #define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */ |
| 76 | #define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */ | 76 | #define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */ |
| 77 | #define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */ | 77 | #define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */ |
| 78 | #define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */ | 78 | #define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */ |
| 79 | #define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */ | 79 | #define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */ |
| 80 | #define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */ | 80 | #define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */ |
| 81 | #define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */ | 81 | #define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */ |
| 82 | #define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */ | 82 | #define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */ |
| 83 | #define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */ | 83 | #define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */ |
| 84 | #define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */ | 84 | #define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */ |
| 85 | #define MCFSIM_DMCR 0xc6 /* Default control */ | 85 | #define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */ |
| 86 | 86 | ||
| 87 | #ifdef CONFIG_M5206e | 87 | #ifdef CONFIG_M5206e |
| 88 | #define MCFSIM_PAR 0xca /* Pin Assignment reg (r/w) */ | 88 | #define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */ |
| 89 | #else | 89 | #else |
| 90 | #define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */ | 90 | #define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */ |
| 91 | #endif | 91 | #endif |
| 92 | 92 | ||
| 93 | #define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */ | 93 | #define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */ |