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-rw-r--r--arch/m68k/include/asm/m5206sim.h16
1 files changed, 3 insertions, 13 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 7be8a2d3e659..b50061aaf8f0 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -117,21 +117,11 @@
117#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */ 117#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
118#endif 118#endif
119 119
120#if defined(CONFIG_M5206e)
121#define MCFSIM_IMR_MASKALL 0xfffe /* All SIM intr sources */
122#endif
123
124/* 120/*
125 * Macro to get and set IMR register. It is 16 bits on the 5206. 121 * Let the common interrupt handler code know that the ColdFire 5206*
122 * family of CPU's only has a 16bit sized IMR register.
126 */ 123 */
127#define mcf_getimr() \ 124#define MCFSIM_IMR_IS_16BITS
128 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR))
129
130#define mcf_setimr(imr) \
131 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) = (imr)
132
133#define mcf_getipr() \
134 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IPR))
135 125
136/****************************************************************************/ 126/****************************************************************************/
137#endif /* m5206sim_h */ 127#endif /* m5206sim_h */