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-rw-r--r--arch/m32r/include/asm/atomic.h2
-rw-r--r--arch/m32r/include/asm/scatterlist.h15
-rw-r--r--arch/m32r/include/asm/thread_info.h2
-rw-r--r--arch/m32r/kernel/time.c47
4 files changed, 10 insertions, 56 deletions
diff --git a/arch/m32r/include/asm/atomic.h b/arch/m32r/include/asm/atomic.h
index 63f0cf0f50dd..d44a51e5271b 100644
--- a/arch/m32r/include/asm/atomic.h
+++ b/arch/m32r/include/asm/atomic.h
@@ -26,7 +26,7 @@
26 * 26 *
27 * Atomically reads the value of @v. 27 * Atomically reads the value of @v.
28 */ 28 */
29#define atomic_read(v) ((v)->counter) 29#define atomic_read(v) (*(volatile int *)&(v)->counter)
30 30
31/** 31/**
32 * atomic_set - set atomic variable 32 * atomic_set - set atomic variable
diff --git a/arch/m32r/include/asm/scatterlist.h b/arch/m32r/include/asm/scatterlist.h
index 1ed372c73d0b..aeeddd8dac17 100644
--- a/arch/m32r/include/asm/scatterlist.h
+++ b/arch/m32r/include/asm/scatterlist.h
@@ -1,20 +1,7 @@
1#ifndef _ASM_M32R_SCATTERLIST_H 1#ifndef _ASM_M32R_SCATTERLIST_H
2#define _ASM_M32R_SCATTERLIST_H 2#define _ASM_M32R_SCATTERLIST_H
3 3
4#include <asm/types.h> 4#include <asm-generic/scatterlist.h>
5
6struct scatterlist {
7#ifdef CONFIG_DEBUG_SG
8 unsigned long sg_magic;
9#endif
10 char * address; /* Location data is to be transferred to, NULL for
11 * highmem page */
12 unsigned long page_link;
13 unsigned int offset;/* for highmem, page offset */
14
15 dma_addr_t dma_address;
16 unsigned int length;
17};
18 5
19#define ISA_DMA_THRESHOLD (0x1fffffff) 6#define ISA_DMA_THRESHOLD (0x1fffffff)
20 7
diff --git a/arch/m32r/include/asm/thread_info.h b/arch/m32r/include/asm/thread_info.h
index ed240b6e8e77..71faff5bcc27 100644
--- a/arch/m32r/include/asm/thread_info.h
+++ b/arch/m32r/include/asm/thread_info.h
@@ -142,7 +142,7 @@ static inline unsigned int get_thread_fault_code(void)
142#define TIF_RESTORE_SIGMASK 8 /* restore signal mask in do_signal() */ 142#define TIF_RESTORE_SIGMASK 8 /* restore signal mask in do_signal() */
143#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ 143#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
144#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ 144#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */
145#define TIF_MEMDIE 18 /* OOM killer killed process */ 145#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
146#define TIF_FREEZE 19 /* is freezing for suspend */ 146#define TIF_FREEZE 19 /* is freezing for suspend */
147 147
148#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 148#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
diff --git a/arch/m32r/kernel/time.c b/arch/m32r/kernel/time.c
index 9cedcef11575..bda86820bffd 100644
--- a/arch/m32r/kernel/time.c
+++ b/arch/m32r/kernel/time.c
@@ -106,24 +106,6 @@ u32 arch_gettimeoffset(void)
106} 106}
107 107
108/* 108/*
109 * In order to set the CMOS clock precisely, set_rtc_mmss has to be
110 * called 500 ms after the second nowtime has started, because when
111 * nowtime is written into the registers of the CMOS clock, it will
112 * jump to the next second precisely 500 ms later. Check the Motorola
113 * MC146818A or Dallas DS12887 data sheet for details.
114 *
115 * BUG: This routine does not handle hour overflow properly; it just
116 * sets the minutes. Usually you won't notice until after reboot!
117 */
118static inline int set_rtc_mmss(unsigned long nowtime)
119{
120 return 0;
121}
122
123/* last time the cmos clock got updated */
124static long last_rtc_update = 0;
125
126/*
127 * timer_interrupt() needs to keep up the real-time clock, 109 * timer_interrupt() needs to keep up the real-time clock,
128 * as well as call the "do_timer()" routine every clocktick 110 * as well as call the "do_timer()" routine every clocktick
129 */ 111 */
@@ -138,23 +120,6 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
138#ifndef CONFIG_SMP 120#ifndef CONFIG_SMP
139 update_process_times(user_mode(get_irq_regs())); 121 update_process_times(user_mode(get_irq_regs()));
140#endif 122#endif
141 /*
142 * If we have an externally synchronized Linux clock, then update
143 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
144 * called as close as possible to 500 ms before the new second starts.
145 */
146 write_seqlock(&xtime_lock);
147 if (ntp_synced()
148 && xtime.tv_sec > last_rtc_update + 660
149 && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned)TICK_SIZE) / 2
150 && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned)TICK_SIZE) / 2)
151 {
152 if (set_rtc_mmss(xtime.tv_sec) == 0)
153 last_rtc_update = xtime.tv_sec;
154 else /* do it again in 60 s */
155 last_rtc_update = xtime.tv_sec - 600;
156 }
157 write_sequnlock(&xtime_lock);
158 /* As we return to user mode fire off the other CPU schedulers.. 123 /* As we return to user mode fire off the other CPU schedulers..
159 this is basically because we don't yet share IRQ's around. 124 this is basically because we don't yet share IRQ's around.
160 This message is rigged to be safe on the 386 - basically it's 125 This message is rigged to be safe on the 386 - basically it's
@@ -174,7 +139,7 @@ static struct irqaction irq0 = {
174 .name = "MFT2", 139 .name = "MFT2",
175}; 140};
176 141
177void __init time_init(void) 142void read_persistent_clock(struct timespec *ts)
178{ 143{
179 unsigned int epoch, year, mon, day, hour, min, sec; 144 unsigned int epoch, year, mon, day, hour, min, sec;
180 145
@@ -194,11 +159,13 @@ void __init time_init(void)
194 epoch = 1952; 159 epoch = 1952;
195 year += epoch; 160 year += epoch;
196 161
197 xtime.tv_sec = mktime(year, mon, day, hour, min, sec); 162 ts->tv_sec = mktime(year, mon, day, hour, min, sec);
198 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ); 163 ts->tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
199 set_normalized_timespec(&wall_to_monotonic, 164}
200 -xtime.tv_sec, -xtime.tv_nsec);
201 165
166
167void __init time_init(void)
168{
202#if defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_XNUX2) \ 169#if defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_XNUX2) \
203 || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_M32700) \ 170 || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_M32700) \
204 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104) 171 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)