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-rw-r--r--arch/m32r/platforms/m32104ut/setup.c58
-rw-r--r--arch/m32r/platforms/m32700ut/setup.c214
-rw-r--r--arch/m32r/platforms/mappi/setup.c78
-rw-r--r--arch/m32r/platforms/mappi2/setup.c89
-rw-r--r--arch/m32r/platforms/mappi3/setup.c92
-rw-r--r--arch/m32r/platforms/oaks32r/setup.c65
-rw-r--r--arch/m32r/platforms/opsput/setup.c220
-rw-r--r--arch/m32r/platforms/usrv/setup.c115
8 files changed, 318 insertions, 613 deletions
diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c
index 402a59d7219b..4a693d02c1e1 100644
--- a/arch/m32r/platforms/m32104ut/setup.c
+++ b/arch/m32r/platforms/m32104ut/setup.c
@@ -39,39 +39,30 @@ static void enable_m32104ut_irq(unsigned int irq)
39 outl(data, port); 39 outl(data, port);
40} 40}
41 41
42static void mask_and_ack_m32104ut(unsigned int irq) 42static void mask_m32104ut_irq(struct irq_data *data)
43{ 43{
44 disable_m32104ut_irq(irq); 44 disable_m32104ut_irq(data->irq);
45} 45}
46 46
47static void end_m32104ut_irq(unsigned int irq) 47static void unmask_m32104ut_irq(struct irq_data *data)
48{ 48{
49 enable_m32104ut_irq(irq); 49 enable_m32104ut_irq(data->irq);
50} 50}
51 51
52static unsigned int startup_m32104ut_irq(unsigned int irq) 52static void shutdown_m32104ut_irq(struct irq_data *data)
53{ 53{
54 enable_m32104ut_irq(irq); 54 unsigned int irq = data->irq;
55 return (0); 55 unsigned long port = irq2port(irq);
56}
57
58static void shutdown_m32104ut_irq(unsigned int irq)
59{
60 unsigned long port;
61 56
62 port = irq2port(irq);
63 outl(M32R_ICUCR_ILEVEL7, port); 57 outl(M32R_ICUCR_ILEVEL7, port);
64} 58}
65 59
66static struct irq_chip m32104ut_irq_type = 60static struct irq_chip m32104ut_irq_type =
67{ 61{
68 .name = "M32104UT-IRQ", 62 .name = "M32104UT-IRQ",
69 .startup = startup_m32104ut_irq, 63 .irq_shutdown = shutdown_m32104ut_irq,
70 .shutdown = shutdown_m32104ut_irq, 64 .irq_unmask = unmask_m32104ut_irq,
71 .enable = enable_m32104ut_irq, 65 .irq_mask = mask_m32104ut_irq,
72 .disable = disable_m32104ut_irq,
73 .ack = mask_and_ack_m32104ut,
74 .end = end_m32104ut_irq
75}; 66};
76 67
77void __init init_IRQ(void) 68void __init init_IRQ(void)
@@ -85,36 +76,29 @@ void __init init_IRQ(void)
85 76
86#if defined(CONFIG_SMC91X) 77#if defined(CONFIG_SMC91X)
87 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ 78 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 79 set_irq_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type,
89 irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type; 80 handle_level_irq);
90 irq_desc[M32R_IRQ_INT0].action = 0; 81 /* "H" level sense */
91 irq_desc[M32R_IRQ_INT0].depth = 1; 82 cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */
93 disable_m32104ut_irq(M32R_IRQ_INT0); 83 disable_m32104ut_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_SMC91X */ 84#endif /* CONFIG_SMC91X */
95 85
96 /* MFT2 : system timer */ 86 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 87 set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type,
98 irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type; 88 handle_level_irq);
99 irq_desc[M32R_IRQ_MFT2].action = 0;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 89 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_m32104ut_irq(M32R_IRQ_MFT2); 90 disable_m32104ut_irq(M32R_IRQ_MFT2);
103 91
104#ifdef CONFIG_SERIAL_M32R_SIO 92#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 93 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 94 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type,
107 irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type; 95 handle_level_irq);
108 irq_desc[M32R_IRQ_SIO0_R].action = 0;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; 96 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
111 disable_m32104ut_irq(M32R_IRQ_SIO0_R); 97 disable_m32104ut_irq(M32R_IRQ_SIO0_R);
112 98
113 /* SIO0_S : uart send data */ 99 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 100 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type,
115 irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type; 101 handle_level_irq);
116 irq_desc[M32R_IRQ_SIO0_S].action = 0;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; 102 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
119 disable_m32104ut_irq(M32R_IRQ_SIO0_S); 103 disable_m32104ut_irq(M32R_IRQ_SIO0_S);
120#endif /* CONFIG_SERIAL_M32R_SIO */ 104#endif /* CONFIG_SERIAL_M32R_SIO */
diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c
index 80b1a026795a..2074bcc841eb 100644
--- a/arch/m32r/platforms/m32700ut/setup.c
+++ b/arch/m32r/platforms/m32700ut/setup.c
@@ -45,39 +45,30 @@ static void enable_m32700ut_irq(unsigned int irq)
45 outl(data, port); 45 outl(data, port);
46} 46}
47 47
48static void mask_and_ack_m32700ut(unsigned int irq) 48static void mask_m32700ut(struct irq_data *data)
49{ 49{
50 disable_m32700ut_irq(irq); 50 disable_m32700ut_irq(data->irq);
51} 51}
52 52
53static void end_m32700ut_irq(unsigned int irq) 53static void unmask_m32700ut(struct irq_data *data)
54{ 54{
55 enable_m32700ut_irq(irq); 55 enable_m32700ut_irq(data->irq);
56} 56}
57 57
58static unsigned int startup_m32700ut_irq(unsigned int irq) 58static void shutdown_m32700ut(struct irq_data *data)
59{
60 enable_m32700ut_irq(irq);
61 return (0);
62}
63
64static void shutdown_m32700ut_irq(unsigned int irq)
65{ 59{
66 unsigned long port; 60 unsigned long port;
67 61
68 port = irq2port(irq); 62 port = irq2port(data->irq);
69 outl(M32R_ICUCR_ILEVEL7, port); 63 outl(M32R_ICUCR_ILEVEL7, port);
70} 64}
71 65
72static struct irq_chip m32700ut_irq_type = 66static struct irq_chip m32700ut_irq_type =
73{ 67{
74 .name = "M32700UT-IRQ", 68 .name = "M32700UT-IRQ",
75 .startup = startup_m32700ut_irq, 69 .irq_shutdown = shutdown_m32700ut,
76 .shutdown = shutdown_m32700ut_irq, 70 .irq_mask = mask_m32700ut,
77 .enable = enable_m32700ut_irq, 71 .irq_unmask = unmask_m32700ut
78 .disable = disable_m32700ut_irq,
79 .ack = mask_and_ack_m32700ut,
80 .end = end_m32700ut_irq
81}; 72};
82 73
83/* 74/*
@@ -99,7 +90,6 @@ static void disable_m32700ut_pld_irq(unsigned int irq)
99 unsigned int pldirq; 90 unsigned int pldirq;
100 91
101 pldirq = irq2pldirq(irq); 92 pldirq = irq2pldirq(irq);
102// disable_m32700ut_irq(M32R_IRQ_INT1);
103 port = pldirq2port(pldirq); 93 port = pldirq2port(pldirq);
104 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; 94 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
105 outw(data, port); 95 outw(data, port);
@@ -111,50 +101,38 @@ static void enable_m32700ut_pld_irq(unsigned int irq)
111 unsigned int pldirq; 101 unsigned int pldirq;
112 102
113 pldirq = irq2pldirq(irq); 103 pldirq = irq2pldirq(irq);
114// enable_m32700ut_irq(M32R_IRQ_INT1);
115 port = pldirq2port(pldirq); 104 port = pldirq2port(pldirq);
116 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; 105 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
117 outw(data, port); 106 outw(data, port);
118} 107}
119 108
120static void mask_and_ack_m32700ut_pld(unsigned int irq) 109static void mask_m32700ut_pld(struct irq_data *data)
121{
122 disable_m32700ut_pld_irq(irq);
123// mask_and_ack_m32700ut(M32R_IRQ_INT1);
124}
125
126static void end_m32700ut_pld_irq(unsigned int irq)
127{ 110{
128 enable_m32700ut_pld_irq(irq); 111 disable_m32700ut_pld_irq(data->irq);
129 end_m32700ut_irq(M32R_IRQ_INT1);
130} 112}
131 113
132static unsigned int startup_m32700ut_pld_irq(unsigned int irq) 114static void unmask_m32700ut_pld(struct irq_data *data)
133{ 115{
134 enable_m32700ut_pld_irq(irq); 116 enable_m32700ut_pld_irq(data->irq);
135 return (0); 117 enable_m32700ut_irq(M32R_IRQ_INT1);
136} 118}
137 119
138static void shutdown_m32700ut_pld_irq(unsigned int irq) 120static void shutdown_m32700ut_pld_irq(struct irq_data *data)
139{ 121{
140 unsigned long port; 122 unsigned long port;
141 unsigned int pldirq; 123 unsigned int pldirq;
142 124
143 pldirq = irq2pldirq(irq); 125 pldirq = irq2pldirq(data->irq);
144// shutdown_m32700ut_irq(M32R_IRQ_INT1);
145 port = pldirq2port(pldirq); 126 port = pldirq2port(pldirq);
146 outw(PLD_ICUCR_ILEVEL7, port); 127 outw(PLD_ICUCR_ILEVEL7, port);
147} 128}
148 129
149static struct irq_chip m32700ut_pld_irq_type = 130static struct irq_chip m32700ut_pld_irq_type =
150{ 131{
151 .name = "M32700UT-PLD-IRQ", 132 .name = "M32700UT-PLD-IRQ",
152 .startup = startup_m32700ut_pld_irq, 133 .irq_shutdown = shutdown_m32700ut_pld_irq,
153 .shutdown = shutdown_m32700ut_pld_irq, 134 .irq_mask = mask_m32700ut_pld,
154 .enable = enable_m32700ut_pld_irq, 135 .irq_unmask = unmask_m32700ut_pld,
155 .disable = disable_m32700ut_pld_irq,
156 .ack = mask_and_ack_m32700ut_pld,
157 .end = end_m32700ut_pld_irq
158}; 136};
159 137
160/* 138/*
@@ -188,42 +166,33 @@ static void enable_m32700ut_lanpld_irq(unsigned int irq)
188 outw(data, port); 166 outw(data, port);
189} 167}
190 168
191static void mask_and_ack_m32700ut_lanpld(unsigned int irq) 169static void mask_m32700ut_lanpld(struct irq_data *data)
192{ 170{
193 disable_m32700ut_lanpld_irq(irq); 171 disable_m32700ut_lanpld_irq(data->irq);
194} 172}
195 173
196static void end_m32700ut_lanpld_irq(unsigned int irq) 174static void unmask_m32700ut_lanpld(struct irq_data *data)
197{ 175{
198 enable_m32700ut_lanpld_irq(irq); 176 enable_m32700ut_lanpld_irq(data->irq);
199 end_m32700ut_irq(M32R_IRQ_INT0); 177 enable_m32700ut_irq(M32R_IRQ_INT0);
200}
201
202static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
203{
204 enable_m32700ut_lanpld_irq(irq);
205 return (0);
206} 178}
207 179
208static void shutdown_m32700ut_lanpld_irq(unsigned int irq) 180static void shutdown_m32700ut_lanpld(struct irq_data *data)
209{ 181{
210 unsigned long port; 182 unsigned long port;
211 unsigned int pldirq; 183 unsigned int pldirq;
212 184
213 pldirq = irq2lanpldirq(irq); 185 pldirq = irq2lanpldirq(data->irq);
214 port = lanpldirq2port(pldirq); 186 port = lanpldirq2port(pldirq);
215 outw(PLD_ICUCR_ILEVEL7, port); 187 outw(PLD_ICUCR_ILEVEL7, port);
216} 188}
217 189
218static struct irq_chip m32700ut_lanpld_irq_type = 190static struct irq_chip m32700ut_lanpld_irq_type =
219{ 191{
220 .name = "M32700UT-PLD-LAN-IRQ", 192 .name = "M32700UT-PLD-LAN-IRQ",
221 .startup = startup_m32700ut_lanpld_irq, 193 .irq_shutdown = shutdown_m32700ut_lanpld,
222 .shutdown = shutdown_m32700ut_lanpld_irq, 194 .irq_mask = mask_m32700ut_lanpld,
223 .enable = enable_m32700ut_lanpld_irq, 195 .irq_unmask = unmask_m32700ut_lanpld,
224 .disable = disable_m32700ut_lanpld_irq,
225 .ack = mask_and_ack_m32700ut_lanpld,
226 .end = end_m32700ut_lanpld_irq
227}; 196};
228 197
229/* 198/*
@@ -257,143 +226,110 @@ static void enable_m32700ut_lcdpld_irq(unsigned int irq)
257 outw(data, port); 226 outw(data, port);
258} 227}
259 228
260static void mask_and_ack_m32700ut_lcdpld(unsigned int irq) 229static void mask_m32700ut_lcdpld(struct irq_data *data)
261{ 230{
262 disable_m32700ut_lcdpld_irq(irq); 231 disable_m32700ut_lcdpld_irq(data->irq);
263} 232}
264 233
265static void end_m32700ut_lcdpld_irq(unsigned int irq) 234static void unmask_m32700ut_lcdpld(struct irq_data *data)
266{ 235{
267 enable_m32700ut_lcdpld_irq(irq); 236 enable_m32700ut_lcdpld_irq(data->irq);
268 end_m32700ut_irq(M32R_IRQ_INT2); 237 enable_m32700ut_irq(M32R_IRQ_INT2);
269}
270
271static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
272{
273 enable_m32700ut_lcdpld_irq(irq);
274 return (0);
275} 238}
276 239
277static void shutdown_m32700ut_lcdpld_irq(unsigned int irq) 240static void shutdown_m32700ut_lcdpld(struct irq_data *data)
278{ 241{
279 unsigned long port; 242 unsigned long port;
280 unsigned int pldirq; 243 unsigned int pldirq;
281 244
282 pldirq = irq2lcdpldirq(irq); 245 pldirq = irq2lcdpldirq(data->irq);
283 port = lcdpldirq2port(pldirq); 246 port = lcdpldirq2port(pldirq);
284 outw(PLD_ICUCR_ILEVEL7, port); 247 outw(PLD_ICUCR_ILEVEL7, port);
285} 248}
286 249
287static struct irq_chip m32700ut_lcdpld_irq_type = 250static struct irq_chip m32700ut_lcdpld_irq_type =
288{ 251{
289 .name = "M32700UT-PLD-LCD-IRQ", 252 .name = "M32700UT-PLD-LCD-IRQ",
290 .startup = startup_m32700ut_lcdpld_irq, 253 .irq_shutdown = shutdown_m32700ut_lcdpld,
291 .shutdown = shutdown_m32700ut_lcdpld_irq, 254 .irq_mask = mask_m32700ut_lcdpld,
292 .enable = enable_m32700ut_lcdpld_irq, 255 .irq_unmask = unmask_m32700ut_lcdpld,
293 .disable = disable_m32700ut_lcdpld_irq,
294 .ack = mask_and_ack_m32700ut_lcdpld,
295 .end = end_m32700ut_lcdpld_irq
296}; 256};
297 257
298void __init init_IRQ(void) 258void __init init_IRQ(void)
299{ 259{
300#if defined(CONFIG_SMC91X) 260#if defined(CONFIG_SMC91X)
301 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ 261 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
302 irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED; 262 set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN,
303 irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type; 263 &m32700ut_lanpld_irq_type, handle_level_irq);
304 irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
305 irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
306 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ 264 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
307 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN); 265 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
308#endif /* CONFIG_SMC91X */ 266#endif /* CONFIG_SMC91X */
309 267
310 /* MFT2 : system timer */ 268 /* MFT2 : system timer */
311 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 269 set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
312 irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type; 270 handle_level_irq);
313 irq_desc[M32R_IRQ_MFT2].action = 0;
314 irq_desc[M32R_IRQ_MFT2].depth = 1;
315 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 271 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
316 disable_m32700ut_irq(M32R_IRQ_MFT2); 272 disable_m32700ut_irq(M32R_IRQ_MFT2);
317 273
318 /* SIO0 : receive */ 274 /* SIO0 : receive */
319 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 275 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
320 irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type; 276 handle_level_irq);
321 irq_desc[M32R_IRQ_SIO0_R].action = 0;
322 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
323 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 277 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
324 disable_m32700ut_irq(M32R_IRQ_SIO0_R); 278 disable_m32700ut_irq(M32R_IRQ_SIO0_R);
325 279
326 /* SIO0 : send */ 280 /* SIO0 : send */
327 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 281 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
328 irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type; 282 handle_level_irq);
329 irq_desc[M32R_IRQ_SIO0_S].action = 0;
330 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
331 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 283 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
332 disable_m32700ut_irq(M32R_IRQ_SIO0_S); 284 disable_m32700ut_irq(M32R_IRQ_SIO0_S);
333 285
334 /* SIO1 : receive */ 286 /* SIO1 : receive */
335 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 287 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
336 irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type; 288 handle_level_irq);
337 irq_desc[M32R_IRQ_SIO1_R].action = 0;
338 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
339 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 289 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
340 disable_m32700ut_irq(M32R_IRQ_SIO1_R); 290 disable_m32700ut_irq(M32R_IRQ_SIO1_R);
341 291
342 /* SIO1 : send */ 292 /* SIO1 : send */
343 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 293 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
344 irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type; 294 handle_level_irq);
345 irq_desc[M32R_IRQ_SIO1_S].action = 0;
346 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
347 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 295 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
348 disable_m32700ut_irq(M32R_IRQ_SIO1_S); 296 disable_m32700ut_irq(M32R_IRQ_SIO1_S);
349 297
350 /* DMA1 : */ 298 /* DMA1 : */
351 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; 299 set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
352 irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type; 300 handle_level_irq);
353 irq_desc[M32R_IRQ_DMA1].action = 0;
354 irq_desc[M32R_IRQ_DMA1].depth = 1;
355 icu_data[M32R_IRQ_DMA1].icucr = 0; 301 icu_data[M32R_IRQ_DMA1].icucr = 0;
356 disable_m32700ut_irq(M32R_IRQ_DMA1); 302 disable_m32700ut_irq(M32R_IRQ_DMA1);
357 303
358#ifdef CONFIG_SERIAL_M32R_PLDSIO 304#ifdef CONFIG_SERIAL_M32R_PLDSIO
359 /* INT#1: SIO0 Receive on PLD */ 305 /* INT#1: SIO0 Receive on PLD */
360 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; 306 set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
361 irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type; 307 handle_level_irq);
362 irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
363 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
364 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 308 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
365 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); 309 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
366 310
367 /* INT#1: SIO0 Send on PLD */ 311 /* INT#1: SIO0 Send on PLD */
368 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; 312 set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
369 irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type; 313 handle_level_irq);
370 irq_desc[PLD_IRQ_SIO0_SND].action = 0;
371 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
372 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 314 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
373 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); 315 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
374#endif /* CONFIG_SERIAL_M32R_PLDSIO */ 316#endif /* CONFIG_SERIAL_M32R_PLDSIO */
375 317
376 /* INT#1: CFC IREQ on PLD */ 318 /* INT#1: CFC IREQ on PLD */
377 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 319 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
378 irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type; 320 handle_level_irq);
379 irq_desc[PLD_IRQ_CFIREQ].action = 0;
380 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
381 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 321 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
382 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); 322 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
383 323
384 /* INT#1: CFC Insert on PLD */ 324 /* INT#1: CFC Insert on PLD */
385 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 325 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
386 irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type; 326 handle_level_irq);
387 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
388 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
389 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 327 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
390 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); 328 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
391 329
392 /* INT#1: CFC Eject on PLD */ 330 /* INT#1: CFC Eject on PLD */
393 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; 331 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
394 irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type; 332 handle_level_irq);
395 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
396 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
397 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 333 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
398 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); 334 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
399 335
@@ -413,13 +349,11 @@ void __init init_IRQ(void)
413 349
414#if defined(CONFIG_USB) 350#if defined(CONFIG_USB)
415 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ 351 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
352 set_irq_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1,
353 &m32700ut_lcdpld_irq_type, handle_level_irq);
416 354
417 irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; 355 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
418 irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type; 356 disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
419 irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
420 irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
421 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
422 disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
423#endif 357#endif
424 /* 358 /*
425 * INT2# is used for BAT, USB, AUDIO 359 * INT2# is used for BAT, USB, AUDIO
@@ -432,10 +366,8 @@ void __init init_IRQ(void)
432 /* 366 /*
433 * INT3# is used for AR 367 * INT3# is used for AR
434 */ 368 */
435 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 369 set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
436 irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type; 370 handle_level_irq);
437 irq_desc[M32R_IRQ_INT3].action = 0;
438 irq_desc[M32R_IRQ_INT3].depth = 1;
439 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 371 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
440 disable_m32700ut_irq(M32R_IRQ_INT3); 372 disable_m32700ut_irq(M32R_IRQ_INT3);
441#endif /* CONFIG_VIDEO_M32R_AR */ 373#endif /* CONFIG_VIDEO_M32R_AR */
diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c
index ea00c84d6b1b..cdd8c4574027 100644
--- a/arch/m32r/platforms/mappi/setup.c
+++ b/arch/m32r/platforms/mappi/setup.c
@@ -38,40 +38,30 @@ static void enable_mappi_irq(unsigned int irq)
38 outl(data, port); 38 outl(data, port);
39} 39}
40 40
41static void mask_and_ack_mappi(unsigned int irq) 41static void mask_mappi(struct irq_data *data)
42{ 42{
43 disable_mappi_irq(irq); 43 disable_mappi_irq(data->irq);
44} 44}
45 45
46static void end_mappi_irq(unsigned int irq) 46static void unmask_mappi(struct irq_data *data)
47{ 47{
48 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 48 enable_mappi_irq(data->irq);
49 enable_mappi_irq(irq);
50} 49}
51 50
52static unsigned int startup_mappi_irq(unsigned int irq) 51static void shutdown_mappi(struct irq_data *data)
53{
54 enable_mappi_irq(irq);
55 return (0);
56}
57
58static void shutdown_mappi_irq(unsigned int irq)
59{ 52{
60 unsigned long port; 53 unsigned long port;
61 54
62 port = irq2port(irq); 55 port = irq2port(data->irq);
63 outl(M32R_ICUCR_ILEVEL7, port); 56 outl(M32R_ICUCR_ILEVEL7, port);
64} 57}
65 58
66static struct irq_chip mappi_irq_type = 59static struct irq_chip mappi_irq_type =
67{ 60{
68 .name = "MAPPI-IRQ", 61 .name = "MAPPI-IRQ",
69 .startup = startup_mappi_irq, 62 .irq_shutdown = shutdown_mappi,
70 .shutdown = shutdown_mappi_irq, 63 .irq_mask = mask_mappi,
71 .enable = enable_mappi_irq, 64 .irq_unmask = unmask_mappi,
72 .disable = disable_mappi_irq,
73 .ack = mask_and_ack_mappi,
74 .end = end_mappi_irq
75}; 65};
76 66
77void __init init_IRQ(void) 67void __init init_IRQ(void)
@@ -85,70 +75,54 @@ void __init init_IRQ(void)
85 75
86#ifdef CONFIG_NE2000 76#ifdef CONFIG_NE2000
87 /* INT0 : LAN controller (RTL8019AS) */ 77 /* INT0 : LAN controller (RTL8019AS) */
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 78 set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type,
89 irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type; 79 handle_level_irq);
90 irq_desc[M32R_IRQ_INT0].action = NULL;
91 irq_desc[M32R_IRQ_INT0].depth = 1;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; 80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
93 disable_mappi_irq(M32R_IRQ_INT0); 81 disable_mappi_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_M32R_NE2000 */ 82#endif /* CONFIG_M32R_NE2000 */
95 83
96 /* MFT2 : system timer */ 84 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 85 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
98 irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; 86 handle_level_irq);
99 irq_desc[M32R_IRQ_MFT2].action = NULL;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_mappi_irq(M32R_IRQ_MFT2); 88 disable_mappi_irq(M32R_IRQ_MFT2);
103 89
104#ifdef CONFIG_SERIAL_M32R_SIO 90#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 91 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 92 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; 93 handle_level_irq);
108 irq_desc[M32R_IRQ_SIO0_R].action = NULL;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 94 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
111 disable_mappi_irq(M32R_IRQ_SIO0_R); 95 disable_mappi_irq(M32R_IRQ_SIO0_R);
112 96
113 /* SIO0_S : uart send data */ 97 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 98 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; 99 handle_level_irq);
116 irq_desc[M32R_IRQ_SIO0_S].action = NULL;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 100 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
119 disable_mappi_irq(M32R_IRQ_SIO0_S); 101 disable_mappi_irq(M32R_IRQ_SIO0_S);
120 102
121 /* SIO1_R : uart receive data */ 103 /* SIO1_R : uart receive data */
122 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 104 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
123 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; 105 handle_level_irq);
124 irq_desc[M32R_IRQ_SIO1_R].action = NULL;
125 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
126 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 106 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
127 disable_mappi_irq(M32R_IRQ_SIO1_R); 107 disable_mappi_irq(M32R_IRQ_SIO1_R);
128 108
129 /* SIO1_S : uart send data */ 109 /* SIO1_S : uart send data */
130 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 110 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
131 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; 111 handle_level_irq);
132 irq_desc[M32R_IRQ_SIO1_S].action = NULL;
133 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
134 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 112 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
135 disable_mappi_irq(M32R_IRQ_SIO1_S); 113 disable_mappi_irq(M32R_IRQ_SIO1_S);
136#endif /* CONFIG_SERIAL_M32R_SIO */ 114#endif /* CONFIG_SERIAL_M32R_SIO */
137 115
138#if defined(CONFIG_M32R_PCC) 116#if defined(CONFIG_M32R_PCC)
139 /* INT1 : pccard0 interrupt */ 117 /* INT1 : pccard0 interrupt */
140 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 118 set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type,
141 irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type; 119 handle_level_irq);
142 irq_desc[M32R_IRQ_INT1].action = NULL;
143 irq_desc[M32R_IRQ_INT1].depth = 1;
144 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
145 disable_mappi_irq(M32R_IRQ_INT1); 121 disable_mappi_irq(M32R_IRQ_INT1);
146 122
147 /* INT2 : pccard1 interrupt */ 123 /* INT2 : pccard1 interrupt */
148 irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED; 124 set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type,
149 irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type; 125 handle_level_irq);
150 irq_desc[M32R_IRQ_INT2].action = NULL;
151 irq_desc[M32R_IRQ_INT2].depth = 1;
152 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 126 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
153 disable_mappi_irq(M32R_IRQ_INT2); 127 disable_mappi_irq(M32R_IRQ_INT2);
154#endif /* CONFIG_M32RPCC */ 128#endif /* CONFIG_M32RPCC */
diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c
index c049376d0270..9117c30ea365 100644
--- a/arch/m32r/platforms/mappi2/setup.c
+++ b/arch/m32r/platforms/mappi2/setup.c
@@ -46,126 +46,97 @@ static void enable_mappi2_irq(unsigned int irq)
46 outl(data, port); 46 outl(data, port);
47} 47}
48 48
49static void mask_and_ack_mappi2(unsigned int irq) 49static void mask_mappi2(struct irq_data *data)
50{ 50{
51 disable_mappi2_irq(irq); 51 disable_mappi2_irq(data->irq);
52} 52}
53 53
54static void end_mappi2_irq(unsigned int irq) 54static void unmask_mappi2(struct irq_data *data)
55{ 55{
56 enable_mappi2_irq(irq); 56 enable_mappi2_irq(data->irq);
57} 57}
58 58
59static unsigned int startup_mappi2_irq(unsigned int irq) 59static void shutdown_mappi2(struct irq_data *data)
60{
61 enable_mappi2_irq(irq);
62 return (0);
63}
64
65static void shutdown_mappi2_irq(unsigned int irq)
66{ 60{
67 unsigned long port; 61 unsigned long port;
68 62
69 port = irq2port(irq); 63 port = irq2port(data->irq);
70 outl(M32R_ICUCR_ILEVEL7, port); 64 outl(M32R_ICUCR_ILEVEL7, port);
71} 65}
72 66
73static struct irq_chip mappi2_irq_type = 67static struct irq_chip mappi2_irq_type =
74{ 68{
75 .name = "MAPPI2-IRQ", 69 .name = "MAPPI2-IRQ",
76 .startup = startup_mappi2_irq, 70 .irq_shutdown = shutdown_mappi2,
77 .shutdown = shutdown_mappi2_irq, 71 .irq_mask = mask_mappi2,
78 .enable = enable_mappi2_irq, 72 .irq_unmask = unmask_mappi2,
79 .disable = disable_mappi2_irq,
80 .ack = mask_and_ack_mappi2,
81 .end = end_mappi2_irq
82}; 73};
83 74
84void __init init_IRQ(void) 75void __init init_IRQ(void)
85{ 76{
86#if defined(CONFIG_SMC91X) 77#if defined(CONFIG_SMC91X)
87 /* INT0 : LAN controller (SMC91111) */ 78 /* INT0 : LAN controller (SMC91111) */
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 79 set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
89 irq_desc[M32R_IRQ_INT0].chip = &mappi2_irq_type; 80 handle_level_irq);
90 irq_desc[M32R_IRQ_INT0].action = 0;
91 irq_desc[M32R_IRQ_INT0].depth = 1;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 81 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
93 disable_mappi2_irq(M32R_IRQ_INT0); 82 disable_mappi2_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_SMC91X */ 83#endif /* CONFIG_SMC91X */
95 84
96 /* MFT2 : system timer */ 85 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 86 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
98 irq_desc[M32R_IRQ_MFT2].chip = &mappi2_irq_type; 87 handle_level_irq);
99 irq_desc[M32R_IRQ_MFT2].action = 0;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 88 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_mappi2_irq(M32R_IRQ_MFT2); 89 disable_mappi2_irq(M32R_IRQ_MFT2);
103 90
104#ifdef CONFIG_SERIAL_M32R_SIO 91#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 92 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 93 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi2_irq_type; 94 handle_level_irq);
108 irq_desc[M32R_IRQ_SIO0_R].action = 0;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 95 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
111 disable_mappi2_irq(M32R_IRQ_SIO0_R); 96 disable_mappi2_irq(M32R_IRQ_SIO0_R);
112 97
113 /* SIO0_S : uart send data */ 98 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 99 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi2_irq_type; 100 handle_level_irq);
116 irq_desc[M32R_IRQ_SIO0_S].action = 0;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 101 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
119 disable_mappi2_irq(M32R_IRQ_SIO0_S); 102 disable_mappi2_irq(M32R_IRQ_SIO0_S);
120 /* SIO1_R : uart receive data */ 103 /* SIO1_R : uart receive data */
121 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 104 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
122 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi2_irq_type; 105 handle_level_irq);
123 irq_desc[M32R_IRQ_SIO1_R].action = 0;
124 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
125 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 106 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
126 disable_mappi2_irq(M32R_IRQ_SIO1_R); 107 disable_mappi2_irq(M32R_IRQ_SIO1_R);
127 108
128 /* SIO1_S : uart send data */ 109 /* SIO1_S : uart send data */
129 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 110 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
130 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi2_irq_type; 111 handle_level_irq);
131 irq_desc[M32R_IRQ_SIO1_S].action = 0;
132 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
133 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 112 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
134 disable_mappi2_irq(M32R_IRQ_SIO1_S); 113 disable_mappi2_irq(M32R_IRQ_SIO1_S);
135#endif /* CONFIG_M32R_USE_DBG_CONSOLE */ 114#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
136 115
137#if defined(CONFIG_USB) 116#if defined(CONFIG_USB)
138 /* INT1 : USB Host controller interrupt */ 117 /* INT1 : USB Host controller interrupt */
139 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 118 set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
140 irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type; 119 handle_level_irq);
141 irq_desc[M32R_IRQ_INT1].action = 0;
142 irq_desc[M32R_IRQ_INT1].depth = 1;
143 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
144 disable_mappi2_irq(M32R_IRQ_INT1); 121 disable_mappi2_irq(M32R_IRQ_INT1);
145#endif /* CONFIG_USB */ 122#endif /* CONFIG_USB */
146 123
147 /* ICUCR40: CFC IREQ */ 124 /* ICUCR40: CFC IREQ */
148 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 125 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
149 irq_desc[PLD_IRQ_CFIREQ].chip = &mappi2_irq_type; 126 handle_level_irq);
150 irq_desc[PLD_IRQ_CFIREQ].action = 0;
151 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
152 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 127 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
153 disable_mappi2_irq(PLD_IRQ_CFIREQ); 128 disable_mappi2_irq(PLD_IRQ_CFIREQ);
154 129
155#if defined(CONFIG_M32R_CFC) 130#if defined(CONFIG_M32R_CFC)
156 /* ICUCR41: CFC Insert */ 131 /* ICUCR41: CFC Insert */
157 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 132 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
158 irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi2_irq_type; 133 handle_level_irq);
159 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
160 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
161 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 134 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
162 disable_mappi2_irq(PLD_IRQ_CFC_INSERT); 135 disable_mappi2_irq(PLD_IRQ_CFC_INSERT);
163 136
164 /* ICUCR42: CFC Eject */ 137 /* ICUCR42: CFC Eject */
165 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; 138 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
166 irq_desc[PLD_IRQ_CFC_EJECT].chip = &mappi2_irq_type; 139 handle_level_irq);
167 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
168 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
169 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 140 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
170 disable_mappi2_irq(PLD_IRQ_CFC_EJECT); 141 disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
171#endif /* CONFIG_MAPPI2_CFC */ 142#endif /* CONFIG_MAPPI2_CFC */
diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c
index 882de25c6e8c..b44f5ded2bbe 100644
--- a/arch/m32r/platforms/mappi3/setup.c
+++ b/arch/m32r/platforms/mappi3/setup.c
@@ -46,128 +46,98 @@ static void enable_mappi3_irq(unsigned int irq)
46 outl(data, port); 46 outl(data, port);
47} 47}
48 48
49static void mask_and_ack_mappi3(unsigned int irq) 49static void mask_mappi3(struct irq_data *data)
50{ 50{
51 disable_mappi3_irq(irq); 51 disable_mappi3_irq(data->irq);
52} 52}
53 53
54static void end_mappi3_irq(unsigned int irq) 54static void unmask_mappi3(struct irq_data *data)
55{ 55{
56 enable_mappi3_irq(irq); 56 enable_mappi3_irq(data->irq);
57} 57}
58 58
59static unsigned int startup_mappi3_irq(unsigned int irq) 59static void shutdown_mappi3(struct irq_data *data)
60{
61 enable_mappi3_irq(irq);
62 return (0);
63}
64
65static void shutdown_mappi3_irq(unsigned int irq)
66{ 60{
67 unsigned long port; 61 unsigned long port;
68 62
69 port = irq2port(irq); 63 port = irq2port(data->irq);
70 outl(M32R_ICUCR_ILEVEL7, port); 64 outl(M32R_ICUCR_ILEVEL7, port);
71} 65}
72 66
73static struct irq_chip mappi3_irq_type = 67static struct irq_chip mappi3_irq_type = {
74{ 68 .name = "MAPPI3-IRQ",
75 .name = "MAPPI3-IRQ", 69 .irq_shutdown = shutdown_mappi3,
76 .startup = startup_mappi3_irq, 70 .irq_mask = mask_mappi3,
77 .shutdown = shutdown_mappi3_irq, 71 .irq_unmask = unmask_mappi3,
78 .enable = enable_mappi3_irq,
79 .disable = disable_mappi3_irq,
80 .ack = mask_and_ack_mappi3,
81 .end = end_mappi3_irq
82}; 72};
83 73
84void __init init_IRQ(void) 74void __init init_IRQ(void)
85{ 75{
86#if defined(CONFIG_SMC91X) 76#if defined(CONFIG_SMC91X)
87 /* INT0 : LAN controller (SMC91111) */ 77 /* INT0 : LAN controller (SMC91111) */
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 78 set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type,
89 irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type; 79 handle_level_irq);
90 irq_desc[M32R_IRQ_INT0].action = 0;
91 irq_desc[M32R_IRQ_INT0].depth = 1;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
93 disable_mappi3_irq(M32R_IRQ_INT0); 81 disable_mappi3_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_SMC91X */ 82#endif /* CONFIG_SMC91X */
95 83
96 /* MFT2 : system timer */ 84 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 85 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type,
98 irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type; 86 handle_level_irq);
99 irq_desc[M32R_IRQ_MFT2].action = 0;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_mappi3_irq(M32R_IRQ_MFT2); 88 disable_mappi3_irq(M32R_IRQ_MFT2);
103 89
104#ifdef CONFIG_SERIAL_M32R_SIO 90#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 91 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 92 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type,
107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type; 93 handle_level_irq);
108 irq_desc[M32R_IRQ_SIO0_R].action = 0;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 94 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
111 disable_mappi3_irq(M32R_IRQ_SIO0_R); 95 disable_mappi3_irq(M32R_IRQ_SIO0_R);
112 96
113 /* SIO0_S : uart send data */ 97 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 98 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type,
115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type; 99 handle_level_irq);
116 irq_desc[M32R_IRQ_SIO0_S].action = 0;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 100 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
119 disable_mappi3_irq(M32R_IRQ_SIO0_S); 101 disable_mappi3_irq(M32R_IRQ_SIO0_S);
120 /* SIO1_R : uart receive data */ 102 /* SIO1_R : uart receive data */
121 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 103 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type,
122 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type; 104 handle_level_irq);
123 irq_desc[M32R_IRQ_SIO1_R].action = 0;
124 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
125 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 105 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
126 disable_mappi3_irq(M32R_IRQ_SIO1_R); 106 disable_mappi3_irq(M32R_IRQ_SIO1_R);
127 107
128 /* SIO1_S : uart send data */ 108 /* SIO1_S : uart send data */
129 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 109 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type,
130 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type; 110 handle_level_irq);
131 irq_desc[M32R_IRQ_SIO1_S].action = 0;
132 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
133 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 111 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
134 disable_mappi3_irq(M32R_IRQ_SIO1_S); 112 disable_mappi3_irq(M32R_IRQ_SIO1_S);
135#endif /* CONFIG_M32R_USE_DBG_CONSOLE */ 113#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
136 114
137#if defined(CONFIG_USB) 115#if defined(CONFIG_USB)
138 /* INT1 : USB Host controller interrupt */ 116 /* INT1 : USB Host controller interrupt */
139 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 117 set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type,
140 irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type; 118 handle_level_irq);
141 irq_desc[M32R_IRQ_INT1].action = 0;
142 irq_desc[M32R_IRQ_INT1].depth = 1;
143 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 119 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
144 disable_mappi3_irq(M32R_IRQ_INT1); 120 disable_mappi3_irq(M32R_IRQ_INT1);
145#endif /* CONFIG_USB */ 121#endif /* CONFIG_USB */
146 122
147 /* CFC IREQ */ 123 /* CFC IREQ */
148 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 124 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type,
149 irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type; 125 handle_level_irq);
150 irq_desc[PLD_IRQ_CFIREQ].action = 0;
151 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
152 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 126 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
153 disable_mappi3_irq(PLD_IRQ_CFIREQ); 127 disable_mappi3_irq(PLD_IRQ_CFIREQ);
154 128
155#if defined(CONFIG_M32R_CFC) 129#if defined(CONFIG_M32R_CFC)
156 /* ICUCR41: CFC Insert & eject */ 130 /* ICUCR41: CFC Insert & eject */
157 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 131 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type,
158 irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type; 132 handle_level_irq);
159 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
160 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
161 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 133 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
162 disable_mappi3_irq(PLD_IRQ_CFC_INSERT); 134 disable_mappi3_irq(PLD_IRQ_CFC_INSERT);
163 135
164#endif /* CONFIG_M32R_CFC */ 136#endif /* CONFIG_M32R_CFC */
165 137
166 /* IDE IREQ */ 138 /* IDE IREQ */
167 irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED; 139 set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type,
168 irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type; 140 handle_level_irq);
169 irq_desc[PLD_IRQ_IDEIREQ].action = 0;
170 irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */
171 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 141 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
172 disable_mappi3_irq(PLD_IRQ_IDEIREQ); 142 disable_mappi3_irq(PLD_IRQ_IDEIREQ);
173 143
diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c
index d11d93bf74f5..19a02db7b818 100644
--- a/arch/m32r/platforms/oaks32r/setup.c
+++ b/arch/m32r/platforms/oaks32r/setup.c
@@ -37,39 +37,30 @@ static void enable_oaks32r_irq(unsigned int irq)
37 outl(data, port); 37 outl(data, port);
38} 38}
39 39
40static void mask_and_ack_mappi(unsigned int irq) 40static void mask_oaks32r(struct irq_data *data)
41{ 41{
42 disable_oaks32r_irq(irq); 42 disable_oaks32r_irq(data->irq);
43} 43}
44 44
45static void end_oaks32r_irq(unsigned int irq) 45static void unmask_oaks32r(struct irq_data *data)
46{ 46{
47 enable_oaks32r_irq(irq); 47 enable_oaks32r_irq(data->irq);
48} 48}
49 49
50static unsigned int startup_oaks32r_irq(unsigned int irq) 50static void shutdown_oaks32r(struct irq_data *data)
51{
52 enable_oaks32r_irq(irq);
53 return (0);
54}
55
56static void shutdown_oaks32r_irq(unsigned int irq)
57{ 51{
58 unsigned long port; 52 unsigned long port;
59 53
60 port = irq2port(irq); 54 port = irq2port(data->irq);
61 outl(M32R_ICUCR_ILEVEL7, port); 55 outl(M32R_ICUCR_ILEVEL7, port);
62} 56}
63 57
64static struct irq_chip oaks32r_irq_type = 58static struct irq_chip oaks32r_irq_type =
65{ 59{
66 .name = "OAKS32R-IRQ", 60 .name = "OAKS32R-IRQ",
67 .startup = startup_oaks32r_irq, 61 .irq_shutdown = shutdown_oaks32r,
68 .shutdown = shutdown_oaks32r_irq, 62 .irq_mask = mask_oaks32r,
69 .enable = enable_oaks32r_irq, 63 .irq_unmask = unmask_oaks32r,
70 .disable = disable_oaks32r_irq,
71 .ack = mask_and_ack_mappi,
72 .end = end_oaks32r_irq
73}; 64};
74 65
75void __init init_IRQ(void) 66void __init init_IRQ(void)
@@ -83,52 +74,40 @@ void __init init_IRQ(void)
83 74
84#ifdef CONFIG_NE2000 75#ifdef CONFIG_NE2000
85 /* INT3 : LAN controller (RTL8019AS) */ 76 /* INT3 : LAN controller (RTL8019AS) */
86 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 77 set_irq_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type,
87 irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type; 78 handle_level_irq);
88 irq_desc[M32R_IRQ_INT3].action = 0;
89 irq_desc[M32R_IRQ_INT3].depth = 1;
90 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 79 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
91 disable_oaks32r_irq(M32R_IRQ_INT3); 80 disable_oaks32r_irq(M32R_IRQ_INT3);
92#endif /* CONFIG_M32R_NE2000 */ 81#endif /* CONFIG_M32R_NE2000 */
93 82
94 /* MFT2 : system timer */ 83 /* MFT2 : system timer */
95 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 84 set_irq_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type,
96 irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type; 85 handle_level_irq);
97 irq_desc[M32R_IRQ_MFT2].action = 0;
98 irq_desc[M32R_IRQ_MFT2].depth = 1;
99 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 86 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
100 disable_oaks32r_irq(M32R_IRQ_MFT2); 87 disable_oaks32r_irq(M32R_IRQ_MFT2);
101 88
102#ifdef CONFIG_SERIAL_M32R_SIO 89#ifdef CONFIG_SERIAL_M32R_SIO
103 /* SIO0_R : uart receive data */ 90 /* SIO0_R : uart receive data */
104 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 91 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type,
105 irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type; 92 handle_level_irq);
106 irq_desc[M32R_IRQ_SIO0_R].action = 0;
107 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
108 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 93 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
109 disable_oaks32r_irq(M32R_IRQ_SIO0_R); 94 disable_oaks32r_irq(M32R_IRQ_SIO0_R);
110 95
111 /* SIO0_S : uart send data */ 96 /* SIO0_S : uart send data */
112 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 97 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type,
113 irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type; 98 handle_level_irq);
114 irq_desc[M32R_IRQ_SIO0_S].action = 0;
115 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
116 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 99 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
117 disable_oaks32r_irq(M32R_IRQ_SIO0_S); 100 disable_oaks32r_irq(M32R_IRQ_SIO0_S);
118 101
119 /* SIO1_R : uart receive data */ 102 /* SIO1_R : uart receive data */
120 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 103 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type,
121 irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type; 104 handle_level_irq);
122 irq_desc[M32R_IRQ_SIO1_R].action = 0;
123 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
124 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 105 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
125 disable_oaks32r_irq(M32R_IRQ_SIO1_R); 106 disable_oaks32r_irq(M32R_IRQ_SIO1_R);
126 107
127 /* SIO1_S : uart send data */ 108 /* SIO1_S : uart send data */
128 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 109 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type,
129 irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type; 110 handle_level_irq);
130 irq_desc[M32R_IRQ_SIO1_S].action = 0;
131 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
132 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 111 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
133 disable_oaks32r_irq(M32R_IRQ_SIO1_S); 112 disable_oaks32r_irq(M32R_IRQ_SIO1_S);
134#endif /* CONFIG_SERIAL_M32R_SIO */ 113#endif /* CONFIG_SERIAL_M32R_SIO */
diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c
index 5f3402a2fbaf..12731547e8bf 100644
--- a/arch/m32r/platforms/opsput/setup.c
+++ b/arch/m32r/platforms/opsput/setup.c
@@ -46,39 +46,30 @@ static void enable_opsput_irq(unsigned int irq)
46 outl(data, port); 46 outl(data, port);
47} 47}
48 48
49static void mask_and_ack_opsput(unsigned int irq) 49static void mask_opsput(struct irq_data *data)
50{ 50{
51 disable_opsput_irq(irq); 51 disable_opsput_irq(data->irq);
52} 52}
53 53
54static void end_opsput_irq(unsigned int irq) 54static void unmask_opsput(struct irq_data *data)
55{ 55{
56 enable_opsput_irq(irq); 56 enable_opsput_irq(data->irq);
57} 57}
58 58
59static unsigned int startup_opsput_irq(unsigned int irq) 59static void shutdown_opsput(struct irq_data *data)
60{
61 enable_opsput_irq(irq);
62 return (0);
63}
64
65static void shutdown_opsput_irq(unsigned int irq)
66{ 60{
67 unsigned long port; 61 unsigned long port;
68 62
69 port = irq2port(irq); 63 port = irq2port(data->irq);
70 outl(M32R_ICUCR_ILEVEL7, port); 64 outl(M32R_ICUCR_ILEVEL7, port);
71} 65}
72 66
73static struct irq_chip opsput_irq_type = 67static struct irq_chip opsput_irq_type =
74{ 68{
75 .name = "OPSPUT-IRQ", 69 .name = "OPSPUT-IRQ",
76 .startup = startup_opsput_irq, 70 .irq_shutdown = shutdown_opsput,
77 .shutdown = shutdown_opsput_irq, 71 .irq_mask = mask_opsput,
78 .enable = enable_opsput_irq, 72 .irq_unmask = unmask_opsput,
79 .disable = disable_opsput_irq,
80 .ack = mask_and_ack_opsput,
81 .end = end_opsput_irq
82}; 73};
83 74
84/* 75/*
@@ -100,7 +91,6 @@ static void disable_opsput_pld_irq(unsigned int irq)
100 unsigned int pldirq; 91 unsigned int pldirq;
101 92
102 pldirq = irq2pldirq(irq); 93 pldirq = irq2pldirq(irq);
103// disable_opsput_irq(M32R_IRQ_INT1);
104 port = pldirq2port(pldirq); 94 port = pldirq2port(pldirq);
105 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; 95 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
106 outw(data, port); 96 outw(data, port);
@@ -112,50 +102,38 @@ static void enable_opsput_pld_irq(unsigned int irq)
112 unsigned int pldirq; 102 unsigned int pldirq;
113 103
114 pldirq = irq2pldirq(irq); 104 pldirq = irq2pldirq(irq);
115// enable_opsput_irq(M32R_IRQ_INT1);
116 port = pldirq2port(pldirq); 105 port = pldirq2port(pldirq);
117 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; 106 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
118 outw(data, port); 107 outw(data, port);
119} 108}
120 109
121static void mask_and_ack_opsput_pld(unsigned int irq) 110static void mask_opsput_pld(struct irq_data *data)
122{
123 disable_opsput_pld_irq(irq);
124// mask_and_ack_opsput(M32R_IRQ_INT1);
125}
126
127static void end_opsput_pld_irq(unsigned int irq)
128{ 111{
129 enable_opsput_pld_irq(irq); 112 disable_opsput_pld_irq(data->irq);
130 end_opsput_irq(M32R_IRQ_INT1);
131} 113}
132 114
133static unsigned int startup_opsput_pld_irq(unsigned int irq) 115static void unmask_opsput_pld(struct irq_data *data)
134{ 116{
135 enable_opsput_pld_irq(irq); 117 enable_opsput_pld_irq(data->irq);
136 return (0); 118 enable_opsput_irq(M32R_IRQ_INT1);
137} 119}
138 120
139static void shutdown_opsput_pld_irq(unsigned int irq) 121static void shutdown_opsput_pld(struct irq_data *data)
140{ 122{
141 unsigned long port; 123 unsigned long port;
142 unsigned int pldirq; 124 unsigned int pldirq;
143 125
144 pldirq = irq2pldirq(irq); 126 pldirq = irq2pldirq(data->irq);
145// shutdown_opsput_irq(M32R_IRQ_INT1);
146 port = pldirq2port(pldirq); 127 port = pldirq2port(pldirq);
147 outw(PLD_ICUCR_ILEVEL7, port); 128 outw(PLD_ICUCR_ILEVEL7, port);
148} 129}
149 130
150static struct irq_chip opsput_pld_irq_type = 131static struct irq_chip opsput_pld_irq_type =
151{ 132{
152 .name = "OPSPUT-PLD-IRQ", 133 .name = "OPSPUT-PLD-IRQ",
153 .startup = startup_opsput_pld_irq, 134 .irq_shutdown = shutdown_opsput_pld,
154 .shutdown = shutdown_opsput_pld_irq, 135 .irq_mask = mask_opsput_pld,
155 .enable = enable_opsput_pld_irq, 136 .irq_unmask = unmask_opsput_pld,
156 .disable = disable_opsput_pld_irq,
157 .ack = mask_and_ack_opsput_pld,
158 .end = end_opsput_pld_irq
159}; 137};
160 138
161/* 139/*
@@ -189,42 +167,33 @@ static void enable_opsput_lanpld_irq(unsigned int irq)
189 outw(data, port); 167 outw(data, port);
190} 168}
191 169
192static void mask_and_ack_opsput_lanpld(unsigned int irq) 170static void mask_opsput_lanpld(struct irq_data *data)
193{
194 disable_opsput_lanpld_irq(irq);
195}
196
197static void end_opsput_lanpld_irq(unsigned int irq)
198{ 171{
199 enable_opsput_lanpld_irq(irq); 172 disable_opsput_lanpld_irq(data->irq);
200 end_opsput_irq(M32R_IRQ_INT0);
201} 173}
202 174
203static unsigned int startup_opsput_lanpld_irq(unsigned int irq) 175static void unmask_opsput_lanpld(struct irq_data *data)
204{ 176{
205 enable_opsput_lanpld_irq(irq); 177 enable_opsput_lanpld_irq(data->irq);
206 return (0); 178 enable_opsput_irq(M32R_IRQ_INT0);
207} 179}
208 180
209static void shutdown_opsput_lanpld_irq(unsigned int irq) 181static void shutdown_opsput_lanpld(struct irq_data *data)
210{ 182{
211 unsigned long port; 183 unsigned long port;
212 unsigned int pldirq; 184 unsigned int pldirq;
213 185
214 pldirq = irq2lanpldirq(irq); 186 pldirq = irq2lanpldirq(data->irq);
215 port = lanpldirq2port(pldirq); 187 port = lanpldirq2port(pldirq);
216 outw(PLD_ICUCR_ILEVEL7, port); 188 outw(PLD_ICUCR_ILEVEL7, port);
217} 189}
218 190
219static struct irq_chip opsput_lanpld_irq_type = 191static struct irq_chip opsput_lanpld_irq_type =
220{ 192{
221 .name = "OPSPUT-PLD-LAN-IRQ", 193 .name = "OPSPUT-PLD-LAN-IRQ",
222 .startup = startup_opsput_lanpld_irq, 194 .irq_shutdown = shutdown_opsput_lanpld,
223 .shutdown = shutdown_opsput_lanpld_irq, 195 .irq_mask = mask_opsput_lanpld,
224 .enable = enable_opsput_lanpld_irq, 196 .irq_unmask = unmask_opsput_lanpld,
225 .disable = disable_opsput_lanpld_irq,
226 .ack = mask_and_ack_opsput_lanpld,
227 .end = end_opsput_lanpld_irq
228}; 197};
229 198
230/* 199/*
@@ -258,143 +227,109 @@ static void enable_opsput_lcdpld_irq(unsigned int irq)
258 outw(data, port); 227 outw(data, port);
259} 228}
260 229
261static void mask_and_ack_opsput_lcdpld(unsigned int irq) 230static void mask_opsput_lcdpld(struct irq_data *data)
262{
263 disable_opsput_lcdpld_irq(irq);
264}
265
266static void end_opsput_lcdpld_irq(unsigned int irq)
267{ 231{
268 enable_opsput_lcdpld_irq(irq); 232 disable_opsput_lcdpld_irq(data->irq);
269 end_opsput_irq(M32R_IRQ_INT2);
270} 233}
271 234
272static unsigned int startup_opsput_lcdpld_irq(unsigned int irq) 235static void unmask_opsput_lcdpld(struct irq_data *data)
273{ 236{
274 enable_opsput_lcdpld_irq(irq); 237 enable_opsput_lcdpld_irq(data->irq);
275 return (0); 238 enable_opsput_irq(M32R_IRQ_INT2);
276} 239}
277 240
278static void shutdown_opsput_lcdpld_irq(unsigned int irq) 241static void shutdown_opsput_lcdpld(struct irq_data *data)
279{ 242{
280 unsigned long port; 243 unsigned long port;
281 unsigned int pldirq; 244 unsigned int pldirq;
282 245
283 pldirq = irq2lcdpldirq(irq); 246 pldirq = irq2lcdpldirq(data->irq);
284 port = lcdpldirq2port(pldirq); 247 port = lcdpldirq2port(pldirq);
285 outw(PLD_ICUCR_ILEVEL7, port); 248 outw(PLD_ICUCR_ILEVEL7, port);
286} 249}
287 250
288static struct irq_chip opsput_lcdpld_irq_type = 251static struct irq_chip opsput_lcdpld_irq_type = {
289{ 252 .name = "OPSPUT-PLD-LCD-IRQ",
290 "OPSPUT-PLD-LCD-IRQ", 253 .irq_shutdown = shutdown_opsput_lcdpld,
291 startup_opsput_lcdpld_irq, 254 .irq_mask = mask_opsput_lcdpld,
292 shutdown_opsput_lcdpld_irq, 255 .irq_unmask = unmask_opsput_lcdpld,
293 enable_opsput_lcdpld_irq,
294 disable_opsput_lcdpld_irq,
295 mask_and_ack_opsput_lcdpld,
296 end_opsput_lcdpld_irq
297}; 256};
298 257
299void __init init_IRQ(void) 258void __init init_IRQ(void)
300{ 259{
301#if defined(CONFIG_SMC91X) 260#if defined(CONFIG_SMC91X)
302 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ 261 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
303 irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED; 262 set_irq_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type,
304 irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type; 263 handle_level_irq);
305 irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
306 irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
307 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ 264 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
308 disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); 265 disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
309#endif /* CONFIG_SMC91X */ 266#endif /* CONFIG_SMC91X */
310 267
311 /* MFT2 : system timer */ 268 /* MFT2 : system timer */
312 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 269 set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type,
313 irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type; 270 handle_level_irq);
314 irq_desc[M32R_IRQ_MFT2].action = 0;
315 irq_desc[M32R_IRQ_MFT2].depth = 1;
316 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 271 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
317 disable_opsput_irq(M32R_IRQ_MFT2); 272 disable_opsput_irq(M32R_IRQ_MFT2);
318 273
319 /* SIO0 : receive */ 274 /* SIO0 : receive */
320 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 275 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type,
321 irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type; 276 handle_level_irq);
322 irq_desc[M32R_IRQ_SIO0_R].action = 0;
323 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
324 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 277 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
325 disable_opsput_irq(M32R_IRQ_SIO0_R); 278 disable_opsput_irq(M32R_IRQ_SIO0_R);
326 279
327 /* SIO0 : send */ 280 /* SIO0 : send */
328 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 281 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type,
329 irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type; 282 handle_level_irq);
330 irq_desc[M32R_IRQ_SIO0_S].action = 0;
331 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
332 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 283 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
333 disable_opsput_irq(M32R_IRQ_SIO0_S); 284 disable_opsput_irq(M32R_IRQ_SIO0_S);
334 285
335 /* SIO1 : receive */ 286 /* SIO1 : receive */
336 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 287 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type,
337 irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type; 288 handle_level_irq);
338 irq_desc[M32R_IRQ_SIO1_R].action = 0;
339 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
340 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 289 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
341 disable_opsput_irq(M32R_IRQ_SIO1_R); 290 disable_opsput_irq(M32R_IRQ_SIO1_R);
342 291
343 /* SIO1 : send */ 292 /* SIO1 : send */
344 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 293 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type,
345 irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type; 294 handle_level_irq);
346 irq_desc[M32R_IRQ_SIO1_S].action = 0;
347 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
348 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 295 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
349 disable_opsput_irq(M32R_IRQ_SIO1_S); 296 disable_opsput_irq(M32R_IRQ_SIO1_S);
350 297
351 /* DMA1 : */ 298 /* DMA1 : */
352 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; 299 set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type,
353 irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type; 300 handle_level_irq);
354 irq_desc[M32R_IRQ_DMA1].action = 0;
355 irq_desc[M32R_IRQ_DMA1].depth = 1;
356 icu_data[M32R_IRQ_DMA1].icucr = 0; 301 icu_data[M32R_IRQ_DMA1].icucr = 0;
357 disable_opsput_irq(M32R_IRQ_DMA1); 302 disable_opsput_irq(M32R_IRQ_DMA1);
358 303
359#ifdef CONFIG_SERIAL_M32R_PLDSIO 304#ifdef CONFIG_SERIAL_M32R_PLDSIO
360 /* INT#1: SIO0 Receive on PLD */ 305 /* INT#1: SIO0 Receive on PLD */
361 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; 306 set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type,
362 irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type; 307 handle_level_irq);
363 irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
364 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
365 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 308 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
366 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); 309 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
367 310
368 /* INT#1: SIO0 Send on PLD */ 311 /* INT#1: SIO0 Send on PLD */
369 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; 312 set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type,
370 irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type; 313 handle_level_irq);
371 irq_desc[PLD_IRQ_SIO0_SND].action = 0;
372 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
373 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 314 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
374 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); 315 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
375#endif /* CONFIG_SERIAL_M32R_PLDSIO */ 316#endif /* CONFIG_SERIAL_M32R_PLDSIO */
376 317
377 /* INT#1: CFC IREQ on PLD */ 318 /* INT#1: CFC IREQ on PLD */
378 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 319 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type,
379 irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type; 320 handle_level_irq);
380 irq_desc[PLD_IRQ_CFIREQ].action = 0;
381 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
382 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 321 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
383 disable_opsput_pld_irq(PLD_IRQ_CFIREQ); 322 disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
384 323
385 /* INT#1: CFC Insert on PLD */ 324 /* INT#1: CFC Insert on PLD */
386 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 325 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type,
387 irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type; 326 handle_level_irq);
388 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
389 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
390 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 327 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
391 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); 328 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
392 329
393 /* INT#1: CFC Eject on PLD */ 330 /* INT#1: CFC Eject on PLD */
394 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; 331 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type,
395 irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type; 332 handle_level_irq);
396 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
397 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
398 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 333 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
399 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); 334 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
400 335
@@ -413,14 +348,11 @@ void __init init_IRQ(void)
413 enable_opsput_irq(M32R_IRQ_INT1); 348 enable_opsput_irq(M32R_IRQ_INT1);
414 349
415#if defined(CONFIG_USB) 350#if defined(CONFIG_USB)
416 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ 351 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
417 352 set_irq_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1,
418 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; 353 &opsput_lcdpld_irq_type, handle_level_irq);
419 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type; 354 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
420 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0; 355 disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
421 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
422 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
423 disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
424#endif 356#endif
425 /* 357 /*
426 * INT2# is used for BAT, USB, AUDIO 358 * INT2# is used for BAT, USB, AUDIO
@@ -433,10 +365,8 @@ void __init init_IRQ(void)
433 /* 365 /*
434 * INT3# is used for AR 366 * INT3# is used for AR
435 */ 367 */
436 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 368 set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type,
437 irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type; 369 handle_level_irq);
438 irq_desc[M32R_IRQ_INT3].action = 0;
439 irq_desc[M32R_IRQ_INT3].depth = 1;
440 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 370 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
441 disable_opsput_irq(M32R_IRQ_INT3); 371 disable_opsput_irq(M32R_IRQ_INT3);
442#endif /* CONFIG_VIDEO_M32R_AR */ 372#endif /* CONFIG_VIDEO_M32R_AR */
diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c
index 1beac7a51ed4..f3cff26d6e74 100644
--- a/arch/m32r/platforms/usrv/setup.c
+++ b/arch/m32r/platforms/usrv/setup.c
@@ -37,39 +37,30 @@ static void enable_mappi_irq(unsigned int irq)
37 outl(data, port); 37 outl(data, port);
38} 38}
39 39
40static void mask_and_ack_mappi(unsigned int irq) 40static void mask_mappi(struct irq_data *data)
41{ 41{
42 disable_mappi_irq(irq); 42 disable_mappi_irq(data->irq);
43} 43}
44 44
45static void end_mappi_irq(unsigned int irq) 45static void unmask_mappi(struct irq_data *data)
46{ 46{
47 enable_mappi_irq(irq); 47 enable_mappi_irq(data->irq);
48} 48}
49 49
50static unsigned int startup_mappi_irq(unsigned int irq) 50static void shutdown_mappi(struct irq_data *data)
51{
52 enable_mappi_irq(irq);
53 return 0;
54}
55
56static void shutdown_mappi_irq(unsigned int irq)
57{ 51{
58 unsigned long port; 52 unsigned long port;
59 53
60 port = irq2port(irq); 54 port = irq2port(data->irq);
61 outl(M32R_ICUCR_ILEVEL7, port); 55 outl(M32R_ICUCR_ILEVEL7, port);
62} 56}
63 57
64static struct irq_chip mappi_irq_type = 58static struct irq_chip mappi_irq_type =
65{ 59{
66 .name = "M32700-IRQ", 60 .name = "M32700-IRQ",
67 .startup = startup_mappi_irq, 61 .irq_shutdown = shutdown_mappi,
68 .shutdown = shutdown_mappi_irq, 62 .irq_mask = mask_mappi,
69 .enable = enable_mappi_irq, 63 .irq_unmask = unmask_mappi,
70 .disable = disable_mappi_irq,
71 .ack = mask_and_ack_mappi,
72 .end = end_mappi_irq
73}; 64};
74 65
75/* 66/*
@@ -107,42 +98,33 @@ static void enable_m32700ut_pld_irq(unsigned int irq)
107 outw(data, port); 98 outw(data, port);
108} 99}
109 100
110static void mask_and_ack_m32700ut_pld(unsigned int irq) 101static void mask_m32700ut_pld(struct irq_data *data)
111{ 102{
112 disable_m32700ut_pld_irq(irq); 103 disable_m32700ut_pld_irq(data->irq);
113} 104}
114 105
115static void end_m32700ut_pld_irq(unsigned int irq) 106static void unmask_m32700ut_pld(struct irq_data *data)
116{ 107{
117 enable_m32700ut_pld_irq(irq); 108 enable_m32700ut_pld_irq(data->irq);
118 end_mappi_irq(M32R_IRQ_INT1); 109 enable_mappi_irq(M32R_IRQ_INT1);
119}
120
121static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
122{
123 enable_m32700ut_pld_irq(irq);
124 return 0;
125} 110}
126 111
127static void shutdown_m32700ut_pld_irq(unsigned int irq) 112static void shutdown_m32700ut_pld(struct irq_data *data)
128{ 113{
129 unsigned long port; 114 unsigned long port;
130 unsigned int pldirq; 115 unsigned int pldirq;
131 116
132 pldirq = irq2pldirq(irq); 117 pldirq = irq2pldirq(data->irq);
133 port = pldirq2port(pldirq); 118 port = pldirq2port(pldirq);
134 outw(PLD_ICUCR_ILEVEL7, port); 119 outw(PLD_ICUCR_ILEVEL7, port);
135} 120}
136 121
137static struct irq_chip m32700ut_pld_irq_type = 122static struct irq_chip m32700ut_pld_irq_type =
138{ 123{
139 .name = "USRV-PLD-IRQ", 124 .name = "USRV-PLD-IRQ",
140 .startup = startup_m32700ut_pld_irq, 125 .irq_shutdown = shutdown_m32700ut_pld,
141 .shutdown = shutdown_m32700ut_pld_irq, 126 .irq_mask = mask_m32700ut_pld,
142 .enable = enable_m32700ut_pld_irq, 127 .irq_unmask = unmask_m32700ut_pld,
143 .disable = disable_m32700ut_pld_irq,
144 .ack = mask_and_ack_m32700ut_pld,
145 .end = end_m32700ut_pld_irq
146}; 128};
147 129
148void __init init_IRQ(void) 130void __init init_IRQ(void)
@@ -156,53 +138,42 @@ void __init init_IRQ(void)
156 once++; 138 once++;
157 139
158 /* MFT2 : system timer */ 140 /* MFT2 : system timer */
159 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 141 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
160 irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; 142 handle_level_irq);
161 irq_desc[M32R_IRQ_MFT2].action = 0;
162 irq_desc[M32R_IRQ_MFT2].depth = 1;
163 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 143 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
164 disable_mappi_irq(M32R_IRQ_MFT2); 144 disable_mappi_irq(M32R_IRQ_MFT2);
165 145
166#if defined(CONFIG_SERIAL_M32R_SIO) 146#if defined(CONFIG_SERIAL_M32R_SIO)
167 /* SIO0_R : uart receive data */ 147 /* SIO0_R : uart receive data */
168 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 148 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
169 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; 149 handle_level_irq);
170 irq_desc[M32R_IRQ_SIO0_R].action = 0;
171 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
172 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 150 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
173 disable_mappi_irq(M32R_IRQ_SIO0_R); 151 disable_mappi_irq(M32R_IRQ_SIO0_R);
174 152
175 /* SIO0_S : uart send data */ 153 /* SIO0_S : uart send data */
176 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 154 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
177 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; 155 handle_level_irq);
178 irq_desc[M32R_IRQ_SIO0_S].action = 0;
179 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
180 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 156 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
181 disable_mappi_irq(M32R_IRQ_SIO0_S); 157 disable_mappi_irq(M32R_IRQ_SIO0_S);
182 158
183 /* SIO1_R : uart receive data */ 159 /* SIO1_R : uart receive data */
184 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 160 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
185 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; 161 handle_level_irq);
186 irq_desc[M32R_IRQ_SIO1_R].action = 0;
187 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
188 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 162 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
189 disable_mappi_irq(M32R_IRQ_SIO1_R); 163 disable_mappi_irq(M32R_IRQ_SIO1_R);
190 164
191 /* SIO1_S : uart send data */ 165 /* SIO1_S : uart send data */
192 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 166 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
193 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; 167 handle_level_irq);
194 irq_desc[M32R_IRQ_SIO1_S].action = 0;
195 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
196 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 168 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
197 disable_mappi_irq(M32R_IRQ_SIO1_S); 169 disable_mappi_irq(M32R_IRQ_SIO1_S);
198#endif /* CONFIG_SERIAL_M32R_SIO */ 170#endif /* CONFIG_SERIAL_M32R_SIO */
199 171
200 /* INT#67-#71: CFC#0 IREQ on PLD */ 172 /* INT#67-#71: CFC#0 IREQ on PLD */
201 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { 173 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) {
202 irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED; 174 set_irq_chip_and_handler(PLD_IRQ_CF0 + i,
203 irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type; 175 &m32700ut_pld_irq_type,
204 irq_desc[PLD_IRQ_CF0 + i].action = 0; 176 handle_level_irq);
205 irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */
206 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr 177 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
207 = PLD_ICUCR_ISMOD01; /* 'L' level sense */ 178 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
208 disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i); 179 disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
@@ -210,19 +181,15 @@ void __init init_IRQ(void)
210 181
211#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 182#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
212 /* INT#76: 16552D#0 IREQ on PLD */ 183 /* INT#76: 16552D#0 IREQ on PLD */
213 irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED; 184 set_irq_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type,
214 irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type; 185 handle_level_irq);
215 irq_desc[PLD_IRQ_UART0].action = 0;
216 irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */
217 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr 186 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
218 = PLD_ICUCR_ISMOD03; /* 'H' level sense */ 187 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
219 disable_m32700ut_pld_irq(PLD_IRQ_UART0); 188 disable_m32700ut_pld_irq(PLD_IRQ_UART0);
220 189
221 /* INT#77: 16552D#1 IREQ on PLD */ 190 /* INT#77: 16552D#1 IREQ on PLD */
222 irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED; 191 set_irq_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type,
223 irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type; 192 handle_level_irq);
224 irq_desc[PLD_IRQ_UART1].action = 0;
225 irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */
226 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr 193 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
227 = PLD_ICUCR_ISMOD03; /* 'H' level sense */ 194 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
228 disable_m32700ut_pld_irq(PLD_IRQ_UART1); 195 disable_m32700ut_pld_irq(PLD_IRQ_UART1);
@@ -230,10 +197,8 @@ void __init init_IRQ(void)
230 197
231#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) 198#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
232 /* INT#80: AK4524 IREQ on PLD */ 199 /* INT#80: AK4524 IREQ on PLD */
233 irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED; 200 set_irq_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type,
234 irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type; 201 handle_level_irq);
235 irq_desc[PLD_IRQ_SNDINT].action = 0;
236 irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */
237 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr 202 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
238 = PLD_ICUCR_ISMOD01; /* 'L' level sense */ 203 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
239 disable_m32700ut_pld_irq(PLD_IRQ_SNDINT); 204 disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-01 16:56:05 -0400