diff options
Diffstat (limited to 'arch/m32r/platforms/oaks32r/setup.c')
-rw-r--r-- | arch/m32r/platforms/oaks32r/setup.c | 30 |
1 files changed, 6 insertions, 24 deletions
diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c index d11d93bf74f5..43bf5a0c9515 100644 --- a/arch/m32r/platforms/oaks32r/setup.c +++ b/arch/m32r/platforms/oaks32r/setup.c | |||
@@ -83,52 +83,34 @@ void __init init_IRQ(void) | |||
83 | 83 | ||
84 | #ifdef CONFIG_NE2000 | 84 | #ifdef CONFIG_NE2000 |
85 | /* INT3 : LAN controller (RTL8019AS) */ | 85 | /* INT3 : LAN controller (RTL8019AS) */ |
86 | irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; | 86 | set_irq_chip(M32R_IRQ_INT3, &oaks32r_irq_type); |
87 | irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type; | ||
88 | irq_desc[M32R_IRQ_INT3].action = 0; | ||
89 | irq_desc[M32R_IRQ_INT3].depth = 1; | ||
90 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 87 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
91 | disable_oaks32r_irq(M32R_IRQ_INT3); | 88 | disable_oaks32r_irq(M32R_IRQ_INT3); |
92 | #endif /* CONFIG_M32R_NE2000 */ | 89 | #endif /* CONFIG_M32R_NE2000 */ |
93 | 90 | ||
94 | /* MFT2 : system timer */ | 91 | /* MFT2 : system timer */ |
95 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 92 | set_irq_chip(M32R_IRQ_MFT2, &oaks32r_irq_type); |
96 | irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type; | ||
97 | irq_desc[M32R_IRQ_MFT2].action = 0; | ||
98 | irq_desc[M32R_IRQ_MFT2].depth = 1; | ||
99 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 93 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
100 | disable_oaks32r_irq(M32R_IRQ_MFT2); | 94 | disable_oaks32r_irq(M32R_IRQ_MFT2); |
101 | 95 | ||
102 | #ifdef CONFIG_SERIAL_M32R_SIO | 96 | #ifdef CONFIG_SERIAL_M32R_SIO |
103 | /* SIO0_R : uart receive data */ | 97 | /* SIO0_R : uart receive data */ |
104 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 98 | set_irq_chip(M32R_IRQ_SIO0_R, &oaks32r_irq_type); |
105 | irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type; | ||
106 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | ||
107 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | ||
108 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 99 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
109 | disable_oaks32r_irq(M32R_IRQ_SIO0_R); | 100 | disable_oaks32r_irq(M32R_IRQ_SIO0_R); |
110 | 101 | ||
111 | /* SIO0_S : uart send data */ | 102 | /* SIO0_S : uart send data */ |
112 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 103 | set_irq_chip(M32R_IRQ_SIO0_S, &oaks32r_irq_type); |
113 | irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type; | ||
114 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | ||
115 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | ||
116 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 104 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
117 | disable_oaks32r_irq(M32R_IRQ_SIO0_S); | 105 | disable_oaks32r_irq(M32R_IRQ_SIO0_S); |
118 | 106 | ||
119 | /* SIO1_R : uart receive data */ | 107 | /* SIO1_R : uart receive data */ |
120 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 108 | set_irq_chip(M32R_IRQ_SIO1_R, &oaks32r_irq_type); |
121 | irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type; | ||
122 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | ||
123 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | ||
124 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 109 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
125 | disable_oaks32r_irq(M32R_IRQ_SIO1_R); | 110 | disable_oaks32r_irq(M32R_IRQ_SIO1_R); |
126 | 111 | ||
127 | /* SIO1_S : uart send data */ | 112 | /* SIO1_S : uart send data */ |
128 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 113 | set_irq_chip(M32R_IRQ_SIO1_S, &oaks32r_irq_type); |
129 | irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type; | ||
130 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | ||
131 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | ||
132 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 114 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
133 | disable_oaks32r_irq(M32R_IRQ_SIO1_S); | 115 | disable_oaks32r_irq(M32R_IRQ_SIO1_S); |
134 | #endif /* CONFIG_SERIAL_M32R_SIO */ | 116 | #endif /* CONFIG_SERIAL_M32R_SIO */ |