diff options
Diffstat (limited to 'arch/m32r/platforms/mappi/setup.c')
| -rw-r--r-- | arch/m32r/platforms/mappi/setup.c | 78 |
1 files changed, 26 insertions, 52 deletions
diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c index ea00c84d6b1b..cdd8c4574027 100644 --- a/arch/m32r/platforms/mappi/setup.c +++ b/arch/m32r/platforms/mappi/setup.c | |||
| @@ -38,40 +38,30 @@ static void enable_mappi_irq(unsigned int irq) | |||
| 38 | outl(data, port); | 38 | outl(data, port); |
| 39 | } | 39 | } |
| 40 | 40 | ||
| 41 | static void mask_and_ack_mappi(unsigned int irq) | 41 | static void mask_mappi(struct irq_data *data) |
| 42 | { | 42 | { |
| 43 | disable_mappi_irq(irq); | 43 | disable_mappi_irq(data->irq); |
| 44 | } | 44 | } |
| 45 | 45 | ||
| 46 | static void end_mappi_irq(unsigned int irq) | 46 | static void unmask_mappi(struct irq_data *data) |
| 47 | { | 47 | { |
| 48 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | 48 | enable_mappi_irq(data->irq); |
| 49 | enable_mappi_irq(irq); | ||
| 50 | } | 49 | } |
| 51 | 50 | ||
| 52 | static unsigned int startup_mappi_irq(unsigned int irq) | 51 | static void shutdown_mappi(struct irq_data *data) |
| 53 | { | ||
| 54 | enable_mappi_irq(irq); | ||
| 55 | return (0); | ||
| 56 | } | ||
| 57 | |||
| 58 | static void shutdown_mappi_irq(unsigned int irq) | ||
| 59 | { | 52 | { |
| 60 | unsigned long port; | 53 | unsigned long port; |
| 61 | 54 | ||
| 62 | port = irq2port(irq); | 55 | port = irq2port(data->irq); |
| 63 | outl(M32R_ICUCR_ILEVEL7, port); | 56 | outl(M32R_ICUCR_ILEVEL7, port); |
| 64 | } | 57 | } |
| 65 | 58 | ||
| 66 | static struct irq_chip mappi_irq_type = | 59 | static struct irq_chip mappi_irq_type = |
| 67 | { | 60 | { |
| 68 | .name = "MAPPI-IRQ", | 61 | .name = "MAPPI-IRQ", |
| 69 | .startup = startup_mappi_irq, | 62 | .irq_shutdown = shutdown_mappi, |
| 70 | .shutdown = shutdown_mappi_irq, | 63 | .irq_mask = mask_mappi, |
| 71 | .enable = enable_mappi_irq, | 64 | .irq_unmask = unmask_mappi, |
| 72 | .disable = disable_mappi_irq, | ||
| 73 | .ack = mask_and_ack_mappi, | ||
| 74 | .end = end_mappi_irq | ||
| 75 | }; | 65 | }; |
| 76 | 66 | ||
| 77 | void __init init_IRQ(void) | 67 | void __init init_IRQ(void) |
| @@ -85,70 +75,54 @@ void __init init_IRQ(void) | |||
| 85 | 75 | ||
| 86 | #ifdef CONFIG_NE2000 | 76 | #ifdef CONFIG_NE2000 |
| 87 | /* INT0 : LAN controller (RTL8019AS) */ | 77 | /* INT0 : LAN controller (RTL8019AS) */ |
| 88 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; | 78 | set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, |
| 89 | irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type; | 79 | handle_level_irq); |
| 90 | irq_desc[M32R_IRQ_INT0].action = NULL; | ||
| 91 | irq_desc[M32R_IRQ_INT0].depth = 1; | ||
| 92 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; | 80 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; |
| 93 | disable_mappi_irq(M32R_IRQ_INT0); | 81 | disable_mappi_irq(M32R_IRQ_INT0); |
| 94 | #endif /* CONFIG_M32R_NE2000 */ | 82 | #endif /* CONFIG_M32R_NE2000 */ |
| 95 | 83 | ||
| 96 | /* MFT2 : system timer */ | 84 | /* MFT2 : system timer */ |
| 97 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 85 | set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, |
| 98 | irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; | 86 | handle_level_irq); |
| 99 | irq_desc[M32R_IRQ_MFT2].action = NULL; | ||
| 100 | irq_desc[M32R_IRQ_MFT2].depth = 1; | ||
| 101 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 87 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
| 102 | disable_mappi_irq(M32R_IRQ_MFT2); | 88 | disable_mappi_irq(M32R_IRQ_MFT2); |
| 103 | 89 | ||
| 104 | #ifdef CONFIG_SERIAL_M32R_SIO | 90 | #ifdef CONFIG_SERIAL_M32R_SIO |
| 105 | /* SIO0_R : uart receive data */ | 91 | /* SIO0_R : uart receive data */ |
| 106 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 92 | set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, |
| 107 | irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; | 93 | handle_level_irq); |
| 108 | irq_desc[M32R_IRQ_SIO0_R].action = NULL; | ||
| 109 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | ||
| 110 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 94 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
| 111 | disable_mappi_irq(M32R_IRQ_SIO0_R); | 95 | disable_mappi_irq(M32R_IRQ_SIO0_R); |
| 112 | 96 | ||
| 113 | /* SIO0_S : uart send data */ | 97 | /* SIO0_S : uart send data */ |
| 114 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 98 | set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, |
| 115 | irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; | 99 | handle_level_irq); |
| 116 | irq_desc[M32R_IRQ_SIO0_S].action = NULL; | ||
| 117 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | ||
| 118 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 100 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
| 119 | disable_mappi_irq(M32R_IRQ_SIO0_S); | 101 | disable_mappi_irq(M32R_IRQ_SIO0_S); |
| 120 | 102 | ||
| 121 | /* SIO1_R : uart receive data */ | 103 | /* SIO1_R : uart receive data */ |
| 122 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 104 | set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, |
| 123 | irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; | 105 | handle_level_irq); |
| 124 | irq_desc[M32R_IRQ_SIO1_R].action = NULL; | ||
| 125 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | ||
| 126 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 106 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
| 127 | disable_mappi_irq(M32R_IRQ_SIO1_R); | 107 | disable_mappi_irq(M32R_IRQ_SIO1_R); |
| 128 | 108 | ||
| 129 | /* SIO1_S : uart send data */ | 109 | /* SIO1_S : uart send data */ |
| 130 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 110 | set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, |
| 131 | irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; | 111 | handle_level_irq); |
| 132 | irq_desc[M32R_IRQ_SIO1_S].action = NULL; | ||
| 133 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | ||
| 134 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 112 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
| 135 | disable_mappi_irq(M32R_IRQ_SIO1_S); | 113 | disable_mappi_irq(M32R_IRQ_SIO1_S); |
| 136 | #endif /* CONFIG_SERIAL_M32R_SIO */ | 114 | #endif /* CONFIG_SERIAL_M32R_SIO */ |
| 137 | 115 | ||
| 138 | #if defined(CONFIG_M32R_PCC) | 116 | #if defined(CONFIG_M32R_PCC) |
| 139 | /* INT1 : pccard0 interrupt */ | 117 | /* INT1 : pccard0 interrupt */ |
| 140 | irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; | 118 | set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, |
| 141 | irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type; | 119 | handle_level_irq); |
| 142 | irq_desc[M32R_IRQ_INT1].action = NULL; | ||
| 143 | irq_desc[M32R_IRQ_INT1].depth = 1; | ||
| 144 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; | 120 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; |
| 145 | disable_mappi_irq(M32R_IRQ_INT1); | 121 | disable_mappi_irq(M32R_IRQ_INT1); |
| 146 | 122 | ||
| 147 | /* INT2 : pccard1 interrupt */ | 123 | /* INT2 : pccard1 interrupt */ |
| 148 | irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED; | 124 | set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, |
| 149 | irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type; | 125 | handle_level_irq); |
| 150 | irq_desc[M32R_IRQ_INT2].action = NULL; | ||
| 151 | irq_desc[M32R_IRQ_INT2].depth = 1; | ||
| 152 | icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; | 126 | icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; |
| 153 | disable_mappi_irq(M32R_IRQ_INT2); | 127 | disable_mappi_irq(M32R_IRQ_INT2); |
| 154 | #endif /* CONFIG_M32RPCC */ | 128 | #endif /* CONFIG_M32RPCC */ |
