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-rw-r--r--arch/m32r/mm/cache.c36
1 files changed, 30 insertions, 6 deletions
diff --git a/arch/m32r/mm/cache.c b/arch/m32r/mm/cache.c
index 31b0789c1992..9f54dd937013 100644
--- a/arch/m32r/mm/cache.c
+++ b/arch/m32r/mm/cache.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/m32r/mm/cache.c 2 * linux/arch/m32r/mm/cache.c
3 * 3 *
4 * Copyright (C) 2002 Hirokazu Takata 4 * Copyright (C) 2002-2005 Hirokazu Takata, Hayato Fujiwara
5 */ 5 */
6 6
7#include <linux/config.h> 7#include <linux/config.h>
@@ -9,7 +9,8 @@
9 9
10#undef MCCR 10#undef MCCR
11 11
12#if defined(CONFIG_CHIP_XNUX2) || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_OPSP) 12#if defined(CONFIG_CHIP_XNUX2) || defined(CONFIG_CHIP_M32700) \
13 || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_OPSP)
13/* Cache Control Register */ 14/* Cache Control Register */
14#define MCCR ((volatile unsigned long*)0xfffffffc) 15#define MCCR ((volatile unsigned long*)0xfffffffc)
15#define MCCR_CC (1UL << 7) /* Cache mode modify bit */ 16#define MCCR_CC (1UL << 7) /* Cache mode modify bit */
@@ -26,7 +27,17 @@
26#define MCCR ((volatile unsigned char*)0xfffffffe) 27#define MCCR ((volatile unsigned char*)0xfffffffe)
27#define MCCR_IIV (1UL << 0) /* I-cache invalidate */ 28#define MCCR_IIV (1UL << 0) /* I-cache invalidate */
28#define MCCR_ICACHE_INV MCCR_IIV 29#define MCCR_ICACHE_INV MCCR_IIV
29#endif /* CONFIG_CHIP_XNUX2 || CONFIG_CHIP_M32700 */ 30#elif defined(CONFIG_CHIP_M32104)
31#define MCCR ((volatile unsigned short*)0xfffffffe)
32#define MCCR_IIV (1UL << 8) /* I-cache invalidate */
33#define MCCR_DIV (1UL << 9) /* D-cache invalidate */
34#define MCCR_DCB (1UL << 10) /* D-cache copy back */
35#define MCCR_ICM (1UL << 0) /* I-cache mode [0:off,1:on] */
36#define MCCR_DCM (1UL << 1) /* D-cache mode [0:off,1:on] */
37#define MCCR_ICACHE_INV MCCR_IIV
38#define MCCR_DCACHE_CB MCCR_DCB
39#define MCCR_DCACHE_CBINV (MCCR_DIV|MCCR_DCB)
40#endif
30 41
31#ifndef MCCR 42#ifndef MCCR
32#error Unknown cache type. 43#error Unknown cache type.
@@ -37,29 +48,42 @@
37void _flush_cache_all(void) 48void _flush_cache_all(void)
38{ 49{
39#if defined(CONFIG_CHIP_M32102) 50#if defined(CONFIG_CHIP_M32102)
51 unsigned char mccr;
40 *MCCR = MCCR_ICACHE_INV; 52 *MCCR = MCCR_ICACHE_INV;
53#elif defined(CONFIG_CHIP_M32104)
54 unsigned short mccr;
55
56 /* Copyback and invalidate D-cache */
57 /* Invalidate I-cache */
58 *MCCR |= (MCCR_ICACHE_INV | MCCR_DCACHE_CBINV);
41#else 59#else
42 unsigned long mccr; 60 unsigned long mccr;
43 61
44 /* Copyback and invalidate D-cache */ 62 /* Copyback and invalidate D-cache */
45 /* Invalidate I-cache */ 63 /* Invalidate I-cache */
46 *MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CBINV; 64 *MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CBINV;
47 while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */
48#endif 65#endif
66 while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */
49} 67}
50 68
51/* Copy back D-cache and invalidate I-cache all */ 69/* Copy back D-cache and invalidate I-cache all */
52void _flush_cache_copyback_all(void) 70void _flush_cache_copyback_all(void)
53{ 71{
54#if defined(CONFIG_CHIP_M32102) 72#if defined(CONFIG_CHIP_M32102)
73 unsigned char mccr;
55 *MCCR = MCCR_ICACHE_INV; 74 *MCCR = MCCR_ICACHE_INV;
75#elif defined(CONFIG_CHIP_M32104)
76 unsigned short mccr;
77
78 /* Copyback and invalidate D-cache */
79 /* Invalidate I-cache */
80 *MCCR |= (MCCR_ICACHE_INV | MCCR_DCACHE_CB);
56#else 81#else
57 unsigned long mccr; 82 unsigned long mccr;
58 83
59 /* Copyback D-cache */ 84 /* Copyback D-cache */
60 /* Invalidate I-cache */ 85 /* Invalidate I-cache */
61 *MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CB; 86 *MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CB;
62 while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */
63
64#endif 87#endif
88 while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */
65} 89}