diff options
Diffstat (limited to 'arch/m32r/kernel')
| -rw-r--r-- | arch/m32r/kernel/smp.c | 48 |
1 files changed, 12 insertions, 36 deletions
diff --git a/arch/m32r/kernel/smp.c b/arch/m32r/kernel/smp.c index 48b187f2d2b3..a4576ac7e870 100644 --- a/arch/m32r/kernel/smp.c +++ b/arch/m32r/kernel/smp.c | |||
| @@ -892,7 +892,6 @@ unsigned long send_IPI_mask_phys(cpumask_t physid_mask, int ipi_num, | |||
| 892 | int try) | 892 | int try) |
| 893 | { | 893 | { |
| 894 | spinlock_t *ipilock; | 894 | spinlock_t *ipilock; |
| 895 | unsigned long flags = 0; | ||
| 896 | volatile unsigned long *ipicr_addr; | 895 | volatile unsigned long *ipicr_addr; |
| 897 | unsigned long ipicr_val; | 896 | unsigned long ipicr_val; |
| 898 | unsigned long my_physid_mask; | 897 | unsigned long my_physid_mask; |
| @@ -916,50 +915,27 @@ unsigned long send_IPI_mask_phys(cpumask_t physid_mask, int ipi_num, | |||
| 916 | * write IPICRi (send IPIi) | 915 | * write IPICRi (send IPIi) |
| 917 | * unlock ipi_lock[i] | 916 | * unlock ipi_lock[i] |
| 918 | */ | 917 | */ |
| 918 | spin_lock(ipilock); | ||
| 919 | __asm__ __volatile__ ( | 919 | __asm__ __volatile__ ( |
| 920 | ";; LOCK ipi_lock[i] \n\t" | 920 | ";; CHECK IPICRi == 0 \n\t" |
| 921 | ".fillinsn \n" | 921 | ".fillinsn \n" |
| 922 | "1: \n\t" | 922 | "1: \n\t" |
| 923 | "mvfc %1, psw \n\t" | 923 | "ld %0, @%1 \n\t" |
| 924 | "clrpsw #0x40 -> nop \n\t" | 924 | "and %0, %4 \n\t" |
| 925 | DCACHE_CLEAR("r4", "r5", "%2") | 925 | "beqz %0, 2f \n\t" |
| 926 | "lock r4, @%2 \n\t" | 926 | "bnez %3, 3f \n\t" |
| 927 | "addi r4, #-1 \n\t" | ||
| 928 | "unlock r4, @%2 \n\t" | ||
| 929 | "mvtc %1, psw \n\t" | ||
| 930 | "bnez r4, 2f \n\t" | ||
| 931 | LOCK_SECTION_START(".balign 4 \n\t") | ||
| 932 | ".fillinsn \n" | ||
| 933 | "2: \n\t" | ||
| 934 | "ld r4, @%2 \n\t" | ||
| 935 | "blez r4, 2b \n\t" | ||
| 936 | "bra 1b \n\t" | 927 | "bra 1b \n\t" |
| 937 | LOCK_SECTION_END | ||
| 938 | ";; CHECK IPICRi == 0 \n\t" | ||
| 939 | ".fillinsn \n" | ||
| 940 | "3: \n\t" | ||
| 941 | "ld %0, @%3 \n\t" | ||
| 942 | "and %0, %6 \n\t" | ||
| 943 | "beqz %0, 4f \n\t" | ||
| 944 | "bnez %5, 5f \n\t" | ||
| 945 | "bra 3b \n\t" | ||
| 946 | ";; WRITE IPICRi (send IPIi) \n\t" | 928 | ";; WRITE IPICRi (send IPIi) \n\t" |
| 947 | ".fillinsn \n" | 929 | ".fillinsn \n" |
| 948 | "4: \n\t" | 930 | "2: \n\t" |
| 949 | "st %4, @%3 \n\t" | 931 | "st %2, @%1 \n\t" |
| 950 | ";; UNLOCK ipi_lock[i] \n\t" | ||
| 951 | ".fillinsn \n" | 932 | ".fillinsn \n" |
| 952 | "5: \n\t" | 933 | "3: \n\t" |
| 953 | "ldi r4, #1 \n\t" | ||
| 954 | "st r4, @%2 \n\t" | ||
| 955 | : "=&r"(ipicr_val) | 934 | : "=&r"(ipicr_val) |
| 956 | : "r"(flags), "r"(&ipilock->slock), "r"(ipicr_addr), | 935 | : "r"(ipicr_addr), "r"(mask), "r"(try), "r"(my_physid_mask) |
| 957 | "r"(mask), "r"(try), "r"(my_physid_mask) | 936 | : "memory" |
| 958 | : "memory", "r4" | ||
| 959 | #ifdef CONFIG_CHIP_M32700_TS1 | ||
| 960 | , "r5" | ||
| 961 | #endif /* CONFIG_CHIP_M32700_TS1 */ | ||
| 962 | ); | 937 | ); |
| 938 | spin_unlock(ipilock); | ||
| 963 | 939 | ||
| 964 | return ipicr_val; | 940 | return ipicr_val; |
| 965 | } | 941 | } |