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Diffstat (limited to 'arch/m32r/kernel/setup_oaks32r.c')
-rw-r--r--arch/m32r/kernel/setup_oaks32r.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/m32r/kernel/setup_oaks32r.c b/arch/m32r/kernel/setup_oaks32r.c
index 0e9e63538c0f..ea64831aef7a 100644
--- a/arch/m32r/kernel/setup_oaks32r.c
+++ b/arch/m32r/kernel/setup_oaks32r.c
@@ -85,7 +85,7 @@ void __init init_IRQ(void)
85#ifdef CONFIG_NE2000 85#ifdef CONFIG_NE2000
86 /* INT3 : LAN controller (RTL8019AS) */ 86 /* INT3 : LAN controller (RTL8019AS) */
87 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 87 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
88 irq_desc[M32R_IRQ_INT3].handler = &oaks32r_irq_type; 88 irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type;
89 irq_desc[M32R_IRQ_INT3].action = 0; 89 irq_desc[M32R_IRQ_INT3].action = 0;
90 irq_desc[M32R_IRQ_INT3].depth = 1; 90 irq_desc[M32R_IRQ_INT3].depth = 1;
91 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 91 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
@@ -94,7 +94,7 @@ void __init init_IRQ(void)
94 94
95 /* MFT2 : system timer */ 95 /* MFT2 : system timer */
96 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 96 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
97 irq_desc[M32R_IRQ_MFT2].handler = &oaks32r_irq_type; 97 irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type;
98 irq_desc[M32R_IRQ_MFT2].action = 0; 98 irq_desc[M32R_IRQ_MFT2].action = 0;
99 irq_desc[M32R_IRQ_MFT2].depth = 1; 99 irq_desc[M32R_IRQ_MFT2].depth = 1;
100 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 100 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
@@ -103,7 +103,7 @@ void __init init_IRQ(void)
103#ifdef CONFIG_SERIAL_M32R_SIO 103#ifdef CONFIG_SERIAL_M32R_SIO
104 /* SIO0_R : uart receive data */ 104 /* SIO0_R : uart receive data */
105 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 105 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
106 irq_desc[M32R_IRQ_SIO0_R].handler = &oaks32r_irq_type; 106 irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type;
107 irq_desc[M32R_IRQ_SIO0_R].action = 0; 107 irq_desc[M32R_IRQ_SIO0_R].action = 0;
108 irq_desc[M32R_IRQ_SIO0_R].depth = 1; 108 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
109 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 109 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
@@ -111,7 +111,7 @@ void __init init_IRQ(void)
111 111
112 /* SIO0_S : uart send data */ 112 /* SIO0_S : uart send data */
113 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 113 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
114 irq_desc[M32R_IRQ_SIO0_S].handler = &oaks32r_irq_type; 114 irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type;
115 irq_desc[M32R_IRQ_SIO0_S].action = 0; 115 irq_desc[M32R_IRQ_SIO0_S].action = 0;
116 irq_desc[M32R_IRQ_SIO0_S].depth = 1; 116 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
117 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 117 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
@@ -119,7 +119,7 @@ void __init init_IRQ(void)
119 119
120 /* SIO1_R : uart receive data */ 120 /* SIO1_R : uart receive data */
121 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 121 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
122 irq_desc[M32R_IRQ_SIO1_R].handler = &oaks32r_irq_type; 122 irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type;
123 irq_desc[M32R_IRQ_SIO1_R].action = 0; 123 irq_desc[M32R_IRQ_SIO1_R].action = 0;
124 irq_desc[M32R_IRQ_SIO1_R].depth = 1; 124 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
125 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 125 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
@@ -127,7 +127,7 @@ void __init init_IRQ(void)
127 127
128 /* SIO1_S : uart send data */ 128 /* SIO1_S : uart send data */
129 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 129 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
130 irq_desc[M32R_IRQ_SIO1_S].handler = &oaks32r_irq_type; 130 irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type;
131 irq_desc[M32R_IRQ_SIO1_S].action = 0; 131 irq_desc[M32R_IRQ_SIO1_S].action = 0;
132 irq_desc[M32R_IRQ_SIO1_S].depth = 1; 132 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
133 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 133 icu_data[M32R_IRQ_SIO1_S].icucr = 0;