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-rw-r--r--arch/m32r/boot/compressed/head.S5
-rw-r--r--arch/m32r/boot/setup.S9
2 files changed, 14 insertions, 0 deletions
diff --git a/arch/m32r/boot/compressed/head.S b/arch/m32r/boot/compressed/head.S
index 07cfd6ad1ae4..234d8b1e0ac1 100644
--- a/arch/m32r/boot/compressed/head.S
+++ b/arch/m32r/boot/compressed/head.S
@@ -143,6 +143,11 @@ startup:
143 ldi r0, -2 143 ldi r0, -2
144 ldi r1, 0x0100 ; invalidate 144 ldi r1, 0x0100 ; invalidate
145 stb r1, @r0 145 stb r1, @r0
146#elif defined(CONFIG_CHIP_M32104)
147 /* Cache flush */
148 ldi r0, -2
149 ldi r1, 0x0700 ; invalidate i-cache, copy back d-cache
150 sth r1, @r0
146#else 151#else
147#error "put your cache flush function, please" 152#error "put your cache flush function, please"
148#endif 153#endif
diff --git a/arch/m32r/boot/setup.S b/arch/m32r/boot/setup.S
index 5d256434b4ad..742669fab8a9 100644
--- a/arch/m32r/boot/setup.S
+++ b/arch/m32r/boot/setup.S
@@ -80,6 +80,10 @@ ENTRY(boot)
80 ldi r1, #0x101 ; cache on (with invalidation) 80 ldi r1, #0x101 ; cache on (with invalidation)
81; ldi r1, #0x00 ; cache off 81; ldi r1, #0x00 ; cache off
82 st r1, @r0 82 st r1, @r0
83#elif defined(CONFIG_CHIP_M32104)
84 ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
85 ldi r1, #0x703 ; cache on (with invalidation)
86 st r1, @r0
83#else 87#else
84#error unknown chip configuration 88#error unknown chip configuration
85#endif 89#endif
@@ -115,10 +119,15 @@ mmu_on:
115 st r1, @(MATM_offset,r0) ; Set MATM (T bit ON) 119 st r1, @(MATM_offset,r0) ; Set MATM (T bit ON)
116 ld r0, @(MATM_offset,r0) ; Check 120 ld r0, @(MATM_offset,r0) ; Check
117#else 121#else
122#if defined(CONFIG_CHIP_M32700)
118 seth r0,#high(M32R_MCDCAR) 123 seth r0,#high(M32R_MCDCAR)
119 or3 r0,r0,#low(M32R_MCDCAR) 124 or3 r0,r0,#low(M32R_MCDCAR)
120 ld24 r1,#0x8080 125 ld24 r1,#0x8080
121 st r1,@r0 126 st r1,@r0
127#elif defined(CONFIG_CHIP_M32104)
128 LDIMM (r2, eit_vector) ; set EVB(cr5)
129 mvtc r2, cr5
130#endif
122#endif /* CONFIG_MMU */ 131#endif /* CONFIG_MMU */
123 jmp r13 132 jmp r13
124 nop 133 nop