diff options
Diffstat (limited to 'arch/ia64')
-rw-r--r-- | arch/ia64/kernel/process.c | 2 | ||||
-rw-r--r-- | arch/ia64/sn/pci/pcibr/pcibr_reg.c | 48 | ||||
-rw-r--r-- | arch/ia64/sn/pci/tioca_provider.c | 12 |
3 files changed, 32 insertions, 30 deletions
diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c index a4da715a360c..e9904c74d2ba 100644 --- a/arch/ia64/kernel/process.c +++ b/arch/ia64/kernel/process.c | |||
@@ -721,11 +721,13 @@ flush_thread (void) | |||
721 | /* drop floating-point and debug-register state if it exists: */ | 721 | /* drop floating-point and debug-register state if it exists: */ |
722 | current->thread.flags &= ~(IA64_THREAD_FPH_VALID | IA64_THREAD_DBG_VALID); | 722 | current->thread.flags &= ~(IA64_THREAD_FPH_VALID | IA64_THREAD_DBG_VALID); |
723 | ia64_drop_fpu(current); | 723 | ia64_drop_fpu(current); |
724 | #ifdef CONFIG_IA32_SUPPORT | ||
724 | if (IS_IA32_PROCESS(ia64_task_regs(current))) { | 725 | if (IS_IA32_PROCESS(ia64_task_regs(current))) { |
725 | ia32_drop_partial_page_list(current); | 726 | ia32_drop_partial_page_list(current); |
726 | current->thread.task_size = IA32_PAGE_OFFSET; | 727 | current->thread.task_size = IA32_PAGE_OFFSET; |
727 | set_fs(USER_DS); | 728 | set_fs(USER_DS); |
728 | } | 729 | } |
730 | #endif | ||
729 | } | 731 | } |
730 | 732 | ||
731 | /* | 733 | /* |
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_reg.c b/arch/ia64/sn/pci/pcibr/pcibr_reg.c index 5d534091262c..79fdb91d7259 100644 --- a/arch/ia64/sn/pci/pcibr/pcibr_reg.c +++ b/arch/ia64/sn/pci/pcibr/pcibr_reg.c | |||
@@ -25,7 +25,7 @@ union br_ptr { | |||
25 | */ | 25 | */ |
26 | void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) | 26 | void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) |
27 | { | 27 | { |
28 | union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; | 28 | union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; |
29 | 29 | ||
30 | if (pcibus_info) { | 30 | if (pcibus_info) { |
31 | switch (pcibus_info->pbi_bridge_type) { | 31 | switch (pcibus_info->pbi_bridge_type) { |
@@ -38,14 +38,14 @@ void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) | |||
38 | default: | 38 | default: |
39 | panic | 39 | panic |
40 | ("pcireg_control_bit_clr: unknown bridgetype bridge 0x%p", | 40 | ("pcireg_control_bit_clr: unknown bridgetype bridge 0x%p", |
41 | (void *)ptr); | 41 | ptr); |
42 | } | 42 | } |
43 | } | 43 | } |
44 | } | 44 | } |
45 | 45 | ||
46 | void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) | 46 | void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) |
47 | { | 47 | { |
48 | union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; | 48 | union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; |
49 | 49 | ||
50 | if (pcibus_info) { | 50 | if (pcibus_info) { |
51 | switch (pcibus_info->pbi_bridge_type) { | 51 | switch (pcibus_info->pbi_bridge_type) { |
@@ -58,7 +58,7 @@ void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) | |||
58 | default: | 58 | default: |
59 | panic | 59 | panic |
60 | ("pcireg_control_bit_set: unknown bridgetype bridge 0x%p", | 60 | ("pcireg_control_bit_set: unknown bridgetype bridge 0x%p", |
61 | (void *)ptr); | 61 | ptr); |
62 | } | 62 | } |
63 | } | 63 | } |
64 | } | 64 | } |
@@ -68,7 +68,7 @@ void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) | |||
68 | */ | 68 | */ |
69 | uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info) | 69 | uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info) |
70 | { | 70 | { |
71 | union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; | 71 | union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; |
72 | uint64_t ret = 0; | 72 | uint64_t ret = 0; |
73 | 73 | ||
74 | if (pcibus_info) { | 74 | if (pcibus_info) { |
@@ -82,7 +82,7 @@ uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info) | |||
82 | default: | 82 | default: |
83 | panic | 83 | panic |
84 | ("pcireg_tflush_get: unknown bridgetype bridge 0x%p", | 84 | ("pcireg_tflush_get: unknown bridgetype bridge 0x%p", |
85 | (void *)ptr); | 85 | ptr); |
86 | } | 86 | } |
87 | } | 87 | } |
88 | 88 | ||
@@ -98,7 +98,7 @@ uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info) | |||
98 | */ | 98 | */ |
99 | uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info) | 99 | uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info) |
100 | { | 100 | { |
101 | union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; | 101 | union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; |
102 | uint64_t ret = 0; | 102 | uint64_t ret = 0; |
103 | 103 | ||
104 | if (pcibus_info) { | 104 | if (pcibus_info) { |
@@ -112,7 +112,7 @@ uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info) | |||
112 | default: | 112 | default: |
113 | panic | 113 | panic |
114 | ("pcireg_intr_status_get: unknown bridgetype bridge 0x%p", | 114 | ("pcireg_intr_status_get: unknown bridgetype bridge 0x%p", |
115 | (void *)ptr); | 115 | ptr); |
116 | } | 116 | } |
117 | } | 117 | } |
118 | return ret; | 118 | return ret; |
@@ -123,7 +123,7 @@ uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info) | |||
123 | */ | 123 | */ |
124 | void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) | 124 | void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) |
125 | { | 125 | { |
126 | union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; | 126 | union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; |
127 | 127 | ||
128 | if (pcibus_info) { | 128 | if (pcibus_info) { |
129 | switch (pcibus_info->pbi_bridge_type) { | 129 | switch (pcibus_info->pbi_bridge_type) { |
@@ -136,14 +136,14 @@ void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) | |||
136 | default: | 136 | default: |
137 | panic | 137 | panic |
138 | ("pcireg_intr_enable_bit_clr: unknown bridgetype bridge 0x%p", | 138 | ("pcireg_intr_enable_bit_clr: unknown bridgetype bridge 0x%p", |
139 | (void *)ptr); | 139 | ptr); |
140 | } | 140 | } |
141 | } | 141 | } |
142 | } | 142 | } |
143 | 143 | ||
144 | void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) | 144 | void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) |
145 | { | 145 | { |
146 | union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; | 146 | union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; |
147 | 147 | ||
148 | if (pcibus_info) { | 148 | if (pcibus_info) { |
149 | switch (pcibus_info->pbi_bridge_type) { | 149 | switch (pcibus_info->pbi_bridge_type) { |
@@ -156,7 +156,7 @@ void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) | |||
156 | default: | 156 | default: |
157 | panic | 157 | panic |
158 | ("pcireg_intr_enable_bit_set: unknown bridgetype bridge 0x%p", | 158 | ("pcireg_intr_enable_bit_set: unknown bridgetype bridge 0x%p", |
159 | (void *)ptr); | 159 | ptr); |
160 | } | 160 | } |
161 | } | 161 | } |
162 | } | 162 | } |
@@ -167,7 +167,7 @@ void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) | |||
167 | void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n, | 167 | void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n, |
168 | uint64_t addr) | 168 | uint64_t addr) |
169 | { | 169 | { |
170 | union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; | 170 | union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; |
171 | 171 | ||
172 | if (pcibus_info) { | 172 | if (pcibus_info) { |
173 | switch (pcibus_info->pbi_bridge_type) { | 173 | switch (pcibus_info->pbi_bridge_type) { |
@@ -186,7 +186,7 @@ void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n, | |||
186 | default: | 186 | default: |
187 | panic | 187 | panic |
188 | ("pcireg_intr_addr_addr_get: unknown bridgetype bridge 0x%p", | 188 | ("pcireg_intr_addr_addr_get: unknown bridgetype bridge 0x%p", |
189 | (void *)ptr); | 189 | ptr); |
190 | } | 190 | } |
191 | } | 191 | } |
192 | } | 192 | } |
@@ -196,7 +196,7 @@ void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n, | |||
196 | */ | 196 | */ |
197 | void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n) | 197 | void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n) |
198 | { | 198 | { |
199 | union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; | 199 | union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; |
200 | 200 | ||
201 | if (pcibus_info) { | 201 | if (pcibus_info) { |
202 | switch (pcibus_info->pbi_bridge_type) { | 202 | switch (pcibus_info->pbi_bridge_type) { |
@@ -209,7 +209,7 @@ void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n) | |||
209 | default: | 209 | default: |
210 | panic | 210 | panic |
211 | ("pcireg_force_intr_set: unknown bridgetype bridge 0x%p", | 211 | ("pcireg_force_intr_set: unknown bridgetype bridge 0x%p", |
212 | (void *)ptr); | 212 | ptr); |
213 | } | 213 | } |
214 | } | 214 | } |
215 | } | 215 | } |
@@ -219,7 +219,7 @@ void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n) | |||
219 | */ | 219 | */ |
220 | uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) | 220 | uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) |
221 | { | 221 | { |
222 | union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; | 222 | union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; |
223 | uint64_t ret = 0; | 223 | uint64_t ret = 0; |
224 | 224 | ||
225 | if (pcibus_info) { | 225 | if (pcibus_info) { |
@@ -233,7 +233,7 @@ uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) | |||
233 | __sn_readq_relaxed(&ptr->pic.p_wr_req_buf[device]); | 233 | __sn_readq_relaxed(&ptr->pic.p_wr_req_buf[device]); |
234 | break; | 234 | break; |
235 | default: | 235 | default: |
236 | panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", (void *)ptr); | 236 | panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", ptr); |
237 | } | 237 | } |
238 | 238 | ||
239 | } | 239 | } |
@@ -244,7 +244,7 @@ uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) | |||
244 | void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index, | 244 | void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index, |
245 | uint64_t val) | 245 | uint64_t val) |
246 | { | 246 | { |
247 | union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; | 247 | union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; |
248 | 248 | ||
249 | if (pcibus_info) { | 249 | if (pcibus_info) { |
250 | switch (pcibus_info->pbi_bridge_type) { | 250 | switch (pcibus_info->pbi_bridge_type) { |
@@ -257,15 +257,15 @@ void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index, | |||
257 | default: | 257 | default: |
258 | panic | 258 | panic |
259 | ("pcireg_int_ate_set: unknown bridgetype bridge 0x%p", | 259 | ("pcireg_int_ate_set: unknown bridgetype bridge 0x%p", |
260 | (void *)ptr); | 260 | ptr); |
261 | } | 261 | } |
262 | } | 262 | } |
263 | } | 263 | } |
264 | 264 | ||
265 | uint64_t *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index) | 265 | uint64_t __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index) |
266 | { | 266 | { |
267 | union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; | 267 | union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; |
268 | uint64_t *ret = (uint64_t *) 0; | 268 | uint64_t __iomem *ret = NULL; |
269 | 269 | ||
270 | if (pcibus_info) { | 270 | if (pcibus_info) { |
271 | switch (pcibus_info->pbi_bridge_type) { | 271 | switch (pcibus_info->pbi_bridge_type) { |
@@ -278,7 +278,7 @@ uint64_t *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index) | |||
278 | default: | 278 | default: |
279 | panic | 279 | panic |
280 | ("pcireg_int_ate_addr: unknown bridgetype bridge 0x%p", | 280 | ("pcireg_int_ate_addr: unknown bridgetype bridge 0x%p", |
281 | (void *)ptr); | 281 | ptr); |
282 | } | 282 | } |
283 | } | 283 | } |
284 | return ret; | 284 | return ret; |
diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c index 46b646a6d345..27aa1842dacc 100644 --- a/arch/ia64/sn/pci/tioca_provider.c +++ b/arch/ia64/sn/pci/tioca_provider.c | |||
@@ -38,10 +38,10 @@ tioca_gart_init(struct tioca_kernel *tioca_kern) | |||
38 | uint64_t offset; | 38 | uint64_t offset; |
39 | struct page *tmp; | 39 | struct page *tmp; |
40 | struct tioca_common *tioca_common; | 40 | struct tioca_common *tioca_common; |
41 | struct tioca *ca_base; | 41 | struct tioca __iomem *ca_base; |
42 | 42 | ||
43 | tioca_common = tioca_kern->ca_common; | 43 | tioca_common = tioca_kern->ca_common; |
44 | ca_base = (struct tioca *)tioca_common->ca_common.bs_base; | 44 | ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base; |
45 | 45 | ||
46 | if (list_empty(tioca_kern->ca_devices)) | 46 | if (list_empty(tioca_kern->ca_devices)) |
47 | return 0; | 47 | return 0; |
@@ -215,7 +215,7 @@ tioca_fastwrite_enable(struct tioca_kernel *tioca_kern) | |||
215 | { | 215 | { |
216 | int cap_ptr; | 216 | int cap_ptr; |
217 | uint32_t reg; | 217 | uint32_t reg; |
218 | struct tioca *tioca_base; | 218 | struct tioca __iomem *tioca_base; |
219 | struct pci_dev *pdev; | 219 | struct pci_dev *pdev; |
220 | struct tioca_common *common; | 220 | struct tioca_common *common; |
221 | 221 | ||
@@ -257,7 +257,7 @@ tioca_fastwrite_enable(struct tioca_kernel *tioca_kern) | |||
257 | * Set ca's fw to match | 257 | * Set ca's fw to match |
258 | */ | 258 | */ |
259 | 259 | ||
260 | tioca_base = (struct tioca *)common->ca_common.bs_base; | 260 | tioca_base = (struct tioca __iomem*)common->ca_common.bs_base; |
261 | __sn_setq_relaxed(&tioca_base->ca_control1, CA_AGP_FW_ENABLE); | 261 | __sn_setq_relaxed(&tioca_base->ca_control1, CA_AGP_FW_ENABLE); |
262 | } | 262 | } |
263 | 263 | ||
@@ -322,7 +322,7 @@ static uint64_t | |||
322 | tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr) | 322 | tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr) |
323 | { | 323 | { |
324 | struct tioca_common *tioca_common; | 324 | struct tioca_common *tioca_common; |
325 | struct tioca *ca_base; | 325 | struct tioca __iomem *ca_base; |
326 | uint64_t ct_addr; | 326 | uint64_t ct_addr; |
327 | dma_addr_t bus_addr; | 327 | dma_addr_t bus_addr; |
328 | uint32_t node_upper; | 328 | uint32_t node_upper; |
@@ -330,7 +330,7 @@ tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr) | |||
330 | struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev); | 330 | struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev); |
331 | 331 | ||
332 | tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info; | 332 | tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info; |
333 | ca_base = (struct tioca *)tioca_common->ca_common.bs_base; | 333 | ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base; |
334 | 334 | ||
335 | ct_addr = PHYS_TO_TIODMA(paddr); | 335 | ct_addr = PHYS_TO_TIODMA(paddr); |
336 | if (!ct_addr) | 336 | if (!ct_addr) |