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path: root/arch/ia64/sn/pci/tioce_provider.c
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Diffstat (limited to 'arch/ia64/sn/pci/tioce_provider.c')
-rw-r--r--arch/ia64/sn/pci/tioce_provider.c29
1 files changed, 15 insertions, 14 deletions
diff --git a/arch/ia64/sn/pci/tioce_provider.c b/arch/ia64/sn/pci/tioce_provider.c
index 8e75db2b825d..204826c2fa44 100644
--- a/arch/ia64/sn/pci/tioce_provider.c
+++ b/arch/ia64/sn/pci/tioce_provider.c
@@ -227,7 +227,7 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
227 227
228 ate = ATE_MAKE(addr, pagesize); 228 ate = ATE_MAKE(addr, pagesize);
229 ate_shadow[i + j] = ate; 229 ate_shadow[i + j] = ate;
230 ate_reg[i + j] = ate; 230 writeq(ate, &ate_reg[i + j]);
231 addr += pagesize; 231 addr += pagesize;
232 } 232 }
233 233
@@ -268,10 +268,10 @@ tioce_dma_d32(struct pci_dev *pdev, uint64_t ct_addr)
268 pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port); 268 pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port);
269 269
270 if (ce_kern->ce_port[port].dirmap_refcnt == 0) { 270 if (ce_kern->ce_port[port].dirmap_refcnt == 0) {
271 volatile uint64_t tmp; 271 uint64_t tmp;
272 272
273 ce_kern->ce_port[port].dirmap_shadow = ct_upper; 273 ce_kern->ce_port[port].dirmap_shadow = ct_upper;
274 ce_mmr->ce_ure_dir_map[port] = ct_upper; 274 writeq(ct_upper, &ce_mmr->ce_ure_dir_map[port]);
275 tmp = ce_mmr->ce_ure_dir_map[port]; 275 tmp = ce_mmr->ce_ure_dir_map[port];
276 dma_ok = 1; 276 dma_ok = 1;
277 } else 277 } else
@@ -343,7 +343,7 @@ tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
343 if (TIOCE_D32_ADDR(bus_addr)) { 343 if (TIOCE_D32_ADDR(bus_addr)) {
344 if (--ce_kern->ce_port[port].dirmap_refcnt == 0) { 344 if (--ce_kern->ce_port[port].dirmap_refcnt == 0) {
345 ce_kern->ce_port[port].dirmap_shadow = 0; 345 ce_kern->ce_port[port].dirmap_shadow = 0;
346 ce_mmr->ce_ure_dir_map[port] = 0; 346 writeq(0, &ce_mmr->ce_ure_dir_map[port]);
347 } 347 }
348 } else { 348 } else {
349 struct tioce_dmamap *map; 349 struct tioce_dmamap *map;
@@ -582,18 +582,18 @@ tioce_kern_init(struct tioce_common *tioce_common)
582 */ 582 */
583 583
584 tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base; 584 tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base;
585 tioce_mmr->ce_ure_page_map &= ~CE_URE_PAGESIZE_MASK; 585 __sn_clrq_relaxed(&tioce_mmr->ce_ure_page_map, CE_URE_PAGESIZE_MASK);
586 tioce_mmr->ce_ure_page_map |= CE_URE_256K_PAGESIZE; 586 __sn_setq_relaxed(&tioce_mmr->ce_ure_page_map, CE_URE_256K_PAGESIZE);
587 tioce_kern->ce_ate3240_pagesize = KB(256); 587 tioce_kern->ce_ate3240_pagesize = KB(256);
588 588
589 for (i = 0; i < TIOCE_NUM_M40_ATES; i++) { 589 for (i = 0; i < TIOCE_NUM_M40_ATES; i++) {
590 tioce_kern->ce_ate40_shadow[i] = 0; 590 tioce_kern->ce_ate40_shadow[i] = 0;
591 tioce_mmr->ce_ure_ate40[i] = 0; 591 writeq(0, &tioce_mmr->ce_ure_ate40[i]);
592 } 592 }
593 593
594 for (i = 0; i < TIOCE_NUM_M3240_ATES; i++) { 594 for (i = 0; i < TIOCE_NUM_M3240_ATES; i++) {
595 tioce_kern->ce_ate3240_shadow[i] = 0; 595 tioce_kern->ce_ate3240_shadow[i] = 0;
596 tioce_mmr->ce_ure_ate3240[i] = 0; 596 writeq(0, &tioce_mmr->ce_ure_ate3240[i]);
597 } 597 }
598 598
599 return tioce_kern; 599 return tioce_kern;
@@ -665,7 +665,7 @@ tioce_force_interrupt(struct sn_irq_info *sn_irq_info)
665 default: 665 default:
666 return; 666 return;
667 } 667 }
668 ce_mmr->ce_adm_force_int = force_int_val; 668 writeq(force_int_val, &ce_mmr->ce_adm_force_int);
669} 669}
670 670
671/** 671/**
@@ -686,6 +686,7 @@ tioce_target_interrupt(struct sn_irq_info *sn_irq_info)
686 struct tioce_common *ce_common; 686 struct tioce_common *ce_common;
687 struct tioce *ce_mmr; 687 struct tioce *ce_mmr;
688 int bit; 688 int bit;
689 uint64_t vector;
689 690
690 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; 691 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
691 if (!pcidev_info) 692 if (!pcidev_info)
@@ -696,11 +697,11 @@ tioce_target_interrupt(struct sn_irq_info *sn_irq_info)
696 697
697 bit = sn_irq_info->irq_int_bit; 698 bit = sn_irq_info->irq_int_bit;
698 699
699 ce_mmr->ce_adm_int_mask |= (1UL << bit); 700 __sn_setq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit));
700 ce_mmr->ce_adm_int_dest[bit] = 701 vector = (uint64_t)sn_irq_info->irq_irq << INTR_VECTOR_SHFT;
701 ((uint64_t)sn_irq_info->irq_irq << INTR_VECTOR_SHFT) | 702 vector |= sn_irq_info->irq_xtalkaddr;
702 sn_irq_info->irq_xtalkaddr; 703 writeq(vector, &ce_mmr->ce_adm_int_dest[bit]);
703 ce_mmr->ce_adm_int_mask &= ~(1UL << bit); 704 __sn_clrq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit));
704 705
705 tioce_force_interrupt(sn_irq_info); 706 tioce_force_interrupt(sn_irq_info);
706} 707}