5 files changed, 46 insertions, 16 deletions

diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S
index bb9a506deb78..66946f3fdac7 100644
--- a/arch/ia64/kernel/entry.S
+++ b/arch/ia64/kernel/entry.S
@@ -1574,8 +1574,8 @@ sys_call_table:
         data8 sys_ioprio_set
         data8 sys_ioprio_get                    // 1275
         data8 sys_set_zone_reclaim
-        data8 sys_ni_syscall
-        data8 sys_ni_syscall
-        data8 sys_ni_syscall
+        data8 sys_inotify_init
+        data8 sys_inotify_add_watch
+        data8 sys_inotify_rm_watch
 
         .org sys_call_table + 8*NR_syscalls     // guard against failures to increase NR_syscalls
diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c
index e484910246ad..66e840609808 100644
--- a/arch/ia64/kernel/process.c
+++ b/arch/ia64/kernel/process.c
@@ -807,16 +807,12 @@ machine_restart (char *restart_cmd)
         (*efi.reset_system)(EFI_RESET_WARM, 0, 0, NULL);
 }
 
-EXPORT_SYMBOL(machine_restart);
-
 void
 machine_halt (void)
 {
         cpu_halt();
 }
 
-EXPORT_SYMBOL(machine_halt);
-
 void
 machine_power_off (void)
 {
@@ -825,4 +821,3 @@ machine_power_off (void)
         machine_halt();
 }
 
-EXPORT_SYMBOL(machine_power_off);
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index 5c7c95737bbf..84f89da7c640 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -20,6 +20,7 @@
  * 02/01/00 R.Seth      fixed get_cpuinfo for SMP
  * 01/07/99 S.Eranian   added the support for command line argument
  * 06/24/99 W.Drummond  added boot_cpu_data.
+ * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
  */
 #include <linux/config.h>
 #include <linux/module.h>
@@ -85,6 +86,13 @@ EXPORT_SYMBOL(io_space);
 unsigned int num_io_spaces;
 
 /*
+ * "flush_icache_range()" needs to know what processor dependent stride size to use
+ * when it makes i-cache(s) coherent with d-caches.
+ */
+#define I_CACHE_STRIDE_SHIFT    5       /* Safest way to go: 32 bytes by 32 bytes */
+unsigned long ia64_i_cache_stride_shift = ~0;
+
+/*
  * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1).  This
  * mask specifies a mask of address bits that must be 0 in order for two buffers to be
  * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
@@ -628,6 +636,12 @@ setup_per_cpu_areas (void)
         /* start_kernel() requires this... */
 }
 
+/*
+ * Calculate the max. cache line size.
+ *
+ * In addition, the minimum of the i-cache stride sizes is calculated for
+ * "flush_icache_range()".
+ */
 static void
 get_max_cacheline_size (void)
 {
@@ -641,6 +655,8 @@ get_max_cacheline_size (void)
                 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
                        __FUNCTION__, status);
                 max = SMP_CACHE_BYTES;
+                /* Safest setup for "flush_icache_range()" */
+                ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
                 goto out;
         }
 
@@ -649,14 +665,31 @@ get_max_cacheline_size (void)
                                                     &cci);
                 if (status != 0) {
                         printk(KERN_ERR
-                               "%s: ia64_pal_cache_config_info(l=%lu) failed (status=%ld)\n",
+                               "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
                                __FUNCTION__, l, status);
                         max = SMP_CACHE_BYTES;
+                        /* The safest setup for "flush_icache_range()" */
+                        cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
+                        cci.pcci_unified = 1;
                 }
                 line_size = 1 << cci.pcci_line_size;
                 if (line_size > max)
                         max = line_size;
-        }
+                if (!cci.pcci_unified) {
+                        status = ia64_pal_cache_config_info(l,
+                                                    /* cache_type (instruction)= */ 1,
+                                                    &cci);
+                        if (status != 0) {
+                                printk(KERN_ERR
+                                "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
+                                        __FUNCTION__, l, status);
+                                /* The safest setup for "flush_icache_range()" */
+                                cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
+                        }
+                }
+                if (cci.pcci_stride < ia64_i_cache_stride_shift)
+                        ia64_i_cache_stride_shift = cci.pcci_stride;
+        }
   out:
         if (max > ia64_max_cacheline_size)
                 ia64_max_cacheline_size = max;
diff --git a/arch/ia64/kernel/topology.c b/arch/ia64/kernel/topology.c
index d8030f3bd865..92ff46ad21e2 100644
--- a/arch/ia64/kernel/topology.c
+++ b/arch/ia64/kernel/topology.c
@@ -36,12 +36,14 @@ int arch_register_cpu(int num)
         parent = &sysfs_nodes[cpu_to_node(num)];
 #endif /* CONFIG_NUMA */
 
+#ifdef CONFIG_ACPI_BOOT
         /*
          * If CPEI cannot be re-targetted, and this is
          * CPEI target, then dont create the control file
          */
         if (!can_cpei_retarget() && is_cpu_cpei_target(num))
                 sysfs_cpus[num].cpu.no_control = 1;
+#endif
 
         return register_cpu(&sysfs_cpus[num].cpu, num, parent);
 }
diff --git a/arch/ia64/kernel/unwind.c b/arch/ia64/kernel/unwind.c
index 2776a074c6f1..3288be47bc75 100644
--- a/arch/ia64/kernel/unwind.c
+++ b/arch/ia64/kernel/unwind.c
@@ -362,7 +362,7 @@ unw_access_gr (struct unw_frame_info *info, int regnum, unsigned long *val, char
                         if (info->pri_unat_loc)
                                 nat_addr = info->pri_unat_loc;
                         else
-                                nat_addr = &info->sw->ar_unat;
+                                nat_addr = &info->sw->caller_unat;
                         nat_mask = (1UL << ((long) addr & 0x1f8)/8);
                 }
         } else {
@@ -524,7 +524,7 @@ unw_access_ar (struct unw_frame_info *info, int regnum, unsigned long *val, int
               case UNW_AR_UNAT:
                 addr = info->unat_loc;
                 if (!addr)
-                        addr = &info->sw->ar_unat;
+                        addr = &info->sw->caller_unat;
                 break;
 
               case UNW_AR_LC:
@@ -1775,7 +1775,7 @@ run_script (struct unw_script *script, struct unw_frame_info *state)
 
                       case UNW_INSN_SETNAT_MEMSTK:
                         if (!state->pri_unat_loc)
-                                state->pri_unat_loc = &state->sw->ar_unat;
+                                state->pri_unat_loc = &state->sw->caller_unat;
                         /* register off. is a multiple of 8, so the least 3 bits (type) are 0 */
                         s[dst+1] = ((unsigned long) state->pri_unat_loc - s[dst]) | UNW_NAT_MEMSTK;
                         break;
@@ -2243,11 +2243,11 @@ unw_init (void)
         if (8*sizeof(unw_hash_index_t) < UNW_LOG_HASH_SIZE)
                 unw_hash_index_t_is_too_narrow();
 
-        unw.sw_off[unw.preg_index[UNW_REG_PRI_UNAT_GR]] = SW(AR_UNAT);
+        unw.sw_off[unw.preg_index[UNW_REG_PRI_UNAT_GR]] = SW(CALLER_UNAT);
         unw.sw_off[unw.preg_index[UNW_REG_BSPSTORE]] = SW(AR_BSPSTORE);
-        unw.sw_off[unw.preg_index[UNW_REG_PFS]] = SW(AR_UNAT);
+        unw.sw_off[unw.preg_index[UNW_REG_PFS]] = SW(AR_PFS);
         unw.sw_off[unw.preg_index[UNW_REG_RP]] = SW(B0);
-        unw.sw_off[unw.preg_index[UNW_REG_UNAT]] = SW(AR_UNAT);
+        unw.sw_off[unw.preg_index[UNW_REG_UNAT]] = SW(CALLER_UNAT);
         unw.sw_off[unw.preg_index[UNW_REG_PR]] = SW(PR);
         unw.sw_off[unw.preg_index[UNW_REG_LC]] = SW(AR_LC);
         unw.sw_off[unw.preg_index[UNW_REG_FPSR]] = SW(AR_FPSR);