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-rw-r--r--arch/ia64/kernel/setup.c18
1 files changed, 10 insertions, 8 deletions
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index 593279f33e96..c27d5b2c182b 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -927,17 +927,19 @@ cpu_init (void)
927 if (smp_processor_id() == 0) { 927 if (smp_processor_id() == 0) {
928 cpu_set(0, per_cpu(cpu_sibling_map, 0)); 928 cpu_set(0, per_cpu(cpu_sibling_map, 0));
929 cpu_set(0, cpu_core_map[0]); 929 cpu_set(0, cpu_core_map[0]);
930 } else {
931 /*
932 * Set ar.k3 so that assembly code in MCA handler can compute
933 * physical addresses of per cpu variables with a simple:
934 * phys = ar.k3 + &per_cpu_var
935 * and the alt-dtlb-miss handler can set per-cpu mapping into
936 * the TLB when needed. head.S already did this for cpu0.
937 */
938 ia64_set_kr(IA64_KR_PER_CPU_DATA,
939 ia64_tpa(cpu_data) - (long) __per_cpu_start);
930 } 940 }
931#endif 941#endif
932 942
933 /*
934 * We set ar.k3 so that assembly code in MCA handler can compute
935 * physical addresses of per cpu variables with a simple:
936 * phys = ar.k3 + &per_cpu_var
937 */
938 ia64_set_kr(IA64_KR_PER_CPU_DATA,
939 ia64_tpa(cpu_data) - (long) __per_cpu_start);
940
941 get_max_cacheline_size(); 943 get_max_cacheline_size();
942 944
943 /* 945 /*