diff options
Diffstat (limited to 'arch/ia64/kernel/setup.c')
-rw-r--r-- | arch/ia64/kernel/setup.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c index c33305d8e5eb..c0766575a3a2 100644 --- a/arch/ia64/kernel/setup.c +++ b/arch/ia64/kernel/setup.c | |||
@@ -60,6 +60,7 @@ | |||
60 | #include <asm/smp.h> | 60 | #include <asm/smp.h> |
61 | #include <asm/system.h> | 61 | #include <asm/system.h> |
62 | #include <asm/unistd.h> | 62 | #include <asm/unistd.h> |
63 | #include <asm/system.h> | ||
63 | 64 | ||
64 | #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) | 65 | #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) |
65 | # error "struct cpuinfo_ia64 too big!" | 66 | # error "struct cpuinfo_ia64 too big!" |
@@ -695,6 +696,7 @@ static void | |||
695 | get_max_cacheline_size (void) | 696 | get_max_cacheline_size (void) |
696 | { | 697 | { |
697 | unsigned long line_size, max = 1; | 698 | unsigned long line_size, max = 1; |
699 | unsigned int cache_size = 0; | ||
698 | u64 l, levels, unique_caches; | 700 | u64 l, levels, unique_caches; |
699 | pal_cache_config_info_t cci; | 701 | pal_cache_config_info_t cci; |
700 | s64 status; | 702 | s64 status; |
@@ -724,6 +726,8 @@ get_max_cacheline_size (void) | |||
724 | line_size = 1 << cci.pcci_line_size; | 726 | line_size = 1 << cci.pcci_line_size; |
725 | if (line_size > max) | 727 | if (line_size > max) |
726 | max = line_size; | 728 | max = line_size; |
729 | if (cache_size < cci.pcci_cache_size) | ||
730 | cache_size = cci.pcci_cache_size; | ||
727 | if (!cci.pcci_unified) { | 731 | if (!cci.pcci_unified) { |
728 | status = ia64_pal_cache_config_info(l, | 732 | status = ia64_pal_cache_config_info(l, |
729 | /* cache_type (instruction)= */ 1, | 733 | /* cache_type (instruction)= */ 1, |
@@ -740,6 +744,9 @@ get_max_cacheline_size (void) | |||
740 | ia64_i_cache_stride_shift = cci.pcci_stride; | 744 | ia64_i_cache_stride_shift = cci.pcci_stride; |
741 | } | 745 | } |
742 | out: | 746 | out: |
747 | #ifdef CONFIG_SMP | ||
748 | max_cache_size = max(max_cache_size, cache_size); | ||
749 | #endif | ||
743 | if (max > ia64_max_cacheline_size) | 750 | if (max > ia64_max_cacheline_size) |
744 | ia64_max_cacheline_size = max; | 751 | ia64_max_cacheline_size = max; |
745 | } | 752 | } |
@@ -794,7 +801,7 @@ cpu_init (void) | |||
794 | #endif | 801 | #endif |
795 | 802 | ||
796 | /* Clear the stack memory reserved for pt_regs: */ | 803 | /* Clear the stack memory reserved for pt_regs: */ |
797 | memset(ia64_task_regs(current), 0, sizeof(struct pt_regs)); | 804 | memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); |
798 | 805 | ||
799 | ia64_set_kr(IA64_KR_FPU_OWNER, 0); | 806 | ia64_set_kr(IA64_KR_FPU_OWNER, 0); |
800 | 807 | ||
@@ -870,6 +877,15 @@ cpu_init (void) | |||
870 | pm_idle = default_idle; | 877 | pm_idle = default_idle; |
871 | } | 878 | } |
872 | 879 | ||
880 | /* | ||
881 | * On SMP systems, when the scheduler does migration-cost autodetection, | ||
882 | * it needs a way to flush as much of the CPU's caches as possible. | ||
883 | */ | ||
884 | void sched_cacheflush(void) | ||
885 | { | ||
886 | ia64_sal_cache_flush(3); | ||
887 | } | ||
888 | |||
873 | void | 889 | void |
874 | check_bugs (void) | 890 | check_bugs (void) |
875 | { | 891 | { |