1 files changed, 82 insertions, 0 deletions
diff --git a/arch/ia64/kernel/entry.h b/arch/ia64/kernel/entry.h
new file mode 100644
index 000000000000..6d4ecec989b5
--- /dev/null
+++ b/arch/ia64/kernel/entry.h
@@ -0,0 +1,82 @@
+#include <linux/config.h>
+/*
+ * Preserved registers that are shared between code in ivt.S and
+ * entry.S.  Be careful not to step on these!
+ */
+#define PRED_LEAVE_SYSCALL      1 /* TRUE iff leave from syscall */
+#define PRED_KERNEL_STACK       2 /* returning to kernel-stacks? */
+#define PRED_USER_STACK         3 /* returning to user-stacks? */
+#define PRED_SYSCALL            4 /* inside a system call? */
+#define PRED_NON_SYSCALL        5 /* complement of PRED_SYSCALL */
+#ifdef __ASSEMBLY__
+# define PASTE2(x,y)    x##y
+# define PASTE(x,y)     PASTE2(x,y)
+# define pLvSys         PASTE(p,PRED_LEAVE_SYSCALL)
+# define pKStk          PASTE(p,PRED_KERNEL_STACK)
+# define pUStk          PASTE(p,PRED_USER_STACK)
+# define pSys           PASTE(p,PRED_SYSCALL)
+# define pNonSys        PASTE(p,PRED_NON_SYSCALL)
+#endif
+#define PT(f)           (IA64_PT_REGS_##f##_OFFSET)
+#define SW(f)           (IA64_SWITCH_STACK_##f##_OFFSET)
+#define PT_REGS_SAVES(off)                      \
+        .unwabi 3, 'i';                         \
+        .fframe IA64_PT_REGS_SIZE+16+(off);     \
+        .spillsp rp, PT(CR_IIP)+16+(off);       \
+        .spillsp ar.pfs, PT(CR_IFS)+16+(off);   \
+        .spillsp ar.unat, PT(AR_UNAT)+16+(off); \
+        .spillsp ar.fpsr, PT(AR_FPSR)+16+(off); \
+        .spillsp pr, PT(PR)+16+(off);
+#define PT_REGS_UNWIND_INFO(off)                \
+        .prologue;                              \
+        PT_REGS_SAVES(off);                     \
+        .body
+#define SWITCH_STACK_SAVES(off)                                                 \
+        .savesp ar.unat,SW(CALLER_UNAT)+16+(off);                               \
+        .savesp ar.fpsr,SW(AR_FPSR)+16+(off);                                   \
+        .spillsp f2,SW(F2)+16+(off); .spillsp f3,SW(F3)+16+(off);               \
+        .spillsp f4,SW(F4)+16+(off); .spillsp f5,SW(F5)+16+(off);               \
+        .spillsp f16,SW(F16)+16+(off); .spillsp f17,SW(F17)+16+(off);           \
+        .spillsp f18,SW(F18)+16+(off); .spillsp f19,SW(F19)+16+(off);           \
+        .spillsp f20,SW(F20)+16+(off); .spillsp f21,SW(F21)+16+(off);           \
+        .spillsp f22,SW(F22)+16+(off); .spillsp f23,SW(F23)+16+(off);           \
+        .spillsp f24,SW(F24)+16+(off); .spillsp f25,SW(F25)+16+(off);           \
+        .spillsp f26,SW(F26)+16+(off); .spillsp f27,SW(F27)+16+(off);           \
+        .spillsp f28,SW(F28)+16+(off); .spillsp f29,SW(F29)+16+(off);           \
+        .spillsp f30,SW(F30)+16+(off); .spillsp f31,SW(F31)+16+(off);           \
+        .spillsp r4,SW(R4)+16+(off); .spillsp r5,SW(R5)+16+(off);               \
+        .spillsp r6,SW(R6)+16+(off); .spillsp r7,SW(R7)+16+(off);               \
+        .spillsp b0,SW(B0)+16+(off); .spillsp b1,SW(B1)+16+(off);               \
+        .spillsp b2,SW(B2)+16+(off); .spillsp b3,SW(B3)+16+(off);               \
+        .spillsp b4,SW(B4)+16+(off); .spillsp b5,SW(B5)+16+(off);               \
+        .spillsp ar.pfs,SW(AR_PFS)+16+(off); .spillsp ar.lc,SW(AR_LC)+16+(off); \
+        .spillsp @priunat,SW(AR_UNAT)+16+(off);                                 \
+        .spillsp ar.rnat,SW(AR_RNAT)+16+(off);                                  \
+        .spillsp ar.bspstore,SW(AR_BSPSTORE)+16+(off);                          \
+        .spillsp pr,SW(PR)+16+(off))
+#define DO_SAVE_SWITCH_STACK                    \
+        movl r28=1f;                            \
+        ;;                                      \
+        .fframe IA64_SWITCH_STACK_SIZE;         \
+        adds sp=-IA64_SWITCH_STACK_SIZE,sp;     \
+        mov.ret.sptk b7=r28,1f;                 \
+        SWITCH_STACK_SAVES(0);                  \
+        br.cond.sptk.many save_switch_stack;    \
+1:
+#define DO_LOAD_SWITCH_STACK                    \
+        movl r28=1f;                            \
+        ;;                                      \
+        invala;                                 \
+        mov.ret.sptk b7=r28,1f;                 \
+        br.cond.sptk.many load_switch_stack;    \
+1:      .restore sp;                            \
+        adds sp=IA64_SWITCH_STACK_SIZE,sp

diff --git a/arch/ia64/kernel/entry.h b/arch/ia64/kernel/entry.h new file mode 100644 index 000000000000..6d4ecec989b5 --- /dev/null +++ b/arch/ia64/kernel/entry.h
@@ -0,0 +1,82 @@
	1	#include <linux/config.h>
	2
	3	/*
	4	* Preserved registers that are shared between code in ivt.S and
	5	* entry.S. Be careful not to step on these!
	6	*/
	7	#define PRED_LEAVE_SYSCALL 1 /* TRUE iff leave from syscall */
	8	#define PRED_KERNEL_STACK 2 /* returning to kernel-stacks? */
	9	#define PRED_USER_STACK 3 /* returning to user-stacks? */
	10	#define PRED_SYSCALL 4 /* inside a system call? */
	11	#define PRED_NON_SYSCALL 5 /* complement of PRED_SYSCALL */
	12
	13	#ifdef __ASSEMBLY__
	14	# define PASTE2(x,y) x##y
	15	# define PASTE(x,y) PASTE2(x,y)
	16
	17	# define pLvSys PASTE(p,PRED_LEAVE_SYSCALL)
	18	# define pKStk PASTE(p,PRED_KERNEL_STACK)
	19	# define pUStk PASTE(p,PRED_USER_STACK)
	20	# define pSys PASTE(p,PRED_SYSCALL)
	21	# define pNonSys PASTE(p,PRED_NON_SYSCALL)
	22	#endif
	23
	24	#define PT(f) (IA64_PT_REGS_##f##_OFFSET)
	25	#define SW(f) (IA64_SWITCH_STACK_##f##_OFFSET)
	26
	27	#define PT_REGS_SAVES(off) \
	28	.unwabi 3, 'i'; \
	29	.fframe IA64_PT_REGS_SIZE+16+(off); \
	30	.spillsp rp, PT(CR_IIP)+16+(off); \
	31	.spillsp ar.pfs, PT(CR_IFS)+16+(off); \
	32	.spillsp ar.unat, PT(AR_UNAT)+16+(off); \
	33	.spillsp ar.fpsr, PT(AR_FPSR)+16+(off); \
	34	.spillsp pr, PT(PR)+16+(off);
	35
	36	#define PT_REGS_UNWIND_INFO(off) \
	37	.prologue; \
	38	PT_REGS_SAVES(off); \
	39	.body
	40
	41	#define SWITCH_STACK_SAVES(off) \
	42	.savesp ar.unat,SW(CALLER_UNAT)+16+(off); \
	43	.savesp ar.fpsr,SW(AR_FPSR)+16+(off); \
	44	.spillsp f2,SW(F2)+16+(off); .spillsp f3,SW(F3)+16+(off); \
	45	.spillsp f4,SW(F4)+16+(off); .spillsp f5,SW(F5)+16+(off); \
	46	.spillsp f16,SW(F16)+16+(off); .spillsp f17,SW(F17)+16+(off); \
	47	.spillsp f18,SW(F18)+16+(off); .spillsp f19,SW(F19)+16+(off); \
	48	.spillsp f20,SW(F20)+16+(off); .spillsp f21,SW(F21)+16+(off); \
	49	.spillsp f22,SW(F22)+16+(off); .spillsp f23,SW(F23)+16+(off); \
	50	.spillsp f24,SW(F24)+16+(off); .spillsp f25,SW(F25)+16+(off); \
	51	.spillsp f26,SW(F26)+16+(off); .spillsp f27,SW(F27)+16+(off); \
	52	.spillsp f28,SW(F28)+16+(off); .spillsp f29,SW(F29)+16+(off); \
	53	.spillsp f30,SW(F30)+16+(off); .spillsp f31,SW(F31)+16+(off); \
	54	.spillsp r4,SW(R4)+16+(off); .spillsp r5,SW(R5)+16+(off); \
	55	.spillsp r6,SW(R6)+16+(off); .spillsp r7,SW(R7)+16+(off); \
	56	.spillsp b0,SW(B0)+16+(off); .spillsp b1,SW(B1)+16+(off); \
	57	.spillsp b2,SW(B2)+16+(off); .spillsp b3,SW(B3)+16+(off); \
	58	.spillsp b4,SW(B4)+16+(off); .spillsp b5,SW(B5)+16+(off); \
	59	.spillsp ar.pfs,SW(AR_PFS)+16+(off); .spillsp ar.lc,SW(AR_LC)+16+(off); \
	60	.spillsp @priunat,SW(AR_UNAT)+16+(off); \
	61	.spillsp ar.rnat,SW(AR_RNAT)+16+(off); \
	62	.spillsp ar.bspstore,SW(AR_BSPSTORE)+16+(off); \
	63	.spillsp pr,SW(PR)+16+(off))
	64
	65	#define DO_SAVE_SWITCH_STACK \
	66	movl r28=1f; \
	67	;; \
	68	.fframe IA64_SWITCH_STACK_SIZE; \
	69	adds sp=-IA64_SWITCH_STACK_SIZE,sp; \
	70	mov.ret.sptk b7=r28,1f; \
	71	SWITCH_STACK_SAVES(0); \
	72	br.cond.sptk.many save_switch_stack; \
	73	1:
	74
	75	#define DO_LOAD_SWITCH_STACK \
	76	movl r28=1f; \
	77	;; \
	78	invala; \
	79	mov.ret.sptk b7=r28,1f; \
	80	br.cond.sptk.many load_switch_stack; \
	81	1: .restore sp; \
	82	adds sp=IA64_SWITCH_STACK_SIZE,sp