4 files changed, 60 insertions, 5 deletions

diff --git a/arch/i386/Kconfig b/arch/i386/Kconfig
index f7db71d0b913..f17bd1d2707e 100644
--- a/arch/i386/Kconfig
+++ b/arch/i386/Kconfig
@@ -231,6 +231,15 @@ config SCHED_SMT
           cost of slightly increased overhead in some places. If unsure say
           N here.
 
+config SCHED_MC
+        bool "Multi-core scheduler support"
+        depends on SMP
+        default y
+        help
+          Multi-core scheduler support improves the CPU scheduler's decision
+          making when dealing with multi-core CPU chips at a cost of slightly
+          increased overhead in some places. If unsure say N here.
+
 source "kernel/Kconfig.preempt"
 
 config X86_UP_APIC
diff --git a/arch/i386/kernel/cpu/common.c b/arch/i386/kernel/cpu/common.c
index 7e3d6b6a4e96..a06a49075f10 100644
--- a/arch/i386/kernel/cpu/common.c
+++ b/arch/i386/kernel/cpu/common.c
@@ -266,7 +266,7 @@ static void __init early_cpu_detect(void)
 void __cpuinit generic_identify(struct cpuinfo_x86 * c)
 {
         u32 tfms, xlvl;
-        int junk;
+        int ebx;
 
         if (have_cpuid_p()) {
                 /* Get vendor name */
@@ -282,7 +282,7 @@ void __cpuinit generic_identify(struct cpuinfo_x86 * c)
                 /* Intel-defined flags: level 0x00000001 */
                 if ( c->cpuid_level >= 0x00000001 ) {
                         u32 capability, excap;
-                        cpuid(0x00000001, &tfms, &junk, &excap, &capability);
+                        cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
                         c->x86_capability[0] = capability;
                         c->x86_capability[4] = excap;
                         c->x86 = (tfms >> 8) & 15;
@@ -292,6 +292,11 @@ void __cpuinit generic_identify(struct cpuinfo_x86 * c)
                         if (c->x86 >= 0x6)
                                 c->x86_model += ((tfms >> 16) & 0xF) << 4;
                         c->x86_mask = tfms & 15;
+#ifdef CONFIG_SMP
+                        c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
+#else
+                        c->apicid = (ebx >> 24) & 0xFF;
+#endif
                 } else {
                         /* Have CPUID level 0 only - unheard of */
                         c->x86 = 4;
@@ -474,7 +479,6 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 
         cpuid(1, &eax, &ebx, &ecx, &edx);
 
-        c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
 
         if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
                 return;
diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c
index ce61921369e5..7e7fd4e67dd0 100644
--- a/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ b/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -173,6 +173,10 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
         unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
         unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
         unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
+        unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
+#ifdef CONFIG_SMP
+        unsigned int cpu = (c == &boot_cpu_data) ? 0 : (c - cpu_data);
+#endif
 
         if (c->cpuid_level > 3) {
                 static int is_initialized;
@@ -205,9 +209,15 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
                                         break;
                                     case 2:
                                         new_l2 = this_leaf.size/1024;
+                                        num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
+                                        index_msb = get_count_order(num_threads_sharing);
+                                        l2_id = c->apicid >> index_msb;
                                         break;
                                     case 3:
                                         new_l3 = this_leaf.size/1024;
+                                        num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
+                                        index_msb = get_count_order(num_threads_sharing);
+                                        l3_id = c->apicid >> index_msb;
                                         break;
                                     default:
                                         break;
@@ -273,11 +283,19 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
                 if (new_l1i)
                         l1i = new_l1i;
 
-                if (new_l2)
+                if (new_l2) {
                         l2 = new_l2;
+#ifdef CONFIG_SMP
+                        cpu_llc_id[cpu] = l2_id;
+#endif
+                }
 
-                if (new_l3)
+                if (new_l3) {
                         l3 = new_l3;
+#ifdef CONFIG_SMP
+                        cpu_llc_id[cpu] = l3_id;
+#endif
+                }
 
                 if ( trace )
                         printk (KERN_INFO "CPU: Trace cache: %dK uops", trace);
diff --git a/arch/i386/kernel/smpboot.c b/arch/i386/kernel/smpboot.c
index 82371d83bfa9..a6969903f2d6 100644
--- a/arch/i386/kernel/smpboot.c
+++ b/arch/i386/kernel/smpboot.c
@@ -72,6 +72,9 @@ int phys_proc_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
 /* Core ID of each logical CPU */
 int cpu_core_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
 
+/* Last level cache ID of each logical CPU */
+int cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID};
+
 /* representing HT siblings of each logical CPU */
 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
 EXPORT_SYMBOL(cpu_sibling_map);
@@ -440,6 +443,18 @@ static void __devinit smp_callin(void)
 
 static int cpucount;
 
+/* maps the cpu to the sched domain representing multi-core */
+cpumask_t cpu_coregroup_map(int cpu)
+{
+        struct cpuinfo_x86 *c = cpu_data + cpu;
+        /*
+         * For perf, we return last level cache shared map.
+         * TBD: when power saving sched policy is added, we will return
+         *      cpu_core_map when power saving policy is enabled
+         */
+        return c->llc_shared_map;
+}
+
 /* representing cpus for which sibling maps can be computed */
 static cpumask_t cpu_sibling_setup_map;
 
@@ -459,12 +474,16 @@ set_cpu_sibling_map(int cpu)
                                 cpu_set(cpu, cpu_sibling_map[i]);
                                 cpu_set(i, cpu_core_map[cpu]);
                                 cpu_set(cpu, cpu_core_map[i]);
+                                cpu_set(i, c[cpu].llc_shared_map);
+                                cpu_set(cpu, c[i].llc_shared_map);
                         }
                 }
         } else {
                 cpu_set(cpu, cpu_sibling_map[cpu]);
         }
 
+        cpu_set(cpu, c[cpu].llc_shared_map);
+
         if (current_cpu_data.x86_max_cores == 1) {
                 cpu_core_map[cpu] = cpu_sibling_map[cpu];
                 c[cpu].booted_cores = 1;
@@ -472,6 +491,11 @@ set_cpu_sibling_map(int cpu)
         }
 
         for_each_cpu_mask(i, cpu_sibling_setup_map) {
+                if (cpu_llc_id[cpu] != BAD_APICID &&
+                    cpu_llc_id[cpu] == cpu_llc_id[i]) {
+                        cpu_set(i, c[cpu].llc_shared_map);
+                        cpu_set(cpu, c[i].llc_shared_map);
+                }
                 if (phys_proc_id[cpu] == phys_proc_id[i]) {
                         cpu_set(i, cpu_core_map[cpu]);
                         cpu_set(cpu, cpu_core_map[i]);