aboutsummaryrefslogtreecommitdiffstats
path: root/arch/i386
diff options
context:
space:
mode:
Diffstat (limited to 'arch/i386')
-rw-r--r--arch/i386/kernel/cpu/mtrr/cyrix.c2
-rw-r--r--arch/i386/kernel/cpu/mtrr/state.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/i386/kernel/cpu/mtrr/cyrix.c b/arch/i386/kernel/cpu/mtrr/cyrix.c
index 0737a596db43..9edf5625584f 100644
--- a/arch/i386/kernel/cpu/mtrr/cyrix.c
+++ b/arch/i386/kernel/cpu/mtrr/cyrix.c
@@ -136,7 +136,7 @@ static void prepare_set(void)
136 /* Save value of CR4 and clear Page Global Enable (bit 7) */ 136 /* Save value of CR4 and clear Page Global Enable (bit 7) */
137 if ( cpu_has_pge ) { 137 if ( cpu_has_pge ) {
138 cr4 = read_cr4(); 138 cr4 = read_cr4();
139 write_cr4(cr4 & (unsigned char) ~(1 << 7)); 139 write_cr4(cr4 & ~X86_CR4_PGE);
140 } 140 }
141 141
142 /* Disable and flush caches. Note that wbinvd flushes the TLBs as 142 /* Disable and flush caches. Note that wbinvd flushes the TLBs as
diff --git a/arch/i386/kernel/cpu/mtrr/state.c b/arch/i386/kernel/cpu/mtrr/state.c
index f62ecd15811a..7b39a2f954d9 100644
--- a/arch/i386/kernel/cpu/mtrr/state.c
+++ b/arch/i386/kernel/cpu/mtrr/state.c
@@ -19,7 +19,7 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
19 /* Save value of CR4 and clear Page Global Enable (bit 7) */ 19 /* Save value of CR4 and clear Page Global Enable (bit 7) */
20 if ( cpu_has_pge ) { 20 if ( cpu_has_pge ) {
21 ctxt->cr4val = read_cr4(); 21 ctxt->cr4val = read_cr4();
22 write_cr4(ctxt->cr4val & (unsigned char) ~(1 << 7)); 22 write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
23 } 23 }
24 24
25 /* Disable and flush caches. Note that wbinvd flushes the TLBs as 25 /* Disable and flush caches. Note that wbinvd flushes the TLBs as