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-rw-r--r--arch/i386/kernel/cpu/centaur.c4
-rw-r--r--arch/i386/kernel/cpu/intel_cacheinfo.c11
-rw-r--r--arch/i386/kernel/cpu/mtrr/main.c15
3 files changed, 17 insertions, 13 deletions
diff --git a/arch/i386/kernel/cpu/centaur.c b/arch/i386/kernel/cpu/centaur.c
index 394814e57672..0dd92a23d622 100644
--- a/arch/i386/kernel/cpu/centaur.c
+++ b/arch/i386/kernel/cpu/centaur.c
@@ -405,10 +405,6 @@ static void __init init_centaur(struct cpuinfo_x86 *c)
405 winchip2_protect_mcr(); 405 winchip2_protect_mcr();
406#endif 406#endif
407 break; 407 break;
408 case 10:
409 name="4";
410 /* no info on the WC4 yet */
411 break;
412 default: 408 default:
413 name="??"; 409 name="??";
414 } 410 }
diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c
index fbfd374aa336..af591c73345f 100644
--- a/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ b/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -43,13 +43,23 @@ static struct _cache_table cache_table[] __cpuinitdata =
43 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */ 43 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
44 { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */ 44 { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
45 { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */ 45 { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
46 { 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
46 { 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */ 47 { 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
47 { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */ 48 { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
49 { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
50 { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
48 { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */ 51 { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
49 { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */ 52 { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
50 { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */ 53 { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
51 { 0x44, LVL_2, 1024 }, /* 4-way set assoc, 32 byte line size */ 54 { 0x44, LVL_2, 1024 }, /* 4-way set assoc, 32 byte line size */
52 { 0x45, LVL_2, 2048 }, /* 4-way set assoc, 32 byte line size */ 55 { 0x45, LVL_2, 2048 }, /* 4-way set assoc, 32 byte line size */
56 { 0x46, LVL_3, 4096 }, /* 4-way set assoc, 64 byte line size */
57 { 0x47, LVL_3, 8192 }, /* 8-way set assoc, 64 byte line size */
58 { 0x49, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
59 { 0x4a, LVL_3, 6144 }, /* 12-way set assoc, 64 byte line size */
60 { 0x4b, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
61 { 0x4c, LVL_3, 12288 }, /* 12-way set assoc, 64 byte line size */
62 { 0x4d, LVL_3, 16384 }, /* 16-way set assoc, 64 byte line size */
53 { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */ 63 { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
54 { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */ 64 { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
55 { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */ 65 { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
@@ -57,6 +67,7 @@ static struct _cache_table cache_table[] __cpuinitdata =
57 { 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */ 67 { 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
58 { 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */ 68 { 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
59 { 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */ 69 { 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
70 { 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */
60 { 0x78, LVL_2, 1024 }, /* 4-way set assoc, 64 byte line size */ 71 { 0x78, LVL_2, 1024 }, /* 4-way set assoc, 64 byte line size */
61 { 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */ 72 { 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
62 { 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */ 73 { 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
diff --git a/arch/i386/kernel/cpu/mtrr/main.c b/arch/i386/kernel/cpu/mtrr/main.c
index 1e9db198c440..3b4618bed70d 100644
--- a/arch/i386/kernel/cpu/mtrr/main.c
+++ b/arch/i386/kernel/cpu/mtrr/main.c
@@ -44,12 +44,10 @@
44#include <asm/msr.h> 44#include <asm/msr.h>
45#include "mtrr.h" 45#include "mtrr.h"
46 46
47#define MTRR_VERSION "2.0 (20020519)"
48
49u32 num_var_ranges = 0; 47u32 num_var_ranges = 0;
50 48
51unsigned int *usage_table; 49unsigned int *usage_table;
52static DECLARE_MUTEX(main_lock); 50static DECLARE_MUTEX(mtrr_sem);
53 51
54u32 size_or_mask, size_and_mask; 52u32 size_or_mask, size_and_mask;
55 53
@@ -335,7 +333,7 @@ int mtrr_add_page(unsigned long base, unsigned long size,
335 /* No CPU hotplug when we change MTRR entries */ 333 /* No CPU hotplug when we change MTRR entries */
336 lock_cpu_hotplug(); 334 lock_cpu_hotplug();
337 /* Search for existing MTRR */ 335 /* Search for existing MTRR */
338 down(&main_lock); 336 down(&mtrr_sem);
339 for (i = 0; i < num_var_ranges; ++i) { 337 for (i = 0; i < num_var_ranges; ++i) {
340 mtrr_if->get(i, &lbase, &lsize, &ltype); 338 mtrr_if->get(i, &lbase, &lsize, &ltype);
341 if (base >= lbase + lsize) 339 if (base >= lbase + lsize)
@@ -373,7 +371,7 @@ int mtrr_add_page(unsigned long base, unsigned long size,
373 printk(KERN_INFO "mtrr: no more MTRRs available\n"); 371 printk(KERN_INFO "mtrr: no more MTRRs available\n");
374 error = i; 372 error = i;
375 out: 373 out:
376 up(&main_lock); 374 up(&mtrr_sem);
377 unlock_cpu_hotplug(); 375 unlock_cpu_hotplug();
378 return error; 376 return error;
379} 377}
@@ -466,7 +464,7 @@ int mtrr_del_page(int reg, unsigned long base, unsigned long size)
466 max = num_var_ranges; 464 max = num_var_ranges;
467 /* No CPU hotplug when we change MTRR entries */ 465 /* No CPU hotplug when we change MTRR entries */
468 lock_cpu_hotplug(); 466 lock_cpu_hotplug();
469 down(&main_lock); 467 down(&mtrr_sem);
470 if (reg < 0) { 468 if (reg < 0) {
471 /* Search for existing MTRR */ 469 /* Search for existing MTRR */
472 for (i = 0; i < max; ++i) { 470 for (i = 0; i < max; ++i) {
@@ -505,7 +503,7 @@ int mtrr_del_page(int reg, unsigned long base, unsigned long size)
505 set_mtrr(reg, 0, 0, 0); 503 set_mtrr(reg, 0, 0, 0);
506 error = reg; 504 error = reg;
507 out: 505 out:
508 up(&main_lock); 506 up(&mtrr_sem);
509 unlock_cpu_hotplug(); 507 unlock_cpu_hotplug();
510 return error; 508 return error;
511} 509}
@@ -671,7 +669,6 @@ void __init mtrr_bp_init(void)
671 break; 669 break;
672 } 670 }
673 } 671 }
674 printk(KERN_INFO "mtrr: v%s\n",MTRR_VERSION);
675 672
676 if (mtrr_if) { 673 if (mtrr_if) {
677 set_num_var_ranges(); 674 set_num_var_ranges();
@@ -688,7 +685,7 @@ void mtrr_ap_init(void)
688 if (!mtrr_if || !use_intel()) 685 if (!mtrr_if || !use_intel())
689 return; 686 return;
690 /* 687 /*
691 * Ideally we should hold main_lock here to avoid mtrr entries changed, 688 * Ideally we should hold mtrr_sem here to avoid mtrr entries changed,
692 * but this routine will be called in cpu boot time, holding the lock 689 * but this routine will be called in cpu boot time, holding the lock
693 * breaks it. This routine is called in two cases: 1.very earily time 690 * breaks it. This routine is called in two cases: 1.very earily time
694 * of software resume, when there absolutely isn't mtrr entry changes; 691 * of software resume, when there absolutely isn't mtrr entry changes;