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-rw-r--r--arch/i386/pci/i386.c315
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diff --git a/arch/i386/pci/i386.c b/arch/i386/pci/i386.c
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--- a/arch/i386/pci/i386.c
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1/*
2 * Low-Level PCI Access for i386 machines
3 *
4 * Copyright 1993, 1994 Drew Eckhardt
5 * Visionary Computing
6 * (Unix and Linux consulting and custom programming)
7 * Drew@Colorado.EDU
8 * +1 (303) 786-7975
9 *
10 * Drew's work was sponsored by:
11 * iX Multiuser Multitasking Magazine
12 * Hannover, Germany
13 * hm@ix.de
14 *
15 * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
16 *
17 * For more information, please consult the following manuals (look at
18 * http://www.pcisig.com/ for how to get them):
19 *
20 * PCI BIOS Specification
21 * PCI Local Bus Specification
22 * PCI to PCI Bridge Specification
23 * PCI System Design Guide
24 *
25 */
26
27#include <linux/types.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/ioport.h>
32#include <linux/errno.h>
33
34#include "pci.h"
35
36/*
37 * We need to avoid collisions with `mirrored' VGA ports
38 * and other strange ISA hardware, so we always want the
39 * addresses to be allocated in the 0x000-0x0ff region
40 * modulo 0x400.
41 *
42 * Why? Because some silly external IO cards only decode
43 * the low 10 bits of the IO address. The 0x00-0xff region
44 * is reserved for motherboard devices that decode all 16
45 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
46 * but we want to try to avoid allocating at 0x2900-0x2bff
47 * which might have be mirrored at 0x0100-0x03ff..
48 */
49void
50pcibios_align_resource(void *data, struct resource *res,
51 resource_size_t size, resource_size_t align)
52{
53 if (res->flags & IORESOURCE_IO) {
54 resource_size_t start = res->start;
55
56 if (start & 0x300) {
57 start = (start + 0x3ff) & ~0x3ff;
58 res->start = start;
59 }
60 }
61}
62
63
64/*
65 * Handle resources of PCI devices. If the world were perfect, we could
66 * just allocate all the resource regions and do nothing more. It isn't.
67 * On the other hand, we cannot just re-allocate all devices, as it would
68 * require us to know lots of host bridge internals. So we attempt to
69 * keep as much of the original configuration as possible, but tweak it
70 * when it's found to be wrong.
71 *
72 * Known BIOS problems we have to work around:
73 * - I/O or memory regions not configured
74 * - regions configured, but not enabled in the command register
75 * - bogus I/O addresses above 64K used
76 * - expansion ROMs left enabled (this may sound harmless, but given
77 * the fact the PCI specs explicitly allow address decoders to be
78 * shared between expansion ROMs and other resource regions, it's
79 * at least dangerous)
80 *
81 * Our solution:
82 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
83 * This gives us fixed barriers on where we can allocate.
84 * (2) Allocate resources for all enabled devices. If there is
85 * a collision, just mark the resource as unallocated. Also
86 * disable expansion ROMs during this step.
87 * (3) Try to allocate resources for disabled devices. If the
88 * resources were assigned correctly, everything goes well,
89 * if they weren't, they won't disturb allocation of other
90 * resources.
91 * (4) Assign new addresses to resources which were either
92 * not configured at all or misconfigured. If explicitly
93 * requested by the user, configure expansion ROM address
94 * as well.
95 */
96
97static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
98{
99 struct pci_bus *bus;
100 struct pci_dev *dev;
101 int idx;
102 struct resource *r, *pr;
103
104 /* Depth-First Search on bus tree */
105 list_for_each_entry(bus, bus_list, node) {
106 if ((dev = bus->self)) {
107 for (idx = PCI_BRIDGE_RESOURCES;
108 idx < PCI_NUM_RESOURCES; idx++) {
109 r = &dev->resource[idx];
110 if (!r->flags)
111 continue;
112 pr = pci_find_parent_resource(dev, r);
113 if (!r->start || !pr ||
114 request_resource(pr, r) < 0) {
115 printk(KERN_ERR "PCI: Cannot allocate "
116 "resource region %d "
117 "of bridge %s\n",
118 idx, pci_name(dev));
119 /*
120 * Something is wrong with the region.
121 * Invalidate the resource to prevent
122 * child resource allocations in this
123 * range.
124 */
125 r->flags = 0;
126 }
127 }
128 }
129 pcibios_allocate_bus_resources(&bus->children);
130 }
131}
132
133static void __init pcibios_allocate_resources(int pass)
134{
135 struct pci_dev *dev = NULL;
136 int idx, disabled;
137 u16 command;
138 struct resource *r, *pr;
139
140 for_each_pci_dev(dev) {
141 pci_read_config_word(dev, PCI_COMMAND, &command);
142 for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
143 r = &dev->resource[idx];
144 if (r->parent) /* Already allocated */
145 continue;
146 if (!r->start) /* Address not assigned at all */
147 continue;
148 if (r->flags & IORESOURCE_IO)
149 disabled = !(command & PCI_COMMAND_IO);
150 else
151 disabled = !(command & PCI_COMMAND_MEMORY);
152 if (pass == disabled) {
153 DBG("PCI: Resource %08lx-%08lx "
154 "(f=%lx, d=%d, p=%d)\n",
155 r->start, r->end, r->flags, disabled, pass);
156 pr = pci_find_parent_resource(dev, r);
157 if (!pr || request_resource(pr, r) < 0) {
158 printk(KERN_ERR "PCI: Cannot allocate "
159 "resource region %d "
160 "of device %s\n",
161 idx, pci_name(dev));
162 /* We'll assign a new address later */
163 r->end -= r->start;
164 r->start = 0;
165 }
166 }
167 }
168 if (!pass) {
169 r = &dev->resource[PCI_ROM_RESOURCE];
170 if (r->flags & IORESOURCE_ROM_ENABLE) {
171 /* Turn the ROM off, leave the resource region,
172 * but keep it unregistered. */
173 u32 reg;
174 DBG("PCI: Switching off ROM of %s\n",
175 pci_name(dev));
176 r->flags &= ~IORESOURCE_ROM_ENABLE;
177 pci_read_config_dword(dev,
178 dev->rom_base_reg, &reg);
179 pci_write_config_dword(dev, dev->rom_base_reg,
180 reg & ~PCI_ROM_ADDRESS_ENABLE);
181 }
182 }
183 }
184}
185
186static int __init pcibios_assign_resources(void)
187{
188 struct pci_dev *dev = NULL;
189 struct resource *r, *pr;
190
191 if (!(pci_probe & PCI_ASSIGN_ROMS)) {
192 /*
193 * Try to use BIOS settings for ROMs, otherwise let
194 * pci_assign_unassigned_resources() allocate the new
195 * addresses.
196 */
197 for_each_pci_dev(dev) {
198 r = &dev->resource[PCI_ROM_RESOURCE];
199 if (!r->flags || !r->start)
200 continue;
201 pr = pci_find_parent_resource(dev, r);
202 if (!pr || request_resource(pr, r) < 0) {
203 r->end -= r->start;
204 r->start = 0;
205 }
206 }
207 }
208
209 pci_assign_unassigned_resources();
210
211 return 0;
212}
213
214void __init pcibios_resource_survey(void)
215{
216 DBG("PCI: Allocating resources\n");
217 pcibios_allocate_bus_resources(&pci_root_buses);
218 pcibios_allocate_resources(0);
219 pcibios_allocate_resources(1);
220}
221
222/**
223 * called in fs_initcall (one below subsys_initcall),
224 * give a chance for motherboard reserve resources
225 */
226fs_initcall(pcibios_assign_resources);
227
228int pcibios_enable_resources(struct pci_dev *dev, int mask)
229{
230 u16 cmd, old_cmd;
231 int idx;
232 struct resource *r;
233
234 pci_read_config_word(dev, PCI_COMMAND, &cmd);
235 old_cmd = cmd;
236 for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
237 /* Only set up the requested stuff */
238 if (!(mask & (1 << idx)))
239 continue;
240
241 r = &dev->resource[idx];
242 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
243 continue;
244 if ((idx == PCI_ROM_RESOURCE) &&
245 (!(r->flags & IORESOURCE_ROM_ENABLE)))
246 continue;
247 if (!r->start && r->end) {
248 printk(KERN_ERR "PCI: Device %s not available "
249 "because of resource %d collisions\n",
250 pci_name(dev), idx);
251 return -EINVAL;
252 }
253 if (r->flags & IORESOURCE_IO)
254 cmd |= PCI_COMMAND_IO;
255 if (r->flags & IORESOURCE_MEM)
256 cmd |= PCI_COMMAND_MEMORY;
257 }
258 if (cmd != old_cmd) {
259 printk("PCI: Enabling device %s (%04x -> %04x)\n",
260 pci_name(dev), old_cmd, cmd);
261 pci_write_config_word(dev, PCI_COMMAND, cmd);
262 }
263 return 0;
264}
265
266/*
267 * If we set up a device for bus mastering, we need to check the latency
268 * timer as certain crappy BIOSes forget to set it properly.
269 */
270unsigned int pcibios_max_latency = 255;
271
272void pcibios_set_master(struct pci_dev *dev)
273{
274 u8 lat;
275 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
276 if (lat < 16)
277 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
278 else if (lat > pcibios_max_latency)
279 lat = pcibios_max_latency;
280 else
281 return;
282 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
283 pci_name(dev), lat);
284 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
285}
286
287int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
288 enum pci_mmap_state mmap_state, int write_combine)
289{
290 unsigned long prot;
291
292 /* I/O space cannot be accessed via normal processor loads and
293 * stores on this platform.
294 */
295 if (mmap_state == pci_mmap_io)
296 return -EINVAL;
297
298 /* Leave vm_pgoff as-is, the PCI space address is the physical
299 * address on this platform.
300 */
301 prot = pgprot_val(vma->vm_page_prot);
302 if (boot_cpu_data.x86 > 3)
303 prot |= _PAGE_PCD | _PAGE_PWT;
304 vma->vm_page_prot = __pgprot(prot);
305
306 /* Write-combine setting is ignored, it is changed via the mtrr
307 * interfaces on this platform.
308 */
309 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
310 vma->vm_end - vma->vm_start,
311 vma->vm_page_prot))
312 return -EAGAIN;
313
314 return 0;
315}
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