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-rw-r--r--arch/i386/mach-visws/Makefile8
-rw-r--r--arch/i386/mach-visws/mpparse.c101
-rw-r--r--arch/i386/mach-visws/reboot.c55
-rw-r--r--arch/i386/mach-visws/setup.c183
-rw-r--r--arch/i386/mach-visws/traps.c68
-rw-r--r--arch/i386/mach-visws/visws_apic.c299
6 files changed, 0 insertions, 714 deletions
diff --git a/arch/i386/mach-visws/Makefile b/arch/i386/mach-visws/Makefile
deleted file mode 100644
index 835fd96ad768..000000000000
--- a/arch/i386/mach-visws/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := setup.o traps.o reboot.o
6
7obj-$(CONFIG_X86_VISWS_APIC) += visws_apic.o
8obj-$(CONFIG_X86_LOCAL_APIC) += mpparse.o
diff --git a/arch/i386/mach-visws/mpparse.c b/arch/i386/mach-visws/mpparse.c
deleted file mode 100644
index f3c74fab8b95..000000000000
--- a/arch/i386/mach-visws/mpparse.c
+++ /dev/null
@@ -1,101 +0,0 @@
1
2#include <linux/init.h>
3#include <linux/smp.h>
4
5#include <asm/smp.h>
6#include <asm/io.h>
7
8#include "cobalt.h"
9#include "mach_apic.h"
10
11/* Have we found an MP table */
12int smp_found_config;
13
14/*
15 * Various Linux-internal data structures created from the
16 * MP-table.
17 */
18int apic_version [MAX_APICS];
19
20int pic_mode;
21unsigned long mp_lapic_addr;
22
23/* Processor that is doing the boot up */
24unsigned int boot_cpu_physical_apicid = -1U;
25
26/* Bitmask of physically existing CPUs */
27physid_mask_t phys_cpu_present_map;
28
29unsigned int __initdata maxcpus = NR_CPUS;
30
31/*
32 * The Visual Workstation is Intel MP compliant in the hardware
33 * sense, but it doesn't have a BIOS(-configuration table).
34 * No problem for Linux.
35 */
36
37static void __init MP_processor_info (struct mpc_config_processor *m)
38{
39 int ver, logical_apicid;
40 physid_mask_t apic_cpus;
41
42 if (!(m->mpc_cpuflag & CPU_ENABLED))
43 return;
44
45 logical_apicid = m->mpc_apicid;
46 printk(KERN_INFO "%sCPU #%d %ld:%ld APIC version %d\n",
47 m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
48 m->mpc_apicid,
49 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
50 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
51 m->mpc_apicver);
52
53 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
54 boot_cpu_physical_apicid = m->mpc_apicid;
55
56 ver = m->mpc_apicver;
57 if ((ver >= 0x14 && m->mpc_apicid >= 0xff) || m->mpc_apicid >= 0xf) {
58 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
59 m->mpc_apicid, MAX_APICS);
60 return;
61 }
62
63 apic_cpus = apicid_to_cpu_present(m->mpc_apicid);
64 physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
65 /*
66 * Validate version
67 */
68 if (ver == 0x0) {
69 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
70 "fixing up to 0x10. (tell your hw vendor)\n",
71 m->mpc_apicid);
72 ver = 0x10;
73 }
74 apic_version[m->mpc_apicid] = ver;
75}
76
77void __init find_smp_config(void)
78{
79 struct mpc_config_processor *mp = phys_to_virt(CO_CPU_TAB_PHYS);
80 unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
81
82 if (ncpus > CO_CPU_MAX) {
83 printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
84 ncpus, mp);
85
86 ncpus = CO_CPU_MAX;
87 }
88
89 if (ncpus > maxcpus)
90 ncpus = maxcpus;
91
92 smp_found_config = 1;
93 while (ncpus--)
94 MP_processor_info(mp++);
95
96 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
97}
98
99void __init get_smp_config (void)
100{
101}
diff --git a/arch/i386/mach-visws/reboot.c b/arch/i386/mach-visws/reboot.c
deleted file mode 100644
index 99332abfad42..000000000000
--- a/arch/i386/mach-visws/reboot.c
+++ /dev/null
@@ -1,55 +0,0 @@
1#include <linux/module.h>
2#include <linux/smp.h>
3#include <linux/delay.h>
4
5#include <asm/io.h>
6#include "piix4.h"
7
8void (*pm_power_off)(void);
9EXPORT_SYMBOL(pm_power_off);
10
11void machine_shutdown(void)
12{
13#ifdef CONFIG_SMP
14 smp_send_stop();
15#endif
16}
17
18void machine_emergency_restart(void)
19{
20 /*
21 * Visual Workstations restart after this
22 * register is poked on the PIIX4
23 */
24 outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
25}
26
27void machine_restart(char * __unused)
28{
29 machine_shutdown();
30 machine_emergency_restart();
31}
32
33void machine_power_off(void)
34{
35 unsigned short pm_status;
36 extern unsigned int pci_bus0;
37
38 while ((pm_status = inw(PMSTS_PORT)) & 0x100)
39 outw(pm_status, PMSTS_PORT);
40
41 outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
42
43 mdelay(10);
44
45#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
46 (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
47
48 outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8);
49 outl(PIIX_SPECIAL_STOP, 0xCFC);
50}
51
52void machine_halt(void)
53{
54}
55
diff --git a/arch/i386/mach-visws/setup.c b/arch/i386/mach-visws/setup.c
deleted file mode 100644
index 1f81f10e03a0..000000000000
--- a/arch/i386/mach-visws/setup.c
+++ /dev/null
@@ -1,183 +0,0 @@
1/*
2 * Unmaintained SGI Visual Workstation support.
3 * Split out from setup.c by davej@suse.de
4 */
5
6#include <linux/smp.h>
7#include <linux/init.h>
8#include <linux/interrupt.h>
9#include <linux/module.h>
10
11#include <asm/fixmap.h>
12#include <asm/arch_hooks.h>
13#include <asm/io.h>
14#include <asm/e820.h>
15#include <asm/setup.h>
16#include "cobalt.h"
17#include "piix4.h"
18
19int no_broadcast;
20
21char visws_board_type = -1;
22char visws_board_rev = -1;
23
24void __init visws_get_board_type_and_rev(void)
25{
26 int raw;
27
28 visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
29 >> PIIX_GPI_BD_SHIFT;
30 /*
31 * Get Board rev.
32 * First, we have to initialize the 307 part to allow us access
33 * to the GPIO registers. Let's map them at 0x0fc0 which is right
34 * after the PIIX4 PM section.
35 */
36 outb_p(SIO_DEV_SEL, SIO_INDEX);
37 outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */
38
39 outb_p(SIO_DEV_MSB, SIO_INDEX);
40 outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */
41
42 outb_p(SIO_DEV_LSB, SIO_INDEX);
43 outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */
44
45 outb_p(SIO_DEV_ENB, SIO_INDEX);
46 outb_p(1, SIO_DATA); /* Enable GPIO registers. */
47
48 /*
49 * Now, we have to map the power management section to write
50 * a bit which enables access to the GPIO registers.
51 * What lunatic came up with this shit?
52 */
53 outb_p(SIO_DEV_SEL, SIO_INDEX);
54 outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */
55
56 outb_p(SIO_DEV_MSB, SIO_INDEX);
57 outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */
58
59 outb_p(SIO_DEV_LSB, SIO_INDEX);
60 outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */
61
62 outb_p(SIO_DEV_ENB, SIO_INDEX);
63 outb_p(1, SIO_DATA); /* Enable PM registers. */
64
65 /*
66 * Now, write the PM register which enables the GPIO registers.
67 */
68 outb_p(SIO_PM_FER2, SIO_PM_INDEX);
69 outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
70
71 /*
72 * Now, initialize the GPIO registers.
73 * We want them all to be inputs which is the
74 * power on default, so let's leave them alone.
75 * So, let's just read the board rev!
76 */
77 raw = inb_p(SIO_GP_DATA1);
78 raw &= 0x7f; /* 7 bits of valid board revision ID. */
79
80 if (visws_board_type == VISWS_320) {
81 if (raw < 0x6) {
82 visws_board_rev = 4;
83 } else if (raw < 0xc) {
84 visws_board_rev = 5;
85 } else {
86 visws_board_rev = 6;
87 }
88 } else if (visws_board_type == VISWS_540) {
89 visws_board_rev = 2;
90 } else {
91 visws_board_rev = raw;
92 }
93
94 printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
95 (visws_board_type == VISWS_320 ? "320" :
96 (visws_board_type == VISWS_540 ? "540" :
97 "unknown")), visws_board_rev);
98}
99
100void __init pre_intr_init_hook(void)
101{
102 init_VISWS_APIC_irqs();
103}
104
105void __init intr_init_hook(void)
106{
107#ifdef CONFIG_X86_LOCAL_APIC
108 apic_intr_init();
109#endif
110}
111
112void __init pre_setup_arch_hook()
113{
114 visws_get_board_type_and_rev();
115}
116
117static struct irqaction irq0 = {
118 .handler = timer_interrupt,
119 .flags = IRQF_DISABLED | IRQF_IRQPOLL,
120 .name = "timer",
121};
122
123void __init time_init_hook(void)
124{
125 printk(KERN_INFO "Starting Cobalt Timer system clock\n");
126
127 /* Set the countdown value */
128 co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
129
130 /* Start the timer */
131 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
132
133 /* Enable (unmask) the timer interrupt */
134 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
135
136 /* Wire cpu IDT entry to s/w handler (and Cobalt APIC to IDT) */
137 setup_irq(0, &irq0);
138}
139
140/* Hook for machine specific memory setup. */
141
142#define MB (1024 * 1024)
143
144unsigned long sgivwfb_mem_phys;
145unsigned long sgivwfb_mem_size;
146EXPORT_SYMBOL(sgivwfb_mem_phys);
147EXPORT_SYMBOL(sgivwfb_mem_size);
148
149long long mem_size __initdata = 0;
150
151char * __init machine_specific_memory_setup(void)
152{
153 long long gfx_mem_size = 8 * MB;
154
155 mem_size = ALT_MEM_K;
156
157 if (!mem_size) {
158 printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
159 mem_size = 128 * MB;
160 }
161
162 /*
163 * this hardcodes the graphics memory to 8 MB
164 * it really should be sized dynamically (or at least
165 * set as a boot param)
166 */
167 if (!sgivwfb_mem_size) {
168 printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
169 sgivwfb_mem_size = 8 * MB;
170 }
171
172 /*
173 * Trim to nearest MB
174 */
175 sgivwfb_mem_size &= ~((1 << 20) - 1);
176 sgivwfb_mem_phys = mem_size - gfx_mem_size;
177
178 add_memory_region(0, LOWMEMSIZE(), E820_RAM);
179 add_memory_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
180 add_memory_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
181
182 return "PROM";
183}
diff --git a/arch/i386/mach-visws/traps.c b/arch/i386/mach-visws/traps.c
deleted file mode 100644
index 843b67acf43b..000000000000
--- a/arch/i386/mach-visws/traps.c
+++ /dev/null
@@ -1,68 +0,0 @@
1/* VISWS traps */
2
3#include <linux/sched.h>
4#include <linux/kernel.h>
5#include <linux/init.h>
6#include <linux/pci.h>
7#include <linux/pci_ids.h>
8
9#include <asm/io.h>
10#include <asm/arch_hooks.h>
11#include <asm/apic.h>
12#include "cobalt.h"
13#include "lithium.h"
14
15
16#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
17#define BCD (LI_INTB | LI_INTC | LI_INTD)
18#define ALLDEVS (A01234 | BCD)
19
20static __init void lithium_init(void)
21{
22 set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
23 set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
24
25 if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
26 (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
27 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
28 panic("This machine is not SGI Visual Workstation 320/540");
29 }
30
31 if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
32 (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
33 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
34 panic("This machine is not SGI Visual Workstation 320/540");
35 }
36
37 li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
38 li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
39}
40
41static __init void cobalt_init(void)
42{
43 /*
44 * On normal SMP PC this is used only with SMP, but we have to
45 * use it and set it up here to start the Cobalt clock
46 */
47 set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
48 setup_local_APIC();
49 printk(KERN_INFO "Local APIC Version %#lx, ID %#lx\n",
50 apic_read(APIC_LVR), apic_read(APIC_ID));
51
52 set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
53 set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
54 printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
55 co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
56
57 /* Enable Cobalt APIC being careful to NOT change the ID! */
58 co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
59
60 printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
61 co_apic_read(CO_APIC_ID));
62}
63
64void __init trap_init_hook(void)
65{
66 lithium_init();
67 cobalt_init();
68}
diff --git a/arch/i386/mach-visws/visws_apic.c b/arch/i386/mach-visws/visws_apic.c
deleted file mode 100644
index 710faf71a650..000000000000
--- a/arch/i386/mach-visws/visws_apic.c
+++ /dev/null
@@ -1,299 +0,0 @@
1/*
2 * linux/arch/i386/mach-visws/visws_apic.c
3 *
4 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
5 *
6 * SGI Visual Workstation interrupt controller
7 *
8 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
9 * which serves as the main interrupt controller in the system. Non-legacy
10 * hardware in the system uses this controller directly. Legacy devices
11 * are connected to the PIIX4 which in turn has its 8259(s) connected to
12 * a of the Cobalt APIC entry.
13 *
14 * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
15 *
16 * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
17 */
18
19#include <linux/kernel_stat.h>
20#include <linux/interrupt.h>
21#include <linux/init.h>
22
23#include <asm/io.h>
24#include <asm/apic.h>
25#include <asm/i8259.h>
26
27#include "cobalt.h"
28#include "irq_vectors.h"
29
30
31static DEFINE_SPINLOCK(cobalt_lock);
32
33/*
34 * Set the given Cobalt APIC Redirection Table entry to point
35 * to the given IDT vector/index.
36 */
37static inline void co_apic_set(int entry, int irq)
38{
39 co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
40 co_apic_write(CO_APIC_HI(entry), 0);
41}
42
43/*
44 * Cobalt (IO)-APIC functions to handle PCI devices.
45 */
46static inline int co_apic_ide0_hack(void)
47{
48 extern char visws_board_type;
49 extern char visws_board_rev;
50
51 if (visws_board_type == VISWS_320 && visws_board_rev == 5)
52 return 5;
53 return CO_APIC_IDE0;
54}
55
56static int is_co_apic(unsigned int irq)
57{
58 if (IS_CO_APIC(irq))
59 return CO_APIC(irq);
60
61 switch (irq) {
62 case 0: return CO_APIC_CPU;
63 case CO_IRQ_IDE0: return co_apic_ide0_hack();
64 case CO_IRQ_IDE1: return CO_APIC_IDE1;
65 default: return -1;
66 }
67}
68
69
70/*
71 * This is the SGI Cobalt (IO-)APIC:
72 */
73
74static void enable_cobalt_irq(unsigned int irq)
75{
76 co_apic_set(is_co_apic(irq), irq);
77}
78
79static void disable_cobalt_irq(unsigned int irq)
80{
81 int entry = is_co_apic(irq);
82
83 co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
84 co_apic_read(CO_APIC_LO(entry));
85}
86
87/*
88 * "irq" really just serves to identify the device. Here is where we
89 * map this to the Cobalt APIC entry where it's physically wired.
90 * This is called via request_irq -> setup_irq -> irq_desc->startup()
91 */
92static unsigned int startup_cobalt_irq(unsigned int irq)
93{
94 unsigned long flags;
95
96 spin_lock_irqsave(&cobalt_lock, flags);
97 if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
98 irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
99 enable_cobalt_irq(irq);
100 spin_unlock_irqrestore(&cobalt_lock, flags);
101 return 0;
102}
103
104static void ack_cobalt_irq(unsigned int irq)
105{
106 unsigned long flags;
107
108 spin_lock_irqsave(&cobalt_lock, flags);
109 disable_cobalt_irq(irq);
110 apic_write(APIC_EOI, APIC_EIO_ACK);
111 spin_unlock_irqrestore(&cobalt_lock, flags);
112}
113
114static void end_cobalt_irq(unsigned int irq)
115{
116 unsigned long flags;
117
118 spin_lock_irqsave(&cobalt_lock, flags);
119 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
120 enable_cobalt_irq(irq);
121 spin_unlock_irqrestore(&cobalt_lock, flags);
122}
123
124static struct irq_chip cobalt_irq_type = {
125 .typename = "Cobalt-APIC",
126 .startup = startup_cobalt_irq,
127 .shutdown = disable_cobalt_irq,
128 .enable = enable_cobalt_irq,
129 .disable = disable_cobalt_irq,
130 .ack = ack_cobalt_irq,
131 .end = end_cobalt_irq,
132};
133
134
135/*
136 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
137 * -- not the manner expected by the code in i8259.c.
138 *
139 * there is a 'master' physical interrupt source that gets sent to
140 * the CPU. But in the chipset there are various 'virtual' interrupts
141 * waiting to be handled. We represent this to Linux through a 'master'
142 * interrupt controller type, and through a special virtual interrupt-
143 * controller. Device drivers only see the virtual interrupt sources.
144 */
145static unsigned int startup_piix4_master_irq(unsigned int irq)
146{
147 init_8259A(0);
148
149 return startup_cobalt_irq(irq);
150}
151
152static void end_piix4_master_irq(unsigned int irq)
153{
154 unsigned long flags;
155
156 spin_lock_irqsave(&cobalt_lock, flags);
157 enable_cobalt_irq(irq);
158 spin_unlock_irqrestore(&cobalt_lock, flags);
159}
160
161static struct irq_chip piix4_master_irq_type = {
162 .typename = "PIIX4-master",
163 .startup = startup_piix4_master_irq,
164 .ack = ack_cobalt_irq,
165 .end = end_piix4_master_irq,
166};
167
168
169static struct irq_chip piix4_virtual_irq_type = {
170 .typename = "PIIX4-virtual",
171 .shutdown = disable_8259A_irq,
172 .enable = enable_8259A_irq,
173 .disable = disable_8259A_irq,
174};
175
176
177/*
178 * PIIX4-8259 master/virtual functions to handle interrupt requests
179 * from legacy devices: floppy, parallel, serial, rtc.
180 *
181 * None of these get Cobalt APIC entries, neither do they have IDT
182 * entries. These interrupts are purely virtual and distributed from
183 * the 'master' interrupt source: CO_IRQ_8259.
184 *
185 * When the 8259 interrupts its handler figures out which of these
186 * devices is interrupting and dispatches to its handler.
187 *
188 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
189 * enable_irq gets the right irq. This 'master' irq is never directly
190 * manipulated by any driver.
191 */
192static irqreturn_t piix4_master_intr(int irq, void *dev_id)
193{
194 int realirq;
195 irq_desc_t *desc;
196 unsigned long flags;
197
198 spin_lock_irqsave(&i8259A_lock, flags);
199
200 /* Find out what's interrupting in the PIIX4 master 8259 */
201 outb(0x0c, 0x20); /* OCW3 Poll command */
202 realirq = inb(0x20);
203
204 /*
205 * Bit 7 == 0 means invalid/spurious
206 */
207 if (unlikely(!(realirq & 0x80)))
208 goto out_unlock;
209
210 realirq &= 7;
211
212 if (unlikely(realirq == 2)) {
213 outb(0x0c, 0xa0);
214 realirq = inb(0xa0);
215
216 if (unlikely(!(realirq & 0x80)))
217 goto out_unlock;
218
219 realirq = (realirq & 7) + 8;
220 }
221
222 /* mask and ack interrupt */
223 cached_irq_mask |= 1 << realirq;
224 if (unlikely(realirq > 7)) {
225 inb(0xa1);
226 outb(cached_slave_mask, 0xa1);
227 outb(0x60 + (realirq & 7), 0xa0);
228 outb(0x60 + 2, 0x20);
229 } else {
230 inb(0x21);
231 outb(cached_master_mask, 0x21);
232 outb(0x60 + realirq, 0x20);
233 }
234
235 spin_unlock_irqrestore(&i8259A_lock, flags);
236
237 desc = irq_desc + realirq;
238
239 /*
240 * handle this 'virtual interrupt' as a Cobalt one now.
241 */
242 kstat_cpu(smp_processor_id()).irqs[realirq]++;
243
244 if (likely(desc->action != NULL))
245 handle_IRQ_event(realirq, desc->action);
246
247 if (!(desc->status & IRQ_DISABLED))
248 enable_8259A_irq(realirq);
249
250 return IRQ_HANDLED;
251
252out_unlock:
253 spin_unlock_irqrestore(&i8259A_lock, flags);
254 return IRQ_NONE;
255}
256
257static struct irqaction master_action = {
258 .handler = piix4_master_intr,
259 .name = "PIIX4-8259",
260};
261
262static struct irqaction cascade_action = {
263 .handler = no_action,
264 .name = "cascade",
265};
266
267
268void init_VISWS_APIC_irqs(void)
269{
270 int i;
271
272 for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
273 irq_desc[i].status = IRQ_DISABLED;
274 irq_desc[i].action = 0;
275 irq_desc[i].depth = 1;
276
277 if (i == 0) {
278 irq_desc[i].chip = &cobalt_irq_type;
279 }
280 else if (i == CO_IRQ_IDE0) {
281 irq_desc[i].chip = &cobalt_irq_type;
282 }
283 else if (i == CO_IRQ_IDE1) {
284 irq_desc[i].chip = &cobalt_irq_type;
285 }
286 else if (i == CO_IRQ_8259) {
287 irq_desc[i].chip = &piix4_master_irq_type;
288 }
289 else if (i < CO_IRQ_APIC0) {
290 irq_desc[i].chip = &piix4_virtual_irq_type;
291 }
292 else if (IS_CO_APIC(i)) {
293 irq_desc[i].chip = &cobalt_irq_type;
294 }
295 }
296
297 setup_irq(CO_IRQ_8259, &master_action);
298 setup_irq(2, &cascade_action);
299}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 10:53:12 -0500