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-rw-r--r--arch/i386/mach-visws/visws_apic.c299
1 files changed, 0 insertions, 299 deletions
diff --git a/arch/i386/mach-visws/visws_apic.c b/arch/i386/mach-visws/visws_apic.c
deleted file mode 100644
index 710faf71a650..000000000000
--- a/arch/i386/mach-visws/visws_apic.c
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@@ -1,299 +0,0 @@
1/*
2 * linux/arch/i386/mach-visws/visws_apic.c
3 *
4 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
5 *
6 * SGI Visual Workstation interrupt controller
7 *
8 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
9 * which serves as the main interrupt controller in the system. Non-legacy
10 * hardware in the system uses this controller directly. Legacy devices
11 * are connected to the PIIX4 which in turn has its 8259(s) connected to
12 * a of the Cobalt APIC entry.
13 *
14 * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
15 *
16 * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
17 */
18
19#include <linux/kernel_stat.h>
20#include <linux/interrupt.h>
21#include <linux/init.h>
22
23#include <asm/io.h>
24#include <asm/apic.h>
25#include <asm/i8259.h>
26
27#include "cobalt.h"
28#include "irq_vectors.h"
29
30
31static DEFINE_SPINLOCK(cobalt_lock);
32
33/*
34 * Set the given Cobalt APIC Redirection Table entry to point
35 * to the given IDT vector/index.
36 */
37static inline void co_apic_set(int entry, int irq)
38{
39 co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
40 co_apic_write(CO_APIC_HI(entry), 0);
41}
42
43/*
44 * Cobalt (IO)-APIC functions to handle PCI devices.
45 */
46static inline int co_apic_ide0_hack(void)
47{
48 extern char visws_board_type;
49 extern char visws_board_rev;
50
51 if (visws_board_type == VISWS_320 && visws_board_rev == 5)
52 return 5;
53 return CO_APIC_IDE0;
54}
55
56static int is_co_apic(unsigned int irq)
57{
58 if (IS_CO_APIC(irq))
59 return CO_APIC(irq);
60
61 switch (irq) {
62 case 0: return CO_APIC_CPU;
63 case CO_IRQ_IDE0: return co_apic_ide0_hack();
64 case CO_IRQ_IDE1: return CO_APIC_IDE1;
65 default: return -1;
66 }
67}
68
69
70/*
71 * This is the SGI Cobalt (IO-)APIC:
72 */
73
74static void enable_cobalt_irq(unsigned int irq)
75{
76 co_apic_set(is_co_apic(irq), irq);
77}
78
79static void disable_cobalt_irq(unsigned int irq)
80{
81 int entry = is_co_apic(irq);
82
83 co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
84 co_apic_read(CO_APIC_LO(entry));
85}
86
87/*
88 * "irq" really just serves to identify the device. Here is where we
89 * map this to the Cobalt APIC entry where it's physically wired.
90 * This is called via request_irq -> setup_irq -> irq_desc->startup()
91 */
92static unsigned int startup_cobalt_irq(unsigned int irq)
93{
94 unsigned long flags;
95
96 spin_lock_irqsave(&cobalt_lock, flags);
97 if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
98 irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
99 enable_cobalt_irq(irq);
100 spin_unlock_irqrestore(&cobalt_lock, flags);
101 return 0;
102}
103
104static void ack_cobalt_irq(unsigned int irq)
105{
106 unsigned long flags;
107
108 spin_lock_irqsave(&cobalt_lock, flags);
109 disable_cobalt_irq(irq);
110 apic_write(APIC_EOI, APIC_EIO_ACK);
111 spin_unlock_irqrestore(&cobalt_lock, flags);
112}
113
114static void end_cobalt_irq(unsigned int irq)
115{
116 unsigned long flags;
117
118 spin_lock_irqsave(&cobalt_lock, flags);
119 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
120 enable_cobalt_irq(irq);
121 spin_unlock_irqrestore(&cobalt_lock, flags);
122}
123
124static struct irq_chip cobalt_irq_type = {
125 .typename = "Cobalt-APIC",
126 .startup = startup_cobalt_irq,
127 .shutdown = disable_cobalt_irq,
128 .enable = enable_cobalt_irq,
129 .disable = disable_cobalt_irq,
130 .ack = ack_cobalt_irq,
131 .end = end_cobalt_irq,
132};
133
134
135/*
136 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
137 * -- not the manner expected by the code in i8259.c.
138 *
139 * there is a 'master' physical interrupt source that gets sent to
140 * the CPU. But in the chipset there are various 'virtual' interrupts
141 * waiting to be handled. We represent this to Linux through a 'master'
142 * interrupt controller type, and through a special virtual interrupt-
143 * controller. Device drivers only see the virtual interrupt sources.
144 */
145static unsigned int startup_piix4_master_irq(unsigned int irq)
146{
147 init_8259A(0);
148
149 return startup_cobalt_irq(irq);
150}
151
152static void end_piix4_master_irq(unsigned int irq)
153{
154 unsigned long flags;
155
156 spin_lock_irqsave(&cobalt_lock, flags);
157 enable_cobalt_irq(irq);
158 spin_unlock_irqrestore(&cobalt_lock, flags);
159}
160
161static struct irq_chip piix4_master_irq_type = {
162 .typename = "PIIX4-master",
163 .startup = startup_piix4_master_irq,
164 .ack = ack_cobalt_irq,
165 .end = end_piix4_master_irq,
166};
167
168
169static struct irq_chip piix4_virtual_irq_type = {
170 .typename = "PIIX4-virtual",
171 .shutdown = disable_8259A_irq,
172 .enable = enable_8259A_irq,
173 .disable = disable_8259A_irq,
174};
175
176
177/*
178 * PIIX4-8259 master/virtual functions to handle interrupt requests
179 * from legacy devices: floppy, parallel, serial, rtc.
180 *
181 * None of these get Cobalt APIC entries, neither do they have IDT
182 * entries. These interrupts are purely virtual and distributed from
183 * the 'master' interrupt source: CO_IRQ_8259.
184 *
185 * When the 8259 interrupts its handler figures out which of these
186 * devices is interrupting and dispatches to its handler.
187 *
188 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
189 * enable_irq gets the right irq. This 'master' irq is never directly
190 * manipulated by any driver.
191 */
192static irqreturn_t piix4_master_intr(int irq, void *dev_id)
193{
194 int realirq;
195 irq_desc_t *desc;
196 unsigned long flags;
197
198 spin_lock_irqsave(&i8259A_lock, flags);
199
200 /* Find out what's interrupting in the PIIX4 master 8259 */
201 outb(0x0c, 0x20); /* OCW3 Poll command */
202 realirq = inb(0x20);
203
204 /*
205 * Bit 7 == 0 means invalid/spurious
206 */
207 if (unlikely(!(realirq & 0x80)))
208 goto out_unlock;
209
210 realirq &= 7;
211
212 if (unlikely(realirq == 2)) {
213 outb(0x0c, 0xa0);
214 realirq = inb(0xa0);
215
216 if (unlikely(!(realirq & 0x80)))
217 goto out_unlock;
218
219 realirq = (realirq & 7) + 8;
220 }
221
222 /* mask and ack interrupt */
223 cached_irq_mask |= 1 << realirq;
224 if (unlikely(realirq > 7)) {
225 inb(0xa1);
226 outb(cached_slave_mask, 0xa1);
227 outb(0x60 + (realirq & 7), 0xa0);
228 outb(0x60 + 2, 0x20);
229 } else {
230 inb(0x21);
231 outb(cached_master_mask, 0x21);
232 outb(0x60 + realirq, 0x20);
233 }
234
235 spin_unlock_irqrestore(&i8259A_lock, flags);
236
237 desc = irq_desc + realirq;
238
239 /*
240 * handle this 'virtual interrupt' as a Cobalt one now.
241 */
242 kstat_cpu(smp_processor_id()).irqs[realirq]++;
243
244 if (likely(desc->action != NULL))
245 handle_IRQ_event(realirq, desc->action);
246
247 if (!(desc->status & IRQ_DISABLED))
248 enable_8259A_irq(realirq);
249
250 return IRQ_HANDLED;
251
252out_unlock:
253 spin_unlock_irqrestore(&i8259A_lock, flags);
254 return IRQ_NONE;
255}
256
257static struct irqaction master_action = {
258 .handler = piix4_master_intr,
259 .name = "PIIX4-8259",
260};
261
262static struct irqaction cascade_action = {
263 .handler = no_action,
264 .name = "cascade",
265};
266
267
268void init_VISWS_APIC_irqs(void)
269{
270 int i;
271
272 for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
273 irq_desc[i].status = IRQ_DISABLED;
274 irq_desc[i].action = 0;
275 irq_desc[i].depth = 1;
276
277 if (i == 0) {
278 irq_desc[i].chip = &cobalt_irq_type;
279 }
280 else if (i == CO_IRQ_IDE0) {
281 irq_desc[i].chip = &cobalt_irq_type;
282 }
283 else if (i == CO_IRQ_IDE1) {
284 irq_desc[i].chip = &cobalt_irq_type;
285 }
286 else if (i == CO_IRQ_8259) {
287 irq_desc[i].chip = &piix4_master_irq_type;
288 }
289 else if (i < CO_IRQ_APIC0) {
290 irq_desc[i].chip = &piix4_virtual_irq_type;
291 }
292 else if (IS_CO_APIC(i)) {
293 irq_desc[i].chip = &cobalt_irq_type;
294 }
295 }
296
297 setup_irq(CO_IRQ_8259, &master_action);
298 setup_irq(2, &cascade_action);
299}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 19:42:42 -0500