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-rw-r--r--arch/i386/kernel/cpu/Makefile2
-rw-r--r--arch/i386/kernel/cpu/addon_cpuid_features.c50
-rw-r--r--arch/i386/kernel/cpu/common.c2
-rw-r--r--arch/i386/kernel/cpu/cpufreq/Kconfig13
-rw-r--r--arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c13
-rw-r--r--arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c6
-rw-r--r--arch/i386/kernel/cpu/cpufreq/gx-suspmod.c4
-rw-r--r--arch/i386/kernel/cpu/cpufreq/longhaul.c209
-rw-r--r--arch/i386/kernel/cpu/cpufreq/longhaul.h12
-rw-r--r--arch/i386/kernel/cpu/cpufreq/powernow-k8.c5
-rw-r--r--arch/i386/kernel/cpu/cpufreq/speedstep-ich.c4
-rw-r--r--arch/i386/kernel/cpu/proc.c21
-rw-r--r--arch/i386/kernel/e820.c2
-rw-r--r--arch/i386/kernel/setup.c12
-rw-r--r--arch/i386/kernel/verify_cpu.S94
15 files changed, 235 insertions, 214 deletions
diff --git a/arch/i386/kernel/cpu/Makefile b/arch/i386/kernel/cpu/Makefile
index 74f27a463db0..0b6a8551e9e2 100644
--- a/arch/i386/kernel/cpu/Makefile
+++ b/arch/i386/kernel/cpu/Makefile
@@ -8,7 +8,7 @@ obj-y += amd.o
8obj-y += cyrix.o 8obj-y += cyrix.o
9obj-y += centaur.o 9obj-y += centaur.o
10obj-y += transmeta.o 10obj-y += transmeta.o
11obj-y += intel.o intel_cacheinfo.o 11obj-y += intel.o intel_cacheinfo.o addon_cpuid_features.o
12obj-y += rise.o 12obj-y += rise.o
13obj-y += nexgen.o 13obj-y += nexgen.o
14obj-y += umc.o 14obj-y += umc.o
diff --git a/arch/i386/kernel/cpu/addon_cpuid_features.c b/arch/i386/kernel/cpu/addon_cpuid_features.c
new file mode 100644
index 000000000000..3e91d3ee26ec
--- /dev/null
+++ b/arch/i386/kernel/cpu/addon_cpuid_features.c
@@ -0,0 +1,50 @@
1
2/*
3 * Routines to indentify additional cpu features that are scattered in
4 * cpuid space.
5 */
6
7#include <linux/cpu.h>
8
9#include <asm/processor.h>
10
11struct cpuid_bit {
12 u16 feature;
13 u8 reg;
14 u8 bit;
15 u32 level;
16};
17
18enum cpuid_regs {
19 CR_EAX = 0,
20 CR_ECX,
21 CR_EDX,
22 CR_EBX
23};
24
25void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
26{
27 u32 max_level;
28 u32 regs[4];
29 const struct cpuid_bit *cb;
30
31 static const struct cpuid_bit cpuid_bits[] = {
32 { X86_FEATURE_IDA, CR_EAX, 1, 0x00000006 },
33 { 0, 0, 0, 0 }
34 };
35
36 for (cb = cpuid_bits; cb->feature; cb++) {
37
38 /* Verify that the level is valid */
39 max_level = cpuid_eax(cb->level & 0xffff0000);
40 if (max_level < cb->level ||
41 max_level > (cb->level | 0xffff))
42 continue;
43
44 cpuid(cb->level, &regs[CR_EAX], &regs[CR_EBX],
45 &regs[CR_ECX], &regs[CR_EDX]);
46
47 if (regs[cb->reg] & (1 << cb->bit))
48 set_bit(cb->feature, c->x86_capability);
49 }
50}
diff --git a/arch/i386/kernel/cpu/common.c b/arch/i386/kernel/cpu/common.c
index 794d593c47eb..e5419a9dec88 100644
--- a/arch/i386/kernel/cpu/common.c
+++ b/arch/i386/kernel/cpu/common.c
@@ -353,6 +353,8 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
353 if ( xlvl >= 0x80000004 ) 353 if ( xlvl >= 0x80000004 )
354 get_model_name(c); /* Default name */ 354 get_model_name(c); /* Default name */
355 } 355 }
356
357 init_scattered_cpuid_features(c);
356 } 358 }
357 359
358 early_intel_workaround(c); 360 early_intel_workaround(c);
diff --git a/arch/i386/kernel/cpu/cpufreq/Kconfig b/arch/i386/kernel/cpu/cpufreq/Kconfig
index e912aae9473c..e77754ca94b4 100644
--- a/arch/i386/kernel/cpu/cpufreq/Kconfig
+++ b/arch/i386/kernel/cpu/cpufreq/Kconfig
@@ -90,10 +90,17 @@ config X86_POWERNOW_K8
90 If in doubt, say N. 90 If in doubt, say N.
91 91
92config X86_POWERNOW_K8_ACPI 92config X86_POWERNOW_K8_ACPI
93 bool 93 bool "ACPI Support"
94 depends on X86_POWERNOW_K8 && ACPI_PROCESSOR 94 select ACPI_PROCESSOR
95 depends on !(X86_POWERNOW_K8 = y && ACPI_PROCESSOR = m) 95 depends on X86_POWERNOW_K8
96 default y 96 default y
97 help
98 This provides access to the K8s Processor Performance States via ACPI.
99 This driver is probably required for CPUFreq to work with multi-socket and
100 SMP systems. It is not required on at least some single-socket yet
101 multi-core systems, even if SMP is enabled.
102
103 It is safe to say Y here.
97 104
98config X86_GX_SUSPMOD 105config X86_GX_SUSPMOD
99 tristate "Cyrix MediaGX/NatSemi Geode Suspend Modulation" 106 tristate "Cyrix MediaGX/NatSemi Geode Suspend Modulation"
diff --git a/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c
index 10baa3501ed3..18c8b67ea3a7 100644
--- a/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -167,11 +167,13 @@ static void do_drv_read(struct drv_cmd *cmd)
167 167
168static void do_drv_write(struct drv_cmd *cmd) 168static void do_drv_write(struct drv_cmd *cmd)
169{ 169{
170 u32 h = 0; 170 u32 lo, hi;
171 171
172 switch (cmd->type) { 172 switch (cmd->type) {
173 case SYSTEM_INTEL_MSR_CAPABLE: 173 case SYSTEM_INTEL_MSR_CAPABLE:
174 wrmsr(cmd->addr.msr.reg, cmd->val, h); 174 rdmsr(cmd->addr.msr.reg, lo, hi);
175 lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE);
176 wrmsr(cmd->addr.msr.reg, lo, hi);
175 break; 177 break;
176 case SYSTEM_IO_CAPABLE: 178 case SYSTEM_IO_CAPABLE:
177 acpi_os_write_port((acpi_io_address)cmd->addr.io.port, 179 acpi_os_write_port((acpi_io_address)cmd->addr.io.port,
@@ -372,7 +374,6 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy,
372 struct cpufreq_freqs freqs; 374 struct cpufreq_freqs freqs;
373 cpumask_t online_policy_cpus; 375 cpumask_t online_policy_cpus;
374 struct drv_cmd cmd; 376 struct drv_cmd cmd;
375 unsigned int msr;
376 unsigned int next_state = 0; /* Index into freq_table */ 377 unsigned int next_state = 0; /* Index into freq_table */
377 unsigned int next_perf_state = 0; /* Index into perf table */ 378 unsigned int next_perf_state = 0; /* Index into perf table */
378 unsigned int i; 379 unsigned int i;
@@ -417,11 +418,7 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy,
417 case SYSTEM_INTEL_MSR_CAPABLE: 418 case SYSTEM_INTEL_MSR_CAPABLE:
418 cmd.type = SYSTEM_INTEL_MSR_CAPABLE; 419 cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
419 cmd.addr.msr.reg = MSR_IA32_PERF_CTL; 420 cmd.addr.msr.reg = MSR_IA32_PERF_CTL;
420 msr = 421 cmd.val = (u32) perf->states[next_perf_state].control;
421 (u32) perf->states[next_perf_state].
422 control & INTEL_MSR_RANGE;
423 cmd.val = get_cur_val(online_policy_cpus);
424 cmd.val = (cmd.val & ~INTEL_MSR_RANGE) | msr;
425 break; 422 break;
426 case SYSTEM_IO_CAPABLE: 423 case SYSTEM_IO_CAPABLE:
427 cmd.type = SYSTEM_IO_CAPABLE; 424 cmd.type = SYSTEM_IO_CAPABLE;
diff --git a/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c b/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
index 0d49d73d1b71..66acd5039918 100644
--- a/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
+++ b/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
@@ -391,8 +391,6 @@ static struct cpufreq_driver nforce2_driver = {
391 */ 391 */
392static unsigned int nforce2_detect_chipset(void) 392static unsigned int nforce2_detect_chipset(void)
393{ 393{
394 u8 revision;
395
396 nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA, 394 nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
397 PCI_DEVICE_ID_NVIDIA_NFORCE2, 395 PCI_DEVICE_ID_NVIDIA_NFORCE2,
398 PCI_ANY_ID, PCI_ANY_ID, NULL); 396 PCI_ANY_ID, PCI_ANY_ID, NULL);
@@ -400,10 +398,8 @@ static unsigned int nforce2_detect_chipset(void)
400 if (nforce2_chipset_dev == NULL) 398 if (nforce2_chipset_dev == NULL)
401 return -ENODEV; 399 return -ENODEV;
402 400
403 pci_read_config_byte(nforce2_chipset_dev, PCI_REVISION_ID, &revision);
404
405 printk(KERN_INFO "cpufreq: Detected nForce2 chipset revision %X\n", 401 printk(KERN_INFO "cpufreq: Detected nForce2 chipset revision %X\n",
406 revision); 402 nforce2_chipset_dev->revision);
407 printk(KERN_INFO 403 printk(KERN_INFO
408 "cpufreq: FSB changing is maybe unstable and can lead to crashes and data loss.\n"); 404 "cpufreq: FSB changing is maybe unstable and can lead to crashes and data loss.\n");
409 405
diff --git a/arch/i386/kernel/cpu/cpufreq/gx-suspmod.c b/arch/i386/kernel/cpu/cpufreq/gx-suspmod.c
index 6667e9cceb9f..194144539a6f 100644
--- a/arch/i386/kernel/cpu/cpufreq/gx-suspmod.c
+++ b/arch/i386/kernel/cpu/cpufreq/gx-suspmod.c
@@ -115,7 +115,6 @@ struct gxfreq_params {
115 u8 pci_suscfg; 115 u8 pci_suscfg;
116 u8 pci_pmer1; 116 u8 pci_pmer1;
117 u8 pci_pmer2; 117 u8 pci_pmer2;
118 u8 pci_rev;
119 struct pci_dev *cs55x0; 118 struct pci_dev *cs55x0;
120}; 119};
121 120
@@ -276,7 +275,7 @@ static void gx_set_cpuspeed(unsigned int khz)
276 pci_write_config_byte(gx_params->cs55x0, PCI_VIDTC, 100);/* typical 50 to 100ms */ 275 pci_write_config_byte(gx_params->cs55x0, PCI_VIDTC, 100);/* typical 50 to 100ms */
277 pci_write_config_byte(gx_params->cs55x0, PCI_PMER1, pmer1); 276 pci_write_config_byte(gx_params->cs55x0, PCI_PMER1, pmer1);
278 277
279 if (gx_params->pci_rev < 0x10) { /* CS5530(rev 1.2, 1.3) */ 278 if (gx_params->cs55x0->revision < 0x10) { /* CS5530(rev 1.2, 1.3) */
280 suscfg = gx_params->pci_suscfg | SUSMOD; 279 suscfg = gx_params->pci_suscfg | SUSMOD;
281 } else { /* CS5530A,B.. */ 280 } else { /* CS5530A,B.. */
282 suscfg = gx_params->pci_suscfg | SUSMOD | PWRSVE; 281 suscfg = gx_params->pci_suscfg | SUSMOD | PWRSVE;
@@ -471,7 +470,6 @@ static int __init cpufreq_gx_init(void)
471 pci_read_config_byte(params->cs55x0, PCI_PMER2, &(params->pci_pmer2)); 470 pci_read_config_byte(params->cs55x0, PCI_PMER2, &(params->pci_pmer2));
472 pci_read_config_byte(params->cs55x0, PCI_MODON, &(params->on_duration)); 471 pci_read_config_byte(params->cs55x0, PCI_MODON, &(params->on_duration));
473 pci_read_config_byte(params->cs55x0, PCI_MODOFF, &(params->off_duration)); 472 pci_read_config_byte(params->cs55x0, PCI_MODOFF, &(params->off_duration));
474 pci_read_config_byte(params->cs55x0, PCI_REVISION_ID, &params->pci_rev);
475 473
476 if ((ret = cpufreq_register_driver(&gx_suspmod_driver))) { 474 if ((ret = cpufreq_register_driver(&gx_suspmod_driver))) {
477 kfree(params); 475 kfree(params);
diff --git a/arch/i386/kernel/cpu/cpufreq/longhaul.c b/arch/i386/kernel/cpu/cpufreq/longhaul.c
index a3df9c039bd4..8eca59d4c8f4 100644
--- a/arch/i386/kernel/cpu/cpufreq/longhaul.c
+++ b/arch/i386/kernel/cpu/cpufreq/longhaul.c
@@ -29,6 +29,7 @@
29#include <linux/pci.h> 29#include <linux/pci.h>
30#include <linux/slab.h> 30#include <linux/slab.h>
31#include <linux/string.h> 31#include <linux/string.h>
32#include <linux/delay.h>
32 33
33#include <asm/msr.h> 34#include <asm/msr.h>
34#include <asm/timex.h> 35#include <asm/timex.h>
@@ -55,7 +56,6 @@
55/* Flags */ 56/* Flags */
56#define USE_ACPI_C3 (1 << 1) 57#define USE_ACPI_C3 (1 << 1)
57#define USE_NORTHBRIDGE (1 << 2) 58#define USE_NORTHBRIDGE (1 << 2)
58#define USE_VT8235 (1 << 3)
59 59
60static int cpu_model; 60static int cpu_model;
61static unsigned int numscales=16; 61static unsigned int numscales=16;
@@ -63,19 +63,15 @@ static unsigned int fsb;
63 63
64static const struct mV_pos *vrm_mV_table; 64static const struct mV_pos *vrm_mV_table;
65static const unsigned char *mV_vrm_table; 65static const unsigned char *mV_vrm_table;
66struct f_msr {
67 u8 vrm;
68 u8 pos;
69};
70static struct f_msr f_msr_table[32];
71 66
72static unsigned int highest_speed, lowest_speed; /* kHz */ 67static unsigned int highest_speed, lowest_speed; /* kHz */
73static unsigned int minmult, maxmult; 68static unsigned int minmult, maxmult;
74static int can_scale_voltage; 69static int can_scale_voltage;
75static struct acpi_processor *pr = NULL; 70static struct acpi_processor *pr = NULL;
76static struct acpi_processor_cx *cx = NULL; 71static struct acpi_processor_cx *cx = NULL;
72static u32 acpi_regs_addr;
77static u8 longhaul_flags; 73static u8 longhaul_flags;
78static u8 longhaul_pos; 74static unsigned int longhaul_index;
79 75
80/* Module parameters */ 76/* Module parameters */
81static int scale_voltage; 77static int scale_voltage;
@@ -144,7 +140,7 @@ static void do_longhaul1(unsigned int clock_ratio_index)
144 rdmsrl(MSR_VIA_BCR2, bcr2.val); 140 rdmsrl(MSR_VIA_BCR2, bcr2.val);
145 /* Enable software clock multiplier */ 141 /* Enable software clock multiplier */
146 bcr2.bits.ESOFTBF = 1; 142 bcr2.bits.ESOFTBF = 1;
147 bcr2.bits.CLOCKMUL = clock_ratio_index; 143 bcr2.bits.CLOCKMUL = clock_ratio_index & 0xff;
148 144
149 /* Sync to timer tick */ 145 /* Sync to timer tick */
150 safe_halt(); 146 safe_halt();
@@ -163,14 +159,12 @@ static void do_longhaul1(unsigned int clock_ratio_index)
163 159
164/* For processor with Longhaul MSR */ 160/* For processor with Longhaul MSR */
165 161
166static void do_powersaver(int cx_address, unsigned int clock_ratio_index) 162static void do_powersaver(int cx_address, unsigned int clock_ratio_index,
163 unsigned int dir)
167{ 164{
168 union msr_longhaul longhaul; 165 union msr_longhaul longhaul;
169 u8 dest_pos;
170 u32 t; 166 u32 t;
171 167
172 dest_pos = f_msr_table[clock_ratio_index].pos;
173
174 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val); 168 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
175 /* Setup new frequency */ 169 /* Setup new frequency */
176 longhaul.bits.RevisionKey = longhaul.bits.RevisionID; 170 longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
@@ -178,11 +172,11 @@ static void do_powersaver(int cx_address, unsigned int clock_ratio_index)
178 longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4; 172 longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
179 /* Setup new voltage */ 173 /* Setup new voltage */
180 if (can_scale_voltage) 174 if (can_scale_voltage)
181 longhaul.bits.SoftVID = f_msr_table[clock_ratio_index].vrm; 175 longhaul.bits.SoftVID = (clock_ratio_index >> 8) & 0x1f;
182 /* Sync to timer tick */ 176 /* Sync to timer tick */
183 safe_halt(); 177 safe_halt();
184 /* Raise voltage if necessary */ 178 /* Raise voltage if necessary */
185 if (can_scale_voltage && longhaul_pos < dest_pos) { 179 if (can_scale_voltage && dir) {
186 longhaul.bits.EnableSoftVID = 1; 180 longhaul.bits.EnableSoftVID = 1;
187 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); 181 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
188 /* Change voltage */ 182 /* Change voltage */
@@ -199,7 +193,6 @@ static void do_powersaver(int cx_address, unsigned int clock_ratio_index)
199 } 193 }
200 longhaul.bits.EnableSoftVID = 0; 194 longhaul.bits.EnableSoftVID = 0;
201 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); 195 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
202 longhaul_pos = dest_pos;
203 } 196 }
204 197
205 /* Change frequency on next halt or sleep */ 198 /* Change frequency on next halt or sleep */
@@ -220,7 +213,7 @@ static void do_powersaver(int cx_address, unsigned int clock_ratio_index)
220 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); 213 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
221 214
222 /* Reduce voltage if necessary */ 215 /* Reduce voltage if necessary */
223 if (can_scale_voltage && longhaul_pos > dest_pos) { 216 if (can_scale_voltage && !dir) {
224 longhaul.bits.EnableSoftVID = 1; 217 longhaul.bits.EnableSoftVID = 1;
225 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); 218 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
226 /* Change voltage */ 219 /* Change voltage */
@@ -237,7 +230,6 @@ static void do_powersaver(int cx_address, unsigned int clock_ratio_index)
237 } 230 }
238 longhaul.bits.EnableSoftVID = 0; 231 longhaul.bits.EnableSoftVID = 0;
239 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); 232 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
240 longhaul_pos = dest_pos;
241 } 233 }
242} 234}
243 235
@@ -248,25 +240,28 @@ static void do_powersaver(int cx_address, unsigned int clock_ratio_index)
248 * Sets a new clock ratio. 240 * Sets a new clock ratio.
249 */ 241 */
250 242
251static void longhaul_setstate(unsigned int clock_ratio_index) 243static void longhaul_setstate(unsigned int table_index)
252{ 244{
245 unsigned int clock_ratio_index;
253 int speed, mult; 246 int speed, mult;
254 struct cpufreq_freqs freqs; 247 struct cpufreq_freqs freqs;
255 static unsigned int old_ratio=-1;
256 unsigned long flags; 248 unsigned long flags;
257 unsigned int pic1_mask, pic2_mask; 249 unsigned int pic1_mask, pic2_mask;
250 u16 bm_status = 0;
251 u32 bm_timeout = 1000;
252 unsigned int dir = 0;
258 253
259 if (old_ratio == clock_ratio_index) 254 clock_ratio_index = longhaul_table[table_index].index;
260 return; 255 /* Safety precautions */
261 old_ratio = clock_ratio_index; 256 mult = clock_ratio[clock_ratio_index & 0x1f];
262
263 mult = clock_ratio[clock_ratio_index];
264 if (mult == -1) 257 if (mult == -1)
265 return; 258 return;
266
267 speed = calc_speed(mult); 259 speed = calc_speed(mult);
268 if ((speed > highest_speed) || (speed < lowest_speed)) 260 if ((speed > highest_speed) || (speed < lowest_speed))
269 return; 261 return;
262 /* Voltage transition before frequency transition? */
263 if (can_scale_voltage && longhaul_index < table_index)
264 dir = 1;
270 265
271 freqs.old = calc_speed(longhaul_get_cpu_mult()); 266 freqs.old = calc_speed(longhaul_get_cpu_mult());
272 freqs.new = speed; 267 freqs.new = speed;
@@ -285,11 +280,24 @@ static void longhaul_setstate(unsigned int clock_ratio_index)
285 outb(0xFF,0xA1); /* Overkill */ 280 outb(0xFF,0xA1); /* Overkill */
286 outb(0xFE,0x21); /* TMR0 only */ 281 outb(0xFE,0x21); /* TMR0 only */
287 282
283 /* Wait while PCI bus is busy. */
284 if (acpi_regs_addr && (longhaul_flags & USE_NORTHBRIDGE
285 || ((pr != NULL) && pr->flags.bm_control))) {
286 bm_status = inw(acpi_regs_addr);
287 bm_status &= 1 << 4;
288 while (bm_status && bm_timeout) {
289 outw(1 << 4, acpi_regs_addr);
290 bm_timeout--;
291 bm_status = inw(acpi_regs_addr);
292 bm_status &= 1 << 4;
293 }
294 }
295
288 if (longhaul_flags & USE_NORTHBRIDGE) { 296 if (longhaul_flags & USE_NORTHBRIDGE) {
289 /* Disable AGP and PCI arbiters */ 297 /* Disable AGP and PCI arbiters */
290 outb(3, 0x22); 298 outb(3, 0x22);
291 } else if ((pr != NULL) && pr->flags.bm_control) { 299 } else if ((pr != NULL) && pr->flags.bm_control) {
292 /* Disable bus master arbitration */ 300 /* Disable bus master arbitration */
293 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); 301 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
294 } 302 }
295 switch (longhaul_version) { 303 switch (longhaul_version) {
@@ -314,9 +322,9 @@ static void longhaul_setstate(unsigned int clock_ratio_index)
314 if (longhaul_flags & USE_ACPI_C3) { 322 if (longhaul_flags & USE_ACPI_C3) {
315 /* Don't allow wakeup */ 323 /* Don't allow wakeup */
316 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); 324 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
317 do_powersaver(cx->address, clock_ratio_index); 325 do_powersaver(cx->address, clock_ratio_index, dir);
318 } else { 326 } else {
319 do_powersaver(0, clock_ratio_index); 327 do_powersaver(0, clock_ratio_index, dir);
320 } 328 }
321 break; 329 break;
322 } 330 }
@@ -336,6 +344,9 @@ static void longhaul_setstate(unsigned int clock_ratio_index)
336 344
337 freqs.new = calc_speed(longhaul_get_cpu_mult()); 345 freqs.new = calc_speed(longhaul_get_cpu_mult());
338 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 346 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
347
348 if (!bm_timeout)
349 printk(KERN_INFO PFX "Warning: Timeout while waiting for idle PCI bus.\n");
339} 350}
340 351
341/* 352/*
@@ -369,7 +380,8 @@ static int guess_fsb(int mult)
369 380
370static int __init longhaul_get_ranges(void) 381static int __init longhaul_get_ranges(void)
371{ 382{
372 unsigned int j, k = 0; 383 unsigned int i, j, k = 0;
384 unsigned int ratio;
373 int mult; 385 int mult;
374 386
375 /* Get current frequency */ 387 /* Get current frequency */
@@ -423,8 +435,7 @@ static int __init longhaul_get_ranges(void)
423 if(!longhaul_table) 435 if(!longhaul_table)
424 return -ENOMEM; 436 return -ENOMEM;
425 437
426 for (j=0; j < numscales; j++) { 438 for (j = 0; j < numscales; j++) {
427 unsigned int ratio;
428 ratio = clock_ratio[j]; 439 ratio = clock_ratio[j];
429 if (ratio == -1) 440 if (ratio == -1)
430 continue; 441 continue;
@@ -434,13 +445,41 @@ static int __init longhaul_get_ranges(void)
434 longhaul_table[k].index = j; 445 longhaul_table[k].index = j;
435 k++; 446 k++;
436 } 447 }
448 if (k <= 1) {
449 kfree(longhaul_table);
450 return -ENODEV;
451 }
452 /* Sort */
453 for (j = 0; j < k - 1; j++) {
454 unsigned int min_f, min_i;
455 min_f = longhaul_table[j].frequency;
456 min_i = j;
457 for (i = j + 1; i < k; i++) {
458 if (longhaul_table[i].frequency < min_f) {
459 min_f = longhaul_table[i].frequency;
460 min_i = i;
461 }
462 }
463 if (min_i != j) {
464 unsigned int temp;
465 temp = longhaul_table[j].frequency;
466 longhaul_table[j].frequency = longhaul_table[min_i].frequency;
467 longhaul_table[min_i].frequency = temp;
468 temp = longhaul_table[j].index;
469 longhaul_table[j].index = longhaul_table[min_i].index;
470 longhaul_table[min_i].index = temp;
471 }
472 }
437 473
438 longhaul_table[k].frequency = CPUFREQ_TABLE_END; 474 longhaul_table[k].frequency = CPUFREQ_TABLE_END;
439 if (!k) {
440 kfree (longhaul_table);
441 return -EINVAL;
442 }
443 475
476 /* Find index we are running on */
477 for (j = 0; j < k; j++) {
478 if (clock_ratio[longhaul_table[j].index & 0x1f] == mult) {
479 longhaul_index = j;
480 break;
481 }
482 }
444 return 0; 483 return 0;
445} 484}
446 485
@@ -448,7 +487,7 @@ static int __init longhaul_get_ranges(void)
448static void __init longhaul_setup_voltagescaling(void) 487static void __init longhaul_setup_voltagescaling(void)
449{ 488{
450 union msr_longhaul longhaul; 489 union msr_longhaul longhaul;
451 struct mV_pos minvid, maxvid; 490 struct mV_pos minvid, maxvid, vid;
452 unsigned int j, speed, pos, kHz_step, numvscales; 491 unsigned int j, speed, pos, kHz_step, numvscales;
453 int min_vid_speed; 492 int min_vid_speed;
454 493
@@ -459,11 +498,11 @@ static void __init longhaul_setup_voltagescaling(void)
459 } 498 }
460 499
461 if (!longhaul.bits.VRMRev) { 500 if (!longhaul.bits.VRMRev) {
462 printk (KERN_INFO PFX "VRM 8.5\n"); 501 printk(KERN_INFO PFX "VRM 8.5\n");
463 vrm_mV_table = &vrm85_mV[0]; 502 vrm_mV_table = &vrm85_mV[0];
464 mV_vrm_table = &mV_vrm85[0]; 503 mV_vrm_table = &mV_vrm85[0];
465 } else { 504 } else {
466 printk (KERN_INFO PFX "Mobile VRM\n"); 505 printk(KERN_INFO PFX "Mobile VRM\n");
467 if (cpu_model < CPU_NEHEMIAH) 506 if (cpu_model < CPU_NEHEMIAH)
468 return; 507 return;
469 vrm_mV_table = &mobilevrm_mV[0]; 508 vrm_mV_table = &mobilevrm_mV[0];
@@ -523,7 +562,6 @@ static void __init longhaul_setup_voltagescaling(void)
523 /* Calculate kHz for one voltage step */ 562 /* Calculate kHz for one voltage step */
524 kHz_step = (highest_speed - min_vid_speed) / numvscales; 563 kHz_step = (highest_speed - min_vid_speed) / numvscales;
525 564
526
527 j = 0; 565 j = 0;
528 while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) { 566 while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
529 speed = longhaul_table[j].frequency; 567 speed = longhaul_table[j].frequency;
@@ -531,15 +569,14 @@ static void __init longhaul_setup_voltagescaling(void)
531 pos = (speed - min_vid_speed) / kHz_step + minvid.pos; 569 pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
532 else 570 else
533 pos = minvid.pos; 571 pos = minvid.pos;
534 f_msr_table[longhaul_table[j].index].vrm = mV_vrm_table[pos]; 572 longhaul_table[j].index |= mV_vrm_table[pos] << 8;
535 f_msr_table[longhaul_table[j].index].pos = pos; 573 vid = vrm_mV_table[mV_vrm_table[pos]];
574 printk(KERN_INFO PFX "f: %d kHz, index: %d, vid: %d mV\n", speed, j, vid.mV);
536 j++; 575 j++;
537 } 576 }
538 577
539 longhaul_pos = maxvid.pos;
540 can_scale_voltage = 1; 578 can_scale_voltage = 1;
541 printk(KERN_INFO PFX "Voltage scaling enabled. " 579 printk(KERN_INFO PFX "Voltage scaling enabled.\n");
542 "Use of \"conservative\" governor is highly recommended.\n");
543} 580}
544 581
545 582
@@ -553,15 +590,44 @@ static int longhaul_target(struct cpufreq_policy *policy,
553 unsigned int target_freq, unsigned int relation) 590 unsigned int target_freq, unsigned int relation)
554{ 591{
555 unsigned int table_index = 0; 592 unsigned int table_index = 0;
556 unsigned int new_clock_ratio = 0; 593 unsigned int i;
594 unsigned int dir = 0;
595 u8 vid, current_vid;
557 596
558 if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index)) 597 if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
559 return -EINVAL; 598 return -EINVAL;
560 599
561 new_clock_ratio = longhaul_table[table_index].index & 0xFF; 600 /* Don't set same frequency again */
562 601 if (longhaul_index == table_index)
563 longhaul_setstate(new_clock_ratio); 602 return 0;
564 603
604 if (!can_scale_voltage)
605 longhaul_setstate(table_index);
606 else {
607 /* On test system voltage transitions exceeding single
608 * step up or down were turning motherboard off. Both
609 * "ondemand" and "userspace" are unsafe. C7 is doing
610 * this in hardware, C3 is old and we need to do this
611 * in software. */
612 i = longhaul_index;
613 current_vid = (longhaul_table[longhaul_index].index >> 8) & 0x1f;
614 if (table_index > longhaul_index)
615 dir = 1;
616 while (i != table_index) {
617 vid = (longhaul_table[i].index >> 8) & 0x1f;
618 if (vid != current_vid) {
619 longhaul_setstate(i);
620 current_vid = vid;
621 msleep(200);
622 }
623 if (dir)
624 i++;
625 else
626 i--;
627 }
628 longhaul_setstate(table_index);
629 }
630 longhaul_index = table_index;
565 return 0; 631 return 0;
566} 632}
567 633
@@ -590,11 +656,10 @@ static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
590static int enable_arbiter_disable(void) 656static int enable_arbiter_disable(void)
591{ 657{
592 struct pci_dev *dev; 658 struct pci_dev *dev;
593 int status; 659 int status = 1;
594 int reg; 660 int reg;
595 u8 pci_cmd; 661 u8 pci_cmd;
596 662
597 status = 1;
598 /* Find PLE133 host bridge */ 663 /* Find PLE133 host bridge */
599 reg = 0x78; 664 reg = 0x78;
600 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0, 665 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0,
@@ -627,13 +692,17 @@ static int enable_arbiter_disable(void)
627 return 0; 692 return 0;
628} 693}
629 694
630static int longhaul_setup_vt8235(void) 695static int longhaul_setup_southbridge(void)
631{ 696{
632 struct pci_dev *dev; 697 struct pci_dev *dev;
633 u8 pci_cmd; 698 u8 pci_cmd;
634 699
635 /* Find VT8235 southbridge */ 700 /* Find VT8235 southbridge */
636 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL); 701 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
702 if (dev == NULL)
703 /* Find VT8237 southbridge */
704 dev = pci_get_device(PCI_VENDOR_ID_VIA,
705 PCI_DEVICE_ID_VIA_8237, NULL);
637 if (dev != NULL) { 706 if (dev != NULL) {
638 /* Set transition time to max */ 707 /* Set transition time to max */
639 pci_read_config_byte(dev, 0xec, &pci_cmd); 708 pci_read_config_byte(dev, 0xec, &pci_cmd);
@@ -645,6 +714,14 @@ static int longhaul_setup_vt8235(void)
645 pci_read_config_byte(dev, 0xe5, &pci_cmd); 714 pci_read_config_byte(dev, 0xe5, &pci_cmd);
646 pci_cmd |= 1 << 7; 715 pci_cmd |= 1 << 7;
647 pci_write_config_byte(dev, 0xe5, pci_cmd); 716 pci_write_config_byte(dev, 0xe5, pci_cmd);
717 /* Get address of ACPI registers block*/
718 pci_read_config_byte(dev, 0x81, &pci_cmd);
719 if (pci_cmd & 1 << 7) {
720 pci_read_config_dword(dev, 0x88, &acpi_regs_addr);
721 acpi_regs_addr &= 0xff00;
722 printk(KERN_INFO PFX "ACPI I/O at 0x%x\n", acpi_regs_addr);
723 }
724
648 pci_dev_put(dev); 725 pci_dev_put(dev);
649 return 1; 726 return 1;
650 } 727 }
@@ -657,7 +734,6 @@ static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
657 char *cpuname=NULL; 734 char *cpuname=NULL;
658 int ret; 735 int ret;
659 u32 lo, hi; 736 u32 lo, hi;
660 int vt8235_present;
661 737
662 /* Check what we have on this motherboard */ 738 /* Check what we have on this motherboard */
663 switch (c->x86_model) { 739 switch (c->x86_model) {
@@ -755,7 +831,7 @@ static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
755 }; 831 };
756 832
757 /* Doesn't hurt */ 833 /* Doesn't hurt */
758 vt8235_present = longhaul_setup_vt8235(); 834 longhaul_setup_southbridge();
759 835
760 /* Find ACPI data for processor */ 836 /* Find ACPI data for processor */
761 acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT, 837 acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
@@ -765,35 +841,26 @@ static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
765 /* Check ACPI support for C3 state */ 841 /* Check ACPI support for C3 state */
766 if (pr != NULL && longhaul_version == TYPE_POWERSAVER) { 842 if (pr != NULL && longhaul_version == TYPE_POWERSAVER) {
767 cx = &pr->power.states[ACPI_STATE_C3]; 843 cx = &pr->power.states[ACPI_STATE_C3];
768 if (cx->address > 0 && cx->latency <= 1000) { 844 if (cx->address > 0 && cx->latency <= 1000)
769 longhaul_flags |= USE_ACPI_C3; 845 longhaul_flags |= USE_ACPI_C3;
770 goto print_support_type;
771 }
772 } 846 }
773 /* Check if northbridge is friendly */ 847 /* Check if northbridge is friendly */
774 if (enable_arbiter_disable()) { 848 if (enable_arbiter_disable())
775 longhaul_flags |= USE_NORTHBRIDGE; 849 longhaul_flags |= USE_NORTHBRIDGE;
776 goto print_support_type; 850
777 }
778 /* Use VT8235 southbridge if present */
779 if (longhaul_version == TYPE_POWERSAVER && vt8235_present) {
780 longhaul_flags |= USE_VT8235;
781 goto print_support_type;
782 }
783 /* Check ACPI support for bus master arbiter disable */ 851 /* Check ACPI support for bus master arbiter disable */
784 if ((pr == NULL) || !(pr->flags.bm_control)) { 852 if (!(longhaul_flags & USE_ACPI_C3
853 || longhaul_flags & USE_NORTHBRIDGE)
854 && ((pr == NULL) || !(pr->flags.bm_control))) {
785 printk(KERN_ERR PFX 855 printk(KERN_ERR PFX
786 "No ACPI support. Unsupported northbridge.\n"); 856 "No ACPI support. Unsupported northbridge.\n");
787 return -ENODEV; 857 return -ENODEV;
788 } 858 }
789 859
790print_support_type:
791 if (longhaul_flags & USE_NORTHBRIDGE) 860 if (longhaul_flags & USE_NORTHBRIDGE)
792 printk (KERN_INFO PFX "Using northbridge support.\n"); 861 printk(KERN_INFO PFX "Using northbridge support.\n");
793 else if (longhaul_flags & USE_VT8235) 862 if (longhaul_flags & USE_ACPI_C3)
794 printk (KERN_INFO PFX "Using VT8235 support.\n"); 863 printk(KERN_INFO PFX "Using ACPI support.\n");
795 else
796 printk (KERN_INFO PFX "Using ACPI support.\n");
797 864
798 ret = longhaul_get_ranges(); 865 ret = longhaul_get_ranges();
799 if (ret != 0) 866 if (ret != 0)
diff --git a/arch/i386/kernel/cpu/cpufreq/longhaul.h b/arch/i386/kernel/cpu/cpufreq/longhaul.h
index 102548f12842..4fcc320997df 100644
--- a/arch/i386/kernel/cpu/cpufreq/longhaul.h
+++ b/arch/i386/kernel/cpu/cpufreq/longhaul.h
@@ -180,7 +180,7 @@ static const int __initdata ezrat_clock_ratio[32] = {
180 180
181 -1, /* 0000 -> RESERVED (10.0x) */ 181 -1, /* 0000 -> RESERVED (10.0x) */
182 110, /* 0001 -> 11.0x */ 182 110, /* 0001 -> 11.0x */
183 120, /* 0010 -> 12.0x */ 183 -1, /* 0010 -> 12.0x */
184 -1, /* 0011 -> RESERVED (9.0x)*/ 184 -1, /* 0011 -> RESERVED (9.0x)*/
185 105, /* 0100 -> 10.5x */ 185 105, /* 0100 -> 10.5x */
186 115, /* 0101 -> 11.5x */ 186 115, /* 0101 -> 11.5x */
@@ -237,7 +237,7 @@ static const int __initdata ezrat_eblcr[32] = {
237 237
238static const int __initdata nehemiah_clock_ratio[32] = { 238static const int __initdata nehemiah_clock_ratio[32] = {
239 100, /* 0000 -> 10.0x */ 239 100, /* 0000 -> 10.0x */
240 160, /* 0001 -> 16.0x */ 240 -1, /* 0001 -> 16.0x */
241 40, /* 0010 -> 4.0x */ 241 40, /* 0010 -> 4.0x */
242 90, /* 0011 -> 9.0x */ 242 90, /* 0011 -> 9.0x */
243 95, /* 0100 -> 9.5x */ 243 95, /* 0100 -> 9.5x */
@@ -252,10 +252,10 @@ static const int __initdata nehemiah_clock_ratio[32] = {
252 75, /* 1101 -> 7.5x */ 252 75, /* 1101 -> 7.5x */
253 85, /* 1110 -> 8.5x */ 253 85, /* 1110 -> 8.5x */
254 120, /* 1111 -> 12.0x */ 254 120, /* 1111 -> 12.0x */
255 100, /* 0000 -> 10.0x */ 255 -1, /* 0000 -> 10.0x */
256 110, /* 0001 -> 11.0x */ 256 110, /* 0001 -> 11.0x */
257 120, /* 0010 -> 12.0x */ 257 -1, /* 0010 -> 12.0x */
258 90, /* 0011 -> 9.0x */ 258 -1, /* 0011 -> 9.0x */
259 105, /* 0100 -> 10.5x */ 259 105, /* 0100 -> 10.5x */
260 115, /* 0101 -> 11.5x */ 260 115, /* 0101 -> 11.5x */
261 125, /* 0110 -> 12.5x */ 261 125, /* 0110 -> 12.5x */
@@ -267,7 +267,7 @@ static const int __initdata nehemiah_clock_ratio[32] = {
267 145, /* 1100 -> 14.5x */ 267 145, /* 1100 -> 14.5x */
268 155, /* 1101 -> 15.5x */ 268 155, /* 1101 -> 15.5x */
269 -1, /* 1110 -> RESERVED (13.0x) */ 269 -1, /* 1110 -> RESERVED (13.0x) */
270 120, /* 1111 -> 12.0x */ 270 -1, /* 1111 -> 12.0x */
271}; 271};
272 272
273static const int __initdata nehemiah_eblcr[32] = { 273static const int __initdata nehemiah_eblcr[32] = {
diff --git a/arch/i386/kernel/cpu/cpufreq/powernow-k8.c b/arch/i386/kernel/cpu/cpufreq/powernow-k8.c
index 4ade55c5f333..977336834127 100644
--- a/arch/i386/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/i386/kernel/cpu/cpufreq/powernow-k8.c
@@ -1330,8 +1330,9 @@ static int __cpuinit powernowk8_init(void)
1330 1330
1331 if (supported_cpus == num_online_cpus()) { 1331 if (supported_cpus == num_online_cpus()) {
1332 printk(KERN_INFO PFX "Found %d %s " 1332 printk(KERN_INFO PFX "Found %d %s "
1333 "processors (" VERSION ")\n", supported_cpus, 1333 "processors (%d cpu cores) (" VERSION ")\n",
1334 boot_cpu_data.x86_model_id); 1334 supported_cpus/cpu_data[0].booted_cores,
1335 boot_cpu_data.x86_model_id, supported_cpus);
1335 return cpufreq_register_driver(&cpufreq_amd64_driver); 1336 return cpufreq_register_driver(&cpufreq_amd64_driver);
1336 } 1337 }
1337 1338
diff --git a/arch/i386/kernel/cpu/cpufreq/speedstep-ich.c b/arch/i386/kernel/cpu/cpufreq/speedstep-ich.c
index 698f980eb443..a5b2346faf1f 100644
--- a/arch/i386/kernel/cpu/cpufreq/speedstep-ich.c
+++ b/arch/i386/kernel/cpu/cpufreq/speedstep-ich.c
@@ -205,7 +205,6 @@ static unsigned int speedstep_detect_chipset (void)
205 * host brige. Abort on these systems. 205 * host brige. Abort on these systems.
206 */ 206 */
207 static struct pci_dev *hostbridge; 207 static struct pci_dev *hostbridge;
208 u8 rev = 0;
209 208
210 hostbridge = pci_get_subsys(PCI_VENDOR_ID_INTEL, 209 hostbridge = pci_get_subsys(PCI_VENDOR_ID_INTEL,
211 PCI_DEVICE_ID_INTEL_82815_MC, 210 PCI_DEVICE_ID_INTEL_82815_MC,
@@ -216,8 +215,7 @@ static unsigned int speedstep_detect_chipset (void)
216 if (!hostbridge) 215 if (!hostbridge)
217 return 2; /* 2-M */ 216 return 2; /* 2-M */
218 217
219 pci_read_config_byte(hostbridge, PCI_REVISION_ID, &rev); 218 if (hostbridge->revision < 5) {
220 if (rev < 5) {
221 dprintk("hostbridge does not support speedstep\n"); 219 dprintk("hostbridge does not support speedstep\n");
222 speedstep_chipset_dev = NULL; 220 speedstep_chipset_dev = NULL;
223 pci_dev_put(hostbridge); 221 pci_dev_put(hostbridge);
diff --git a/arch/i386/kernel/cpu/proc.c b/arch/i386/kernel/cpu/proc.c
index 89d91e6cc972..1e31b6caffb1 100644
--- a/arch/i386/kernel/cpu/proc.c
+++ b/arch/i386/kernel/cpu/proc.c
@@ -29,7 +29,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
29 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 29 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
30 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL, 30 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
31 NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL, 31 NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL,
32 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm", "3dnowext", "3dnow", 32 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
33 "3dnowext", "3dnow",
33 34
34 /* Transmeta-defined */ 35 /* Transmeta-defined */
35 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL, 36 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
@@ -40,8 +41,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
40 /* Other (Linux-defined) */ 41 /* Other (Linux-defined) */
41 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr", 42 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
42 NULL, NULL, NULL, NULL, 43 NULL, NULL, NULL, NULL,
43 "constant_tsc", "up", NULL, NULL, NULL, NULL, NULL, NULL, 44 "constant_tsc", "up", NULL, "arch_perfmon",
44 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 45 "pebs", "bts", NULL, "sync_rdtsc",
46 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
45 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 47 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
46 48
47 /* Intel-defined (#2) */ 49 /* Intel-defined (#2) */
@@ -57,9 +59,16 @@ static int show_cpuinfo(struct seq_file *m, void *v)
57 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 59 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
58 60
59 /* AMD-defined (#2) */ 61 /* AMD-defined (#2) */
60 "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8legacy", "abm", 62 "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",
61 "sse4a", "misalignsse", 63 "altmovcr8", "abm", "sse4a",
62 "3dnowprefetch", "osvw", "ibs", NULL, NULL, NULL, NULL, NULL, 64 "misalignsse", "3dnowprefetch",
65 "osvw", "ibs", NULL, NULL, NULL, NULL,
66 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
67 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
68
69 /* Auxiliary (Linux-defined) */
70 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
71 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
63 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 72 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
64 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 73 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
65 }; 74 };
diff --git a/arch/i386/kernel/e820.c b/arch/i386/kernel/e820.c
index 9645bb51f76a..fc822a46897a 100644
--- a/arch/i386/kernel/e820.c
+++ b/arch/i386/kernel/e820.c
@@ -734,7 +734,7 @@ void __init print_memory_map(char *who)
734 case E820_NVS: 734 case E820_NVS:
735 printk("(ACPI NVS)\n"); 735 printk("(ACPI NVS)\n");
736 break; 736 break;
737 default: printk("type %lu\n", e820.map[i].type); 737 default: printk("type %u\n", e820.map[i].type);
738 break; 738 break;
739 } 739 }
740 } 740 }
diff --git a/arch/i386/kernel/setup.c b/arch/i386/kernel/setup.c
index 698c24fe482e..2d61e65eeb50 100644
--- a/arch/i386/kernel/setup.c
+++ b/arch/i386/kernel/setup.c
@@ -102,19 +102,10 @@ static unsigned int highmem_pages = -1;
102/* 102/*
103 * Setup options 103 * Setup options
104 */ 104 */
105struct drive_info_struct { char dummy[32]; } drive_info;
106#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_HD) || \
107 defined(CONFIG_BLK_DEV_IDE_MODULE) || defined(CONFIG_BLK_DEV_HD_MODULE)
108EXPORT_SYMBOL(drive_info);
109#endif
110struct screen_info screen_info; 105struct screen_info screen_info;
111EXPORT_SYMBOL(screen_info); 106EXPORT_SYMBOL(screen_info);
112struct apm_info apm_info; 107struct apm_info apm_info;
113EXPORT_SYMBOL(apm_info); 108EXPORT_SYMBOL(apm_info);
114struct sys_desc_table_struct {
115 unsigned short length;
116 unsigned char table[0];
117};
118struct edid_info edid_info; 109struct edid_info edid_info;
119EXPORT_SYMBOL_GPL(edid_info); 110EXPORT_SYMBOL_GPL(edid_info);
120struct ist_info ist_info; 111struct ist_info ist_info;
@@ -134,7 +125,7 @@ unsigned long saved_videomode;
134 125
135static char __initdata command_line[COMMAND_LINE_SIZE]; 126static char __initdata command_line[COMMAND_LINE_SIZE];
136 127
137unsigned char __initdata boot_params[PARAM_SIZE]; 128struct boot_params __initdata boot_params;
138 129
139#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE) 130#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
140struct edd edd; 131struct edd edd;
@@ -528,7 +519,6 @@ void __init setup_arch(char **cmdline_p)
528#endif 519#endif
529 520
530 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV); 521 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
531 drive_info = DRIVE_INFO;
532 screen_info = SCREEN_INFO; 522 screen_info = SCREEN_INFO;
533 edid_info = EDID_INFO; 523 edid_info = EDID_INFO;
534 apm_info.bios = APM_BIOS_INFO; 524 apm_info.bios = APM_BIOS_INFO;
diff --git a/arch/i386/kernel/verify_cpu.S b/arch/i386/kernel/verify_cpu.S
deleted file mode 100644
index f1d1eacf4ab0..000000000000
--- a/arch/i386/kernel/verify_cpu.S
+++ /dev/null
@@ -1,94 +0,0 @@
1/* Check if CPU has some minimum CPUID bits
2 This runs in 16bit mode so that the caller can still use the BIOS
3 to output errors on the screen */
4#include <asm/cpufeature.h>
5#include <asm/msr.h>
6
7verify_cpu:
8 pushfl # Save caller passed flags
9 pushl $0 # Kill any dangerous flags
10 popfl
11
12#if CONFIG_X86_MINIMUM_CPU_MODEL >= 4
13 pushfl
14 pop %eax
15 orl $(1<<18),%eax # try setting AC
16 push %eax
17 popfl
18 pushfl
19 popl %eax
20 testl $(1<<18),%eax
21 jz bad
22#endif
23#if REQUIRED_MASK1 != 0
24 pushfl # standard way to check for cpuid
25 popl %eax
26 movl %eax,%ebx
27 xorl $0x200000,%eax
28 pushl %eax
29 popfl
30 pushfl
31 popl %eax
32 cmpl %eax,%ebx
33 pushfl # standard way to check for cpuid
34 popl %eax
35 movl %eax,%ebx
36 xorl $0x200000,%eax
37 pushl %eax
38 popfl
39 pushfl
40 popl %eax
41 cmpl %eax,%ebx
42 jz bad # REQUIRED_MASK1 != 0 requires CPUID
43
44 movl $0x0,%eax # See if cpuid 1 is implemented
45 cpuid
46 cmpl $0x1,%eax
47 jb bad # no cpuid 1
48
49#if REQUIRED_MASK1 & NEED_CMPXCHG64
50 /* Some VIA C3s need magic MSRs to enable CX64. Do this here */
51 cmpl $0x746e6543,%ebx # Cent
52 jne 1f
53 cmpl $0x48727561,%edx # aurH
54 jne 1f
55 cmpl $0x736c7561,%ecx # auls
56 jne 1f
57 movl $1,%eax # check model
58 cpuid
59 movl %eax,%ebx
60 shr $8,%ebx
61 andl $0xf,%ebx
62 cmp $6,%ebx # check family == 6
63 jne 1f
64 shr $4,%eax
65 andl $0xf,%eax
66 cmpl $6,%eax # check model >= 6
67 jb 1f
68 # assume models >= 6 all support this MSR
69 movl $MSR_VIA_FCR,%ecx
70 rdmsr
71 orl $((1<<1)|(1<<7)),%eax # enable CMPXCHG64 and PGE
72 wrmsr
731:
74#endif
75 movl $0x1,%eax # Does the cpu have what it takes
76 cpuid
77
78#if CONFIG_X86_MINIMUM_CPU_MODEL > 4
79#error add proper model checking here
80#endif
81
82 andl $REQUIRED_MASK1,%edx
83 xorl $REQUIRED_MASK1,%edx
84 jnz bad
85#endif /* REQUIRED_MASK1 */
86
87 popfl
88 xor %eax,%eax
89 ret
90
91bad:
92 popfl
93 movl $1,%eax
94 ret
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-20 12:33:24 -0400