4 files changed, 18 insertions, 7 deletions

diff --git a/arch/i386/kernel/acpi/boot.c b/arch/i386/kernel/acpi/boot.c
index 4c785a67d585..40e5aba3ad3d 100644
--- a/arch/i386/kernel/acpi/boot.c
+++ b/arch/i386/kernel/acpi/boot.c
@@ -1102,9 +1102,6 @@ int __init acpi_boot_table_init(void)
         dmi_check_system(acpi_dmi_table);
 #endif
 
-        if (!cpu_has_apic)
-                return -ENODEV;
-
         /*
          * If acpi_disabled, bail out
          * One exception: acpi=ht continues far enough to enumerate LAPICs
@@ -1151,9 +1148,6 @@ int __init acpi_boot_init(void)
 
         acpi_table_parse(ACPI_BOOT, acpi_parse_sbf);
 
-        if (!cpu_has_apic)
-                return -ENODEV;
-
         /*
          * set sci_int and PM timer address
          */
diff --git a/arch/i386/kernel/io_apic.c b/arch/i386/kernel/io_apic.c
index f8f132aa5472..d70f2ade5cde 100644
--- a/arch/i386/kernel/io_apic.c
+++ b/arch/i386/kernel/io_apic.c
@@ -2238,6 +2238,8 @@ static inline void unlock_ExtINT_logic(void)
         spin_unlock_irqrestore(&ioapic_lock, flags);
 }
 
+int timer_uses_ioapic_pin_0;
+
 /*
  * This code may look a bit paranoid, but it's supposed to cooperate with
  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
@@ -2274,6 +2276,9 @@ static inline void check_timer(void)
         pin2  = ioapic_i8259.pin;
         apic2 = ioapic_i8259.apic;
 
+        if (pin1 == 0)
+                timer_uses_ioapic_pin_0 = 1;
+
         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
                 vector, apic1, pin1, apic2, pin2);
 
diff --git a/arch/i386/kernel/mpparse.c b/arch/i386/kernel/mpparse.c
index 34d21e21e012..6b1392d33ed5 100644
--- a/arch/i386/kernel/mpparse.c
+++ b/arch/i386/kernel/mpparse.c
@@ -1130,7 +1130,17 @@ int mp_register_gsi (u32 gsi, int triggering, int polarity)
                  */
                 int irq = gsi;
                 if (gsi < MAX_GSI_NUM) {
-                        if (gsi > 15)
+                        /*
+                         * Retain the VIA chipset work-around (gsi > 15), but
+                         * avoid a problem where the 8254 timer (IRQ0) is setup
+                         * via an override (so it's not on pin 0 of the ioapic),
+                         * and at the same time, the pin 0 interrupt is a PCI
+                         * type.  The gsi > 15 test could cause these two pins
+                         * to be shared as IRQ0, and they are not shareable.
+                         * So test for this condition, and if necessary, avoid
+                         * the pin collision.
+                         */
+                        if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
                                 gsi = pci_irq++;
                         /*
                          * Don't assign IRQ used by ACPI SCI
diff --git a/arch/i386/kernel/setup.c b/arch/i386/kernel/setup.c
index d77e89ac0d54..846e1639ef7c 100644
--- a/arch/i386/kernel/setup.c
+++ b/arch/i386/kernel/setup.c
@@ -1320,6 +1320,8 @@ legacy_init_iomem_resources(struct resource *code_resource, struct resource *dat
         probe_roms();
         for (i = 0; i < e820.nr_map; i++) {
                 struct resource *res;
+                if (e820.map[i].addr + e820.map[i].size > 0x100000000ULL)
+                        continue;
                 res = kzalloc(sizeof(struct resource), GFP_ATOMIC);
                 switch (e820.map[i].type) {
                 case E820_RAM:  res->name = "System RAM"; break;