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-rw-r--r--arch/i386/kernel/mpparse.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/i386/kernel/mpparse.c b/arch/i386/kernel/mpparse.c
index 91a64016956e..0102f3d50e57 100644
--- a/arch/i386/kernel/mpparse.c
+++ b/arch/i386/kernel/mpparse.c
@@ -1080,7 +1080,7 @@ void __init mp_config_acpi_legacy_irqs (void)
1080 1080
1081#define MAX_GSI_NUM 4096 1081#define MAX_GSI_NUM 4096
1082 1082
1083int mp_register_gsi (u32 gsi, int edge_level, int active_high_low) 1083int mp_register_gsi (u32 gsi, int triggering, int polarity)
1084{ 1084{
1085 int ioapic = -1; 1085 int ioapic = -1;
1086 int ioapic_pin = 0; 1086 int ioapic_pin = 0;
@@ -1129,7 +1129,7 @@ int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
1129 1129
1130 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); 1130 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1131 1131
1132 if (edge_level) { 1132 if (triggering == ACPI_LEVEL_SENSITIVE) {
1133 /* 1133 /*
1134 * For PCI devices assign IRQs in order, avoiding gaps 1134 * For PCI devices assign IRQs in order, avoiding gaps
1135 * due to unused I/O APIC pins. 1135 * due to unused I/O APIC pins.
@@ -1151,8 +1151,8 @@ int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
1151 } 1151 }
1152 1152
1153 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, 1153 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1154 edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1, 1154 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1155 active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1); 1155 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1156 return gsi; 1156 return gsi;
1157} 1157}
1158 1158