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-rw-r--r--arch/i386/kernel/cpu/amd.c14
-rw-r--r--arch/i386/kernel/cpu/changelog63
-rw-r--r--arch/i386/kernel/cpu/common.c27
-rw-r--r--arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c76
-rw-r--r--arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c3
-rw-r--r--arch/i386/kernel/cpu/cpufreq/powernow-k8.c54
-rw-r--r--arch/i386/kernel/cpu/cpufreq/powernow-k8.h9
-rw-r--r--arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c17
-rw-r--r--arch/i386/kernel/cpu/cpufreq/speedstep-est-common.h25
-rw-r--r--arch/i386/kernel/cpu/cpufreq/speedstep-ich.c47
-rw-r--r--arch/i386/kernel/cpu/cpufreq/speedstep-lib.c32
-rw-r--r--arch/i386/kernel/cpu/cpufreq/speedstep-lib.h1
-rw-r--r--arch/i386/kernel/cpu/cpufreq/speedstep-smi.c1
-rw-r--r--arch/i386/kernel/cpu/cyrix.c27
-rw-r--r--arch/i386/kernel/cpu/intel.c5
-rw-r--r--arch/i386/kernel/cpu/mtrr/changelog229
-rw-r--r--arch/i386/kernel/cpu/mtrr/if.c1
-rw-r--r--arch/i386/kernel/cpu/proc.c33
18 files changed, 191 insertions, 473 deletions
diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c
index e344ef88cfcd..333578a4e91a 100644
--- a/arch/i386/kernel/cpu/amd.c
+++ b/arch/i386/kernel/cpu/amd.c
@@ -161,8 +161,13 @@ static void __init init_amd(struct cpuinfo_x86 *c)
161 set_bit(X86_FEATURE_K6_MTRR, c->x86_capability); 161 set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
162 break; 162 break;
163 } 163 }
164 break;
165 164
165 if (c->x86_model == 10) {
166 /* AMD Geode LX is model 10 */
167 /* placeholder for any needed mods */
168 break;
169 }
170 break;
166 case 6: /* An Athlon/Duron */ 171 case 6: /* An Athlon/Duron */
167 172
168 /* Bit 15 of Athlon specific MSR 15, needs to be 0 173 /* Bit 15 of Athlon specific MSR 15, needs to be 0
@@ -211,6 +216,12 @@ static void __init init_amd(struct cpuinfo_x86 *c)
211 c->x86_max_cores = 1; 216 c->x86_max_cores = 1;
212 } 217 }
213 218
219 if (cpuid_eax(0x80000000) >= 0x80000007) {
220 c->x86_power = cpuid_edx(0x80000007);
221 if (c->x86_power & (1<<8))
222 set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
223 }
224
214#ifdef CONFIG_X86_HT 225#ifdef CONFIG_X86_HT
215 /* 226 /*
216 * On a AMD dual core setup the lower bits of the APIC id 227 * On a AMD dual core setup the lower bits of the APIC id
@@ -228,6 +239,7 @@ static void __init init_amd(struct cpuinfo_x86 *c)
228 cpu, c->x86_max_cores, cpu_core_id[cpu]); 239 cpu, c->x86_max_cores, cpu_core_id[cpu]);
229 } 240 }
230#endif 241#endif
242
231} 243}
232 244
233static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size) 245static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
diff --git a/arch/i386/kernel/cpu/changelog b/arch/i386/kernel/cpu/changelog
deleted file mode 100644
index cef76b80a710..000000000000
--- a/arch/i386/kernel/cpu/changelog
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * Enhanced CPU type detection by Mike Jagdis, Patrick St. Jean
3 * and Martin Mares, November 1997.
4 *
5 * Force Cyrix 6x86(MX) and M II processors to report MTRR capability
6 * and Cyrix "coma bug" recognition by
7 * Zoltán Böszörményi <zboszor@mail.externet.hu> February 1999.
8 *
9 * Force Centaur C6 processors to report MTRR capability.
10 * Bart Hartgers <bart@etpmod.phys.tue.nl>, May 1999.
11 *
12 * Intel Mobile Pentium II detection fix. Sean Gilley, June 1999.
13 *
14 * IDT Winchip tweaks, misc clean ups.
15 * Dave Jones <davej@suse.de>, August 1999
16 *
17 * Better detection of Centaur/IDT WinChip models.
18 * Bart Hartgers <bart@etpmod.phys.tue.nl>, August 1999.
19 *
20 * Cleaned up cache-detection code
21 * Dave Jones <davej@suse.de>, October 1999
22 *
23 * Added proper L2 cache detection for Coppermine
24 * Dragan Stancevic <visitor@valinux.com>, October 1999
25 *
26 * Added the original array for capability flags but forgot to credit
27 * myself :) (~1998) Fixed/cleaned up some cpu_model_info and other stuff
28 * Jauder Ho <jauderho@carumba.com>, January 2000
29 *
30 * Detection for Celeron coppermine, identify_cpu() overhauled,
31 * and a few other clean ups.
32 * Dave Jones <davej@suse.de>, April 2000
33 *
34 * Pentium III FXSR, SSE support
35 * General FPU state handling cleanups
36 * Gareth Hughes <gareth@valinux.com>, May 2000
37 *
38 * Added proper Cascades CPU and L2 cache detection for Cascades
39 * and 8-way type cache happy bunch from Intel:^)
40 * Dragan Stancevic <visitor@valinux.com>, May 2000
41 *
42 * Forward port AMD Duron errata T13 from 2.2.17pre
43 * Dave Jones <davej@suse.de>, August 2000
44 *
45 * Forward port lots of fixes/improvements from 2.2.18pre
46 * Cyrix III, Pentium IV support.
47 * Dave Jones <davej@suse.de>, October 2000
48 *
49 * Massive cleanup of CPU detection and bug handling;
50 * Transmeta CPU detection,
51 * H. Peter Anvin <hpa@zytor.com>, November 2000
52 *
53 * VIA C3 Support.
54 * Dave Jones <davej@suse.de>, March 2001
55 *
56 * AMD Athlon/Duron/Thunderbird bluesmoke support.
57 * Dave Jones <davej@suse.de>, April 2001.
58 *
59 * CacheSize bug workaround updates for AMD, Intel & VIA Cyrix.
60 * Dave Jones <davej@suse.de>, September, October 2001.
61 *
62 */
63
diff --git a/arch/i386/kernel/cpu/common.c b/arch/i386/kernel/cpu/common.c
index 31e344b26bae..15aee26ec2b6 100644
--- a/arch/i386/kernel/cpu/common.c
+++ b/arch/i386/kernel/cpu/common.c
@@ -18,9 +18,6 @@
18 18
19#include "cpu.h" 19#include "cpu.h"
20 20
21DEFINE_PER_CPU(struct desc_struct, cpu_gdt_table[GDT_ENTRIES]);
22EXPORT_PER_CPU_SYMBOL(cpu_gdt_table);
23
24DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]); 21DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
25EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack); 22EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack);
26 23
@@ -207,7 +204,10 @@ static int __devinit have_cpuid_p(void)
207 204
208/* Do minimum CPU detection early. 205/* Do minimum CPU detection early.
209 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment. 206 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
210 The others are not touched to avoid unwanted side effects. */ 207 The others are not touched to avoid unwanted side effects.
208
209 WARNING: this function is only called on the BP. Don't add code here
210 that is supposed to run on all CPUs. */
211static void __init early_cpu_detect(void) 211static void __init early_cpu_detect(void)
212{ 212{
213 struct cpuinfo_x86 *c = &boot_cpu_data; 213 struct cpuinfo_x86 *c = &boot_cpu_data;
@@ -239,12 +239,6 @@ static void __init early_cpu_detect(void)
239 if (cap0 & (1<<19)) 239 if (cap0 & (1<<19))
240 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8; 240 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
241 } 241 }
242
243 early_intel_workaround(c);
244
245#ifdef CONFIG_X86_HT
246 phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
247#endif
248} 242}
249 243
250void __devinit generic_identify(struct cpuinfo_x86 * c) 244void __devinit generic_identify(struct cpuinfo_x86 * c)
@@ -292,6 +286,12 @@ void __devinit generic_identify(struct cpuinfo_x86 * c)
292 get_model_name(c); /* Default name */ 286 get_model_name(c); /* Default name */
293 } 287 }
294 } 288 }
289
290 early_intel_workaround(c);
291
292#ifdef CONFIG_X86_HT
293 phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
294#endif
295} 295}
296 296
297static void __devinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 297static void __devinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
@@ -599,11 +599,6 @@ void __devinit cpu_init(void)
599 load_idt(&idt_descr); 599 load_idt(&idt_descr);
600 600
601 /* 601 /*
602 * Delete NT
603 */
604 __asm__("pushfl ; andl $0xffffbfff,(%esp) ; popfl");
605
606 /*
607 * Set up and load the per-CPU TSS and LDT 602 * Set up and load the per-CPU TSS and LDT
608 */ 603 */
609 atomic_inc(&init_mm.mm_count); 604 atomic_inc(&init_mm.mm_count);
@@ -617,8 +612,10 @@ void __devinit cpu_init(void)
617 load_TR_desc(); 612 load_TR_desc();
618 load_LDT(&init_mm.context); 613 load_LDT(&init_mm.context);
619 614
615#ifdef CONFIG_DOUBLEFAULT
620 /* Set up doublefault TSS pointer in the GDT */ 616 /* Set up doublefault TSS pointer in the GDT */
621 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 617 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
618#endif
622 619
623 /* Clear %fs and %gs. */ 620 /* Clear %fs and %gs. */
624 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs"); 621 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
diff --git a/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c
index 871366b83b3f..3852d0a4c1b5 100644
--- a/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -40,8 +40,6 @@
40#include <linux/acpi.h> 40#include <linux/acpi.h>
41#include <acpi/processor.h> 41#include <acpi/processor.h>
42 42
43#include "speedstep-est-common.h"
44
45#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "acpi-cpufreq", msg) 43#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "acpi-cpufreq", msg)
46 44
47MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); 45MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski");
@@ -297,68 +295,6 @@ acpi_cpufreq_guess_freq (
297} 295}
298 296
299 297
300/*
301 * acpi_processor_cpu_init_pdc_est - let BIOS know about the SMP capabilities
302 * of this driver
303 * @perf: processor-specific acpi_io_data struct
304 * @cpu: CPU being initialized
305 *
306 * To avoid issues with legacy OSes, some BIOSes require to be informed of
307 * the SMP capabilities of OS P-state driver. Here we set the bits in _PDC
308 * accordingly, for Enhanced Speedstep. Actual call to _PDC is done in
309 * driver/acpi/processor.c
310 */
311static void
312acpi_processor_cpu_init_pdc_est(
313 struct acpi_processor_performance *perf,
314 unsigned int cpu,
315 struct acpi_object_list *obj_list
316 )
317{
318 union acpi_object *obj;
319 u32 *buf;
320 struct cpuinfo_x86 *c = cpu_data + cpu;
321 dprintk("acpi_processor_cpu_init_pdc_est\n");
322
323 if (!cpu_has(c, X86_FEATURE_EST))
324 return;
325
326 /* Initialize pdc. It will be used later. */
327 if (!obj_list)
328 return;
329
330 if (!(obj_list->count && obj_list->pointer))
331 return;
332
333 obj = obj_list->pointer;
334 if ((obj->buffer.length == 12) && obj->buffer.pointer) {
335 buf = (u32 *)obj->buffer.pointer;
336 buf[0] = ACPI_PDC_REVISION_ID;
337 buf[1] = 1;
338 buf[2] = ACPI_PDC_EST_CAPABILITY_SMP;
339 perf->pdc = obj_list;
340 }
341 return;
342}
343
344
345/* CPU specific PDC initialization */
346static void
347acpi_processor_cpu_init_pdc(
348 struct acpi_processor_performance *perf,
349 unsigned int cpu,
350 struct acpi_object_list *obj_list
351 )
352{
353 struct cpuinfo_x86 *c = cpu_data + cpu;
354 dprintk("acpi_processor_cpu_init_pdc\n");
355 perf->pdc = NULL;
356 if (cpu_has(c, X86_FEATURE_EST))
357 acpi_processor_cpu_init_pdc_est(perf, cpu, obj_list);
358 return;
359}
360
361
362static int 298static int
363acpi_cpufreq_cpu_init ( 299acpi_cpufreq_cpu_init (
364 struct cpufreq_policy *policy) 300 struct cpufreq_policy *policy)
@@ -367,15 +303,9 @@ acpi_cpufreq_cpu_init (
367 unsigned int cpu = policy->cpu; 303 unsigned int cpu = policy->cpu;
368 struct cpufreq_acpi_io *data; 304 struct cpufreq_acpi_io *data;
369 unsigned int result = 0; 305 unsigned int result = 0;
370 306 struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
371 union acpi_object arg0 = {ACPI_TYPE_BUFFER};
372 u32 arg0_buf[3];
373 struct acpi_object_list arg_list = {1, &arg0};
374 307
375 dprintk("acpi_cpufreq_cpu_init\n"); 308 dprintk("acpi_cpufreq_cpu_init\n");
376 /* setup arg_list for _PDC settings */
377 arg0.buffer.length = 12;
378 arg0.buffer.pointer = (u8 *) arg0_buf;
379 309
380 data = kzalloc(sizeof(struct cpufreq_acpi_io), GFP_KERNEL); 310 data = kzalloc(sizeof(struct cpufreq_acpi_io), GFP_KERNEL);
381 if (!data) 311 if (!data)
@@ -383,14 +313,12 @@ acpi_cpufreq_cpu_init (
383 313
384 acpi_io_data[cpu] = data; 314 acpi_io_data[cpu] = data;
385 315
386 acpi_processor_cpu_init_pdc(&data->acpi_data, cpu, &arg_list);
387 result = acpi_processor_register_performance(&data->acpi_data, cpu); 316 result = acpi_processor_register_performance(&data->acpi_data, cpu);
388 data->acpi_data.pdc = NULL;
389 317
390 if (result) 318 if (result)
391 goto err_free; 319 goto err_free;
392 320
393 if (is_const_loops_cpu(cpu)) { 321 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
394 acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; 322 acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS;
395 } 323 }
396 324
diff --git a/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c b/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
index 04a405345203..2b62dee35c6c 100644
--- a/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
+++ b/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
@@ -177,9 +177,10 @@ static unsigned int nforce2_fsb_read(int bootfsb)
177 */ 177 */
178static int nforce2_set_fsb(unsigned int fsb) 178static int nforce2_set_fsb(unsigned int fsb)
179{ 179{
180 u32 pll, temp = 0; 180 u32 temp = 0;
181 unsigned int tfsb; 181 unsigned int tfsb;
182 int diff; 182 int diff;
183 int pll = 0;
183 184
184 if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) { 185 if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
185 printk(KERN_ERR "cpufreq: FSB %d is out of range!\n", fsb); 186 printk(KERN_ERR "cpufreq: FSB %d is out of range!\n", fsb);
diff --git a/arch/i386/kernel/cpu/cpufreq/powernow-k8.c b/arch/i386/kernel/cpu/cpufreq/powernow-k8.c
index 68a1fc87f4ca..e11a09207ec8 100644
--- a/arch/i386/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/i386/kernel/cpu/cpufreq/powernow-k8.c
@@ -45,7 +45,7 @@
45 45
46#define PFX "powernow-k8: " 46#define PFX "powernow-k8: "
47#define BFX PFX "BIOS error: " 47#define BFX PFX "BIOS error: "
48#define VERSION "version 1.50.4" 48#define VERSION "version 1.60.0"
49#include "powernow-k8.h" 49#include "powernow-k8.h"
50 50
51/* serialize freq changes */ 51/* serialize freq changes */
@@ -216,10 +216,10 @@ static int write_new_vid(struct powernow_k8_data *data, u32 vid)
216 216
217 do { 217 do {
218 wrmsr(MSR_FIDVID_CTL, lo, STOP_GRANT_5NS); 218 wrmsr(MSR_FIDVID_CTL, lo, STOP_GRANT_5NS);
219 if (i++ > 100) { 219 if (i++ > 100) {
220 printk(KERN_ERR PFX "internal error - pending bit very stuck - no further pstate changes possible\n"); 220 printk(KERN_ERR PFX "internal error - pending bit very stuck - no further pstate changes possible\n");
221 return 1; 221 return 1;
222 } 222 }
223 } while (query_current_values_with_pending_wait(data)); 223 } while (query_current_values_with_pending_wait(data));
224 224
225 if (savefid != data->currfid) { 225 if (savefid != data->currfid) {
@@ -336,7 +336,7 @@ static int core_voltage_pre_transition(struct powernow_k8_data *data, u32 reqvid
336/* Phase 2 - core frequency transition */ 336/* Phase 2 - core frequency transition */
337static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid) 337static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid)
338{ 338{
339 u32 vcoreqfid, vcocurrfid, vcofiddiff, savevid = data->currvid; 339 u32 vcoreqfid, vcocurrfid, vcofiddiff, fid_interval, savevid = data->currvid;
340 340
341 if ((reqfid < HI_FID_TABLE_BOTTOM) && (data->currfid < HI_FID_TABLE_BOTTOM)) { 341 if ((reqfid < HI_FID_TABLE_BOTTOM) && (data->currfid < HI_FID_TABLE_BOTTOM)) {
342 printk(KERN_ERR PFX "ph2: illegal lo-lo transition 0x%x 0x%x\n", 342 printk(KERN_ERR PFX "ph2: illegal lo-lo transition 0x%x 0x%x\n",
@@ -359,9 +359,11 @@ static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid)
359 : vcoreqfid - vcocurrfid; 359 : vcoreqfid - vcocurrfid;
360 360
361 while (vcofiddiff > 2) { 361 while (vcofiddiff > 2) {
362 (data->currfid & 1) ? (fid_interval = 1) : (fid_interval = 2);
363
362 if (reqfid > data->currfid) { 364 if (reqfid > data->currfid) {
363 if (data->currfid > LO_FID_TABLE_TOP) { 365 if (data->currfid > LO_FID_TABLE_TOP) {
364 if (write_new_fid(data, data->currfid + 2)) { 366 if (write_new_fid(data, data->currfid + fid_interval)) {
365 return 1; 367 return 1;
366 } 368 }
367 } else { 369 } else {
@@ -371,7 +373,7 @@ static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid)
371 } 373 }
372 } 374 }
373 } else { 375 } else {
374 if (write_new_fid(data, data->currfid - 2)) 376 if (write_new_fid(data, data->currfid - fid_interval))
375 return 1; 377 return 1;
376 } 378 }
377 379
@@ -464,7 +466,7 @@ static int check_supported_cpu(unsigned int cpu)
464 set_cpus_allowed(current, cpumask_of_cpu(cpu)); 466 set_cpus_allowed(current, cpumask_of_cpu(cpu));
465 467
466 if (smp_processor_id() != cpu) { 468 if (smp_processor_id() != cpu) {
467 printk(KERN_ERR "limiting to cpu %u failed\n", cpu); 469 printk(KERN_ERR PFX "limiting to cpu %u failed\n", cpu);
468 goto out; 470 goto out;
469 } 471 }
470 472
@@ -474,7 +476,7 @@ static int check_supported_cpu(unsigned int cpu)
474 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); 476 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
475 if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) || 477 if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) ||
476 ((eax & CPUID_XFAM) != CPUID_XFAM_K8) || 478 ((eax & CPUID_XFAM) != CPUID_XFAM_K8) ||
477 ((eax & CPUID_XMOD) > CPUID_XMOD_REV_F)) { 479 ((eax & CPUID_XMOD) > CPUID_XMOD_REV_G)) {
478 printk(KERN_INFO PFX "Processor cpuid %x not supported\n", eax); 480 printk(KERN_INFO PFX "Processor cpuid %x not supported\n", eax);
479 goto out; 481 goto out;
480 } 482 }
@@ -517,22 +519,24 @@ static int check_pst_table(struct powernow_k8_data *data, struct pst_s *pst, u8
517 printk(KERN_ERR BFX "maxvid exceeded with pstate %d\n", j); 519 printk(KERN_ERR BFX "maxvid exceeded with pstate %d\n", j);
518 return -ENODEV; 520 return -ENODEV;
519 } 521 }
520 if ((pst[j].fid > MAX_FID) 522 if (pst[j].fid > MAX_FID) {
521 || (pst[j].fid & 1) 523 printk(KERN_ERR BFX "maxfid exceeded with pstate %d\n", j);
522 || (j && (pst[j].fid < HI_FID_TABLE_BOTTOM))) { 524 return -ENODEV;
525 }
526 if (j && (pst[j].fid < HI_FID_TABLE_BOTTOM)) {
523 /* Only first fid is allowed to be in "low" range */ 527 /* Only first fid is allowed to be in "low" range */
524 printk(KERN_ERR PFX "two low fids - %d : 0x%x\n", j, pst[j].fid); 528 printk(KERN_ERR BFX "two low fids - %d : 0x%x\n", j, pst[j].fid);
525 return -EINVAL; 529 return -EINVAL;
526 } 530 }
527 if (pst[j].fid < lastfid) 531 if (pst[j].fid < lastfid)
528 lastfid = pst[j].fid; 532 lastfid = pst[j].fid;
529 } 533 }
530 if (lastfid & 1) { 534 if (lastfid & 1) {
531 printk(KERN_ERR PFX "lastfid invalid\n"); 535 printk(KERN_ERR BFX "lastfid invalid\n");
532 return -EINVAL; 536 return -EINVAL;
533 } 537 }
534 if (lastfid > LO_FID_TABLE_TOP) 538 if (lastfid > LO_FID_TABLE_TOP)
535 printk(KERN_INFO PFX "first fid not from lo freq table\n"); 539 printk(KERN_INFO BFX "first fid not from lo freq table\n");
536 540
537 return 0; 541 return 0;
538} 542}
@@ -631,7 +635,7 @@ static int find_psb_table(struct powernow_k8_data *data)
631 635
632 dprintk("table vers: 0x%x\n", psb->tableversion); 636 dprintk("table vers: 0x%x\n", psb->tableversion);
633 if (psb->tableversion != PSB_VERSION_1_4) { 637 if (psb->tableversion != PSB_VERSION_1_4) {
634 printk(KERN_INFO BFX "PSB table is not v1.4\n"); 638 printk(KERN_ERR BFX "PSB table is not v1.4\n");
635 return -ENODEV; 639 return -ENODEV;
636 } 640 }
637 641
@@ -689,7 +693,7 @@ static int find_psb_table(struct powernow_k8_data *data)
689 * BIOS and Kernel Developer's Guide, which is available on 693 * BIOS and Kernel Developer's Guide, which is available on
690 * www.amd.com 694 * www.amd.com
691 */ 695 */
692 printk(KERN_INFO PFX "BIOS error - no PSB or ACPI _PSS objects\n"); 696 printk(KERN_ERR PFX "BIOS error - no PSB or ACPI _PSS objects\n");
693 return -ENODEV; 697 return -ENODEV;
694} 698}
695 699
@@ -912,7 +916,7 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi
912 set_cpus_allowed(current, cpumask_of_cpu(pol->cpu)); 916 set_cpus_allowed(current, cpumask_of_cpu(pol->cpu));
913 917
914 if (smp_processor_id() != pol->cpu) { 918 if (smp_processor_id() != pol->cpu) {
915 printk(KERN_ERR "limiting to cpu %u failed\n", pol->cpu); 919 printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu);
916 goto err_out; 920 goto err_out;
917 } 921 }
918 922
@@ -976,12 +980,15 @@ static int powernowk8_verify(struct cpufreq_policy *pol)
976} 980}
977 981
978/* per CPU init entry point to the driver */ 982/* per CPU init entry point to the driver */
979static int __init powernowk8_cpu_init(struct cpufreq_policy *pol) 983static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
980{ 984{
981 struct powernow_k8_data *data; 985 struct powernow_k8_data *data;
982 cpumask_t oldmask = CPU_MASK_ALL; 986 cpumask_t oldmask = CPU_MASK_ALL;
983 int rc, i; 987 int rc, i;
984 988
989 if (!cpu_online(pol->cpu))
990 return -ENODEV;
991
985 if (!check_supported_cpu(pol->cpu)) 992 if (!check_supported_cpu(pol->cpu))
986 return -ENODEV; 993 return -ENODEV;
987 994
@@ -1021,7 +1028,7 @@ static int __init powernowk8_cpu_init(struct cpufreq_policy *pol)
1021 set_cpus_allowed(current, cpumask_of_cpu(pol->cpu)); 1028 set_cpus_allowed(current, cpumask_of_cpu(pol->cpu));
1022 1029
1023 if (smp_processor_id() != pol->cpu) { 1030 if (smp_processor_id() != pol->cpu) {
1024 printk(KERN_ERR "limiting to cpu %u failed\n", pol->cpu); 1031 printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu);
1025 goto err_out; 1032 goto err_out;
1026 } 1033 }
1027 1034
@@ -1134,7 +1141,7 @@ static struct cpufreq_driver cpufreq_amd64_driver = {
1134}; 1141};
1135 1142
1136/* driver entry point for init */ 1143/* driver entry point for init */
1137static int __init powernowk8_init(void) 1144static int __cpuinit powernowk8_init(void)
1138{ 1145{
1139 unsigned int i, supported_cpus = 0; 1146 unsigned int i, supported_cpus = 0;
1140 1147
@@ -1162,10 +1169,9 @@ static void __exit powernowk8_exit(void)
1162 cpufreq_unregister_driver(&cpufreq_amd64_driver); 1169 cpufreq_unregister_driver(&cpufreq_amd64_driver);
1163} 1170}
1164 1171
1165MODULE_AUTHOR("Paul Devriendt <paul.devriendt@amd.com> and Mark Langsdorf <mark.langsdorf@amd.com."); 1172MODULE_AUTHOR("Paul Devriendt <paul.devriendt@amd.com> and Mark Langsdorf <mark.langsdorf@amd.com>");
1166MODULE_DESCRIPTION("AMD Athlon 64 and Opteron processor frequency driver."); 1173MODULE_DESCRIPTION("AMD Athlon 64 and Opteron processor frequency driver.");
1167MODULE_LICENSE("GPL"); 1174MODULE_LICENSE("GPL");
1168 1175
1169late_initcall(powernowk8_init); 1176late_initcall(powernowk8_init);
1170module_exit(powernowk8_exit); 1177module_exit(powernowk8_exit);
1171
diff --git a/arch/i386/kernel/cpu/cpufreq/powernow-k8.h b/arch/i386/kernel/cpu/cpufreq/powernow-k8.h
index b1e85bb36396..d0de37d58e9a 100644
--- a/arch/i386/kernel/cpu/cpufreq/powernow-k8.h
+++ b/arch/i386/kernel/cpu/cpufreq/powernow-k8.h
@@ -42,7 +42,7 @@ struct powernow_k8_data {
42#define CPUID_XFAM 0x0ff00000 /* extended family */ 42#define CPUID_XFAM 0x0ff00000 /* extended family */
43#define CPUID_XFAM_K8 0 43#define CPUID_XFAM_K8 0
44#define CPUID_XMOD 0x000f0000 /* extended model */ 44#define CPUID_XMOD 0x000f0000 /* extended model */
45#define CPUID_XMOD_REV_F 0x00040000 45#define CPUID_XMOD_REV_G 0x00060000
46#define CPUID_USE_XFAM_XMOD 0x00000f00 46#define CPUID_USE_XFAM_XMOD 0x00000f00
47#define CPUID_GET_MAX_CAPABILITIES 0x80000000 47#define CPUID_GET_MAX_CAPABILITIES 0x80000000
48#define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007 48#define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
@@ -86,13 +86,14 @@ struct powernow_k8_data {
86 * low fid table 86 * low fid table
87 * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry 87 * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
88 * in the low fid table 88 * in the low fid table
89 * - the parts can only step at 200 MHz intervals, so 1.9 GHz is never valid 89 * - the parts can only step at <= 200 MHz intervals, odd fid values are
90 * supported in revision G and later revisions.
90 * - lowest frequency must be >= interprocessor hypertransport link speed 91 * - lowest frequency must be >= interprocessor hypertransport link speed
91 * (only applies to MP systems obviously) 92 * (only applies to MP systems obviously)
92 */ 93 */
93 94
94/* fids (frequency identifiers) are arranged in 2 tables - lo and hi */ 95/* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
95#define LO_FID_TABLE_TOP 6 /* fid values marking the boundary */ 96#define LO_FID_TABLE_TOP 7 /* fid values marking the boundary */
96#define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */ 97#define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */
97 98
98#define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */ 99#define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */
@@ -106,7 +107,7 @@ struct powernow_k8_data {
106#define MIN_FREQ 800 /* Min and max freqs, per spec */ 107#define MIN_FREQ 800 /* Min and max freqs, per spec */
107#define MAX_FREQ 5000 108#define MAX_FREQ 5000
108 109
109#define INVALID_FID_MASK 0xffffffc1 /* not a valid fid if these bits are set */ 110#define INVALID_FID_MASK 0xffffffc0 /* not a valid fid if these bits are set */
110#define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */ 111#define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */
111 112
112#define VID_OFF 0x3f 113#define VID_OFF 0x3f
diff --git a/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c b/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c
index edb9873e27e3..c173c0fa117a 100644
--- a/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c
+++ b/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c
@@ -35,8 +35,6 @@
35#include <asm/processor.h> 35#include <asm/processor.h>
36#include <asm/cpufeature.h> 36#include <asm/cpufeature.h>
37 37
38#include "speedstep-est-common.h"
39
40#define PFX "speedstep-centrino: " 38#define PFX "speedstep-centrino: "
41#define MAINTAINER "Jeremy Fitzhardinge <jeremy@goop.org>" 39#define MAINTAINER "Jeremy Fitzhardinge <jeremy@goop.org>"
42 40
@@ -364,22 +362,10 @@ static struct acpi_processor_performance p;
364 */ 362 */
365static int centrino_cpu_init_acpi(struct cpufreq_policy *policy) 363static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
366{ 364{
367 union acpi_object arg0 = {ACPI_TYPE_BUFFER};
368 u32 arg0_buf[3];
369 struct acpi_object_list arg_list = {1, &arg0};
370 unsigned long cur_freq; 365 unsigned long cur_freq;
371 int result = 0, i; 366 int result = 0, i;
372 unsigned int cpu = policy->cpu; 367 unsigned int cpu = policy->cpu;
373 368
374 /* _PDC settings */
375 arg0.buffer.length = 12;
376 arg0.buffer.pointer = (u8 *) arg0_buf;
377 arg0_buf[0] = ACPI_PDC_REVISION_ID;
378 arg0_buf[1] = 1;
379 arg0_buf[2] = ACPI_PDC_EST_CAPABILITY_SMP_MSR;
380
381 p.pdc = &arg_list;
382
383 /* register with ACPI core */ 369 /* register with ACPI core */
384 if (acpi_processor_register_performance(&p, cpu)) { 370 if (acpi_processor_register_performance(&p, cpu)) {
385 dprintk(KERN_INFO PFX "obtaining ACPI data failed\n"); 371 dprintk(KERN_INFO PFX "obtaining ACPI data failed\n");
@@ -493,12 +479,13 @@ static int centrino_cpu_init(struct cpufreq_policy *policy)
493 unsigned l, h; 479 unsigned l, h;
494 int ret; 480 int ret;
495 int i; 481 int i;
482 struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
496 483
497 /* Only Intel makes Enhanced Speedstep-capable CPUs */ 484 /* Only Intel makes Enhanced Speedstep-capable CPUs */
498 if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST)) 485 if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
499 return -ENODEV; 486 return -ENODEV;
500 487
501 if (is_const_loops_cpu(policy->cpu)) { 488 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
502 centrino_driver.flags |= CPUFREQ_CONST_LOOPS; 489 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
503 } 490 }
504 491
diff --git a/arch/i386/kernel/cpu/cpufreq/speedstep-est-common.h b/arch/i386/kernel/cpu/cpufreq/speedstep-est-common.h
deleted file mode 100644
index 5ce995c9d866..000000000000
--- a/arch/i386/kernel/cpu/cpufreq/speedstep-est-common.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Routines common for drivers handling Enhanced Speedstep Technology
3 * Copyright (C) 2004 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
4 *
5 * Licensed under the terms of the GNU GPL License version 2 -- see
6 * COPYING for details.
7 */
8
9static inline int is_const_loops_cpu(unsigned int cpu)
10{
11 struct cpuinfo_x86 *c = cpu_data + cpu;
12
13 if (c->x86_vendor != X86_VENDOR_INTEL || !cpu_has(c, X86_FEATURE_EST))
14 return 0;
15
16 /*
17 * on P-4s, the TSC runs with constant frequency independent of cpu freq
18 * when we use EST
19 */
20 if (c->x86 == 0xf)
21 return 1;
22
23 return 0;
24}
25
diff --git a/arch/i386/kernel/cpu/cpufreq/speedstep-ich.c b/arch/i386/kernel/cpu/cpufreq/speedstep-ich.c
index 5b7d18a06afa..b425cd3d1838 100644
--- a/arch/i386/kernel/cpu/cpufreq/speedstep-ich.c
+++ b/arch/i386/kernel/cpu/cpufreq/speedstep-ich.c
@@ -40,6 +40,7 @@ static struct pci_dev *speedstep_chipset_dev;
40 */ 40 */
41static unsigned int speedstep_processor = 0; 41static unsigned int speedstep_processor = 0;
42 42
43static u32 pmbase;
43 44
44/* 45/*
45 * There are only two frequency states for each processor. Values 46 * There are only two frequency states for each processor. Values
@@ -56,34 +57,47 @@ static struct cpufreq_frequency_table speedstep_freqs[] = {
56 57
57 58
58/** 59/**
59 * speedstep_set_state - set the SpeedStep state 60 * speedstep_find_register - read the PMBASE address
60 * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
61 * 61 *
62 * Tries to change the SpeedStep state. 62 * Returns: -ENODEV if no register could be found
63 */ 63 */
64static void speedstep_set_state (unsigned int state) 64static int speedstep_find_register (void)
65{ 65{
66 u32 pmbase; 66 if (!speedstep_chipset_dev)
67 u8 pm2_blk; 67 return -ENODEV;
68 u8 value;
69 unsigned long flags;
70
71 if (!speedstep_chipset_dev || (state > 0x1))
72 return;
73 68
74 /* get PMBASE */ 69 /* get PMBASE */
75 pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase); 70 pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);
76 if (!(pmbase & 0x01)) { 71 if (!(pmbase & 0x01)) {
77 printk(KERN_ERR "speedstep-ich: could not find speedstep register\n"); 72 printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
78 return; 73 return -ENODEV;
79 } 74 }
80 75
81 pmbase &= 0xFFFFFFFE; 76 pmbase &= 0xFFFFFFFE;
82 if (!pmbase) { 77 if (!pmbase) {
83 printk(KERN_ERR "speedstep-ich: could not find speedstep register\n"); 78 printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
84 return; 79 return -ENODEV;
85 } 80 }
86 81
82 dprintk("pmbase is 0x%x\n", pmbase);
83 return 0;
84}
85
86/**
87 * speedstep_set_state - set the SpeedStep state
88 * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
89 *
90 * Tries to change the SpeedStep state.
91 */
92static void speedstep_set_state (unsigned int state)
93{
94 u8 pm2_blk;
95 u8 value;
96 unsigned long flags;
97
98 if (state > 0x1)
99 return;
100
87 /* Disable IRQs */ 101 /* Disable IRQs */
88 local_irq_save(flags); 102 local_irq_save(flags);
89 103
@@ -315,10 +329,11 @@ static int speedstep_cpu_init(struct cpufreq_policy *policy)
315 cpus_allowed = current->cpus_allowed; 329 cpus_allowed = current->cpus_allowed;
316 set_cpus_allowed(current, policy->cpus); 330 set_cpus_allowed(current, policy->cpus);
317 331
318 /* detect low and high frequency */ 332 /* detect low and high frequency and transition latency */
319 result = speedstep_get_freqs(speedstep_processor, 333 result = speedstep_get_freqs(speedstep_processor,
320 &speedstep_freqs[SPEEDSTEP_LOW].frequency, 334 &speedstep_freqs[SPEEDSTEP_LOW].frequency,
321 &speedstep_freqs[SPEEDSTEP_HIGH].frequency, 335 &speedstep_freqs[SPEEDSTEP_HIGH].frequency,
336 &policy->cpuinfo.transition_latency,
322 &speedstep_set_state); 337 &speedstep_set_state);
323 set_cpus_allowed(current, cpus_allowed); 338 set_cpus_allowed(current, cpus_allowed);
324 if (result) 339 if (result)
@@ -335,7 +350,6 @@ static int speedstep_cpu_init(struct cpufreq_policy *policy)
335 350
336 /* cpuinfo and default policy values */ 351 /* cpuinfo and default policy values */
337 policy->governor = CPUFREQ_DEFAULT_GOVERNOR; 352 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
338 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
339 policy->cur = speed; 353 policy->cur = speed;
340 354
341 result = cpufreq_frequency_table_cpuinfo(policy, speedstep_freqs); 355 result = cpufreq_frequency_table_cpuinfo(policy, speedstep_freqs);
@@ -400,6 +414,9 @@ static int __init speedstep_init(void)
400 return -EINVAL; 414 return -EINVAL;
401 } 415 }
402 416
417 if (speedstep_find_register())
418 return -ENODEV;
419
403 return cpufreq_register_driver(&speedstep_driver); 420 return cpufreq_register_driver(&speedstep_driver);
404} 421}
405 422
diff --git a/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c b/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c
index d368b3f5fce8..7c47005a1805 100644
--- a/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c
+++ b/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c
@@ -320,11 +320,13 @@ EXPORT_SYMBOL_GPL(speedstep_detect_processor);
320unsigned int speedstep_get_freqs(unsigned int processor, 320unsigned int speedstep_get_freqs(unsigned int processor,
321 unsigned int *low_speed, 321 unsigned int *low_speed,
322 unsigned int *high_speed, 322 unsigned int *high_speed,
323 unsigned int *transition_latency,
323 void (*set_state) (unsigned int state)) 324 void (*set_state) (unsigned int state))
324{ 325{
325 unsigned int prev_speed; 326 unsigned int prev_speed;
326 unsigned int ret = 0; 327 unsigned int ret = 0;
327 unsigned long flags; 328 unsigned long flags;
329 struct timeval tv1, tv2;
328 330
329 if ((!processor) || (!low_speed) || (!high_speed) || (!set_state)) 331 if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
330 return -EINVAL; 332 return -EINVAL;
@@ -337,7 +339,7 @@ unsigned int speedstep_get_freqs(unsigned int processor,
337 return -EIO; 339 return -EIO;
338 340
339 dprintk("previous speed is %u\n", prev_speed); 341 dprintk("previous speed is %u\n", prev_speed);
340 342
341 local_irq_save(flags); 343 local_irq_save(flags);
342 344
343 /* switch to low state */ 345 /* switch to low state */
@@ -350,8 +352,17 @@ unsigned int speedstep_get_freqs(unsigned int processor,
350 352
351 dprintk("low speed is %u\n", *low_speed); 353 dprintk("low speed is %u\n", *low_speed);
352 354
355 /* start latency measurement */
356 if (transition_latency)
357 do_gettimeofday(&tv1);
358
353 /* switch to high state */ 359 /* switch to high state */
354 set_state(SPEEDSTEP_HIGH); 360 set_state(SPEEDSTEP_HIGH);
361
362 /* end latency measurement */
363 if (transition_latency)
364 do_gettimeofday(&tv2);
365
355 *high_speed = speedstep_get_processor_frequency(processor); 366 *high_speed = speedstep_get_processor_frequency(processor);
356 if (!*high_speed) { 367 if (!*high_speed) {
357 ret = -EIO; 368 ret = -EIO;
@@ -369,6 +380,25 @@ unsigned int speedstep_get_freqs(unsigned int processor,
369 if (*high_speed != prev_speed) 380 if (*high_speed != prev_speed)
370 set_state(SPEEDSTEP_LOW); 381 set_state(SPEEDSTEP_LOW);
371 382
383 if (transition_latency) {
384 *transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC +
385 tv2.tv_usec - tv1.tv_usec;
386 dprintk("transition latency is %u uSec\n", *transition_latency);
387
388 /* convert uSec to nSec and add 20% for safety reasons */
389 *transition_latency *= 1200;
390
391 /* check if the latency measurement is too high or too low
392 * and set it to a safe value (500uSec) in that case
393 */
394 if (*transition_latency > 10000000 || *transition_latency < 50000) {
395 printk (KERN_WARNING "speedstep: frequency transition measured seems out of "
396 "range (%u nSec), falling back to a safe one of %u nSec.\n",
397 *transition_latency, 500000);
398 *transition_latency = 500000;
399 }
400 }
401
372 out: 402 out:
373 local_irq_restore(flags); 403 local_irq_restore(flags);
374 return (ret); 404 return (ret);
diff --git a/arch/i386/kernel/cpu/cpufreq/speedstep-lib.h b/arch/i386/kernel/cpu/cpufreq/speedstep-lib.h
index 261a2c9b7f6b..6a727fd3a77e 100644
--- a/arch/i386/kernel/cpu/cpufreq/speedstep-lib.h
+++ b/arch/i386/kernel/cpu/cpufreq/speedstep-lib.h
@@ -44,4 +44,5 @@ extern unsigned int speedstep_get_processor_frequency(unsigned int processor);
44extern unsigned int speedstep_get_freqs(unsigned int processor, 44extern unsigned int speedstep_get_freqs(unsigned int processor,
45 unsigned int *low_speed, 45 unsigned int *low_speed,
46 unsigned int *high_speed, 46 unsigned int *high_speed,
47 unsigned int *transition_latency,
47 void (*set_state) (unsigned int state)); 48 void (*set_state) (unsigned int state));
diff --git a/arch/i386/kernel/cpu/cpufreq/speedstep-smi.c b/arch/i386/kernel/cpu/cpufreq/speedstep-smi.c
index 2718fb6f6aba..28cc5d524afc 100644
--- a/arch/i386/kernel/cpu/cpufreq/speedstep-smi.c
+++ b/arch/i386/kernel/cpu/cpufreq/speedstep-smi.c
@@ -269,6 +269,7 @@ static int speedstep_cpu_init(struct cpufreq_policy *policy)
269 result = speedstep_get_freqs(speedstep_processor, 269 result = speedstep_get_freqs(speedstep_processor,
270 &speedstep_freqs[SPEEDSTEP_LOW].frequency, 270 &speedstep_freqs[SPEEDSTEP_LOW].frequency,
271 &speedstep_freqs[SPEEDSTEP_HIGH].frequency, 271 &speedstep_freqs[SPEEDSTEP_HIGH].frequency,
272 NULL,
272 &speedstep_set_state); 273 &speedstep_set_state);
273 274
274 if (result) { 275 if (result) {
diff --git a/arch/i386/kernel/cpu/cyrix.c b/arch/i386/kernel/cpu/cyrix.c
index ff87cc22b323..75015975d038 100644
--- a/arch/i386/kernel/cpu/cyrix.c
+++ b/arch/i386/kernel/cpu/cyrix.c
@@ -343,6 +343,31 @@ static void __init init_cyrix(struct cpuinfo_x86 *c)
343} 343}
344 344
345/* 345/*
346 * Handle National Semiconductor branded processors
347 */
348static void __devinit init_nsc(struct cpuinfo_x86 *c)
349{
350 /* There may be GX1 processors in the wild that are branded
351 * NSC and not Cyrix.
352 *
353 * This function only handles the GX processor, and kicks every
354 * thing else to the Cyrix init function above - that should
355 * cover any processors that might have been branded differently
356 * after NSC aquired Cyrix.
357 *
358 * If this breaks your GX1 horribly, please e-mail
359 * info-linux@ldcmail.amd.com to tell us.
360 */
361
362 /* Handle the GX (Formally known as the GX2) */
363
364 if (c->x86 == 5 && c->x86_model == 5)
365 display_cacheinfo(c);
366 else
367 init_cyrix(c);
368}
369
370/*
346 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 371 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
347 * by the fact that they preserve the flags across the division of 5/2. 372 * by the fact that they preserve the flags across the division of 5/2.
348 * PII and PPro exhibit this behavior too, but they have cpuid available. 373 * PII and PPro exhibit this behavior too, but they have cpuid available.
@@ -422,7 +447,7 @@ int __init cyrix_init_cpu(void)
422static struct cpu_dev nsc_cpu_dev __initdata = { 447static struct cpu_dev nsc_cpu_dev __initdata = {
423 .c_vendor = "NSC", 448 .c_vendor = "NSC",
424 .c_ident = { "Geode by NSC" }, 449 .c_ident = { "Geode by NSC" },
425 .c_init = init_cyrix, 450 .c_init = init_nsc,
426 .c_identify = generic_identify, 451 .c_identify = generic_identify,
427}; 452};
428 453
diff --git a/arch/i386/kernel/cpu/intel.c b/arch/i386/kernel/cpu/intel.c
index 5e2da704f0fa..8c0120186b9f 100644
--- a/arch/i386/kernel/cpu/intel.c
+++ b/arch/i386/kernel/cpu/intel.c
@@ -183,10 +183,13 @@ static void __devinit init_intel(struct cpuinfo_x86 *c)
183 } 183 }
184#endif 184#endif
185 185
186 if (c->x86 == 15) 186 if (c->x86 == 15)
187 set_bit(X86_FEATURE_P4, c->x86_capability); 187 set_bit(X86_FEATURE_P4, c->x86_capability);
188 if (c->x86 == 6) 188 if (c->x86 == 6)
189 set_bit(X86_FEATURE_P3, c->x86_capability); 189 set_bit(X86_FEATURE_P3, c->x86_capability);
190 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
191 (c->x86 == 0x6 && c->x86_model >= 0x0e))
192 set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
190} 193}
191 194
192 195
diff --git a/arch/i386/kernel/cpu/mtrr/changelog b/arch/i386/kernel/cpu/mtrr/changelog
deleted file mode 100644
index af1368535955..000000000000
--- a/arch/i386/kernel/cpu/mtrr/changelog
+++ /dev/null
@@ -1,229 +0,0 @@
1 ChangeLog
2
3 Prehistory Martin Tischhäuser <martin@ikcbarka.fzk.de>
4 Initial register-setting code (from proform-1.0).
5 19971216 Richard Gooch <rgooch@atnf.csiro.au>
6 Original version for /proc/mtrr interface, SMP-safe.
7 v1.0
8 19971217 Richard Gooch <rgooch@atnf.csiro.au>
9 Bug fix for ioctls()'s.
10 Added sample code in Documentation/mtrr.txt
11 v1.1
12 19971218 Richard Gooch <rgooch@atnf.csiro.au>
13 Disallow overlapping regions.
14 19971219 Jens Maurer <jmaurer@menuett.rhein-main.de>
15 Register-setting fixups.
16 v1.2
17 19971222 Richard Gooch <rgooch@atnf.csiro.au>
18 Fixups for kernel 2.1.75.
19 v1.3
20 19971229 David Wragg <dpw@doc.ic.ac.uk>
21 Register-setting fixups and conformity with Intel conventions.
22 19971229 Richard Gooch <rgooch@atnf.csiro.au>
23 Cosmetic changes and wrote this ChangeLog ;-)
24 19980106 Richard Gooch <rgooch@atnf.csiro.au>
25 Fixups for kernel 2.1.78.
26 v1.4
27 19980119 David Wragg <dpw@doc.ic.ac.uk>
28 Included passive-release enable code (elsewhere in PCI setup).
29 v1.5
30 19980131 Richard Gooch <rgooch@atnf.csiro.au>
31 Replaced global kernel lock with private spinlock.
32 v1.6
33 19980201 Richard Gooch <rgooch@atnf.csiro.au>
34 Added wait for other CPUs to complete changes.
35 v1.7
36 19980202 Richard Gooch <rgooch@atnf.csiro.au>
37 Bug fix in definition of <set_mtrr> for UP.
38 v1.8
39 19980319 Richard Gooch <rgooch@atnf.csiro.au>
40 Fixups for kernel 2.1.90.
41 19980323 Richard Gooch <rgooch@atnf.csiro.au>
42 Move SMP BIOS fixup before secondary CPUs call <calibrate_delay>
43 v1.9
44 19980325 Richard Gooch <rgooch@atnf.csiro.au>
45 Fixed test for overlapping regions: confused by adjacent regions
46 19980326 Richard Gooch <rgooch@atnf.csiro.au>
47 Added wbinvd in <set_mtrr_prepare>.
48 19980401 Richard Gooch <rgooch@atnf.csiro.au>
49 Bug fix for non-SMP compilation.
50 19980418 David Wragg <dpw@doc.ic.ac.uk>
51 Fixed-MTRR synchronisation for SMP and use atomic operations
52 instead of spinlocks.
53 19980418 Richard Gooch <rgooch@atnf.csiro.au>
54 Differentiate different MTRR register classes for BIOS fixup.
55 v1.10
56 19980419 David Wragg <dpw@doc.ic.ac.uk>
57 Bug fix in variable MTRR synchronisation.
58 v1.11
59 19980419 Richard Gooch <rgooch@atnf.csiro.au>
60 Fixups for kernel 2.1.97.
61 v1.12
62 19980421 Richard Gooch <rgooch@atnf.csiro.au>
63 Safer synchronisation across CPUs when changing MTRRs.
64 v1.13
65 19980423 Richard Gooch <rgooch@atnf.csiro.au>
66 Bugfix for SMP systems without MTRR support.
67 v1.14
68 19980427 Richard Gooch <rgooch@atnf.csiro.au>
69 Trap calls to <mtrr_add> and <mtrr_del> on non-MTRR machines.
70 v1.15
71 19980427 Richard Gooch <rgooch@atnf.csiro.au>
72 Use atomic bitops for setting SMP change mask.
73 v1.16
74 19980428 Richard Gooch <rgooch@atnf.csiro.au>
75 Removed spurious diagnostic message.
76 v1.17
77 19980429 Richard Gooch <rgooch@atnf.csiro.au>
78 Moved register-setting macros into this file.
79 Moved setup code from init/main.c to i386-specific areas.
80 v1.18
81 19980502 Richard Gooch <rgooch@atnf.csiro.au>
82 Moved MTRR detection outside conditionals in <mtrr_init>.
83 v1.19
84 19980502 Richard Gooch <rgooch@atnf.csiro.au>
85 Documentation improvement: mention Pentium II and AGP.
86 v1.20
87 19980521 Richard Gooch <rgooch@atnf.csiro.au>
88 Only manipulate interrupt enable flag on local CPU.
89 Allow enclosed uncachable regions.
90 v1.21
91 19980611 Richard Gooch <rgooch@atnf.csiro.au>
92 Always define <main_lock>.
93 v1.22
94 19980901 Richard Gooch <rgooch@atnf.csiro.au>
95 Removed module support in order to tidy up code.
96 Added sanity check for <mtrr_add>/<mtrr_del> before <mtrr_init>.
97 Created addition queue for prior to SMP commence.
98 v1.23
99 19980902 Richard Gooch <rgooch@atnf.csiro.au>
100 Ported patch to kernel 2.1.120-pre3.
101 v1.24
102 19980910 Richard Gooch <rgooch@atnf.csiro.au>
103 Removed sanity checks and addition queue: Linus prefers an OOPS.
104 v1.25
105 19981001 Richard Gooch <rgooch@atnf.csiro.au>
106 Fixed harmless compiler warning in include/asm-i386/mtrr.h
107 Fixed version numbering and history for v1.23 -> v1.24.
108 v1.26
109 19990118 Richard Gooch <rgooch@atnf.csiro.au>
110 Added devfs support.
111 v1.27
112 19990123 Richard Gooch <rgooch@atnf.csiro.au>
113 Changed locking to spin with reschedule.
114 Made use of new <smp_call_function>.
115 v1.28
116 19990201 Zoltán Böszörményi <zboszor@mail.externet.hu>
117 Extended the driver to be able to use Cyrix style ARRs.
118 19990204 Richard Gooch <rgooch@atnf.csiro.au>
119 Restructured Cyrix support.
120 v1.29
121 19990204 Zoltán Böszörményi <zboszor@mail.externet.hu>
122 Refined ARR support: enable MAPEN in set_mtrr_prepare()
123 and disable MAPEN in set_mtrr_done().
124 19990205 Richard Gooch <rgooch@atnf.csiro.au>
125 Minor cleanups.
126 v1.30
127 19990208 Zoltán Böszörményi <zboszor@mail.externet.hu>
128 Protect plain 6x86s (and other processors without the
129 Page Global Enable feature) against accessing CR4 in
130 set_mtrr_prepare() and set_mtrr_done().
131 19990210 Richard Gooch <rgooch@atnf.csiro.au>
132 Turned <set_mtrr_up> and <get_mtrr> into function pointers.
133 v1.31
134 19990212 Zoltán Böszörményi <zboszor@mail.externet.hu>
135 Major rewrite of cyrix_arr_init(): do not touch ARRs,
136 leave them as the BIOS have set them up.
137 Enable usage of all 8 ARRs.
138 Avoid multiplications by 3 everywhere and other
139 code clean ups/speed ups.
140 19990213 Zoltán Böszörményi <zboszor@mail.externet.hu>
141 Set up other Cyrix processors identical to the boot cpu.
142 Since Cyrix don't support Intel APIC, this is l'art pour l'art.
143 Weigh ARRs by size:
144 If size <= 32M is given, set up ARR# we were given.
145 If size > 32M is given, set up ARR7 only if it is free,
146 fail otherwise.
147 19990214 Zoltán Böszörményi <zboszor@mail.externet.hu>
148 Also check for size >= 256K if we are to set up ARR7,
149 mtrr_add() returns the value it gets from set_mtrr()
150 19990218 Zoltán Böszörményi <zboszor@mail.externet.hu>
151 Remove Cyrix "coma bug" workaround from here.
152 Moved to linux/arch/i386/kernel/setup.c and
153 linux/include/asm-i386/bugs.h
154 19990228 Richard Gooch <rgooch@atnf.csiro.au>
155 Added MTRRIOC_KILL_ENTRY ioctl(2)
156 Trap for counter underflow in <mtrr_file_del>.
157 Trap for 4 MiB aligned regions for PPro, stepping <= 7.
158 19990301 Richard Gooch <rgooch@atnf.csiro.au>
159 Created <get_free_region> hook.
160 19990305 Richard Gooch <rgooch@atnf.csiro.au>
161 Temporarily disable AMD support now MTRR capability flag is set.
162 v1.32
163 19990308 Zoltán Böszörményi <zboszor@mail.externet.hu>
164 Adjust my changes (19990212-19990218) to Richard Gooch's
165 latest changes. (19990228-19990305)
166 v1.33
167 19990309 Richard Gooch <rgooch@atnf.csiro.au>
168 Fixed typo in <printk> message.
169 19990310 Richard Gooch <rgooch@atnf.csiro.au>
170 Support K6-II/III based on Alan Cox's <alan@redhat.com> patches.
171 v1.34
172 19990511 Bart Hartgers <bart@etpmod.phys.tue.nl>
173 Support Centaur C6 MCR's.
174 19990512 Richard Gooch <rgooch@atnf.csiro.au>
175 Minor cleanups.
176 v1.35
177 19990707 Zoltán Böszörményi <zboszor@mail.externet.hu>
178 Check whether ARR3 is protected in cyrix_get_free_region()
179 and mtrr_del(). The code won't attempt to delete or change it
180 from now on if the BIOS protected ARR3. It silently skips ARR3
181 in cyrix_get_free_region() or returns with an error code from
182 mtrr_del().
183 19990711 Zoltán Böszörményi <zboszor@mail.externet.hu>
184 Reset some bits in the CCRs in cyrix_arr_init() to disable SMM
185 if ARR3 isn't protected. This is needed because if SMM is active
186 and ARR3 isn't protected then deleting and setting ARR3 again
187 may lock up the processor. With SMM entirely disabled, it does
188 not happen.
189 19990812 Zoltán Böszörményi <zboszor@mail.externet.hu>
190 Rearrange switch() statements so the driver accomodates to
191 the fact that the AMD Athlon handles its MTRRs the same way
192 as Intel does.
193 19990814 Zoltán Böszörményi <zboszor@mail.externet.hu>
194 Double check for Intel in mtrr_add()'s big switch() because
195 that revision check is only valid for Intel CPUs.
196 19990819 Alan Cox <alan@redhat.com>
197 Tested Zoltan's changes on a pre production Athlon - 100%
198 success.
199 19991008 Manfred Spraul <manfreds@colorfullife.com>
200 replaced spin_lock_reschedule() with a normal semaphore.
201 v1.36
202 20000221 Richard Gooch <rgooch@atnf.csiro.au>
203 Compile fix if procfs and devfs not enabled.
204 Formatting changes.
205 v1.37
206 20001109 H. Peter Anvin <hpa@zytor.com>
207 Use the new centralized CPU feature detects.
208
209 v1.38
210 20010309 Dave Jones <davej@suse.de>
211 Add support for Cyrix III.
212
213 v1.39
214 20010312 Dave Jones <davej@suse.de>
215 Ugh, I broke AMD support.
216 Reworked fix by Troels Walsted Hansen <troels@thule.no>
217
218 v1.40
219 20010327 Dave Jones <davej@suse.de>
220 Adapted Cyrix III support to include VIA C3.
221
222 v2.0
223 20020306 Patrick Mochel <mochel@osdl.org>
224 Split mtrr.c -> mtrr/*.c
225 Converted to Linux Kernel Coding Style
226 Fixed several minor nits in form
227 Moved some SMP-only functions out, so they can be used
228 for power management in the future.
229 TODO: Fix user interface cruft.
diff --git a/arch/i386/kernel/cpu/mtrr/if.c b/arch/i386/kernel/cpu/mtrr/if.c
index cf39e205d33c..5ac051bb9d55 100644
--- a/arch/i386/kernel/cpu/mtrr/if.c
+++ b/arch/i386/kernel/cpu/mtrr/if.c
@@ -1,5 +1,6 @@
1#include <linux/init.h> 1#include <linux/init.h>
2#include <linux/proc_fs.h> 2#include <linux/proc_fs.h>
3#include <linux/capability.h>
3#include <linux/ctype.h> 4#include <linux/ctype.h>
4#include <linux/module.h> 5#include <linux/module.h>
5#include <linux/seq_file.h> 6#include <linux/seq_file.h>
diff --git a/arch/i386/kernel/cpu/proc.c b/arch/i386/kernel/cpu/proc.c
index e7921315ae9d..89a85af33d28 100644
--- a/arch/i386/kernel/cpu/proc.c
+++ b/arch/i386/kernel/cpu/proc.c
@@ -3,6 +3,7 @@
3#include <linux/string.h> 3#include <linux/string.h>
4#include <asm/semaphore.h> 4#include <asm/semaphore.h>
5#include <linux/seq_file.h> 5#include <linux/seq_file.h>
6#include <linux/cpufreq.h>
6 7
7/* 8/*
8 * Get CPU information for use by the procfs. 9 * Get CPU information for use by the procfs.
@@ -28,7 +29,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
28 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 29 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
29 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL, 30 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
30 NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL, 31 NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL,
31 NULL, "fxsr_opt", NULL, NULL, NULL, "lm", "3dnowext", "3dnow", 32 NULL, "fxsr_opt", "rdtscp", NULL, NULL, "lm", "3dnowext", "3dnow",
32 33
33 /* Transmeta-defined */ 34 /* Transmeta-defined */
34 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL, 35 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
@@ -39,7 +40,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
39 /* Other (Linux-defined) */ 40 /* Other (Linux-defined) */
40 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr", 41 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
41 NULL, NULL, NULL, NULL, 42 NULL, NULL, NULL, NULL,
42 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 43 "constant_tsc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
43 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 44 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
44 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 45 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
45 46
@@ -56,11 +57,21 @@ static int show_cpuinfo(struct seq_file *m, void *v)
56 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 57 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
57 58
58 /* AMD-defined (#2) */ 59 /* AMD-defined (#2) */
59 "lahf_lm", "cmp_legacy", NULL, NULL, NULL, NULL, NULL, NULL, 60 "lahf_lm", "cmp_legacy", "svm", NULL, "cr8legacy", NULL, NULL, NULL,
60 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 61 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
61 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 62 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
62 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 63 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
63 }; 64 };
65 static char *x86_power_flags[] = {
66 "ts", /* temperature sensor */
67 "fid", /* frequency id control */
68 "vid", /* voltage id control */
69 "ttp", /* thermal trip */
70 "tm",
71 "stc",
72 NULL,
73 /* nothing */ /* constant_tsc - moved to flags */
74 };
64 struct cpuinfo_x86 *c = v; 75 struct cpuinfo_x86 *c = v;
65 int i, n = c - cpu_data; 76 int i, n = c - cpu_data;
66 int fpu_exception; 77 int fpu_exception;
@@ -86,8 +97,11 @@ static int show_cpuinfo(struct seq_file *m, void *v)
86 seq_printf(m, "stepping\t: unknown\n"); 97 seq_printf(m, "stepping\t: unknown\n");
87 98
88 if ( cpu_has(c, X86_FEATURE_TSC) ) { 99 if ( cpu_has(c, X86_FEATURE_TSC) ) {
100 unsigned int freq = cpufreq_quick_get(n);
101 if (!freq)
102 freq = cpu_khz;
89 seq_printf(m, "cpu MHz\t\t: %u.%03u\n", 103 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
90 cpu_khz / 1000, (cpu_khz % 1000)); 104 freq / 1000, (freq % 1000));
91 } 105 }
92 106
93 /* Cache size */ 107 /* Cache size */
@@ -127,6 +141,17 @@ static int show_cpuinfo(struct seq_file *m, void *v)
127 x86_cap_flags[i] != NULL ) 141 x86_cap_flags[i] != NULL )
128 seq_printf(m, " %s", x86_cap_flags[i]); 142 seq_printf(m, " %s", x86_cap_flags[i]);
129 143
144 for (i = 0; i < 32; i++)
145 if (c->x86_power & (1 << i)) {
146 if (i < ARRAY_SIZE(x86_power_flags) &&
147 x86_power_flags[i])
148 seq_printf(m, "%s%s",
149 x86_power_flags[i][0]?" ":"",
150 x86_power_flags[i]);
151 else
152 seq_printf(m, " [%d]", i);
153 }
154
130 seq_printf(m, "\nbogomips\t: %lu.%02lu\n\n", 155 seq_printf(m, "\nbogomips\t: %lu.%02lu\n\n",
131 c->loops_per_jiffy/(500000/HZ), 156 c->loops_per_jiffy/(500000/HZ),
132 (c->loops_per_jiffy/(5000/HZ)) % 100); 157 (c->loops_per_jiffy/(5000/HZ)) % 100);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 03:31:14 -0500