6 files changed, 144 insertions, 42 deletions

diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c
index 786d1a57048b..e6a2d6b80cda 100644
--- a/arch/i386/kernel/cpu/amd.c
+++ b/arch/i386/kernel/cpu/amd.c
@@ -224,22 +224,26 @@ static void __init init_amd(struct cpuinfo_x86 *c)
 
 #ifdef CONFIG_X86_HT
         /*
-         * On a AMD dual core setup the lower bits of the APIC id
-         * distingush the cores.  Assumes number of cores is a power
-         * of two.
+         * On a AMD multi core setup the lower bits of the APIC id
+         * distingush the cores.
          */
         if (c->x86_max_cores > 1) {
                 int cpu = smp_processor_id();
-                unsigned bits = 0;
-                while ((1 << bits) < c->x86_max_cores)
-                        bits++;
-                cpu_core_id[cpu] = phys_proc_id[cpu] & ((1<<bits)-1);
-                phys_proc_id[cpu] >>= bits;
+                unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
+
+                if (bits == 0) {
+                        while ((1 << bits) < c->x86_max_cores)
+                                bits++;
+                }
+                c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
+                c->phys_proc_id >>= bits;
                 printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
-                       cpu, c->x86_max_cores, cpu_core_id[cpu]);
+                       cpu, c->x86_max_cores, c->cpu_core_id);
         }
 #endif
 
+        if (cpuid_eax(0x80000000) >= 0x80000006)
+                num_cache_leaves = 3;
 }
 
 static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
diff --git a/arch/i386/kernel/cpu/common.c b/arch/i386/kernel/cpu/common.c
index 44f2c5f2dda1..70c87de582c7 100644
--- a/arch/i386/kernel/cpu/common.c
+++ b/arch/i386/kernel/cpu/common.c
@@ -294,7 +294,7 @@ void __cpuinit generic_identify(struct cpuinfo_x86 * c)
                         if (c->x86 >= 0x6)
                                 c->x86_model += ((tfms >> 16) & 0xF) << 4;
                         c->x86_mask = tfms & 15;
-#ifdef CONFIG_SMP
+#ifdef CONFIG_X86_HT
                         c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
 #else
                         c->apicid = (ebx >> 24) & 0xFF;
@@ -319,7 +319,7 @@ void __cpuinit generic_identify(struct cpuinfo_x86 * c)
         early_intel_workaround(c);
 
 #ifdef CONFIG_X86_HT
-        phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
+        c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
 #endif
 }
 
@@ -477,11 +477,9 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 {
         u32     eax, ebx, ecx, edx;
         int     index_msb, core_bits;
-        int     cpu = smp_processor_id();
 
         cpuid(1, &eax, &ebx, &ecx, &edx);
 
-
         if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
                 return;
 
@@ -492,16 +490,17 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
         } else if (smp_num_siblings > 1 ) {
 
                 if (smp_num_siblings > NR_CPUS) {
-                        printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
+                        printk(KERN_WARNING "CPU: Unsupported number of the "
+                                        "siblings %d", smp_num_siblings);
                         smp_num_siblings = 1;
                         return;
                 }
 
                 index_msb = get_count_order(smp_num_siblings);
-                phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
+                c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
 
                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
-                       phys_proc_id[cpu]);
+                       c->phys_proc_id);
 
                 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
 
@@ -509,12 +508,12 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 
                 core_bits = get_count_order(c->x86_max_cores);
 
-                cpu_core_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
+                c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
                                                ((1 << core_bits) - 1);
 
                 if (c->x86_max_cores > 1)
                         printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
-                               cpu_core_id[cpu]);
+                               c->cpu_core_id);
         }
 }
 #endif
@@ -613,6 +612,12 @@ void __cpuinit cpu_init(void)
                 set_in_cr4(X86_CR4_TSD);
         }
 
+        /* The CPU hotplug case */
+        if (cpu_gdt_descr->address) {
+                gdt = (struct desc_struct *)cpu_gdt_descr->address;
+                memset(gdt, 0, PAGE_SIZE);
+                goto old_gdt;
+        }
         /*
          * This is a horrible hack to allocate the GDT.  The problem
          * is that cpu_init() is called really early for the boot CPU
@@ -631,7 +636,7 @@ void __cpuinit cpu_init(void)
                                 local_irq_enable();
                 }
         }
-
+old_gdt:
         /*
          * Initialize the per-CPU GDT with the boot GDT,
          * and set up the GDT descriptor:
diff --git a/arch/i386/kernel/cpu/cyrix.c b/arch/i386/kernel/cpu/cyrix.c
index fc32c8028e24..f03b7f94c304 100644
--- a/arch/i386/kernel/cpu/cyrix.c
+++ b/arch/i386/kernel/cpu/cyrix.c
@@ -354,7 +354,7 @@ static void __init init_nsc(struct cpuinfo_x86 *c)
          * This function only handles the GX processor, and kicks every
          * thing else to the Cyrix init function above - that should
          * cover any processors that might have been branded differently
-         * after NSC aquired Cyrix.
+         * after NSC acquired Cyrix.
          *
          * If this breaks your GX1 horribly, please e-mail
          * info-linux@ldcmail.amd.com to tell us.
diff --git a/arch/i386/kernel/cpu/intel.c b/arch/i386/kernel/cpu/intel.c
index 5386b29bb5a5..10afc645c540 100644
--- a/arch/i386/kernel/cpu/intel.c
+++ b/arch/i386/kernel/cpu/intel.c
@@ -122,6 +122,12 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
         select_idle_routine(c);
         l2 = init_intel_cacheinfo(c);
+        if (c->cpuid_level > 9 ) {
+                unsigned eax = cpuid_eax(10);
+                /* Check for version and the number of counters */
+                if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
+                        set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
+        }
 
         /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c
index c8547a6fa7e6..e9f0b928b0a9 100644
--- a/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ b/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -4,6 +4,7 @@
  *      Changes:
  *      Venkatesh Pallipadi     : Adding cache identification through cpuid(4)
  *              Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
+ *      Andi Kleen              : CPUID4 emulation on AMD.
  */
 
 #include <linux/init.h>
@@ -130,25 +131,111 @@ struct _cpuid4_info {
         cpumask_t shared_cpu_map;
 };
 
-static unsigned short                   num_cache_leaves;
+unsigned short                  num_cache_leaves;
+
+/* AMD doesn't have CPUID4. Emulate it here to report the same
+   information to the user.  This makes some assumptions about the machine:
+   No L3, L2 not shared, no SMT etc. that is currently true on AMD CPUs.
+
+   In theory the TLBs could be reported as fake type (they are in "dummy").
+   Maybe later */
+union l1_cache {
+        struct {
+                unsigned line_size : 8;
+                unsigned lines_per_tag : 8;
+                unsigned assoc : 8;
+                unsigned size_in_kb : 8;
+        };
+        unsigned val;
+};
+
+union l2_cache {
+        struct {
+                unsigned line_size : 8;
+                unsigned lines_per_tag : 4;
+                unsigned assoc : 4;
+                unsigned size_in_kb : 16;
+        };
+        unsigned val;
+};
+
+static const unsigned short assocs[] = {
+        [1] = 1, [2] = 2, [4] = 4, [6] = 8,
+        [8] = 16,
+        [0xf] = 0xffff // ??
+        };
+static const unsigned char levels[] = { 1, 1, 2 };
+static const unsigned char types[] = { 1, 2, 3 };
+
+static void __cpuinit amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
+                       union _cpuid4_leaf_ebx *ebx,
+                       union _cpuid4_leaf_ecx *ecx)
+{
+        unsigned dummy;
+        unsigned line_size, lines_per_tag, assoc, size_in_kb;
+        union l1_cache l1i, l1d;
+        union l2_cache l2;
+
+        eax->full = 0;
+        ebx->full = 0;
+        ecx->full = 0;
+
+        cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
+        cpuid(0x80000006, &dummy, &dummy, &l2.val, &dummy);
+
+        if (leaf > 2 || !l1d.val || !l1i.val || !l2.val)
+                return;
+
+        eax->split.is_self_initializing = 1;
+        eax->split.type = types[leaf];
+        eax->split.level = levels[leaf];
+        eax->split.num_threads_sharing = 0;
+        eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
+
+        if (leaf <= 1) {
+                union l1_cache *l1 = leaf == 0 ? &l1d : &l1i;
+                assoc = l1->assoc;
+                line_size = l1->line_size;
+                lines_per_tag = l1->lines_per_tag;
+                size_in_kb = l1->size_in_kb;
+        } else {
+                assoc = l2.assoc;
+                line_size = l2.line_size;
+                lines_per_tag = l2.lines_per_tag;
+                /* cpu_data has errata corrections for K7 applied */
+                size_in_kb = current_cpu_data.x86_cache_size;
+        }
+
+        if (assoc == 0xf)
+                eax->split.is_fully_associative = 1;
+        ebx->split.coherency_line_size = line_size - 1;
+        ebx->split.ways_of_associativity = assocs[assoc] - 1;
+        ebx->split.physical_line_partition = lines_per_tag - 1;
+        ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
+                (ebx->split.ways_of_associativity + 1) - 1;
+}
 
 static int __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
 {
-        unsigned int            eax, ebx, ecx, edx;
-        union _cpuid4_leaf_eax  cache_eax;
+        union _cpuid4_leaf_eax  eax;
+        union _cpuid4_leaf_ebx  ebx;
+        union _cpuid4_leaf_ecx  ecx;
+        unsigned                edx;
 
-        cpuid_count(4, index, &eax, &ebx, &ecx, &edx);
-        cache_eax.full = eax;
-        if (cache_eax.split.type == CACHE_TYPE_NULL)
+        if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+                amd_cpuid4(index, &eax, &ebx, &ecx);
+        else
+                cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full,  &edx);
+        if (eax.split.type == CACHE_TYPE_NULL)
                 return -EIO; /* better error ? */
 
-        this_leaf->eax.full = eax;
-        this_leaf->ebx.full = ebx;
-        this_leaf->ecx.full = ecx;
-        this_leaf->size = (this_leaf->ecx.split.number_of_sets + 1) *
-                (this_leaf->ebx.split.coherency_line_size + 1) *
-                (this_leaf->ebx.split.physical_line_partition + 1) *
-                (this_leaf->ebx.split.ways_of_associativity + 1);
+        this_leaf->eax = eax;
+        this_leaf->ebx = ebx;
+        this_leaf->ecx = ecx;
+        this_leaf->size = (ecx.split.number_of_sets + 1) *
+                (ebx.split.coherency_line_size + 1) *
+                (ebx.split.physical_line_partition + 1) *
+                (ebx.split.ways_of_associativity + 1);
         return 0;
 }
 
@@ -174,7 +261,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
         unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
         unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
         unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
-#ifdef CONFIG_SMP
+#ifdef CONFIG_X86_HT
         unsigned int cpu = (c == &boot_cpu_data) ? 0 : (c - cpu_data);
 #endif
 
@@ -296,14 +383,14 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
 
         if (new_l2) {
                 l2 = new_l2;
-#ifdef CONFIG_SMP
+#ifdef CONFIG_X86_HT
                 cpu_llc_id[cpu] = l2_id;
 #endif
         }
 
         if (new_l3) {
                 l3 = new_l3;
-#ifdef CONFIG_SMP
+#ifdef CONFIG_X86_HT
                 cpu_llc_id[cpu] = l3_id;
 #endif
         }
@@ -642,7 +729,7 @@ static void __cpuexit cache_remove_dev(struct sys_device * sys_dev)
         return;
 }
 
-static int cacheinfo_cpu_callback(struct notifier_block *nfb,
+static int __cpuinit cacheinfo_cpu_callback(struct notifier_block *nfb,
                                         unsigned long action, void *hcpu)
 {
         unsigned int cpu = (unsigned long)hcpu;
@@ -660,7 +747,7 @@ static int cacheinfo_cpu_callback(struct notifier_block *nfb,
         return NOTIFY_OK;
 }
 
-static struct notifier_block cacheinfo_cpu_notifier =
+static struct notifier_block __cpuinitdata cacheinfo_cpu_notifier =
 {
     .notifier_call = cacheinfo_cpu_callback,
 };
diff --git a/arch/i386/kernel/cpu/proc.c b/arch/i386/kernel/cpu/proc.c
index a19fcb262dbb..f54a15268ed7 100644
--- a/arch/i386/kernel/cpu/proc.c
+++ b/arch/i386/kernel/cpu/proc.c
@@ -18,7 +18,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
          * applications want to get the raw CPUID data, they should access
          * /dev/cpu/<cpu_nr>/cpuid instead.
          */
-        static char *x86_cap_flags[] = {
+        static const char * const x86_cap_flags[] = {
                 /* Intel-defined */
                 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
                 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
@@ -62,7 +62,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
         };
-        static char *x86_power_flags[] = {
+        static const char * const x86_power_flags[] = {
                 "ts",   /* temperature sensor */
                 "fid",  /* frequency id control */
                 "vid",  /* voltage id control */
@@ -109,9 +109,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
 #ifdef CONFIG_X86_HT
         if (c->x86_max_cores * smp_num_siblings > 1) {
-                seq_printf(m, "physical id\t: %d\n", phys_proc_id[n]);
+                seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
                 seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[n]));
-                seq_printf(m, "core id\t\t: %d\n", cpu_core_id[n]);
+                seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
                 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
         }
 #endif