1 files changed, 29 insertions, 23 deletions

diff --git a/arch/i386/kernel/cpu/cyrix.c b/arch/i386/kernel/cpu/cyrix.c
index c0c3b59de32c..de27bd07bc9c 100644
--- a/arch/i386/kernel/cpu/cyrix.c
+++ b/arch/i386/kernel/cpu/cyrix.c
@@ -6,6 +6,7 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/timer.h>
+#include <asm/pci-direct.h>
 
 #include "cpu.h"
 
@@ -161,19 +162,19 @@ static void __cpuinit set_cx86_inc(void)
 static void __cpuinit geode_configure(void)
 {
         unsigned long flags;
-        u8 ccr3, ccr4;
+        u8 ccr3;
         local_irq_save(flags);
 
         /* Suspend on halt power saving and enable #SUSP pin */
         setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
 
         ccr3 = getCx86(CX86_CCR3);
-        setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);       /* Enable */
-        
-        ccr4 = getCx86(CX86_CCR4);
-        ccr4 |= 0x38;           /* FPU fast, DTE cache, Mem bypass */
+        setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);       /* enable MAPEN */
         
-        setCx86(CX86_CCR3, ccr3);
+
+        /* FPU fast, DTE cache, Mem bypass */
+        setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38);
+        setCx86(CX86_CCR3, ccr3);                       /* disable MAPEN */
         
         set_cx86_memwb();
         set_cx86_reorder();     
@@ -183,14 +184,6 @@ static void __cpuinit geode_configure(void)
 }
 
 
-#ifdef CONFIG_PCI
-static struct pci_device_id __cpuinitdata cyrix_55x0[] = {
-        { PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510) },
-        { PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520) },
-        { },
-};
-#endif
-
 static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
 {
         unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
@@ -258,6 +251,8 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
 
         case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
 #ifdef CONFIG_PCI
+        {
+                u32 vendor, device;
                 /* It isn't really a PCI quirk directly, but the cure is the
                    same. The MediaGX has deep magic SMM stuff that handles the
                    SB emulation. It thows away the fifo on disable_dma() which
@@ -273,22 +268,34 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
                 printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n");
                 isa_dma_bridge_buggy = 2;
 
+                /* We do this before the PCI layer is running. However we
+                   are safe here as we know the bridge must be a Cyrix
+                   companion and must be present */
+                vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID);
+                device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID);
 
                 /*
                  *  The 5510/5520 companion chips have a funky PIT.
                  */  
-                if (pci_dev_present(cyrix_55x0))
+                if (vendor == PCI_VENDOR_ID_CYRIX &&
+         (device == PCI_DEVICE_ID_CYRIX_5510 || device == PCI_DEVICE_ID_CYRIX_5520))
                         pit_latch_buggy = 1;
+        }
 #endif
                 c->x86_cache_size=16;   /* Yep 16K integrated cache thats it */
 
                 /* GXm supports extended cpuid levels 'ala' AMD */
                 if (c->cpuid_level == 2) {
                         /* Enable cxMMX extensions (GX1 Datasheet 54) */
-                        setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
+                        setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);
                         
-                        /* GXlv/GXm/GX1 */
-                        if((dir1 >= 0x50 && dir1 <= 0x54) || dir1 >= 0x63)
+                        /*
+                         * GXm : 0x30 ... 0x5f GXm  datasheet 51
+                         * GXlv: 0x6x          GXlv datasheet 54
+                         *  ?  : 0x7x
+                         * GX1 : 0x8x          GX1  datasheet 56
+                         */
+                        if((0x30 <= dir1 && dir1 <= 0x6f) || (0x80 <=dir1 && dir1 <= 0x8f))
                                 geode_configure();
                         get_model_name(c);  /* get CPU marketing name */
                         return;
@@ -415,15 +422,14 @@ static void __cpuinit cyrix_identify(struct cpuinfo_x86 * c)
                 
                 if (dir0 == 5 || dir0 == 3)
                 {
-                        unsigned char ccr3, ccr4;
+                        unsigned char ccr3;
                         unsigned long flags;
                         printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
                         local_irq_save(flags);
                         ccr3 = getCx86(CX86_CCR3);
-                        setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN  */
-                        ccr4 = getCx86(CX86_CCR4);
-                        setCx86(CX86_CCR4, ccr4 | 0x80);          /* enable cpuid  */
-                        setCx86(CX86_CCR3, ccr3);                 /* disable MAPEN */
+                        setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);       /* enable MAPEN  */
+                        setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x80);  /* enable cpuid  */
+                        setCx86(CX86_CCR3, ccr3);                       /* disable MAPEN */
                         local_irq_restore(flags);
                 }
         }