diff options
Diffstat (limited to 'arch/i386/kernel/cpu/cpufreq')
-rw-r--r-- | arch/i386/kernel/cpu/cpufreq/longhaul.c | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/arch/i386/kernel/cpu/cpufreq/longhaul.c b/arch/i386/kernel/cpu/cpufreq/longhaul.c index dde4e3149179..2841735e3feb 100644 --- a/arch/i386/kernel/cpu/cpufreq/longhaul.c +++ b/arch/i386/kernel/cpu/cpufreq/longhaul.c | |||
@@ -69,6 +69,7 @@ static unsigned int minmult, maxmult; | |||
69 | static int can_scale_voltage; | 69 | static int can_scale_voltage; |
70 | static struct acpi_processor *pr = NULL; | 70 | static struct acpi_processor *pr = NULL; |
71 | static struct acpi_processor_cx *cx = NULL; | 71 | static struct acpi_processor_cx *cx = NULL; |
72 | static u32 acpi_regs_addr; | ||
72 | static u8 longhaul_flags; | 73 | static u8 longhaul_flags; |
73 | static unsigned int longhaul_index; | 74 | static unsigned int longhaul_index; |
74 | 75 | ||
@@ -247,7 +248,7 @@ static void longhaul_setstate(unsigned int table_index) | |||
247 | unsigned long flags; | 248 | unsigned long flags; |
248 | unsigned int pic1_mask, pic2_mask; | 249 | unsigned int pic1_mask, pic2_mask; |
249 | u32 bm_status = 0; | 250 | u32 bm_status = 0; |
250 | u32 bm_timeout = 100000; | 251 | u32 bm_timeout = 1000; |
251 | unsigned int dir = 0; | 252 | unsigned int dir = 0; |
252 | 253 | ||
253 | clock_ratio_index = longhaul_table[table_index].index; | 254 | clock_ratio_index = longhaul_table[table_index].index; |
@@ -282,12 +283,13 @@ static void longhaul_setstate(unsigned int table_index) | |||
282 | /* Wait while PCI bus is busy. */ | 283 | /* Wait while PCI bus is busy. */ |
283 | if (longhaul_flags & USE_NORTHBRIDGE | 284 | if (longhaul_flags & USE_NORTHBRIDGE |
284 | || ((pr != NULL) && pr->flags.bm_control)) { | 285 | || ((pr != NULL) && pr->flags.bm_control)) { |
285 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); | 286 | bm_status = inl(acpi_regs_addr); |
287 | bm_status &= 1 << 4; | ||
286 | while (bm_status && bm_timeout) { | 288 | while (bm_status && bm_timeout) { |
287 | acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); | 289 | outl(1 << 4, acpi_regs_addr); |
288 | bm_timeout--; | 290 | bm_timeout--; |
289 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, | 291 | bm_status = inl(acpi_regs_addr); |
290 | &bm_status); | 292 | bm_status &= 1 << 4; |
291 | } | 293 | } |
292 | } | 294 | } |
293 | 295 | ||
@@ -344,8 +346,7 @@ static void longhaul_setstate(unsigned int table_index) | |||
344 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | 346 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); |
345 | 347 | ||
346 | if (!bm_timeout) | 348 | if (!bm_timeout) |
347 | printk(KERN_INFO PFX "Warning: Timeout while waiting for " | 349 | printk(KERN_INFO PFX "Warning: Timeout while waiting for idle PCI bus.\n"); |
348 | "idle PCI bus.\n"); | ||
349 | } | 350 | } |
350 | 351 | ||
351 | /* | 352 | /* |
@@ -713,6 +714,14 @@ static int longhaul_setup_southbridge(void) | |||
713 | pci_read_config_byte(dev, 0xe5, &pci_cmd); | 714 | pci_read_config_byte(dev, 0xe5, &pci_cmd); |
714 | pci_cmd |= 1 << 7; | 715 | pci_cmd |= 1 << 7; |
715 | pci_write_config_byte(dev, 0xe5, pci_cmd); | 716 | pci_write_config_byte(dev, 0xe5, pci_cmd); |
717 | /* Get address of ACPI registers block*/ | ||
718 | pci_read_config_byte(dev, 0x81, &pci_cmd); | ||
719 | if (pci_cmd & 1 << 7) { | ||
720 | pci_read_config_dword(dev, 0x88, &acpi_regs_addr); | ||
721 | acpi_regs_addr &= 0xff00; | ||
722 | printk(KERN_INFO PFX "ACPI I/O at 0x%x\n", acpi_regs_addr); | ||
723 | } | ||
724 | |||
716 | pci_dev_put(dev); | 725 | pci_dev_put(dev); |
717 | return 1; | 726 | return 1; |
718 | } | 727 | } |