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diff --git a/arch/i386/kernel/apic.c b/arch/i386/kernel/apic.c
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1/*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17#include <linux/config.h>
18#include <linux/init.h>
19
20#include <linux/mm.h>
21#include <linux/irq.h>
22#include <linux/delay.h>
23#include <linux/bootmem.h>
24#include <linux/smp_lock.h>
25#include <linux/interrupt.h>
26#include <linux/mc146818rtc.h>
27#include <linux/kernel_stat.h>
28#include <linux/sysdev.h>
29
30#include <asm/atomic.h>
31#include <asm/smp.h>
32#include <asm/mtrr.h>
33#include <asm/mpspec.h>
34#include <asm/desc.h>
35#include <asm/arch_hooks.h>
36#include <asm/hpet.h>
37
38#include <mach_apic.h>
39
40#include "io_ports.h"
41
42/*
43 * Debug level
44 */
45int apic_verbosity;
46
47
48static void apic_pm_activate(void);
49
50/*
51 * 'what should we do if we get a hw irq event on an illegal vector'.
52 * each architecture has to answer this themselves.
53 */
54void ack_bad_irq(unsigned int irq)
55{
56 printk("unexpected IRQ trap at vector %02x\n", irq);
57 /*
58 * Currently unexpected vectors happen only on SMP and APIC.
59 * We _must_ ack these because every local APIC has only N
60 * irq slots per priority level, and a 'hanging, unacked' IRQ
61 * holds up an irq slot - in excessive cases (when multiple
62 * unexpected vectors occur) that might lock up the APIC
63 * completely.
64 */
65 ack_APIC_irq();
66}
67
68void __init apic_intr_init(void)
69{
70#ifdef CONFIG_SMP
71 smp_intr_init();
72#endif
73 /* self generated IPI for local APIC timer */
74 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
75
76 /* IPI vectors for APIC spurious and error interrupts */
77 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
78 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
79
80 /* thermal monitor LVT interrupt */
81#ifdef CONFIG_X86_MCE_P4THERMAL
82 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
83#endif
84}
85
86/* Using APIC to generate smp_local_timer_interrupt? */
87int using_apic_timer = 0;
88
89static DEFINE_PER_CPU(int, prof_multiplier) = 1;
90static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
91static DEFINE_PER_CPU(int, prof_counter) = 1;
92
93static int enabled_via_apicbase;
94
95void enable_NMI_through_LVT0 (void * dummy)
96{
97 unsigned int v, ver;
98
99 ver = apic_read(APIC_LVR);
100 ver = GET_APIC_VERSION(ver);
101 v = APIC_DM_NMI; /* unmask and set to NMI */
102 if (!APIC_INTEGRATED(ver)) /* 82489DX */
103 v |= APIC_LVT_LEVEL_TRIGGER;
104 apic_write_around(APIC_LVT0, v);
105}
106
107int get_physical_broadcast(void)
108{
109 unsigned int lvr, version;
110 lvr = apic_read(APIC_LVR);
111 version = GET_APIC_VERSION(lvr);
112 if (!APIC_INTEGRATED(version) || version >= 0x14)
113 return 0xff;
114 else
115 return 0xf;
116}
117
118int get_maxlvt(void)
119{
120 unsigned int v, ver, maxlvt;
121
122 v = apic_read(APIC_LVR);
123 ver = GET_APIC_VERSION(v);
124 /* 82489DXs do not report # of LVT entries. */
125 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
126 return maxlvt;
127}
128
129void clear_local_APIC(void)
130{
131 int maxlvt;
132 unsigned long v;
133
134 maxlvt = get_maxlvt();
135
136 /*
137 * Masking an LVT entry on a P6 can trigger a local APIC error
138 * if the vector is zero. Mask LVTERR first to prevent this.
139 */
140 if (maxlvt >= 3) {
141 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
142 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
143 }
144 /*
145 * Careful: we have to set masks only first to deassert
146 * any level-triggered sources.
147 */
148 v = apic_read(APIC_LVTT);
149 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
150 v = apic_read(APIC_LVT0);
151 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
152 v = apic_read(APIC_LVT1);
153 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
154 if (maxlvt >= 4) {
155 v = apic_read(APIC_LVTPC);
156 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
157 }
158
159/* lets not touch this if we didn't frob it */
160#ifdef CONFIG_X86_MCE_P4THERMAL
161 if (maxlvt >= 5) {
162 v = apic_read(APIC_LVTTHMR);
163 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
164 }
165#endif
166 /*
167 * Clean APIC state for other OSs:
168 */
169 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
170 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
171 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
172 if (maxlvt >= 3)
173 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
174 if (maxlvt >= 4)
175 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
176
177#ifdef CONFIG_X86_MCE_P4THERMAL
178 if (maxlvt >= 5)
179 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
180#endif
181 v = GET_APIC_VERSION(apic_read(APIC_LVR));
182 if (APIC_INTEGRATED(v)) { /* !82489DX */
183 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
184 apic_write(APIC_ESR, 0);
185 apic_read(APIC_ESR);
186 }
187}
188
189void __init connect_bsp_APIC(void)
190{
191 if (pic_mode) {
192 /*
193 * Do not trust the local APIC being empty at bootup.
194 */
195 clear_local_APIC();
196 /*
197 * PIC mode, enable APIC mode in the IMCR, i.e.
198 * connect BSP's local APIC to INT and NMI lines.
199 */
200 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
201 "enabling APIC mode.\n");
202 outb(0x70, 0x22);
203 outb(0x01, 0x23);
204 }
205 enable_apic_mode();
206}
207
208void disconnect_bsp_APIC(void)
209{
210 if (pic_mode) {
211 /*
212 * Put the board back into PIC mode (has an effect
213 * only on certain older boards). Note that APIC
214 * interrupts, including IPIs, won't work beyond
215 * this point! The only exception are INIT IPIs.
216 */
217 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
218 "entering PIC mode.\n");
219 outb(0x70, 0x22);
220 outb(0x00, 0x23);
221 }
222}
223
224void disable_local_APIC(void)
225{
226 unsigned long value;
227
228 clear_local_APIC();
229
230 /*
231 * Disable APIC (implies clearing of registers
232 * for 82489DX!).
233 */
234 value = apic_read(APIC_SPIV);
235 value &= ~APIC_SPIV_APIC_ENABLED;
236 apic_write_around(APIC_SPIV, value);
237
238 if (enabled_via_apicbase) {
239 unsigned int l, h;
240 rdmsr(MSR_IA32_APICBASE, l, h);
241 l &= ~MSR_IA32_APICBASE_ENABLE;
242 wrmsr(MSR_IA32_APICBASE, l, h);
243 }
244}
245
246/*
247 * This is to verify that we're looking at a real local APIC.
248 * Check these against your board if the CPUs aren't getting
249 * started for no apparent reason.
250 */
251int __init verify_local_APIC(void)
252{
253 unsigned int reg0, reg1;
254
255 /*
256 * The version register is read-only in a real APIC.
257 */
258 reg0 = apic_read(APIC_LVR);
259 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
260 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
261 reg1 = apic_read(APIC_LVR);
262 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
263
264 /*
265 * The two version reads above should print the same
266 * numbers. If the second one is different, then we
267 * poke at a non-APIC.
268 */
269 if (reg1 != reg0)
270 return 0;
271
272 /*
273 * Check if the version looks reasonably.
274 */
275 reg1 = GET_APIC_VERSION(reg0);
276 if (reg1 == 0x00 || reg1 == 0xff)
277 return 0;
278 reg1 = get_maxlvt();
279 if (reg1 < 0x02 || reg1 == 0xff)
280 return 0;
281
282 /*
283 * The ID register is read/write in a real APIC.
284 */
285 reg0 = apic_read(APIC_ID);
286 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
287
288 /*
289 * The next two are just to see if we have sane values.
290 * They're only really relevant if we're in Virtual Wire
291 * compatibility mode, but most boxes are anymore.
292 */
293 reg0 = apic_read(APIC_LVT0);
294 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
295 reg1 = apic_read(APIC_LVT1);
296 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
297
298 return 1;
299}
300
301void __init sync_Arb_IDs(void)
302{
303 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
304 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
305 if (ver >= 0x14) /* P4 or higher */
306 return;
307 /*
308 * Wait for idle.
309 */
310 apic_wait_icr_idle();
311
312 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
313 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
314 | APIC_DM_INIT);
315}
316
317extern void __error_in_apic_c (void);
318
319/*
320 * An initial setup of the virtual wire mode.
321 */
322void __init init_bsp_APIC(void)
323{
324 unsigned long value, ver;
325
326 /*
327 * Don't do the setup now if we have a SMP BIOS as the
328 * through-I/O-APIC virtual wire mode might be active.
329 */
330 if (smp_found_config || !cpu_has_apic)
331 return;
332
333 value = apic_read(APIC_LVR);
334 ver = GET_APIC_VERSION(value);
335
336 /*
337 * Do not trust the local APIC being empty at bootup.
338 */
339 clear_local_APIC();
340
341 /*
342 * Enable APIC.
343 */
344 value = apic_read(APIC_SPIV);
345 value &= ~APIC_VECTOR_MASK;
346 value |= APIC_SPIV_APIC_ENABLED;
347
348 /* This bit is reserved on P4/Xeon and should be cleared */
349 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
350 value &= ~APIC_SPIV_FOCUS_DISABLED;
351 else
352 value |= APIC_SPIV_FOCUS_DISABLED;
353 value |= SPURIOUS_APIC_VECTOR;
354 apic_write_around(APIC_SPIV, value);
355
356 /*
357 * Set up the virtual wire mode.
358 */
359 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
360 value = APIC_DM_NMI;
361 if (!APIC_INTEGRATED(ver)) /* 82489DX */
362 value |= APIC_LVT_LEVEL_TRIGGER;
363 apic_write_around(APIC_LVT1, value);
364}
365
366void __init setup_local_APIC (void)
367{
368 unsigned long oldvalue, value, ver, maxlvt;
369
370 /* Pound the ESR really hard over the head with a big hammer - mbligh */
371 if (esr_disable) {
372 apic_write(APIC_ESR, 0);
373 apic_write(APIC_ESR, 0);
374 apic_write(APIC_ESR, 0);
375 apic_write(APIC_ESR, 0);
376 }
377
378 value = apic_read(APIC_LVR);
379 ver = GET_APIC_VERSION(value);
380
381 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
382 __error_in_apic_c();
383
384 /*
385 * Double-check whether this APIC is really registered.
386 */
387 if (!apic_id_registered())
388 BUG();
389
390 /*
391 * Intel recommends to set DFR, LDR and TPR before enabling
392 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
393 * document number 292116). So here it goes...
394 */
395 init_apic_ldr();
396
397 /*
398 * Set Task Priority to 'accept all'. We never change this
399 * later on.
400 */
401 value = apic_read(APIC_TASKPRI);
402 value &= ~APIC_TPRI_MASK;
403 apic_write_around(APIC_TASKPRI, value);
404
405 /*
406 * Now that we are all set up, enable the APIC
407 */
408 value = apic_read(APIC_SPIV);
409 value &= ~APIC_VECTOR_MASK;
410 /*
411 * Enable APIC
412 */
413 value |= APIC_SPIV_APIC_ENABLED;
414
415 /*
416 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
417 * certain networking cards. If high frequency interrupts are
418 * happening on a particular IOAPIC pin, plus the IOAPIC routing
419 * entry is masked/unmasked at a high rate as well then sooner or
420 * later IOAPIC line gets 'stuck', no more interrupts are received
421 * from the device. If focus CPU is disabled then the hang goes
422 * away, oh well :-(
423 *
424 * [ This bug can be reproduced easily with a level-triggered
425 * PCI Ne2000 networking cards and PII/PIII processors, dual
426 * BX chipset. ]
427 */
428 /*
429 * Actually disabling the focus CPU check just makes the hang less
430 * frequent as it makes the interrupt distributon model be more
431 * like LRU than MRU (the short-term load is more even across CPUs).
432 * See also the comment in end_level_ioapic_irq(). --macro
433 */
434#if 1
435 /* Enable focus processor (bit==0) */
436 value &= ~APIC_SPIV_FOCUS_DISABLED;
437#else
438 /* Disable focus processor (bit==1) */
439 value |= APIC_SPIV_FOCUS_DISABLED;
440#endif
441 /*
442 * Set spurious IRQ vector
443 */
444 value |= SPURIOUS_APIC_VECTOR;
445 apic_write_around(APIC_SPIV, value);
446
447 /*
448 * Set up LVT0, LVT1:
449 *
450 * set up through-local-APIC on the BP's LINT0. This is not
451 * strictly necessery in pure symmetric-IO mode, but sometimes
452 * we delegate interrupts to the 8259A.
453 */
454 /*
455 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
456 */
457 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
458 if (!smp_processor_id() && (pic_mode || !value)) {
459 value = APIC_DM_EXTINT;
460 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
461 smp_processor_id());
462 } else {
463 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
464 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
465 smp_processor_id());
466 }
467 apic_write_around(APIC_LVT0, value);
468
469 /*
470 * only the BP should see the LINT1 NMI signal, obviously.
471 */
472 if (!smp_processor_id())
473 value = APIC_DM_NMI;
474 else
475 value = APIC_DM_NMI | APIC_LVT_MASKED;
476 if (!APIC_INTEGRATED(ver)) /* 82489DX */
477 value |= APIC_LVT_LEVEL_TRIGGER;
478 apic_write_around(APIC_LVT1, value);
479
480 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
481 maxlvt = get_maxlvt();
482 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
483 apic_write(APIC_ESR, 0);
484 oldvalue = apic_read(APIC_ESR);
485
486 value = ERROR_APIC_VECTOR; // enables sending errors
487 apic_write_around(APIC_LVTERR, value);
488 /*
489 * spec says clear errors after enabling vector.
490 */
491 if (maxlvt > 3)
492 apic_write(APIC_ESR, 0);
493 value = apic_read(APIC_ESR);
494 if (value != oldvalue)
495 apic_printk(APIC_VERBOSE, "ESR value before enabling "
496 "vector: 0x%08lx after: 0x%08lx\n",
497 oldvalue, value);
498 } else {
499 if (esr_disable)
500 /*
501 * Something untraceble is creating bad interrupts on
502 * secondary quads ... for the moment, just leave the
503 * ESR disabled - we can't do anything useful with the
504 * errors anyway - mbligh
505 */
506 printk("Leaving ESR disabled.\n");
507 else
508 printk("No ESR for 82489DX.\n");
509 }
510
511 if (nmi_watchdog == NMI_LOCAL_APIC)
512 setup_apic_nmi_watchdog();
513 apic_pm_activate();
514}
515
516/*
517 * If Linux enabled the LAPIC against the BIOS default
518 * disable it down before re-entering the BIOS on shutdown.
519 * Otherwise the BIOS may get confused and not power-off.
520 */
521void lapic_shutdown(void)
522{
523 if (!cpu_has_apic || !enabled_via_apicbase)
524 return;
525
526 local_irq_disable();
527 disable_local_APIC();
528 local_irq_enable();
529}
530
531#ifdef CONFIG_PM
532
533static struct {
534 int active;
535 /* r/w apic fields */
536 unsigned int apic_id;
537 unsigned int apic_taskpri;
538 unsigned int apic_ldr;
539 unsigned int apic_dfr;
540 unsigned int apic_spiv;
541 unsigned int apic_lvtt;
542 unsigned int apic_lvtpc;
543 unsigned int apic_lvt0;
544 unsigned int apic_lvt1;
545 unsigned int apic_lvterr;
546 unsigned int apic_tmict;
547 unsigned int apic_tdcr;
548 unsigned int apic_thmr;
549} apic_pm_state;
550
551static int lapic_suspend(struct sys_device *dev, u32 state)
552{
553 unsigned long flags;
554
555 if (!apic_pm_state.active)
556 return 0;
557
558 apic_pm_state.apic_id = apic_read(APIC_ID);
559 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
560 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
561 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
562 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
563 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
564 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
565 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
566 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
567 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
568 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
569 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
570 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
571
572 local_irq_save(flags);
573 disable_local_APIC();
574 local_irq_restore(flags);
575 return 0;
576}
577
578static int lapic_resume(struct sys_device *dev)
579{
580 unsigned int l, h;
581 unsigned long flags;
582
583 if (!apic_pm_state.active)
584 return 0;
585
586 local_irq_save(flags);
587
588 /*
589 * Make sure the APICBASE points to the right address
590 *
591 * FIXME! This will be wrong if we ever support suspend on
592 * SMP! We'll need to do this as part of the CPU restore!
593 */
594 rdmsr(MSR_IA32_APICBASE, l, h);
595 l &= ~MSR_IA32_APICBASE_BASE;
596 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
597 wrmsr(MSR_IA32_APICBASE, l, h);
598
599 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
600 apic_write(APIC_ID, apic_pm_state.apic_id);
601 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
602 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
603 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
604 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
605 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
606 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
607 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
608 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
609 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
610 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
611 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
612 apic_write(APIC_ESR, 0);
613 apic_read(APIC_ESR);
614 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
615 apic_write(APIC_ESR, 0);
616 apic_read(APIC_ESR);
617 local_irq_restore(flags);
618 return 0;
619}
620
621/*
622 * This device has no shutdown method - fully functioning local APICs
623 * are needed on every CPU up until machine_halt/restart/poweroff.
624 */
625
626static struct sysdev_class lapic_sysclass = {
627 set_kset_name("lapic"),
628 .resume = lapic_resume,
629 .suspend = lapic_suspend,
630};
631
632static struct sys_device device_lapic = {
633 .id = 0,
634 .cls = &lapic_sysclass,
635};
636
637static void __init apic_pm_activate(void)
638{
639 apic_pm_state.active = 1;
640}
641
642static int __init init_lapic_sysfs(void)
643{
644 int error;
645
646 if (!cpu_has_apic)
647 return 0;
648 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
649
650 error = sysdev_class_register(&lapic_sysclass);
651 if (!error)
652 error = sysdev_register(&device_lapic);
653 return error;
654}
655device_initcall(init_lapic_sysfs);
656
657#else /* CONFIG_PM */
658
659static void apic_pm_activate(void) { }
660
661#endif /* CONFIG_PM */
662
663/*
664 * Detect and enable local APICs on non-SMP boards.
665 * Original code written by Keir Fraser.
666 */
667
668/*
669 * Knob to control our willingness to enable the local APIC.
670 */
671int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
672
673static int __init lapic_disable(char *str)
674{
675 enable_local_apic = -1;
676 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
677 return 0;
678}
679__setup("nolapic", lapic_disable);
680
681static int __init lapic_enable(char *str)
682{
683 enable_local_apic = 1;
684 return 0;
685}
686__setup("lapic", lapic_enable);
687
688static int __init apic_set_verbosity(char *str)
689{
690 if (strcmp("debug", str) == 0)
691 apic_verbosity = APIC_DEBUG;
692 else if (strcmp("verbose", str) == 0)
693 apic_verbosity = APIC_VERBOSE;
694 else
695 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
696 " use apic=verbose or apic=debug", str);
697
698 return 0;
699}
700
701__setup("apic=", apic_set_verbosity);
702
703static int __init detect_init_APIC (void)
704{
705 u32 h, l, features;
706 extern void get_cpu_vendor(struct cpuinfo_x86*);
707
708 /* Disabled by kernel option? */
709 if (enable_local_apic < 0)
710 return -1;
711
712 /* Workaround for us being called before identify_cpu(). */
713 get_cpu_vendor(&boot_cpu_data);
714
715 switch (boot_cpu_data.x86_vendor) {
716 case X86_VENDOR_AMD:
717 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
718 (boot_cpu_data.x86 == 15))
719 break;
720 goto no_apic;
721 case X86_VENDOR_INTEL:
722 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
723 (boot_cpu_data.x86 == 5 && cpu_has_apic))
724 break;
725 goto no_apic;
726 default:
727 goto no_apic;
728 }
729
730 if (!cpu_has_apic) {
731 /*
732 * Over-ride BIOS and try to enable the local
733 * APIC only if "lapic" specified.
734 */
735 if (enable_local_apic <= 0) {
736 printk("Local APIC disabled by BIOS -- "
737 "you can enable it with \"lapic\"\n");
738 return -1;
739 }
740 /*
741 * Some BIOSes disable the local APIC in the
742 * APIC_BASE MSR. This can only be done in
743 * software for Intel P6 or later and AMD K7
744 * (Model > 1) or later.
745 */
746 rdmsr(MSR_IA32_APICBASE, l, h);
747 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
748 printk("Local APIC disabled by BIOS -- reenabling.\n");
749 l &= ~MSR_IA32_APICBASE_BASE;
750 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
751 wrmsr(MSR_IA32_APICBASE, l, h);
752 enabled_via_apicbase = 1;
753 }
754 }
755 /*
756 * The APIC feature bit should now be enabled
757 * in `cpuid'
758 */
759 features = cpuid_edx(1);
760 if (!(features & (1 << X86_FEATURE_APIC))) {
761 printk("Could not enable APIC!\n");
762 return -1;
763 }
764 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
765 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
766
767 /* The BIOS may have set up the APIC at some other address */
768 rdmsr(MSR_IA32_APICBASE, l, h);
769 if (l & MSR_IA32_APICBASE_ENABLE)
770 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
771
772 if (nmi_watchdog != NMI_NONE)
773 nmi_watchdog = NMI_LOCAL_APIC;
774
775 printk("Found and enabled local APIC!\n");
776
777 apic_pm_activate();
778
779 return 0;
780
781no_apic:
782 printk("No local APIC present or hardware disabled\n");
783 return -1;
784}
785
786void __init init_apic_mappings(void)
787{
788 unsigned long apic_phys;
789
790 /*
791 * If no local APIC can be found then set up a fake all
792 * zeroes page to simulate the local APIC and another
793 * one for the IO-APIC.
794 */
795 if (!smp_found_config && detect_init_APIC()) {
796 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
797 apic_phys = __pa(apic_phys);
798 } else
799 apic_phys = mp_lapic_addr;
800
801 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
802 printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
803 apic_phys);
804
805 /*
806 * Fetch the APIC ID of the BSP in case we have a
807 * default configuration (or the MP table is broken).
808 */
809 if (boot_cpu_physical_apicid == -1U)
810 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
811
812#ifdef CONFIG_X86_IO_APIC
813 {
814 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
815 int i;
816
817 for (i = 0; i < nr_ioapics; i++) {
818 if (smp_found_config) {
819 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
820 if (!ioapic_phys) {
821 printk(KERN_ERR
822 "WARNING: bogus zero IO-APIC "
823 "address found in MPTABLE, "
824 "disabling IO/APIC support!\n");
825 smp_found_config = 0;
826 skip_ioapic_setup = 1;
827 goto fake_ioapic_page;
828 }
829 } else {
830fake_ioapic_page:
831 ioapic_phys = (unsigned long)
832 alloc_bootmem_pages(PAGE_SIZE);
833 ioapic_phys = __pa(ioapic_phys);
834 }
835 set_fixmap_nocache(idx, ioapic_phys);
836 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
837 __fix_to_virt(idx), ioapic_phys);
838 idx++;
839 }
840 }
841#endif
842}
843
844/*
845 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
846 * per second. We assume that the caller has already set up the local
847 * APIC.
848 *
849 * The APIC timer is not exactly sync with the external timer chip, it
850 * closely follows bus clocks.
851 */
852
853/*
854 * The timer chip is already set up at HZ interrupts per second here,
855 * but we do not accept timer interrupts yet. We only allow the BP
856 * to calibrate.
857 */
858static unsigned int __init get_8254_timer_count(void)
859{
860 extern spinlock_t i8253_lock;
861 unsigned long flags;
862
863 unsigned int count;
864
865 spin_lock_irqsave(&i8253_lock, flags);
866
867 outb_p(0x00, PIT_MODE);
868 count = inb_p(PIT_CH0);
869 count |= inb_p(PIT_CH0) << 8;
870
871 spin_unlock_irqrestore(&i8253_lock, flags);
872
873 return count;
874}
875
876/* next tick in 8254 can be caught by catching timer wraparound */
877static void __init wait_8254_wraparound(void)
878{
879 unsigned int curr_count, prev_count;
880
881 curr_count = get_8254_timer_count();
882 do {
883 prev_count = curr_count;
884 curr_count = get_8254_timer_count();
885
886 /* workaround for broken Mercury/Neptune */
887 if (prev_count >= curr_count + 0x100)
888 curr_count = get_8254_timer_count();
889
890 } while (prev_count >= curr_count);
891}
892
893/*
894 * Default initialization for 8254 timers. If we use other timers like HPET,
895 * we override this later
896 */
897void (*wait_timer_tick)(void) __initdata = wait_8254_wraparound;
898
899/*
900 * This function sets up the local APIC timer, with a timeout of
901 * 'clocks' APIC bus clock. During calibration we actually call
902 * this function twice on the boot CPU, once with a bogus timeout
903 * value, second time for real. The other (noncalibrating) CPUs
904 * call this function only once, with the real, calibrated value.
905 *
906 * We do reads before writes even if unnecessary, to get around the
907 * P5 APIC double write bug.
908 */
909
910#define APIC_DIVISOR 16
911
912static void __setup_APIC_LVTT(unsigned int clocks)
913{
914 unsigned int lvtt_value, tmp_value, ver;
915
916 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
917 lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
918 if (!APIC_INTEGRATED(ver))
919 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
920 apic_write_around(APIC_LVTT, lvtt_value);
921
922 /*
923 * Divide PICLK by 16
924 */
925 tmp_value = apic_read(APIC_TDCR);
926 apic_write_around(APIC_TDCR, (tmp_value
927 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
928 | APIC_TDR_DIV_16);
929
930 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
931}
932
933static void __init setup_APIC_timer(unsigned int clocks)
934{
935 unsigned long flags;
936
937 local_irq_save(flags);
938
939 /*
940 * Wait for IRQ0's slice:
941 */
942 wait_timer_tick();
943
944 __setup_APIC_LVTT(clocks);
945
946 local_irq_restore(flags);
947}
948
949/*
950 * In this function we calibrate APIC bus clocks to the external
951 * timer. Unfortunately we cannot use jiffies and the timer irq
952 * to calibrate, since some later bootup code depends on getting
953 * the first irq? Ugh.
954 *
955 * We want to do the calibration only once since we
956 * want to have local timer irqs syncron. CPUs connected
957 * by the same APIC bus have the very same bus frequency.
958 * And we want to have irqs off anyways, no accidental
959 * APIC irq that way.
960 */
961
962static int __init calibrate_APIC_clock(void)
963{
964 unsigned long long t1 = 0, t2 = 0;
965 long tt1, tt2;
966 long result;
967 int i;
968 const int LOOPS = HZ/10;
969
970 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
971
972 /*
973 * Put whatever arbitrary (but long enough) timeout
974 * value into the APIC clock, we just want to get the
975 * counter running for calibration.
976 */
977 __setup_APIC_LVTT(1000000000);
978
979 /*
980 * The timer chip counts down to zero. Let's wait
981 * for a wraparound to start exact measurement:
982 * (the current tick might have been already half done)
983 */
984
985 wait_timer_tick();
986
987 /*
988 * We wrapped around just now. Let's start:
989 */
990 if (cpu_has_tsc)
991 rdtscll(t1);
992 tt1 = apic_read(APIC_TMCCT);
993
994 /*
995 * Let's wait LOOPS wraprounds:
996 */
997 for (i = 0; i < LOOPS; i++)
998 wait_timer_tick();
999
1000 tt2 = apic_read(APIC_TMCCT);
1001 if (cpu_has_tsc)
1002 rdtscll(t2);
1003
1004 /*
1005 * The APIC bus clock counter is 32 bits only, it
1006 * might have overflown, but note that we use signed
1007 * longs, thus no extra care needed.
1008 *
1009 * underflown to be exact, as the timer counts down ;)
1010 */
1011
1012 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
1013
1014 if (cpu_has_tsc)
1015 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
1016 "%ld.%04ld MHz.\n",
1017 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
1018 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
1019
1020 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
1021 "%ld.%04ld MHz.\n",
1022 result/(1000000/HZ),
1023 result%(1000000/HZ));
1024
1025 return result;
1026}
1027
1028static unsigned int calibration_result;
1029
1030void __init setup_boot_APIC_clock(void)
1031{
1032 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n");
1033 using_apic_timer = 1;
1034
1035 local_irq_disable();
1036
1037 calibration_result = calibrate_APIC_clock();
1038 /*
1039 * Now set up the timer for real.
1040 */
1041 setup_APIC_timer(calibration_result);
1042
1043 local_irq_enable();
1044}
1045
1046void __init setup_secondary_APIC_clock(void)
1047{
1048 setup_APIC_timer(calibration_result);
1049}
1050
1051void __init disable_APIC_timer(void)
1052{
1053 if (using_apic_timer) {
1054 unsigned long v;
1055
1056 v = apic_read(APIC_LVTT);
1057 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
1058 }
1059}
1060
1061void enable_APIC_timer(void)
1062{
1063 if (using_apic_timer) {
1064 unsigned long v;
1065
1066 v = apic_read(APIC_LVTT);
1067 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
1068 }
1069}
1070
1071/*
1072 * the frequency of the profiling timer can be changed
1073 * by writing a multiplier value into /proc/profile.
1074 */
1075int setup_profiling_timer(unsigned int multiplier)
1076{
1077 int i;
1078
1079 /*
1080 * Sanity check. [at least 500 APIC cycles should be
1081 * between APIC interrupts as a rule of thumb, to avoid
1082 * irqs flooding us]
1083 */
1084 if ( (!multiplier) || (calibration_result/multiplier < 500))
1085 return -EINVAL;
1086
1087 /*
1088 * Set the new multiplier for each CPU. CPUs don't start using the
1089 * new values until the next timer interrupt in which they do process
1090 * accounting. At that time they also adjust their APIC timers
1091 * accordingly.
1092 */
1093 for (i = 0; i < NR_CPUS; ++i)
1094 per_cpu(prof_multiplier, i) = multiplier;
1095
1096 return 0;
1097}
1098
1099#undef APIC_DIVISOR
1100
1101/*
1102 * Local timer interrupt handler. It does both profiling and
1103 * process statistics/rescheduling.
1104 *
1105 * We do profiling in every local tick, statistics/rescheduling
1106 * happen only every 'profiling multiplier' ticks. The default
1107 * multiplier is 1 and it can be changed by writing the new multiplier
1108 * value into /proc/profile.
1109 */
1110
1111inline void smp_local_timer_interrupt(struct pt_regs * regs)
1112{
1113 int cpu = smp_processor_id();
1114
1115 profile_tick(CPU_PROFILING, regs);
1116 if (--per_cpu(prof_counter, cpu) <= 0) {
1117 /*
1118 * The multiplier may have changed since the last time we got
1119 * to this point as a result of the user writing to
1120 * /proc/profile. In this case we need to adjust the APIC
1121 * timer accordingly.
1122 *
1123 * Interrupts are already masked off at this point.
1124 */
1125 per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu);
1126 if (per_cpu(prof_counter, cpu) !=
1127 per_cpu(prof_old_multiplier, cpu)) {
1128 __setup_APIC_LVTT(
1129 calibration_result/
1130 per_cpu(prof_counter, cpu));
1131 per_cpu(prof_old_multiplier, cpu) =
1132 per_cpu(prof_counter, cpu);
1133 }
1134
1135#ifdef CONFIG_SMP
1136 update_process_times(user_mode(regs));
1137#endif
1138 }
1139
1140 /*
1141 * We take the 'long' return path, and there every subsystem
1142 * grabs the apropriate locks (kernel lock/ irq lock).
1143 *
1144 * we might want to decouple profiling from the 'long path',
1145 * and do the profiling totally in assembly.
1146 *
1147 * Currently this isn't too much of an issue (performance wise),
1148 * we can take more than 100K local irqs per second on a 100 MHz P5.
1149 */
1150}
1151
1152/*
1153 * Local APIC timer interrupt. This is the most natural way for doing
1154 * local interrupts, but local timer interrupts can be emulated by
1155 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1156 *
1157 * [ if a single-CPU system runs an SMP kernel then we call the local
1158 * interrupt as well. Thus we cannot inline the local irq ... ]
1159 */
1160
1161fastcall void smp_apic_timer_interrupt(struct pt_regs *regs)
1162{
1163 int cpu = smp_processor_id();
1164
1165 /*
1166 * the NMI deadlock-detector uses this.
1167 */
1168 per_cpu(irq_stat, cpu).apic_timer_irqs++;
1169
1170 /*
1171 * NOTE! We'd better ACK the irq immediately,
1172 * because timer handling can be slow.
1173 */
1174 ack_APIC_irq();
1175 /*
1176 * update_process_times() expects us to have done irq_enter().
1177 * Besides, if we don't timer interrupts ignore the global
1178 * interrupt lock, which is the WrongThing (tm) to do.
1179 */
1180 irq_enter();
1181 smp_local_timer_interrupt(regs);
1182 irq_exit();
1183}
1184
1185/*
1186 * This interrupt should _never_ happen with our APIC/SMP architecture
1187 */
1188fastcall void smp_spurious_interrupt(struct pt_regs *regs)
1189{
1190 unsigned long v;
1191
1192 irq_enter();
1193 /*
1194 * Check if this really is a spurious interrupt and ACK it
1195 * if it is a vectored one. Just in case...
1196 * Spurious interrupts should not be ACKed.
1197 */
1198 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1199 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1200 ack_APIC_irq();
1201
1202 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1203 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
1204 smp_processor_id());
1205 irq_exit();
1206}
1207
1208/*
1209 * This interrupt should never happen with our APIC/SMP architecture
1210 */
1211
1212fastcall void smp_error_interrupt(struct pt_regs *regs)
1213{
1214 unsigned long v, v1;
1215
1216 irq_enter();
1217 /* First tickle the hardware, only then report what went on. -- REW */
1218 v = apic_read(APIC_ESR);
1219 apic_write(APIC_ESR, 0);
1220 v1 = apic_read(APIC_ESR);
1221 ack_APIC_irq();
1222 atomic_inc(&irq_err_count);
1223
1224 /* Here is what the APIC error bits mean:
1225 0: Send CS error
1226 1: Receive CS error
1227 2: Send accept error
1228 3: Receive accept error
1229 4: Reserved
1230 5: Send illegal vector
1231 6: Received illegal vector
1232 7: Illegal register address
1233 */
1234 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1235 smp_processor_id(), v , v1);
1236 irq_exit();
1237}
1238
1239/*
1240 * This initializes the IO-APIC and APIC hardware if this is
1241 * a UP kernel.
1242 */
1243int __init APIC_init_uniprocessor (void)
1244{
1245 if (enable_local_apic < 0)
1246 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1247
1248 if (!smp_found_config && !cpu_has_apic)
1249 return -1;
1250
1251 /*
1252 * Complain if the BIOS pretends there is one.
1253 */
1254 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1255 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1256 boot_cpu_physical_apicid);
1257 return -1;
1258 }
1259
1260 verify_local_APIC();
1261
1262 connect_bsp_APIC();
1263
1264 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
1265
1266 setup_local_APIC();
1267
1268 if (nmi_watchdog == NMI_LOCAL_APIC)
1269 check_nmi_watchdog();
1270#ifdef CONFIG_X86_IO_APIC
1271 if (smp_found_config)
1272 if (!skip_ioapic_setup && nr_ioapics)
1273 setup_IO_APIC();
1274#endif
1275 setup_boot_APIC_clock();
1276
1277 return 0;
1278}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 06:18:50 -0500