1 files changed, 870 insertions, 761 deletions

diff --git a/arch/i386/kernel/apic.c b/arch/i386/kernel/apic.c
index 776d9be26af9..9655c233e6f1 100644
--- a/arch/i386/kernel/apic.c
+++ b/arch/i386/kernel/apic.c
@@ -25,6 +25,8 @@
 #include <linux/kernel_stat.h>
 #include <linux/sysdev.h>
 #include <linux/cpu.h>
+#include <linux/clockchips.h>
+#include <linux/acpi_pmtmr.h>
 #include <linux/module.h>
 
 #include <asm/atomic.h>
@@ -36,6 +38,7 @@
 #include <asm/hpet.h>
 #include <asm/i8253.h>
 #include <asm/nmi.h>
+#include <asm/idle.h>
 
 #include <mach_apic.h>
 #include <mach_apicdef.h>
@@ -44,128 +47,549 @@
 #include "io_ports.h"
 
 /*
- * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
- * IPIs in place of local APIC timers
+ * Sanity check
  */
-static cpumask_t timer_bcast_ipi;
+#if (SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F
+# error SPURIOUS_APIC_VECTOR definition error
+#endif
 
 /*
  * Knob to control our willingness to enable the local APIC.
+ *
+ * -1=force-disable, +1=force-enable
  */
-static int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
-
-static inline void lapic_disable(void)
-{
-        enable_local_apic = -1;
-        clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
-}
+static int enable_local_apic __initdata = 0;
 
-static inline void lapic_enable(void)
-{
-        enable_local_apic = 1;
-}
+/* Local APIC timer verification ok */
+static int local_apic_timer_verify_ok;
 
 /*
- * Debug level
+ * Debug level, exported for io_apic.c
  */
 int apic_verbosity;
 
+static unsigned int calibration_result;
 
+static int lapic_next_event(unsigned long delta,
+                            struct clock_event_device *evt);
+static void lapic_timer_setup(enum clock_event_mode mode,
+                              struct clock_event_device *evt);
+static void lapic_timer_broadcast(cpumask_t mask);
 static void apic_pm_activate(void);
 
+/*
+ * The local apic timer can be used for any function which is CPU local.
+ */
+static struct clock_event_device lapic_clockevent = {
+        .name           = "lapic",
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
+                        | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
+        .shift          = 32,
+        .set_mode       = lapic_timer_setup,
+        .set_next_event = lapic_next_event,
+        .broadcast      = lapic_timer_broadcast,
+        .rating         = 100,
+        .irq            = -1,
+};
+static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
+
+/* Local APIC was disabled by the BIOS and enabled by the kernel */
+static int enabled_via_apicbase;
+
+/*
+ * Get the LAPIC version
+ */
+static inline int lapic_get_version(void)
+{
+        return GET_APIC_VERSION(apic_read(APIC_LVR));
+}
+
+/*
+ * Check, if the APIC is integrated or a seperate chip
+ */
+static inline int lapic_is_integrated(void)
+{
+        return APIC_INTEGRATED(lapic_get_version());
+}
+
+/*
+ * Check, whether this is a modern or a first generation APIC
+ */
 static int modern_apic(void)
 {
-        unsigned int lvr, version;
         /* AMD systems use old APIC versions, so check the CPU */
         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-                boot_cpu_data.x86 >= 0xf)
+            boot_cpu_data.x86 >= 0xf)
                 return 1;
-        lvr = apic_read(APIC_LVR);
-        version = GET_APIC_VERSION(lvr);
-        return version >= 0x14;
+        return lapic_get_version() >= 0x14;
 }
 
+/**
+ * enable_NMI_through_LVT0 - enable NMI through local vector table 0
+ */
+void enable_NMI_through_LVT0 (void * dummy)
+{
+        unsigned int v = APIC_DM_NMI;
+
+        /* Level triggered for 82489DX */
+        if (!lapic_is_integrated())
+                v |= APIC_LVT_LEVEL_TRIGGER;
+        apic_write_around(APIC_LVT0, v);
+}
+
+/**
+ * get_physical_broadcast - Get number of physical broadcast IDs
+ */
+int get_physical_broadcast(void)
+{
+        return modern_apic() ? 0xff : 0xf;
+}
+
+/**
+ * lapic_get_maxlvt - get the maximum number of local vector table entries
+ */
+int lapic_get_maxlvt(void)
+{
+        unsigned int v = apic_read(APIC_LVR);
+
+        /* 82489DXs do not report # of LVT entries. */
+        return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
+}
+
+/*
+ * Local APIC timer
+ */
+
+/* Clock divisor is set to 16 */
+#define APIC_DIVISOR 16
+
 /*
- * 'what should we do if we get a hw irq event on an illegal vector'.
- * each architecture has to answer this themselves.
+ * This function sets up the local APIC timer, with a timeout of
+ * 'clocks' APIC bus clock. During calibration we actually call
+ * this function twice on the boot CPU, once with a bogus timeout
+ * value, second time for real. The other (noncalibrating) CPUs
+ * call this function only once, with the real, calibrated value.
+ *
+ * We do reads before writes even if unnecessary, to get around the
+ * P5 APIC double write bug.
  */
-void ack_bad_irq(unsigned int irq)
+static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
 {
-        printk("unexpected IRQ trap at vector %02x\n", irq);
+        unsigned int lvtt_value, tmp_value;
+
+        lvtt_value = LOCAL_TIMER_VECTOR;
+        if (!oneshot)
+                lvtt_value |= APIC_LVT_TIMER_PERIODIC;
+        if (!lapic_is_integrated())
+                lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
+
+        if (!irqen)
+                lvtt_value |= APIC_LVT_MASKED;
+
+        apic_write_around(APIC_LVTT, lvtt_value);
+
         /*
-         * Currently unexpected vectors happen only on SMP and APIC.
-         * We _must_ ack these because every local APIC has only N
-         * irq slots per priority level, and a 'hanging, unacked' IRQ
-         * holds up an irq slot - in excessive cases (when multiple
-         * unexpected vectors occur) that might lock up the APIC
-         * completely.
-         * But only ack when the APIC is enabled -AK
+         * Divide PICLK by 16
          */
-        if (cpu_has_apic)
-                ack_APIC_irq();
+        tmp_value = apic_read(APIC_TDCR);
+        apic_write_around(APIC_TDCR, (tmp_value
+                                & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
+                                | APIC_TDR_DIV_16);
+
+        if (!oneshot)
+                apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
 }
 
-void __init apic_intr_init(void)
+/*
+ * Program the next event, relative to now
+ */
+static int lapic_next_event(unsigned long delta,
+                            struct clock_event_device *evt)
+{
+        apic_write_around(APIC_TMICT, delta);
+        return 0;
+}
+
+/*
+ * Setup the lapic timer in periodic or oneshot mode
+ */
+static void lapic_timer_setup(enum clock_event_mode mode,
+                              struct clock_event_device *evt)
+{
+        unsigned long flags;
+        unsigned int v;
+
+        /* Lapic used for broadcast ? */
+        if (!local_apic_timer_verify_ok)
+                return;
+
+        local_irq_save(flags);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+        case CLOCK_EVT_MODE_ONESHOT:
+                __setup_APIC_LVTT(calibration_result,
+                                  mode != CLOCK_EVT_MODE_PERIODIC, 1);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                v = apic_read(APIC_LVTT);
+                v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
+                apic_write_around(APIC_LVTT, v);
+                break;
+        }
+
+        local_irq_restore(flags);
+}
+
+/*
+ * Local APIC timer broadcast function
+ */
+static void lapic_timer_broadcast(cpumask_t mask)
 {
 #ifdef CONFIG_SMP
-        smp_intr_init();
+        send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
 #endif
-        /* self generated IPI for local APIC timer */
-        set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
+}
 
-        /* IPI vectors for APIC spurious and error interrupts */
-        set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
-        set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
+/*
+ * Setup the local APIC timer for this CPU. Copy the initilized values
+ * of the boot CPU and register the clock event in the framework.
+ */
+static void __devinit setup_APIC_timer(void)
+{
+        struct clock_event_device *levt = &__get_cpu_var(lapic_events);
 
-        /* thermal monitor LVT interrupt */
-#ifdef CONFIG_X86_MCE_P4THERMAL
-        set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
-#endif
+        memcpy(levt, &lapic_clockevent, sizeof(*levt));
+        levt->cpumask = cpumask_of_cpu(smp_processor_id());
+
+        clockevents_register_device(levt);
 }
 
-/* Using APIC to generate smp_local_timer_interrupt? */
-int using_apic_timer __read_mostly = 0;
+/*
+ * In this functions we calibrate APIC bus clocks to the external timer.
+ *
+ * We want to do the calibration only once since we want to have local timer
+ * irqs syncron. CPUs connected by the same APIC bus have the very same bus
+ * frequency.
+ *
+ * This was previously done by reading the PIT/HPET and waiting for a wrap
+ * around to find out, that a tick has elapsed. I have a box, where the PIT
+ * readout is broken, so it never gets out of the wait loop again. This was
+ * also reported by others.
+ *
+ * Monitoring the jiffies value is inaccurate and the clockevents
+ * infrastructure allows us to do a simple substitution of the interrupt
+ * handler.
+ *
+ * The calibration routine also uses the pm_timer when possible, as the PIT
+ * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
+ * back to normal later in the boot process).
+ */
+
+#define LAPIC_CAL_LOOPS         (HZ/10)
 
-static int enabled_via_apicbase;
+static __initdata volatile int lapic_cal_loops = -1;
+static __initdata long lapic_cal_t1, lapic_cal_t2;
+static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
+static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
+static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
 
-void enable_NMI_through_LVT0 (void * dummy)
+/*
+ * Temporary interrupt handler.
+ */
+static void __init lapic_cal_handler(struct clock_event_device *dev)
 {
-        unsigned int v, ver;
+        unsigned long long tsc = 0;
+        long tapic = apic_read(APIC_TMCCT);
+        unsigned long pm = acpi_pm_read_early();
 
-        ver = apic_read(APIC_LVR);
-        ver = GET_APIC_VERSION(ver);
-        v = APIC_DM_NMI;                        /* unmask and set to NMI */
-        if (!APIC_INTEGRATED(ver))              /* 82489DX */
-                v |= APIC_LVT_LEVEL_TRIGGER;
-        apic_write_around(APIC_LVT0, v);
+        if (cpu_has_tsc)
+                rdtscll(tsc);
+
+        switch (lapic_cal_loops++) {
+        case 0:
+                lapic_cal_t1 = tapic;
+                lapic_cal_tsc1 = tsc;
+                lapic_cal_pm1 = pm;
+                lapic_cal_j1 = jiffies;
+                break;
+
+        case LAPIC_CAL_LOOPS:
+                lapic_cal_t2 = tapic;
+                lapic_cal_tsc2 = tsc;
+                if (pm < lapic_cal_pm1)
+                        pm += ACPI_PM_OVRRUN;
+                lapic_cal_pm2 = pm;
+                lapic_cal_j2 = jiffies;
+                break;
+        }
 }
 
-int get_physical_broadcast(void)
+/*
+ * Setup the boot APIC
+ *
+ * Calibrate and verify the result.
+ */
+void __init setup_boot_APIC_clock(void)
 {
-        if (modern_apic())
-                return 0xff;
-        else
-                return 0xf;
+        struct clock_event_device *levt = &__get_cpu_var(lapic_events);
+        const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
+        const long pm_thresh = pm_100ms/100;
+        void (*real_handler)(struct clock_event_device *dev);
+        unsigned long deltaj;
+        long delta, deltapm;
+
+        apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
+                    "calibrating APIC timer ...\n");
+
+        local_irq_disable();
+
+        /* Replace the global interrupt handler */
+        real_handler = global_clock_event->event_handler;
+        global_clock_event->event_handler = lapic_cal_handler;
+
+        /*
+         * Setup the APIC counter to 1e9. There is no way the lapic
+         * can underflow in the 100ms detection time frame
+         */
+        __setup_APIC_LVTT(1000000000, 0, 0);
+
+        /* Let the interrupts run */
+        local_irq_enable();
+
+        while(lapic_cal_loops <= LAPIC_CAL_LOOPS);
+
+        local_irq_disable();
+
+        /* Restore the real event handler */
+        global_clock_event->event_handler = real_handler;
+
+        /* Build delta t1-t2 as apic timer counts down */
+        delta = lapic_cal_t1 - lapic_cal_t2;
+        apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
+
+        /* Check, if the PM timer is available */
+        deltapm = lapic_cal_pm2 - lapic_cal_pm1;
+        apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
+
+        if (deltapm) {
+                unsigned long mult;
+                u64 res;
+
+                mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
+
+                if (deltapm > (pm_100ms - pm_thresh) &&
+                    deltapm < (pm_100ms + pm_thresh)) {
+                        apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
+                } else {
+                        res = (((u64) deltapm) *  mult) >> 22;
+                        do_div(res, 1000000);
+                        printk(KERN_WARNING "APIC calibration not consistent "
+                               "with PM Timer: %ldms instead of 100ms\n",
+                               (long)res);
+                        /* Correct the lapic counter value */
+                        res = (((u64) delta ) * pm_100ms);
+                        do_div(res, deltapm);
+                        printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
+                               "%lu (%ld)\n", (unsigned long) res, delta);
+                        delta = (long) res;
+                }
+        }
+
+        /* Calculate the scaled math multiplication factor */
+        lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 32);
+        lapic_clockevent.max_delta_ns =
+                clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
+        lapic_clockevent.min_delta_ns =
+                clockevent_delta2ns(0xF, &lapic_clockevent);
+
+        calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
+
+        apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
+        apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
+        apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
+                    calibration_result);
+
+        if (cpu_has_tsc) {
+                delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
+                apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
+                            "%ld.%04ld MHz.\n",
+                            (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
+                            (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
+        }
+
+        apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
+                    "%u.%04u MHz.\n",
+                    calibration_result / (1000000 / HZ),
+                    calibration_result % (1000000 / HZ));
+
+
+        apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
+
+        /*
+         * Setup the apic timer manually
+         */
+        local_apic_timer_verify_ok = 1;
+        levt->event_handler = lapic_cal_handler;
+        lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
+        lapic_cal_loops = -1;
+
+        /* Let the interrupts run */
+        local_irq_enable();
+
+        while(lapic_cal_loops <= LAPIC_CAL_LOOPS);
+
+        local_irq_disable();
+
+        /* Stop the lapic timer */
+        lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
+
+        local_irq_enable();
+
+        /* Jiffies delta */
+        deltaj = lapic_cal_j2 - lapic_cal_j1;
+        apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
+
+        /* Check, if the PM timer is available */
+        deltapm = lapic_cal_pm2 - lapic_cal_pm1;
+        apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
+
+        local_apic_timer_verify_ok = 0;
+
+        if (deltapm) {
+                if (deltapm > (pm_100ms - pm_thresh) &&
+                    deltapm < (pm_100ms + pm_thresh)) {
+                        apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
+                        /* Check, if the jiffies result is consistent */
+                        if (deltaj < LAPIC_CAL_LOOPS-2 ||
+                            deltaj > LAPIC_CAL_LOOPS+2) {
+                                /*
+                                 * Not sure, what we can do about this one.
+                                 * When high resultion timers are active
+                                 * and the lapic timer does not stop in C3
+                                 * we are fine. Otherwise more trouble might
+                                 * be waiting. -- tglx
+                                 */
+                                printk(KERN_WARNING "Global event device %s "
+                                       "has wrong frequency "
+                                       "(%lu ticks instead of %d)\n",
+                                       global_clock_event->name, deltaj,
+                                       LAPIC_CAL_LOOPS);
+                        }
+                        local_apic_timer_verify_ok = 1;
+                }
+        } else {
+                /* Check, if the jiffies result is consistent */
+                if (deltaj >= LAPIC_CAL_LOOPS-2 &&
+                    deltaj <= LAPIC_CAL_LOOPS+2) {
+                        apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
+                        local_apic_timer_verify_ok = 1;
+                }
+        }
+
+        if (!local_apic_timer_verify_ok) {
+                printk(KERN_WARNING
+                       "APIC timer disabled due to verification failure.\n");
+                /* No broadcast on UP ! */
+                if (num_possible_cpus() == 1)
+                        return;
+        } else
+                lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
+
+        /* Setup the lapic or request the broadcast */
+        setup_APIC_timer();
+}
+
+void __devinit setup_secondary_APIC_clock(void)
+{
+        setup_APIC_timer();
 }
 
-int get_maxlvt(void)
+/*
+ * The guts of the apic timer interrupt
+ */
+static void local_apic_timer_interrupt(void)
 {
-        unsigned int v, ver, maxlvt;
+        int cpu = smp_processor_id();
+        struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
 
-        v = apic_read(APIC_LVR);
-        ver = GET_APIC_VERSION(v);
-        /* 82489DXs do not report # of LVT entries. */
-        maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
-        return maxlvt;
+        /*
+         * Normally we should not be here till LAPIC has been initialized but
+         * in some cases like kdump, its possible that there is a pending LAPIC
+         * timer interrupt from previous kernel's context and is delivered in
+         * new kernel the moment interrupts are enabled.
+         *
+         * Interrupts are enabled early and LAPIC is setup much later, hence
+         * its possible that when we get here evt->event_handler is NULL.
+         * Check for event_handler being NULL and discard the interrupt as
+         * spurious.
+         */
+        if (!evt->event_handler) {
+                printk(KERN_WARNING
+                       "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
+                /* Switch it off */
+                lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
+                return;
+        }
+
+        per_cpu(irq_stat, cpu).apic_timer_irqs++;
+
+        evt->event_handler(evt);
 }
 
+/*
+ * Local APIC timer interrupt. This is the most natural way for doing
+ * local interrupts, but local timer interrupts can be emulated by
+ * broadcast interrupts too. [in case the hw doesn't support APIC timers]
+ *
+ * [ if a single-CPU system runs an SMP kernel then we call the local
+ *   interrupt as well. Thus we cannot inline the local irq ... ]
+ */
+
+void fastcall smp_apic_timer_interrupt(struct pt_regs *regs)
+{
+        struct pt_regs *old_regs = set_irq_regs(regs);
+
+        /*
+         * NOTE! We'd better ACK the irq immediately,
+         * because timer handling can be slow.
+         */
+        ack_APIC_irq();
+        /*
+         * update_process_times() expects us to have done irq_enter().
+         * Besides, if we don't timer interrupts ignore the global
+         * interrupt lock, which is the WrongThing (tm) to do.
+         */
+        exit_idle();
+        irq_enter();
+        local_apic_timer_interrupt();
+        irq_exit();
+
+        set_irq_regs(old_regs);
+}
+
+int setup_profiling_timer(unsigned int multiplier)
+{
+        return -EINVAL;
+}
+
+/*
+ * Local APIC start and shutdown
+ */
+
+/**
+ * clear_local_APIC - shutdown the local APIC
+ *
+ * This is called, when a CPU is disabled and before rebooting, so the state of
+ * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
+ * leftovers during boot.
+ */
 void clear_local_APIC(void)
 {
-        int maxlvt;
+        int maxlvt = lapic_get_maxlvt();
         unsigned long v;
 
-        maxlvt = get_maxlvt();
-
         /*
          * Masking an LVT entry can trigger a local APIC error
          * if the vector is zero. Mask LVTERR first to prevent this.
@@ -189,7 +613,7 @@ void clear_local_APIC(void)
                 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
         }
 
-/* lets not touch this if we didn't frob it */
+        /* lets not touch this if we didn't frob it */
 #ifdef CONFIG_X86_MCE_P4THERMAL
         if (maxlvt >= 5) {
                 v = apic_read(APIC_LVTTHMR);
@@ -211,85 +635,18 @@ void clear_local_APIC(void)
         if (maxlvt >= 5)
                 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
 #endif
-        v = GET_APIC_VERSION(apic_read(APIC_LVR));
-        if (APIC_INTEGRATED(v)) {       /* !82489DX */
-                if (maxlvt > 3)         /* Due to Pentium errata 3AP and 11AP. */
+        /* Integrated APIC (!82489DX) ? */
+        if (lapic_is_integrated()) {
+                if (maxlvt > 3)
+                        /* Clear ESR due to Pentium errata 3AP and 11AP */
                         apic_write(APIC_ESR, 0);
                 apic_read(APIC_ESR);
         }
 }
 
-void __init connect_bsp_APIC(void)
-{
-        if (pic_mode) {
-                /*
-                 * Do not trust the local APIC being empty at bootup.
-                 */
-                clear_local_APIC();
-                /*
-                 * PIC mode, enable APIC mode in the IMCR, i.e.
-                 * connect BSP's local APIC to INT and NMI lines.
-                 */
-                apic_printk(APIC_VERBOSE, "leaving PIC mode, "
-                                "enabling APIC mode.\n");
-                outb(0x70, 0x22);
-                outb(0x01, 0x23);
-        }
-        enable_apic_mode();
-}
-
-void disconnect_bsp_APIC(int virt_wire_setup)
-{
-        if (pic_mode) {
-                /*
-                 * Put the board back into PIC mode (has an effect
-                 * only on certain older boards).  Note that APIC
-                 * interrupts, including IPIs, won't work beyond
-                 * this point!  The only exception are INIT IPIs.
-                 */
-                apic_printk(APIC_VERBOSE, "disabling APIC mode, "
-                                "entering PIC mode.\n");
-                outb(0x70, 0x22);
-                outb(0x00, 0x23);
-        }
-        else {
-                /* Go back to Virtual Wire compatibility mode */
-                unsigned long value;
-
-                /* For the spurious interrupt use vector F, and enable it */
-                value = apic_read(APIC_SPIV);
-                value &= ~APIC_VECTOR_MASK;
-                value |= APIC_SPIV_APIC_ENABLED;
-                value |= 0xf;
-                apic_write_around(APIC_SPIV, value);
-
-                if (!virt_wire_setup) {
-                        /* For LVT0 make it edge triggered, active high, external and enabled */
-                        value = apic_read(APIC_LVT0);
-                        value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
-                                APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
-                                APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
-                        value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
-                        value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
-                        apic_write_around(APIC_LVT0, value);
-                }
-                else {
-                        /* Disable LVT0 */
-                        apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
-                }
-
-                /* For LVT1 make it edge triggered, active high, nmi and enabled */
-                value = apic_read(APIC_LVT1);
-                value &= ~(
-                        APIC_MODE_MASK | APIC_SEND_PENDING |
-                        APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
-                        APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
-                value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
-                value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
-                apic_write_around(APIC_LVT1, value);
-        }
-}
-
+/**
+ * disable_local_APIC - clear and disable the local APIC
+ */
 void disable_local_APIC(void)
 {
         unsigned long value;
@@ -304,8 +661,13 @@ void disable_local_APIC(void)
         value &= ~APIC_SPIV_APIC_ENABLED;
         apic_write_around(APIC_SPIV, value);
 
+        /*
+         * When LAPIC was disabled by the BIOS and enabled by the kernel,
+         * restore the disabled state.
+         */
         if (enabled_via_apicbase) {
                 unsigned int l, h;
+
                 rdmsr(MSR_IA32_APICBASE, l, h);
                 l &= ~MSR_IA32_APICBASE_ENABLE;
                 wrmsr(MSR_IA32_APICBASE, l, h);
@@ -313,6 +675,28 @@ void disable_local_APIC(void)
 }
 
 /*
+ * If Linux enabled the LAPIC against the BIOS default disable it down before
+ * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
+ * not power-off.  Additionally clear all LVT entries before disable_local_APIC
+ * for the case where Linux didn't enable the LAPIC.
+ */
+void lapic_shutdown(void)
+{
+        unsigned long flags;
+
+        if (!cpu_has_apic)
+                return;
+
+        local_irq_save(flags);
+        clear_local_APIC();
+
+        if (enabled_via_apicbase)
+                disable_local_APIC();
+
+        local_irq_restore(flags);
+}
+
+/*
  * This is to verify that we're looking at a real local APIC.
  * Check these against your board if the CPUs aren't getting
  * started for no apparent reason.
@@ -344,7 +728,7 @@ int __init verify_local_APIC(void)
         reg1 = GET_APIC_VERSION(reg0);
         if (reg1 == 0x00 || reg1 == 0xff)
                 return 0;
-        reg1 = get_maxlvt();
+        reg1 = lapic_get_maxlvt();
         if (reg1 < 0x02 || reg1 == 0xff)
                 return 0;
 
@@ -367,10 +751,15 @@ int __init verify_local_APIC(void)
         return 1;
 }
 
+/**
+ * sync_Arb_IDs - synchronize APIC bus arbitration IDs
+ */
 void __init sync_Arb_IDs(void)
 {
-        /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1
-           And not needed on AMD */
+        /*
+         * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
+         * needed on AMD.
+         */
         if (modern_apic())
                 return;
         /*
@@ -383,14 +772,12 @@ void __init sync_Arb_IDs(void)
                                 | APIC_DM_INIT);
 }
 
-extern void __error_in_apic_c (void);
-
 /*
  * An initial setup of the virtual wire mode.
  */
 void __init init_bsp_APIC(void)
 {
-        unsigned long value, ver;
+        unsigned long value;
 
         /*
          * Don't do the setup now if we have a SMP BIOS as the
@@ -399,9 +786,6 @@ void __init init_bsp_APIC(void)
         if (smp_found_config || !cpu_has_apic)
                 return;
 
-        value = apic_read(APIC_LVR);
-        ver = GET_APIC_VERSION(value);
-
         /*
          * Do not trust the local APIC being empty at bootup.
          */
@@ -413,9 +797,10 @@ void __init init_bsp_APIC(void)
         value = apic_read(APIC_SPIV);
         value &= ~APIC_VECTOR_MASK;
         value |= APIC_SPIV_APIC_ENABLED;
-        
+
         /* This bit is reserved on P4/Xeon and should be cleared */
-        if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
+        if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
+            (boot_cpu_data.x86 == 15))
                 value &= ~APIC_SPIV_FOCUS_DISABLED;
         else
                 value |= APIC_SPIV_FOCUS_DISABLED;
@@ -427,14 +812,17 @@ void __init init_bsp_APIC(void)
          */
         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
         value = APIC_DM_NMI;
-        if (!APIC_INTEGRATED(ver))              /* 82489DX */
+        if (!lapic_is_integrated())             /* 82489DX */
                 value |= APIC_LVT_LEVEL_TRIGGER;
         apic_write_around(APIC_LVT1, value);
 }
 
+/**
+ * setup_local_APIC - setup the local APIC
+ */
 void __devinit setup_local_APIC(void)
 {
-        unsigned long oldvalue, value, ver, maxlvt;
+        unsigned long oldvalue, value, maxlvt, integrated;
         int i, j;
 
         /* Pound the ESR really hard over the head with a big hammer - mbligh */
@@ -445,11 +833,7 @@ void __devinit setup_local_APIC(void)
                 apic_write(APIC_ESR, 0);
         }
 
-        value = apic_read(APIC_LVR);
-        ver = GET_APIC_VERSION(value);
-
-        if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
-                __error_in_apic_c();
+        integrated = lapic_is_integrated();
 
         /*
          * Double-check whether this APIC is really registered.
@@ -520,13 +904,10 @@ void __devinit setup_local_APIC(void)
          * like LRU than MRU (the short-term load is more even across CPUs).
          * See also the comment in end_level_ioapic_irq().  --macro
          */
-#if 1
+
         /* Enable focus processor (bit==0) */
         value &= ~APIC_SPIV_FOCUS_DISABLED;
-#else
-        /* Disable focus processor (bit==1) */
-        value |= APIC_SPIV_FOCUS_DISABLED;
-#endif
+
         /*
          * Set spurious IRQ vector
          */
@@ -562,17 +943,18 @@ void __devinit setup_local_APIC(void)
                 value = APIC_DM_NMI;
         else
                 value = APIC_DM_NMI | APIC_LVT_MASKED;
-        if (!APIC_INTEGRATED(ver))              /* 82489DX */
+        if (!integrated)                /* 82489DX */
                 value |= APIC_LVT_LEVEL_TRIGGER;
         apic_write_around(APIC_LVT1, value);
 
-        if (APIC_INTEGRATED(ver) && !esr_disable) {             /* !82489DX */
-                maxlvt = get_maxlvt();
+        if (integrated && !esr_disable) {               /* !82489DX */
+                maxlvt = lapic_get_maxlvt();
                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
                         apic_write(APIC_ESR, 0);
                 oldvalue = apic_read(APIC_ESR);
 
-                value = ERROR_APIC_VECTOR;      // enables sending errors
+                /* enables sending errors */
+                value = ERROR_APIC_VECTOR;
                 apic_write_around(APIC_LVTERR, value);
                 /*
                  * spec says clear errors after enabling vector.
@@ -585,207 +967,30 @@ void __devinit setup_local_APIC(void)
                                 "vector: 0x%08lx  after: 0x%08lx\n",
                                 oldvalue, value);
         } else {
-                if (esr_disable)        
-                        /* 
-                         * Something untraceble is creating bad interrupts on 
+                if (esr_disable)
+                        /*
+                         * Something untraceble is creating bad interrupts on
                          * secondary quads ... for the moment, just leave the
                          * ESR disabled - we can't do anything useful with the
                          * errors anyway - mbligh
                          */
-                        printk("Leaving ESR disabled.\n");
-                else 
-                        printk("No ESR for 82489DX.\n");
+                        printk(KERN_INFO "Leaving ESR disabled.\n");
+                else
+                        printk(KERN_INFO "No ESR for 82489DX.\n");
         }
 
+        /* Disable the local apic timer */
+        value = apic_read(APIC_LVTT);
+        value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
+        apic_write_around(APIC_LVTT, value);
+
         setup_apic_nmi_watchdog(NULL);
         apic_pm_activate();
 }
 
 /*
- * If Linux enabled the LAPIC against the BIOS default
- * disable it down before re-entering the BIOS on shutdown.
- * Otherwise the BIOS may get confused and not power-off.
- * Additionally clear all LVT entries before disable_local_APIC
- * for the case where Linux didn't enable the LAPIC.
+ * Detect and initialize APIC
  */
-void lapic_shutdown(void)
-{
-        unsigned long flags;
-
-        if (!cpu_has_apic)
-                return;
-
-        local_irq_save(flags);
-        clear_local_APIC();
-
-        if (enabled_via_apicbase)
-                disable_local_APIC();
-
-        local_irq_restore(flags);
-}
-
-#ifdef CONFIG_PM
-
-static struct {
-        int active;
-        /* r/w apic fields */
-        unsigned int apic_id;
-        unsigned int apic_taskpri;
-        unsigned int apic_ldr;
-        unsigned int apic_dfr;
-        unsigned int apic_spiv;
-        unsigned int apic_lvtt;
-        unsigned int apic_lvtpc;
-        unsigned int apic_lvt0;
-        unsigned int apic_lvt1;
-        unsigned int apic_lvterr;
-        unsigned int apic_tmict;
-        unsigned int apic_tdcr;
-        unsigned int apic_thmr;
-} apic_pm_state;
-
-static int lapic_suspend(struct sys_device *dev, pm_message_t state)
-{
-        unsigned long flags;
-        int maxlvt;
-
-        if (!apic_pm_state.active)
-                return 0;
-
-        maxlvt = get_maxlvt();
-
-        apic_pm_state.apic_id = apic_read(APIC_ID);
-        apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
-        apic_pm_state.apic_ldr = apic_read(APIC_LDR);
-        apic_pm_state.apic_dfr = apic_read(APIC_DFR);
-        apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
-        apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
-        if (maxlvt >= 4)
-                apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
-        apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
-        apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
-        apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
-        apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
-        apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
-#ifdef CONFIG_X86_MCE_P4THERMAL
-        if (maxlvt >= 5)
-                apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
-#endif
-        
-        local_irq_save(flags);
-        disable_local_APIC();
-        local_irq_restore(flags);
-        return 0;
-}
-
-static int lapic_resume(struct sys_device *dev)
-{
-        unsigned int l, h;
-        unsigned long flags;
-        int maxlvt;
-
-        if (!apic_pm_state.active)
-                return 0;
-
-        maxlvt = get_maxlvt();
-
-        local_irq_save(flags);
-
-        /*
-         * Make sure the APICBASE points to the right address
-         *
-         * FIXME! This will be wrong if we ever support suspend on
-         * SMP! We'll need to do this as part of the CPU restore!
-         */
-        rdmsr(MSR_IA32_APICBASE, l, h);
-        l &= ~MSR_IA32_APICBASE_BASE;
-        l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
-        wrmsr(MSR_IA32_APICBASE, l, h);
-
-        apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
-        apic_write(APIC_ID, apic_pm_state.apic_id);
-        apic_write(APIC_DFR, apic_pm_state.apic_dfr);
-        apic_write(APIC_LDR, apic_pm_state.apic_ldr);
-        apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
-        apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
-        apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
-        apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
-#ifdef CONFIG_X86_MCE_P4THERMAL
-        if (maxlvt >= 5)
-                apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
-#endif
-        if (maxlvt >= 4)
-                apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
-        apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
-        apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
-        apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
-        apic_write(APIC_ESR, 0);
-        apic_read(APIC_ESR);
-        apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
-        apic_write(APIC_ESR, 0);
-        apic_read(APIC_ESR);
-        local_irq_restore(flags);
-        return 0;
-}
-
-/*
- * This device has no shutdown method - fully functioning local APICs
- * are needed on every CPU up until machine_halt/restart/poweroff.
- */
-
-static struct sysdev_class lapic_sysclass = {
-        set_kset_name("lapic"),
-        .resume         = lapic_resume,
-        .suspend        = lapic_suspend,
-};
-
-static struct sys_device device_lapic = {
-        .id     = 0,
-        .cls    = &lapic_sysclass,
-};
-
-static void __devinit apic_pm_activate(void)
-{
-        apic_pm_state.active = 1;
-}
-
-static int __init init_lapic_sysfs(void)
-{
-        int error;
-
-        if (!cpu_has_apic)
-                return 0;
-        /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
-
-        error = sysdev_class_register(&lapic_sysclass);
-        if (!error)
-                error = sysdev_register(&device_lapic);
-        return error;
-}
-device_initcall(init_lapic_sysfs);
-
-#else   /* CONFIG_PM */
-
-static void apic_pm_activate(void) { }
-
-#endif  /* CONFIG_PM */
-
-/*
- * Detect and enable local APICs on non-SMP boards.
- * Original code written by Keir Fraser.
- */
-
-static int __init apic_set_verbosity(char *str)
-{
-        if (strcmp("debug", str) == 0)
-                apic_verbosity = APIC_DEBUG;
-        else if (strcmp("verbose", str) == 0)
-                apic_verbosity = APIC_VERBOSE;
-        return 1;
-}
-
-__setup("apic=", apic_set_verbosity);
-
 static int __init detect_init_APIC (void)
 {
         u32 h, l, features;
@@ -797,7 +1002,7 @@ static int __init detect_init_APIC (void)
         switch (boot_cpu_data.x86_vendor) {
         case X86_VENDOR_AMD:
                 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
-                    (boot_cpu_data.x86 == 15))      
+                    (boot_cpu_data.x86 == 15))
                         break;
                 goto no_apic;
         case X86_VENDOR_INTEL:
@@ -811,23 +1016,23 @@ static int __init detect_init_APIC (void)
 
         if (!cpu_has_apic) {
                 /*
-                 * Over-ride BIOS and try to enable the local
-                 * APIC only if "lapic" specified.
+                 * Over-ride BIOS and try to enable the local APIC only if
+                 * "lapic" specified.
                  */
                 if (enable_local_apic <= 0) {
-                        printk("Local APIC disabled by BIOS -- "
+                        printk(KERN_INFO "Local APIC disabled by BIOS -- "
                                "you can enable it with \"lapic\"\n");
                         return -1;
                 }
                 /*
-                 * Some BIOSes disable the local APIC in the
-                 * APIC_BASE MSR. This can only be done in
-                 * software for Intel P6 or later and AMD K7
-                 * (Model > 1) or later.
+                 * Some BIOSes disable the local APIC in the APIC_BASE
+                 * MSR. This can only be done in software for Intel P6 or later
+                 * and AMD K7 (Model > 1) or later.
                  */
                 rdmsr(MSR_IA32_APICBASE, l, h);
                 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
-                        printk("Local APIC disabled by BIOS -- reenabling.\n");
+                        printk(KERN_INFO
+                               "Local APIC disabled by BIOS -- reenabling.\n");
                         l &= ~MSR_IA32_APICBASE_BASE;
                         l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
                         wrmsr(MSR_IA32_APICBASE, l, h);
@@ -840,7 +1045,7 @@ static int __init detect_init_APIC (void)
          */
         features = cpuid_edx(1);
         if (!(features & (1 << X86_FEATURE_APIC))) {
-                printk("Could not enable APIC!\n");
+                printk(KERN_WARNING "Could not enable APIC!\n");
                 return -1;
         }
         set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
@@ -854,17 +1059,20 @@ static int __init detect_init_APIC (void)
         if (nmi_watchdog != NMI_NONE)
                 nmi_watchdog = NMI_LOCAL_APIC;
 
-        printk("Found and enabled local APIC!\n");
+        printk(KERN_INFO "Found and enabled local APIC!\n");
 
         apic_pm_activate();
 
         return 0;
 
 no_apic:
-        printk("No local APIC present or hardware disabled\n");
+        printk(KERN_INFO "No local APIC present or hardware disabled\n");
         return -1;
 }
 
+/**
+ * init_apic_mappings - initialize APIC mappings
+ */
 void __init init_apic_mappings(void)
 {
         unsigned long apic_phys;
@@ -924,387 +1132,96 @@ fake_ioapic_page:
 }
 
 /*
- * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
- * per second. We assume that the caller has already set up the local
- * APIC.
- *
- * The APIC timer is not exactly sync with the external timer chip, it
- * closely follows bus clocks.
- */
-
-/*
- * The timer chip is already set up at HZ interrupts per second here,
- * but we do not accept timer interrupts yet. We only allow the BP
- * to calibrate.
- */
-static unsigned int __devinit get_8254_timer_count(void)
-{
-        unsigned long flags;
-
-        unsigned int count;
-
-        spin_lock_irqsave(&i8253_lock, flags);
-
-        outb_p(0x00, PIT_MODE);
-        count = inb_p(PIT_CH0);
-        count |= inb_p(PIT_CH0) << 8;
-
-        spin_unlock_irqrestore(&i8253_lock, flags);
-
-        return count;
-}
-
-/* next tick in 8254 can be caught by catching timer wraparound */
-static void __devinit wait_8254_wraparound(void)
-{
-        unsigned int curr_count, prev_count;
-
-        curr_count = get_8254_timer_count();
-        do {
-                prev_count = curr_count;
-                curr_count = get_8254_timer_count();
-
-                /* workaround for broken Mercury/Neptune */
-                if (prev_count >= curr_count + 0x100)
-                        curr_count = get_8254_timer_count();
-
-        } while (prev_count >= curr_count);
-}
-
-/*
- * Default initialization for 8254 timers. If we use other timers like HPET,
- * we override this later
- */
-void (*wait_timer_tick)(void) __devinitdata = wait_8254_wraparound;
-
-/*
- * This function sets up the local APIC timer, with a timeout of
- * 'clocks' APIC bus clock. During calibration we actually call
- * this function twice on the boot CPU, once with a bogus timeout
- * value, second time for real. The other (noncalibrating) CPUs
- * call this function only once, with the real, calibrated value.
- *
- * We do reads before writes even if unnecessary, to get around the
- * P5 APIC double write bug.
+ * This initializes the IO-APIC and APIC hardware if this is
+ * a UP kernel.
  */
-
-#define APIC_DIVISOR 16
-
-static void __setup_APIC_LVTT(unsigned int clocks)
+int __init APIC_init_uniprocessor (void)
 {
-        unsigned int lvtt_value, tmp_value, ver;
-        int cpu = smp_processor_id();
-
-        ver = GET_APIC_VERSION(apic_read(APIC_LVR));
-        lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
-        if (!APIC_INTEGRATED(ver))
-                lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
-
-        if (cpu_isset(cpu, timer_bcast_ipi))
-                lvtt_value |= APIC_LVT_MASKED;
+        if (enable_local_apic < 0)
+                clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
 
-        apic_write_around(APIC_LVTT, lvtt_value);
+        if (!smp_found_config && !cpu_has_apic)
+                return -1;
 
         /*
-         * Divide PICLK by 16
+         * Complain if the BIOS pretends there is one.
          */
-        tmp_value = apic_read(APIC_TDCR);
-        apic_write_around(APIC_TDCR, (tmp_value
-                                & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
-                                | APIC_TDR_DIV_16);
-
-        apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
-}
+        if (!cpu_has_apic &&
+            APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
+                printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
+                       boot_cpu_physical_apicid);
+                clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
+                return -1;
+        }
 
-static void __devinit setup_APIC_timer(unsigned int clocks)
-{
-        unsigned long flags;
+        verify_local_APIC();
 
-        local_irq_save(flags);
+        connect_bsp_APIC();
 
         /*
-         * Wait for IRQ0's slice:
+         * Hack: In case of kdump, after a crash, kernel might be booting
+         * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
+         * might be zero if read from MP tables. Get it from LAPIC.
          */
-        wait_timer_tick();
+#ifdef CONFIG_CRASH_DUMP
+        boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
+#endif
+        phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
 
-        __setup_APIC_LVTT(clocks);
+        setup_local_APIC();
 
-        local_irq_restore(flags);
+#ifdef CONFIG_X86_IO_APIC
+        if (smp_found_config)
+                if (!skip_ioapic_setup && nr_ioapics)
+                        setup_IO_APIC();
+#endif
+        setup_boot_clock();
+
+        return 0;
 }
 
 /*
- * In this function we calibrate APIC bus clocks to the external
- * timer. Unfortunately we cannot use jiffies and the timer irq
- * to calibrate, since some later bootup code depends on getting
- * the first irq? Ugh.
- *
- * We want to do the calibration only once since we
- * want to have local timer irqs syncron. CPUs connected
- * by the same APIC bus have the very same bus frequency.
- * And we want to have irqs off anyways, no accidental
- * APIC irq that way.
+ * APIC command line parameters
  */
-
-static int __init calibrate_APIC_clock(void)
-{
-        unsigned long long t1 = 0, t2 = 0;
-        long tt1, tt2;
-        long result;
-        int i;
-        const int LOOPS = HZ/10;
-
-        apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
-
-        /*
-         * Put whatever arbitrary (but long enough) timeout
-         * value into the APIC clock, we just want to get the
-         * counter running for calibration.
-         */
-        __setup_APIC_LVTT(1000000000);
-
-        /*
-         * The timer chip counts down to zero. Let's wait
-         * for a wraparound to start exact measurement:
-         * (the current tick might have been already half done)
-         */
-
-        wait_timer_tick();
-
-        /*
-         * We wrapped around just now. Let's start:
-         */
-        if (cpu_has_tsc)
-                rdtscll(t1);
-        tt1 = apic_read(APIC_TMCCT);
-
-        /*
-         * Let's wait LOOPS wraprounds:
-         */
-        for (i = 0; i < LOOPS; i++)
-                wait_timer_tick();
-
-        tt2 = apic_read(APIC_TMCCT);
-        if (cpu_has_tsc)
-                rdtscll(t2);
-
-        /*
-         * The APIC bus clock counter is 32 bits only, it
-         * might have overflown, but note that we use signed
-         * longs, thus no extra care needed.
-         *
-         * underflown to be exact, as the timer counts down ;)
-         */
-
-        result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
-
-        if (cpu_has_tsc)
-                apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
-                        "%ld.%04ld MHz.\n",
-                        ((long)(t2-t1)/LOOPS)/(1000000/HZ),
-                        ((long)(t2-t1)/LOOPS)%(1000000/HZ));
-
-        apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
-                "%ld.%04ld MHz.\n",
-                result/(1000000/HZ),
-                result%(1000000/HZ));
-
-        return result;
-}
-
-static unsigned int calibration_result;
-
-void __init setup_boot_APIC_clock(void)
-{
-        unsigned long flags;
-        apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n");
-        using_apic_timer = 1;
-
-        local_irq_save(flags);
-
-        calibration_result = calibrate_APIC_clock();
-        /*
-         * Now set up the timer for real.
-         */
-        setup_APIC_timer(calibration_result);
-
-        local_irq_restore(flags);
-}
-
-void __devinit setup_secondary_APIC_clock(void)
-{
-        setup_APIC_timer(calibration_result);
-}
-
-void disable_APIC_timer(void)
-{
-        if (using_apic_timer) {
-                unsigned long v;
-
-                v = apic_read(APIC_LVTT);
-                /*
-                 * When an illegal vector value (0-15) is written to an LVT
-                 * entry and delivery mode is Fixed, the APIC may signal an
-                 * illegal vector error, with out regard to whether the mask
-                 * bit is set or whether an interrupt is actually seen on input.
-                 *
-                 * Boot sequence might call this function when the LVTT has
-                 * '0' vector value. So make sure vector field is set to
-                 * valid value.
-                 */
-                v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
-                apic_write_around(APIC_LVTT, v);
-        }
-}
-
-void enable_APIC_timer(void)
+static int __init parse_lapic(char *arg)
 {
-        int cpu = smp_processor_id();
-
-        if (using_apic_timer &&
-            !cpu_isset(cpu, timer_bcast_ipi)) {
-                unsigned long v;
-
-                v = apic_read(APIC_LVTT);
-                apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
-        }
+        enable_local_apic = 1;
+        return 0;
 }
+early_param("lapic", parse_lapic);
 
-void switch_APIC_timer_to_ipi(void *cpumask)
+static int __init parse_nolapic(char *arg)
 {
-        cpumask_t mask = *(cpumask_t *)cpumask;
-        int cpu = smp_processor_id();
-
-        if (cpu_isset(cpu, mask) &&
-            !cpu_isset(cpu, timer_bcast_ipi)) {
-                disable_APIC_timer();
-                cpu_set(cpu, timer_bcast_ipi);
-        }
+        enable_local_apic = -1;
+        clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
+        return 0;
 }
-EXPORT_SYMBOL(switch_APIC_timer_to_ipi);
+early_param("nolapic", parse_nolapic);
 
-void switch_ipi_to_APIC_timer(void *cpumask)
+static int __init apic_set_verbosity(char *str)
 {
-        cpumask_t mask = *(cpumask_t *)cpumask;
-        int cpu = smp_processor_id();
-
-        if (cpu_isset(cpu, mask) &&
-            cpu_isset(cpu, timer_bcast_ipi)) {
-                cpu_clear(cpu, timer_bcast_ipi);
-                enable_APIC_timer();
-        }
+        if (strcmp("debug", str) == 0)
+                apic_verbosity = APIC_DEBUG;
+        else if (strcmp("verbose", str) == 0)
+                apic_verbosity = APIC_VERBOSE;
+        return 1;
 }
-EXPORT_SYMBOL(switch_ipi_to_APIC_timer);
-
-#undef APIC_DIVISOR
 
-/*
- * Local timer interrupt handler. It does both profiling and
- * process statistics/rescheduling.
- *
- * We do profiling in every local tick, statistics/rescheduling
- * happen only every 'profiling multiplier' ticks. The default
- * multiplier is 1 and it can be changed by writing the new multiplier
- * value into /proc/profile.
- */
-
-inline void smp_local_timer_interrupt(void)
-{
-        profile_tick(CPU_PROFILING);
-#ifdef CONFIG_SMP
-        update_process_times(user_mode_vm(get_irq_regs()));
-#endif
+__setup("apic=", apic_set_verbosity);
 
-        /*
-         * We take the 'long' return path, and there every subsystem
-         * grabs the apropriate locks (kernel lock/ irq lock).
-         *
-         * we might want to decouple profiling from the 'long path',
-         * and do the profiling totally in assembly.
-         *
-         * Currently this isn't too much of an issue (performance wise),
-         * we can take more than 100K local irqs per second on a 100 MHz P5.
-         */
-}
 
 /*
- * Local APIC timer interrupt. This is the most natural way for doing
- * local interrupts, but local timer interrupts can be emulated by
- * broadcast interrupts too. [in case the hw doesn't support APIC timers]
- *
- * [ if a single-CPU system runs an SMP kernel then we call the local
- *   interrupt as well. Thus we cannot inline the local irq ... ]
+ * Local APIC interrupts
  */
 
-fastcall void smp_apic_timer_interrupt(struct pt_regs *regs)
-{
-        struct pt_regs *old_regs = set_irq_regs(regs);
-        int cpu = smp_processor_id();
-
-        /*
-         * the NMI deadlock-detector uses this.
-         */
-        per_cpu(irq_stat, cpu).apic_timer_irqs++;
-
-        /*
-         * NOTE! We'd better ACK the irq immediately,
-         * because timer handling can be slow.
-         */
-        ack_APIC_irq();
-        /*
-         * update_process_times() expects us to have done irq_enter().
-         * Besides, if we don't timer interrupts ignore the global
-         * interrupt lock, which is the WrongThing (tm) to do.
-         */
-        irq_enter();
-        smp_local_timer_interrupt();
-        irq_exit();
-        set_irq_regs(old_regs);
-}
-
-#ifndef CONFIG_SMP
-static void up_apic_timer_interrupt_call(void)
-{
-        int cpu = smp_processor_id();
-
-        /*
-         * the NMI deadlock-detector uses this.
-         */
-        per_cpu(irq_stat, cpu).apic_timer_irqs++;
-
-        smp_local_timer_interrupt();
-}
-#endif
-
-void smp_send_timer_broadcast_ipi(void)
-{
-        cpumask_t mask;
-
-        cpus_and(mask, cpu_online_map, timer_bcast_ipi);
-        if (!cpus_empty(mask)) {
-#ifdef CONFIG_SMP
-                send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
-#else
-                /*
-                 * We can directly call the apic timer interrupt handler
-                 * in UP case. Minus all irq related functions
-                 */
-                up_apic_timer_interrupt_call();
-#endif
-        }
-}
-
-int setup_profiling_timer(unsigned int multiplier)
-{
-        return -EINVAL;
-}
-
 /*
  * This interrupt should _never_ happen with our APIC/SMP architecture
  */
-fastcall void smp_spurious_interrupt(struct pt_regs *regs)
+void smp_spurious_interrupt(struct pt_regs *regs)
 {
         unsigned long v;
 
+        exit_idle();
         irq_enter();
         /*
          * Check if this really is a spurious interrupt and ACK it
@@ -1316,19 +1233,19 @@ fastcall void smp_spurious_interrupt(struct pt_regs *regs)
                 ack_APIC_irq();
 
         /* see sw-dev-man vol 3, chapter 7.4.13.5 */
-        printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
-                        smp_processor_id());
+        printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
+               "should never happen.\n", smp_processor_id());
         irq_exit();
 }
 
 /*
  * This interrupt should never happen with our APIC/SMP architecture
  */
-
-fastcall void smp_error_interrupt(struct pt_regs *regs)
+void smp_error_interrupt(struct pt_regs *regs)
 {
         unsigned long v, v1;
 
+        exit_idle();
         irq_enter();
         /* First tickle the hardware, only then report what went on. -- REW */
         v = apic_read(APIC_ESR);
@@ -1348,69 +1265,261 @@ fastcall void smp_error_interrupt(struct pt_regs *regs)
            7: Illegal register address
         */
         printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
-                smp_processor_id(), v , v1);
+                smp_processor_id(), v , v1);
         irq_exit();
 }
 
 /*
- * This initializes the IO-APIC and APIC hardware if this is
- * a UP kernel.
+ * Initialize APIC interrupts
  */
-int __init APIC_init_uniprocessor (void)
+void __init apic_intr_init(void)
 {
-        if (enable_local_apic < 0)
-                clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
+#ifdef CONFIG_SMP
+        smp_intr_init();
+#endif
+        /* self generated IPI for local APIC timer */
+        set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 
-        if (!smp_found_config && !cpu_has_apic)
-                return -1;
+        /* IPI vectors for APIC spurious and error interrupts */
+        set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
+        set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 
-        /*
-         * Complain if the BIOS pretends there is one.
-         */
-        if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
-                printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
-                        boot_cpu_physical_apicid);
-                clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
-                return -1;
+        /* thermal monitor LVT interrupt */
+#ifdef CONFIG_X86_MCE_P4THERMAL
+        set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
+#endif
+}
+
+/**
+ * connect_bsp_APIC - attach the APIC to the interrupt system
+ */
+void __init connect_bsp_APIC(void)
+{
+        if (pic_mode) {
+                /*
+                 * Do not trust the local APIC being empty at bootup.
+                 */
+                clear_local_APIC();
+                /*
+                 * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
+                 * local APIC to INT and NMI lines.
+                 */
+                apic_printk(APIC_VERBOSE, "leaving PIC mode, "
+                                "enabling APIC mode.\n");
+                outb(0x70, 0x22);
+                outb(0x01, 0x23);
         }
+        enable_apic_mode();
+}
 
-        verify_local_APIC();
+/**
+ * disconnect_bsp_APIC - detach the APIC from the interrupt system
+ * @virt_wire_setup:    indicates, whether virtual wire mode is selected
+ *
+ * Virtual wire mode is necessary to deliver legacy interrupts even when the
+ * APIC is disabled.
+ */
+void disconnect_bsp_APIC(int virt_wire_setup)
+{
+        if (pic_mode) {
+                /*
+                 * Put the board back into PIC mode (has an effect only on
+                 * certain older boards).  Note that APIC interrupts, including
+                 * IPIs, won't work beyond this point!  The only exception are
+                 * INIT IPIs.
+                 */
+                apic_printk(APIC_VERBOSE, "disabling APIC mode, "
+                                "entering PIC mode.\n");
+                outb(0x70, 0x22);
+                outb(0x00, 0x23);
+        } else {
+                /* Go back to Virtual Wire compatibility mode */
+                unsigned long value;
 
-        connect_bsp_APIC();
+                /* For the spurious interrupt use vector F, and enable it */
+                value = apic_read(APIC_SPIV);
+                value &= ~APIC_VECTOR_MASK;
+                value |= APIC_SPIV_APIC_ENABLED;
+                value |= 0xf;
+                apic_write_around(APIC_SPIV, value);
 
-        /*
-         * Hack: In case of kdump, after a crash, kernel might be booting
-         * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
-         * might be zero if read from MP tables. Get it from LAPIC.
-         */
-#ifdef CONFIG_CRASH_DUMP
-        boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
-#endif
-        phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
+                if (!virt_wire_setup) {
+                        /*
+                         * For LVT0 make it edge triggered, active high,
+                         * external and enabled
+                         */
+                        value = apic_read(APIC_LVT0);
+                        value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
+                                APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
+                                APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
+                        value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
+                        value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
+                        apic_write_around(APIC_LVT0, value);
+                } else {
+                        /* Disable LVT0 */
+                        apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
+                }
 
-        setup_local_APIC();
+                /*
+                 * For LVT1 make it edge triggered, active high, nmi and
+                 * enabled
+                 */
+                value = apic_read(APIC_LVT1);
+                value &= ~(
+                        APIC_MODE_MASK | APIC_SEND_PENDING |
+                        APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
+                        APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
+                value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
+                value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
+                apic_write_around(APIC_LVT1, value);
+        }
+}
 
-#ifdef CONFIG_X86_IO_APIC
-        if (smp_found_config)
-                if (!skip_ioapic_setup && nr_ioapics)
-                        setup_IO_APIC();
+/*
+ * Power management
+ */
+#ifdef CONFIG_PM
+
+static struct {
+        int active;
+        /* r/w apic fields */
+        unsigned int apic_id;
+        unsigned int apic_taskpri;
+        unsigned int apic_ldr;
+        unsigned int apic_dfr;
+        unsigned int apic_spiv;
+        unsigned int apic_lvtt;
+        unsigned int apic_lvtpc;
+        unsigned int apic_lvt0;
+        unsigned int apic_lvt1;
+        unsigned int apic_lvterr;
+        unsigned int apic_tmict;
+        unsigned int apic_tdcr;
+        unsigned int apic_thmr;
+} apic_pm_state;
+
+static int lapic_suspend(struct sys_device *dev, pm_message_t state)
+{
+        unsigned long flags;
+        int maxlvt;
+
+        if (!apic_pm_state.active)
+                return 0;
+
+        maxlvt = lapic_get_maxlvt();
+
+        apic_pm_state.apic_id = apic_read(APIC_ID);
+        apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
+        apic_pm_state.apic_ldr = apic_read(APIC_LDR);
+        apic_pm_state.apic_dfr = apic_read(APIC_DFR);
+        apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
+        apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
+        if (maxlvt >= 4)
+                apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
+        apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
+        apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
+        apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
+        apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
+        apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
+#ifdef CONFIG_X86_MCE_P4THERMAL
+        if (maxlvt >= 5)
+                apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
 #endif
-        setup_boot_APIC_clock();
 
+        local_irq_save(flags);
+        disable_local_APIC();
+        local_irq_restore(flags);
         return 0;
 }
 
-static int __init parse_lapic(char *arg)
+static int lapic_resume(struct sys_device *dev)
 {
-        lapic_enable();
+        unsigned int l, h;
+        unsigned long flags;
+        int maxlvt;
+
+        if (!apic_pm_state.active)
+                return 0;
+
+        maxlvt = lapic_get_maxlvt();
+
+        local_irq_save(flags);
+
+        /*
+         * Make sure the APICBASE points to the right address
+         *
+         * FIXME! This will be wrong if we ever support suspend on
+         * SMP! We'll need to do this as part of the CPU restore!
+         */
+        rdmsr(MSR_IA32_APICBASE, l, h);
+        l &= ~MSR_IA32_APICBASE_BASE;
+        l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
+        wrmsr(MSR_IA32_APICBASE, l, h);
+
+        apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
+        apic_write(APIC_ID, apic_pm_state.apic_id);
+        apic_write(APIC_DFR, apic_pm_state.apic_dfr);
+        apic_write(APIC_LDR, apic_pm_state.apic_ldr);
+        apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
+        apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
+        apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
+        apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
+#ifdef CONFIG_X86_MCE_P4THERMAL
+        if (maxlvt >= 5)
+                apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
+#endif
+        if (maxlvt >= 4)
+                apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
+        apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
+        apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
+        apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
+        apic_write(APIC_ESR, 0);
+        apic_read(APIC_ESR);
+        apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
+        apic_write(APIC_ESR, 0);
+        apic_read(APIC_ESR);
+        local_irq_restore(flags);
         return 0;
 }
-early_param("lapic", parse_lapic);
 
-static int __init parse_nolapic(char *arg)
+/*
+ * This device has no shutdown method - fully functioning local APICs
+ * are needed on every CPU up until machine_halt/restart/poweroff.
+ */
+
+static struct sysdev_class lapic_sysclass = {
+        set_kset_name("lapic"),
+        .resume         = lapic_resume,
+        .suspend        = lapic_suspend,
+};
+
+static struct sys_device device_lapic = {
+        .id     = 0,
+        .cls    = &lapic_sysclass,
+};
+
+static void __devinit apic_pm_activate(void)
 {
-        lapic_disable();
-        return 0;
+        apic_pm_state.active = 1;
 }
-early_param("nolapic", parse_nolapic);
 
+static int __init init_lapic_sysfs(void)
+{
+        int error;
+
+        if (!cpu_has_apic)
+                return 0;
+        /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
+
+        error = sysdev_class_register(&lapic_sysclass);
+        if (!error)
+                error = sysdev_register(&device_lapic);
+        return error;
+}
+device_initcall(init_lapic_sysfs);
+
+#else   /* CONFIG_PM */
+
+static void apic_pm_activate(void) { }
+
+#endif  /* CONFIG_PM */