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-rw-r--r--arch/i386/kernel/acpi/cstate.c164
1 files changed, 0 insertions, 164 deletions
diff --git a/arch/i386/kernel/acpi/cstate.c b/arch/i386/kernel/acpi/cstate.c
deleted file mode 100644
index 2d39f55d29a8..000000000000
--- a/arch/i386/kernel/acpi/cstate.c
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * arch/i386/kernel/acpi/cstate.c
3 *
4 * Copyright (C) 2005 Intel Corporation
5 * Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
6 * - Added _PDC for SMP C-states on Intel CPUs
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/init.h>
12#include <linux/acpi.h>
13#include <linux/cpu.h>
14#include <linux/sched.h>
15
16#include <acpi/processor.h>
17#include <asm/acpi.h>
18
19/*
20 * Initialize bm_flags based on the CPU cache properties
21 * On SMP it depends on cache configuration
22 * - When cache is not shared among all CPUs, we flush cache
23 * before entering C3.
24 * - When cache is shared among all CPUs, we use bm_check
25 * mechanism as in UP case
26 *
27 * This routine is called only after all the CPUs are online
28 */
29void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
30 unsigned int cpu)
31{
32 struct cpuinfo_x86 *c = cpu_data + cpu;
33
34 flags->bm_check = 0;
35 if (num_online_cpus() == 1)
36 flags->bm_check = 1;
37 else if (c->x86_vendor == X86_VENDOR_INTEL) {
38 /*
39 * Today all CPUs that support C3 share cache.
40 * TBD: This needs to look at cache shared map, once
41 * multi-core detection patch makes to the base.
42 */
43 flags->bm_check = 1;
44 }
45}
46EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
47
48/* The code below handles cstate entry with monitor-mwait pair on Intel*/
49
50struct cstate_entry {
51 struct {
52 unsigned int eax;
53 unsigned int ecx;
54 } states[ACPI_PROCESSOR_MAX_POWER];
55};
56static struct cstate_entry *cpu_cstate_entry; /* per CPU ptr */
57
58static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
59
60#define MWAIT_SUBSTATE_MASK (0xf)
61#define MWAIT_SUBSTATE_SIZE (4)
62
63#define CPUID_MWAIT_LEAF (5)
64#define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1)
65#define CPUID5_ECX_INTERRUPT_BREAK (0x2)
66
67#define MWAIT_ECX_INTERRUPT_BREAK (0x1)
68
69#define NATIVE_CSTATE_BEYOND_HALT (2)
70
71int acpi_processor_ffh_cstate_probe(unsigned int cpu,
72 struct acpi_processor_cx *cx, struct acpi_power_register *reg)
73{
74 struct cstate_entry *percpu_entry;
75 struct cpuinfo_x86 *c = cpu_data + cpu;
76
77 cpumask_t saved_mask;
78 int retval;
79 unsigned int eax, ebx, ecx, edx;
80 unsigned int edx_part;
81 unsigned int cstate_type; /* C-state type and not ACPI C-state type */
82 unsigned int num_cstate_subtype;
83
84 if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF )
85 return -1;
86
87 if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
88 return -1;
89
90 percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
91 percpu_entry->states[cx->index].eax = 0;
92 percpu_entry->states[cx->index].ecx = 0;
93
94 /* Make sure we are running on right CPU */
95 saved_mask = current->cpus_allowed;
96 retval = set_cpus_allowed(current, cpumask_of_cpu(cpu));
97 if (retval)
98 return -1;
99
100 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
101
102 /* Check whether this particular cx_type (in CST) is supported or not */
103 cstate_type = (cx->address >> MWAIT_SUBSTATE_SIZE) + 1;
104 edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE);
105 num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
106
107 retval = 0;
108 if (num_cstate_subtype < (cx->address & MWAIT_SUBSTATE_MASK)) {
109 retval = -1;
110 goto out;
111 }
112
113 /* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */
114 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
115 !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) {
116 retval = -1;
117 goto out;
118 }
119 percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
120
121 /* Use the hint in CST */
122 percpu_entry->states[cx->index].eax = cx->address;
123
124 if (!mwait_supported[cstate_type]) {
125 mwait_supported[cstate_type] = 1;
126 printk(KERN_DEBUG "Monitor-Mwait will be used to enter C-%d "
127 "state\n", cx->type);
128 }
129
130out:
131 set_cpus_allowed(current, saved_mask);
132 return retval;
133}
134EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
135
136void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx)
137{
138 unsigned int cpu = smp_processor_id();
139 struct cstate_entry *percpu_entry;
140
141 percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
142 mwait_idle_with_hints(percpu_entry->states[cx->index].eax,
143 percpu_entry->states[cx->index].ecx);
144}
145EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter);
146
147static int __init ffh_cstate_init(void)
148{
149 struct cpuinfo_x86 *c = &boot_cpu_data;
150 if (c->x86_vendor != X86_VENDOR_INTEL)
151 return -1;
152
153 cpu_cstate_entry = alloc_percpu(struct cstate_entry);
154 return 0;
155}
156
157static void __exit ffh_cstate_exit(void)
158{
159 free_percpu(cpu_cstate_entry);
160 cpu_cstate_entry = NULL;
161}
162
163arch_initcall(ffh_cstate_init);
164__exitcall(ffh_cstate_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 17:27:54 -0400