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1# Put here option for CPU selection and depending optimization
2if !X86_ELAN
3
4choice
5 prompt "Processor family"
6 default M686
7
8config M386
9 bool "386"
10 ---help---
11 This is the processor type of your CPU. This information is used for
12 optimizing purposes. In order to compile a kernel that can run on
13 all x86 CPU types (albeit not optimally fast), you can specify
14 "386" here.
15
16 The kernel will not necessarily run on earlier architectures than
17 the one you have chosen, e.g. a Pentium optimized kernel will run on
18 a PPro, but not necessarily on a i486.
19
20 Here are the settings recommended for greatest speed:
21 - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI
22 486DLC/DLC2, UMC 486SX-S and NexGen Nx586. Only "386" kernels
23 will run on a 386 class machine.
24 - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
25 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
26 - "586" for generic Pentium CPUs lacking the TSC
27 (time stamp counter) register.
28 - "Pentium-Classic" for the Intel Pentium.
29 - "Pentium-MMX" for the Intel Pentium MMX.
30 - "Pentium-Pro" for the Intel Pentium Pro.
31 - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
32 - "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
33 - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
34 - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
35 - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
36 - "Crusoe" for the Transmeta Crusoe series.
37 - "Efficeon" for the Transmeta Efficeon series.
38 - "Winchip-C6" for original IDT Winchip.
39 - "Winchip-2" for IDT Winchip 2.
40 - "Winchip-2A" for IDT Winchips with 3dNow! capabilities.
41 - "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
42 - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
43 - "VIA C3-2 for VIA C3-2 "Nehemiah" (model 9 and above).
44
45 If you don't know what to do, choose "386".
46
47config M486
48 bool "486"
49 help
50 Select this for a 486 series processor, either Intel or one of the
51 compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX,
52 DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or
53 U5S.
54
55config M586
56 bool "586/K5/5x86/6x86/6x86MX"
57 help
58 Select this for an 586 or 686 series processor such as the AMD K5,
59 the Cyrix 5x86, 6x86 and 6x86MX. This choice does not
60 assume the RDTSC (Read Time Stamp Counter) instruction.
61
62config M586TSC
63 bool "Pentium-Classic"
64 help
65 Select this for a Pentium Classic processor with the RDTSC (Read
66 Time Stamp Counter) instruction for benchmarking.
67
68config M586MMX
69 bool "Pentium-MMX"
70 help
71 Select this for a Pentium with the MMX graphics/multimedia
72 extended instructions.
73
74config M686
75 bool "Pentium-Pro"
76 help
77 Select this for Intel Pentium Pro chips. This enables the use of
78 Pentium Pro extended instructions, and disables the init-time guard
79 against the f00f bug found in earlier Pentiums.
80
81config MPENTIUMII
82 bool "Pentium-II/Celeron(pre-Coppermine)"
83 help
84 Select this for Intel chips based on the Pentium-II and
85 pre-Coppermine Celeron core. This option enables an unaligned
86 copy optimization, compiles the kernel with optimization flags
87 tailored for the chip, and applies any applicable Pentium Pro
88 optimizations.
89
90config MPENTIUMIII
91 bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
92 help
93 Select this for Intel chips based on the Pentium-III and
94 Celeron-Coppermine core. This option enables use of some
95 extended prefetch instructions in addition to the Pentium II
96 extensions.
97
98config MPENTIUMM
99 bool "Pentium M"
100 help
101 Select this for Intel Pentium M (not Pentium-4 M)
102 notebook chips.
103
104config MPENTIUM4
105 bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/Xeon"
106 help
107 Select this for Intel Pentium 4 chips. This includes the
108 Pentium 4, P4-based Celeron and Xeon, and Pentium-4 M
109 (not Pentium M) chips. This option enables compile flags
110 optimized for the chip, uses the correct cache shift, and
111 applies any applicable Pentium III optimizations.
112
113config MK6
114 bool "K6/K6-II/K6-III"
115 help
116 Select this for an AMD K6-family processor. Enables use of
117 some extended instructions, and passes appropriate optimization
118 flags to GCC.
119
120config MK7
121 bool "Athlon/Duron/K7"
122 help
123 Select this for an AMD Athlon K7-family processor. Enables use of
124 some extended instructions, and passes appropriate optimization
125 flags to GCC.
126
127config MK8
128 bool "Opteron/Athlon64/Hammer/K8"
129 help
130 Select this for an AMD Opteron or Athlon64 Hammer-family processor. Enables
131 use of some extended instructions, and passes appropriate optimization
132 flags to GCC.
133
134config MCRUSOE
135 bool "Crusoe"
136 help
137 Select this for a Transmeta Crusoe processor. Treats the processor
138 like a 586 with TSC, and sets some GCC optimization flags (like a
139 Pentium Pro with no alignment requirements).
140
141config MEFFICEON
142 bool "Efficeon"
143 help
144 Select this for a Transmeta Efficeon processor.
145
146config MWINCHIPC6
147 bool "Winchip-C6"
148 help
149 Select this for an IDT Winchip C6 chip. Linux and GCC
150 treat this chip as a 586TSC with some extended instructions
151 and alignment requirements.
152
153config MWINCHIP2
154 bool "Winchip-2"
155 help
156 Select this for an IDT Winchip-2. Linux and GCC
157 treat this chip as a 586TSC with some extended instructions
158 and alignment requirements.
159
160config MWINCHIP3D
161 bool "Winchip-2A/Winchip-3"
162 help
163 Select this for an IDT Winchip-2A or 3. Linux and GCC
164 treat this chip as a 586TSC with some extended instructions
165 and alignment reqirements. Also enable out of order memory
166 stores for this CPU, which can increase performance of some
167 operations.
168
169config MGEODEGX1
170 bool "GeodeGX1"
171 help
172 Select this for a Geode GX1 (Cyrix MediaGX) chip.
173
174config MCYRIXIII
175 bool "CyrixIII/VIA-C3"
176 help
177 Select this for a Cyrix III or C3 chip. Presently Linux and GCC
178 treat this chip as a generic 586. Whilst the CPU is 686 class,
179 it lacks the cmov extension which gcc assumes is present when
180 generating 686 code.
181 Note that Nehemiah (Model 9) and above will not boot with this
182 kernel due to them lacking the 3DNow! instructions used in earlier
183 incarnations of the CPU.
184
185config MVIAC3_2
186 bool "VIA C3-2 (Nehemiah)"
187 help
188 Select this for a VIA C3 "Nehemiah". Selecting this enables usage
189 of SSE and tells gcc to treat the CPU as a 686.
190 Note, this kernel will not boot on older (pre model 9) C3s.
191
192endchoice
193
194config X86_GENERIC
195 bool "Generic x86 support"
196 help
197 Instead of just including optimizations for the selected
198 x86 variant (e.g. PII, Crusoe or Athlon), include some more
199 generic optimizations as well. This will make the kernel
200 perform better on x86 CPUs other than that selected.
201
202 This is really intended for distributors who need more
203 generic optimizations.
204
205endif
206
207#
208# Define implied options from the CPU selection here
209#
210config X86_CMPXCHG
211 bool
212 depends on !M386
213 default y
214
215config X86_XADD
216 bool
217 depends on !M386
218 default y
219
220config X86_L1_CACHE_SHIFT
221 int
222 default "7" if MPENTIUM4 || X86_GENERIC
223 default "4" if X86_ELAN || M486 || M386
224 default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODEGX1
225 default "6" if MK7 || MK8 || MPENTIUMM
226
227config RWSEM_GENERIC_SPINLOCK
228 bool
229 depends on M386
230 default y
231
232config RWSEM_XCHGADD_ALGORITHM
233 bool
234 depends on !M386
235 default y
236
237config GENERIC_CALIBRATE_DELAY
238 bool
239 default y
240
241config X86_PPRO_FENCE
242 bool
243 depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1
244 default y
245
246config X86_F00F_BUG
247 bool
248 depends on M586MMX || M586TSC || M586 || M486 || M386
249 default y
250
251config X86_WP_WORKS_OK
252 bool
253 depends on !M386
254 default y
255
256config X86_INVLPG
257 bool
258 depends on !M386
259 default y
260
261config X86_BSWAP
262 bool
263 depends on !M386
264 default y
265
266config X86_POPAD_OK
267 bool
268 depends on !M386
269 default y
270
271config X86_CMPXCHG64
272 bool
273 depends on !M386 && !M486
274 default y
275
276config X86_ALIGNMENT_16
277 bool
278 depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1
279 default y
280
281config X86_GOOD_APIC
282 bool
283 depends on MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || MK8 || MEFFICEON
284 default y
285
286config X86_INTEL_USERCOPY
287 bool
288 depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON
289 default y
290
291config X86_USE_PPRO_CHECKSUM
292 bool
293 depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON
294 default y
295
296config X86_USE_3DNOW
297 bool
298 depends on MCYRIXIII || MK7
299 default y
300
301config X86_OOSTORE
302 bool
303 depends on (MWINCHIP3D || MWINCHIP2 || MWINCHIPC6) && MTRR
304 default y
305
306config X86_TSC
307 bool
308 depends on (MWINCHIP3D || MWINCHIP2 || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MGEODEGX1) && !X86_NUMAQ
309 default y