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-rw-r--r--arch/frv/kernel/break.S2
-rw-r--r--arch/frv/kernel/entry.S2
-rw-r--r--arch/frv/kernel/vmlinux.lds.S27
-rw-r--r--arch/frv/mm/tlb-miss.S2
4 files changed, 18 insertions, 15 deletions
diff --git a/arch/frv/kernel/break.S b/arch/frv/kernel/break.S
index dac4a5f68c2e..bd0bdf908d93 100644
--- a/arch/frv/kernel/break.S
+++ b/arch/frv/kernel/break.S
@@ -63,7 +63,7 @@ __break_trace_through_exceptions:
63# entry point for Break Exceptions/Interrupts 63# entry point for Break Exceptions/Interrupts
64# 64#
65############################################################################### 65###############################################################################
66 .text 66 .section .text.break
67 .balign 4 67 .balign 4
68 .globl __entry_break 68 .globl __entry_break
69__entry_break: 69__entry_break:
diff --git a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S
index 1e74f3c5cee2..f926c7094776 100644
--- a/arch/frv/kernel/entry.S
+++ b/arch/frv/kernel/entry.S
@@ -38,7 +38,7 @@
38 38
39#define nr_syscalls ((syscall_table_size)/4) 39#define nr_syscalls ((syscall_table_size)/4)
40 40
41 .text 41 .section .text.entry
42 .balign 4 42 .balign 4
43 43
44.macro LEDS val 44.macro LEDS val
diff --git a/arch/frv/kernel/vmlinux.lds.S b/arch/frv/kernel/vmlinux.lds.S
index 3b71e0c86399..a17a81d58bf6 100644
--- a/arch/frv/kernel/vmlinux.lds.S
+++ b/arch/frv/kernel/vmlinux.lds.S
@@ -76,6 +76,12 @@ SECTIONS
76 *(.data.init_task) 76 *(.data.init_task)
77 } 77 }
78 78
79 . = ALIGN(4096);
80 .data.page_aligned : { *(.data.idt) }
81
82 . = ALIGN(L1_CACHE_BYTES);
83 .data.cacheline_aligned : { *(.data.cacheline_aligned) }
84
79 .trap : { 85 .trap : {
80 /* trap table management - read entry-table.S before modifying */ 86 /* trap table management - read entry-table.S before modifying */
81 . = ALIGN(8192); 87 . = ALIGN(8192);
@@ -86,28 +92,25 @@ SECTIONS
86 *(.trap.break) 92 *(.trap.break)
87 } 93 }
88 94
89 . = ALIGN(4096);
90 .data.page_aligned : { *(.data.idt) }
91
92 . = ALIGN(L1_CACHE_BYTES);
93 .data.cacheline_aligned : { *(.data.cacheline_aligned) }
94
95 /* Text and read-only data */ 95 /* Text and read-only data */
96 . = ALIGN(4); 96 . = ALIGN(4);
97 _text = .; 97 _text = .;
98 _stext = .; 98 _stext = .;
99 .text : { 99 .text : {
100 *( 100 *(.text.start)
101 .text.start .text.* 101 *(.text.entry)
102 *(.text.break)
103 *(.text.tlbmiss)
104 TEXT_TEXT
105 SCHED_TEXT
106 LOCK_TEXT
102#ifdef CONFIG_DEBUG_INFO 107#ifdef CONFIG_DEBUG_INFO
108 *(
103 .init.text 109 .init.text
104 .exit.text 110 .exit.text
105 .exitcall.exit 111 .exitcall.exit
106#endif
107 ) 112 )
108 TEXT_TEXT 113#endif
109 SCHED_TEXT
110 LOCK_TEXT
111 *(.fixup) 114 *(.fixup)
112 *(.gnu.warning) 115 *(.gnu.warning)
113 *(.exitcall.exit) 116 *(.exitcall.exit)
diff --git a/arch/frv/mm/tlb-miss.S b/arch/frv/mm/tlb-miss.S
index 04da67468378..07643482cad2 100644
--- a/arch/frv/mm/tlb-miss.S
+++ b/arch/frv/mm/tlb-miss.S
@@ -16,7 +16,7 @@
16#include <asm/highmem.h> 16#include <asm/highmem.h>
17#include <asm/spr-regs.h> 17#include <asm/spr-regs.h>
18 18
19 .section .text 19 .section .text.tlbmiss
20 .balign 4 20 .balign 4
21 21
22 .globl __entry_insn_mmu_miss 22 .globl __entry_insn_mmu_miss