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-rw-r--r--arch/frv/Kconfig3
-rw-r--r--arch/frv/include/asm/system.h9
-rw-r--r--arch/frv/include/asm/thread_info.h4
-rw-r--r--arch/frv/kernel/irq-mb93091.c30
-rw-r--r--arch/frv/kernel/irq-mb93093.c31
-rw-r--r--arch/frv/kernel/irq-mb93493.c25
-rw-r--r--arch/frv/kernel/irq.c80
7 files changed, 66 insertions, 116 deletions
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
index f6037b2da25e..6db8aea5667f 100644
--- a/arch/frv/Kconfig
+++ b/arch/frv/Kconfig
@@ -6,6 +6,8 @@ config FRV
6 select HAVE_IRQ_WORK 6 select HAVE_IRQ_WORK
7 select HAVE_PERF_EVENTS 7 select HAVE_PERF_EVENTS
8 select HAVE_GENERIC_HARDIRQS 8 select HAVE_GENERIC_HARDIRQS
9 select GENERIC_IRQ_SHOW
10 select GENERIC_HARDIRQS_NO_DEPRECATED
9 11
10config ZONE_DMA 12config ZONE_DMA
11 bool 13 bool
@@ -361,7 +363,6 @@ menu "Power management options"
361 363
362config ARCH_SUSPEND_POSSIBLE 364config ARCH_SUSPEND_POSSIBLE
363 def_bool y 365 def_bool y
364 depends on !SMP
365 366
366source kernel/power/Kconfig 367source kernel/power/Kconfig
367endmenu 368endmenu
diff --git a/arch/frv/include/asm/system.h b/arch/frv/include/asm/system.h
index 0a6d8d9ca45b..6c10fd2c626d 100644
--- a/arch/frv/include/asm/system.h
+++ b/arch/frv/include/asm/system.h
@@ -45,21 +45,12 @@ do { \
45#define wmb() asm volatile ("membar" : : :"memory") 45#define wmb() asm volatile ("membar" : : :"memory")
46#define read_barrier_depends() do { } while (0) 46#define read_barrier_depends() do { } while (0)
47 47
48#ifdef CONFIG_SMP
49#define smp_mb() mb()
50#define smp_rmb() rmb()
51#define smp_wmb() wmb()
52#define smp_read_barrier_depends() read_barrier_depends()
53#define set_mb(var, value) \
54 do { xchg(&var, (value)); } while (0)
55#else
56#define smp_mb() barrier() 48#define smp_mb() barrier()
57#define smp_rmb() barrier() 49#define smp_rmb() barrier()
58#define smp_wmb() barrier() 50#define smp_wmb() barrier()
59#define smp_read_barrier_depends() do {} while(0) 51#define smp_read_barrier_depends() do {} while(0)
60#define set_mb(var, value) \ 52#define set_mb(var, value) \
61 do { var = (value); barrier(); } while (0) 53 do { var = (value); barrier(); } while (0)
62#endif
63 54
64extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2))); 55extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2)));
65extern void free_initmem(void); 56extern void free_initmem(void);
diff --git a/arch/frv/include/asm/thread_info.h b/arch/frv/include/asm/thread_info.h
index 8582e9c7531c..cefbe73dc119 100644
--- a/arch/frv/include/asm/thread_info.h
+++ b/arch/frv/include/asm/thread_info.h
@@ -21,6 +21,8 @@
21 21
22#define THREAD_SIZE 8192 22#define THREAD_SIZE 8192
23 23
24#define __HAVE_ARCH_TASK_STRUCT_ALLOCATOR
25
24/* 26/*
25 * low level task data that entry.S needs immediate access to 27 * low level task data that entry.S needs immediate access to
26 * - this struct should fit entirely inside of one cache line 28 * - this struct should fit entirely inside of one cache line
@@ -87,7 +89,7 @@ register struct thread_info *__current_thread_info asm("gr15");
87#define alloc_thread_info_node(tsk, node) \ 89#define alloc_thread_info_node(tsk, node) \
88 kzalloc_node(THREAD_SIZE, GFP_KERNEL, node) 90 kzalloc_node(THREAD_SIZE, GFP_KERNEL, node)
89#else 91#else
90#define alloc_thread_info_node(tsk) \ 92#define alloc_thread_info_node(tsk, node) \
91 kmalloc_node(THREAD_SIZE, GFP_KERNEL, node) 93 kmalloc_node(THREAD_SIZE, GFP_KERNEL, node)
92#endif 94#endif
93 95
diff --git a/arch/frv/kernel/irq-mb93091.c b/arch/frv/kernel/irq-mb93091.c
index 4dd9adaf115a..9afc2ea400dc 100644
--- a/arch/frv/kernel/irq-mb93091.c
+++ b/arch/frv/kernel/irq-mb93091.c
@@ -36,45 +36,45 @@
36/* 36/*
37 * on-motherboard FPGA PIC operations 37 * on-motherboard FPGA PIC operations
38 */ 38 */
39static void frv_fpga_mask(unsigned int irq) 39static void frv_fpga_mask(struct irq_data *d)
40{ 40{
41 uint16_t imr = __get_IMR(); 41 uint16_t imr = __get_IMR();
42 42
43 imr |= 1 << (irq - IRQ_BASE_FPGA); 43 imr |= 1 << (d->irq - IRQ_BASE_FPGA);
44 44
45 __set_IMR(imr); 45 __set_IMR(imr);
46} 46}
47 47
48static void frv_fpga_ack(unsigned int irq) 48static void frv_fpga_ack(struct irq_data *d)
49{ 49{
50 __clr_IFR(1 << (irq - IRQ_BASE_FPGA)); 50 __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
51} 51}
52 52
53static void frv_fpga_mask_ack(unsigned int irq) 53static void frv_fpga_mask_ack(struct irq_data *d)
54{ 54{
55 uint16_t imr = __get_IMR(); 55 uint16_t imr = __get_IMR();
56 56
57 imr |= 1 << (irq - IRQ_BASE_FPGA); 57 imr |= 1 << (d->irq - IRQ_BASE_FPGA);
58 __set_IMR(imr); 58 __set_IMR(imr);
59 59
60 __clr_IFR(1 << (irq - IRQ_BASE_FPGA)); 60 __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
61} 61}
62 62
63static void frv_fpga_unmask(unsigned int irq) 63static void frv_fpga_unmask(struct irq_data *d)
64{ 64{
65 uint16_t imr = __get_IMR(); 65 uint16_t imr = __get_IMR();
66 66
67 imr &= ~(1 << (irq - IRQ_BASE_FPGA)); 67 imr &= ~(1 << (d->irq - IRQ_BASE_FPGA));
68 68
69 __set_IMR(imr); 69 __set_IMR(imr);
70} 70}
71 71
72static struct irq_chip frv_fpga_pic = { 72static struct irq_chip frv_fpga_pic = {
73 .name = "mb93091", 73 .name = "mb93091",
74 .ack = frv_fpga_ack, 74 .irq_ack = frv_fpga_ack,
75 .mask = frv_fpga_mask, 75 .irq_mask = frv_fpga_mask,
76 .mask_ack = frv_fpga_mask_ack, 76 .irq_mask_ack = frv_fpga_mask_ack,
77 .unmask = frv_fpga_unmask, 77 .irq_unmask = frv_fpga_unmask,
78}; 78};
79 79
80/* 80/*
@@ -146,9 +146,9 @@ void __init fpga_init(void)
146 __clr_IFR(0x0000); 146 __clr_IFR(0x0000);
147 147
148 for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++) 148 for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++)
149 set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq); 149 irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq);
150 150
151 set_irq_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq); 151 irq_set_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq);
152 152
153 /* the FPGA drives the first four external IRQ inputs on the CPU PIC */ 153 /* the FPGA drives the first four external IRQ inputs on the CPU PIC */
154 setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]); 154 setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]);
diff --git a/arch/frv/kernel/irq-mb93093.c b/arch/frv/kernel/irq-mb93093.c
index e45209031873..4d4ad09d3c91 100644
--- a/arch/frv/kernel/irq-mb93093.c
+++ b/arch/frv/kernel/irq-mb93093.c
@@ -35,45 +35,44 @@
35/* 35/*
36 * off-CPU FPGA PIC operations 36 * off-CPU FPGA PIC operations
37 */ 37 */
38static void frv_fpga_mask(unsigned int irq) 38static void frv_fpga_mask(struct irq_data *d)
39{ 39{
40 uint16_t imr = __get_IMR(); 40 uint16_t imr = __get_IMR();
41 41
42 imr |= 1 << (irq - IRQ_BASE_FPGA); 42 imr |= 1 << (d->irq - IRQ_BASE_FPGA);
43 __set_IMR(imr); 43 __set_IMR(imr);
44} 44}
45 45
46static void frv_fpga_ack(unsigned int irq) 46static void frv_fpga_ack(struct irq_data *d)
47{ 47{
48 __clr_IFR(1 << (irq - IRQ_BASE_FPGA)); 48 __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
49} 49}
50 50
51static void frv_fpga_mask_ack(unsigned int irq) 51static void frv_fpga_mask_ack(struct irq_data *d)
52{ 52{
53 uint16_t imr = __get_IMR(); 53 uint16_t imr = __get_IMR();
54 54
55 imr |= 1 << (irq - IRQ_BASE_FPGA); 55 imr |= 1 << (d->irq - IRQ_BASE_FPGA);
56 __set_IMR(imr); 56 __set_IMR(imr);
57 57
58 __clr_IFR(1 << (irq - IRQ_BASE_FPGA)); 58 __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
59} 59}
60 60
61static void frv_fpga_unmask(unsigned int irq) 61static void frv_fpga_unmask(struct irq_data *d)
62{ 62{
63 uint16_t imr = __get_IMR(); 63 uint16_t imr = __get_IMR();
64 64
65 imr &= ~(1 << (irq - IRQ_BASE_FPGA)); 65 imr &= ~(1 << (d->irq - IRQ_BASE_FPGA));
66 66
67 __set_IMR(imr); 67 __set_IMR(imr);
68} 68}
69 69
70static struct irq_chip frv_fpga_pic = { 70static struct irq_chip frv_fpga_pic = {
71 .name = "mb93093", 71 .name = "mb93093",
72 .ack = frv_fpga_ack, 72 .irq_ack = frv_fpga_ack,
73 .mask = frv_fpga_mask, 73 .irq_mask = frv_fpga_mask,
74 .mask_ack = frv_fpga_mask_ack, 74 .irq_mask_ack = frv_fpga_mask_ack,
75 .unmask = frv_fpga_unmask, 75 .irq_unmask = frv_fpga_unmask,
76 .end = frv_fpga_end,
77}; 76};
78 77
79/* 78/*
@@ -94,7 +93,7 @@ static irqreturn_t fpga_interrupt(int irq, void *_mask)
94 irq = 31 - irq; 93 irq = 31 - irq;
95 mask &= ~(1 << irq); 94 mask &= ~(1 << irq);
96 95
97 generic_irq_handle(IRQ_BASE_FPGA + irq); 96 generic_handle_irq(IRQ_BASE_FPGA + irq);
98 } 97 }
99 98
100 return IRQ_HANDLED; 99 return IRQ_HANDLED;
@@ -125,7 +124,7 @@ void __init fpga_init(void)
125 __clr_IFR(0x0000); 124 __clr_IFR(0x0000);
126 125
127 for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++) 126 for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++)
128 set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq); 127 irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq);
129 128
130 /* the FPGA drives external IRQ input #2 on the CPU PIC */ 129 /* the FPGA drives external IRQ input #2 on the CPU PIC */
131 setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]); 130 setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]);
diff --git a/arch/frv/kernel/irq-mb93493.c b/arch/frv/kernel/irq-mb93493.c
index ba55ecdfb245..4d034c7840c9 100644
--- a/arch/frv/kernel/irq-mb93493.c
+++ b/arch/frv/kernel/irq-mb93493.c
@@ -45,46 +45,46 @@
45 * daughter board PIC operations 45 * daughter board PIC operations
46 * - there is no way to ACK interrupts in the MB93493 chip 46 * - there is no way to ACK interrupts in the MB93493 chip
47 */ 47 */
48static void frv_mb93493_mask(unsigned int irq) 48static void frv_mb93493_mask(struct irq_data *d)
49{ 49{
50 uint32_t iqsr; 50 uint32_t iqsr;
51 volatile void *piqsr; 51 volatile void *piqsr;
52 52
53 if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493))) 53 if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493)))
54 piqsr = __addr_MB93493_IQSR(1); 54 piqsr = __addr_MB93493_IQSR(1);
55 else 55 else
56 piqsr = __addr_MB93493_IQSR(0); 56 piqsr = __addr_MB93493_IQSR(0);
57 57
58 iqsr = readl(piqsr); 58 iqsr = readl(piqsr);
59 iqsr &= ~(1 << (irq - IRQ_BASE_MB93493 + 16)); 59 iqsr &= ~(1 << (d->irq - IRQ_BASE_MB93493 + 16));
60 writel(iqsr, piqsr); 60 writel(iqsr, piqsr);
61} 61}
62 62
63static void frv_mb93493_ack(unsigned int irq) 63static void frv_mb93493_ack(struct irq_data *d)
64{ 64{
65} 65}
66 66
67static void frv_mb93493_unmask(unsigned int irq) 67static void frv_mb93493_unmask(struct irq_data *d)
68{ 68{
69 uint32_t iqsr; 69 uint32_t iqsr;
70 volatile void *piqsr; 70 volatile void *piqsr;
71 71
72 if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493))) 72 if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493)))
73 piqsr = __addr_MB93493_IQSR(1); 73 piqsr = __addr_MB93493_IQSR(1);
74 else 74 else
75 piqsr = __addr_MB93493_IQSR(0); 75 piqsr = __addr_MB93493_IQSR(0);
76 76
77 iqsr = readl(piqsr); 77 iqsr = readl(piqsr);
78 iqsr |= 1 << (irq - IRQ_BASE_MB93493 + 16); 78 iqsr |= 1 << (d->irq - IRQ_BASE_MB93493 + 16);
79 writel(iqsr, piqsr); 79 writel(iqsr, piqsr);
80} 80}
81 81
82static struct irq_chip frv_mb93493_pic = { 82static struct irq_chip frv_mb93493_pic = {
83 .name = "mb93093", 83 .name = "mb93093",
84 .ack = frv_mb93493_ack, 84 .irq_ack = frv_mb93493_ack,
85 .mask = frv_mb93493_mask, 85 .irq_mask = frv_mb93493_mask,
86 .mask_ack = frv_mb93493_mask, 86 .irq_mask_ack = frv_mb93493_mask,
87 .unmask = frv_mb93493_unmask, 87 .irq_unmask = frv_mb93493_unmask,
88}; 88};
89 89
90/* 90/*
@@ -139,7 +139,8 @@ void __init mb93493_init(void)
139 int irq; 139 int irq;
140 140
141 for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++) 141 for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++)
142 set_irq_chip_and_handler(irq, &frv_mb93493_pic, handle_edge_irq); 142 irq_set_chip_and_handler(irq, &frv_mb93493_pic,
143 handle_edge_irq);
143 144
144 /* the MB93493 drives external IRQ inputs on the CPU PIC */ 145 /* the MB93493 drives external IRQ inputs on the CPU PIC */
145 setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]); 146 setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]);
diff --git a/arch/frv/kernel/irq.c b/arch/frv/kernel/irq.c
index 625136625a7f..a5f624a9f559 100644
--- a/arch/frv/kernel/irq.c
+++ b/arch/frv/kernel/irq.c
@@ -47,89 +47,45 @@ extern void __init mb93493_init(void);
47 47
48atomic_t irq_err_count; 48atomic_t irq_err_count;
49 49
50/* 50int arch_show_interrupts(struct seq_file *p, int prec)
51 * Generic, controller-independent functions:
52 */
53int show_interrupts(struct seq_file *p, void *v)
54{ 51{
55 int i = *(loff_t *) v, cpu; 52 seq_printf(p, "%*s: ", prec, "ERR");
56 struct irqaction * action; 53 seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
57 unsigned long flags;
58
59 if (i == 0) {
60 char cpuname[12];
61
62 seq_printf(p, " ");
63 for_each_present_cpu(cpu) {
64 sprintf(cpuname, "CPU%d", cpu);
65 seq_printf(p, " %10s", cpuname);
66 }
67 seq_putc(p, '\n');
68 }
69
70 if (i < NR_IRQS) {
71 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
72 action = irq_desc[i].action;
73 if (action) {
74 seq_printf(p, "%3d: ", i);
75 for_each_present_cpu(cpu)
76 seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
77 seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-");
78 seq_printf(p, " %s", action->name);
79 for (action = action->next;
80 action;
81 action = action->next)
82 seq_printf(p, ", %s", action->name);
83
84 seq_putc(p, '\n');
85 }
86
87 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
88 } else if (i == NR_IRQS) {
89 seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count));
90 }
91
92 return 0; 54 return 0;
93} 55}
94 56
95/* 57/*
96 * on-CPU PIC operations 58 * on-CPU PIC operations
97 */ 59 */
98static void frv_cpupic_ack(unsigned int irqlevel) 60static void frv_cpupic_ack(struct irq_data *d)
99{ 61{
100 __clr_RC(irqlevel); 62 __clr_RC(d->irq);
101 __clr_IRL(); 63 __clr_IRL();
102} 64}
103 65
104static void frv_cpupic_mask(unsigned int irqlevel) 66static void frv_cpupic_mask(struct irq_data *d)
105{ 67{
106 __set_MASK(irqlevel); 68 __set_MASK(d->irq);
107} 69}
108 70
109static void frv_cpupic_mask_ack(unsigned int irqlevel) 71static void frv_cpupic_mask_ack(struct irq_data *d)
110{ 72{
111 __set_MASK(irqlevel); 73 __set_MASK(d->irq);
112 __clr_RC(irqlevel); 74 __clr_RC(d->irq);
113 __clr_IRL(); 75 __clr_IRL();
114} 76}
115 77
116static void frv_cpupic_unmask(unsigned int irqlevel) 78static void frv_cpupic_unmask(struct irq_data *d)
117{
118 __clr_MASK(irqlevel);
119}
120
121static void frv_cpupic_end(unsigned int irqlevel)
122{ 79{
123 __clr_MASK(irqlevel); 80 __clr_MASK(d->irq);
124} 81}
125 82
126static struct irq_chip frv_cpu_pic = { 83static struct irq_chip frv_cpu_pic = {
127 .name = "cpu", 84 .name = "cpu",
128 .ack = frv_cpupic_ack, 85 .irq_ack = frv_cpupic_ack,
129 .mask = frv_cpupic_mask, 86 .irq_mask = frv_cpupic_mask,
130 .mask_ack = frv_cpupic_mask_ack, 87 .irq_mask_ack = frv_cpupic_mask_ack,
131 .unmask = frv_cpupic_unmask, 88 .irq_unmask = frv_cpupic_unmask,
132 .end = frv_cpupic_end,
133}; 89};
134 90
135/* 91/*
@@ -161,10 +117,10 @@ void __init init_IRQ(void)
161 int level; 117 int level;
162 118
163 for (level = 1; level <= 14; level++) 119 for (level = 1; level <= 14; level++)
164 set_irq_chip_and_handler(level, &frv_cpu_pic, 120 irq_set_chip_and_handler(level, &frv_cpu_pic,
165 handle_level_irq); 121 handle_level_irq);
166 122
167 set_irq_handler(IRQ_CPU_TIMER0, handle_edge_irq); 123 irq_set_handler(IRQ_CPU_TIMER0, handle_edge_irq);
168 124
169 /* set the trigger levels for internal interrupt sources 125 /* set the trigger levels for internal interrupt sources
170 * - timers all falling-edge 126 * - timers all falling-edge
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 08:17:03 -0500