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-rw-r--r--arch/frv/include/asm/atomic.h198
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diff --git a/arch/frv/include/asm/atomic.h b/arch/frv/include/asm/atomic.h
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1/* atomic.h: atomic operation emulation for FR-V
2 *
3 * For an explanation of how atomic ops work in this arch, see:
4 * Documentation/frv/atomic-ops.txt
5 *
6 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
7 * Written by David Howells (dhowells@redhat.com)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14#ifndef _ASM_ATOMIC_H
15#define _ASM_ATOMIC_H
16
17#include <linux/types.h>
18#include <asm/spr-regs.h>
19#include <asm/system.h>
20
21#ifdef CONFIG_SMP
22#error not SMP safe
23#endif
24
25/*
26 * Atomic operations that C can't guarantee us. Useful for
27 * resource counting etc..
28 *
29 * We do not have SMP systems, so we don't have to deal with that.
30 */
31
32/* Atomic operations are already serializing */
33#define smp_mb__before_atomic_dec() barrier()
34#define smp_mb__after_atomic_dec() barrier()
35#define smp_mb__before_atomic_inc() barrier()
36#define smp_mb__after_atomic_inc() barrier()
37
38#define ATOMIC_INIT(i) { (i) }
39#define atomic_read(v) ((v)->counter)
40#define atomic_set(v, i) (((v)->counter) = (i))
41
42#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
43static inline int atomic_add_return(int i, atomic_t *v)
44{
45 unsigned long val;
46
47 asm("0: \n"
48 " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
49 " ckeq icc3,cc7 \n"
50 " ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
51 " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
52 " add%I2 %1,%2,%1 \n"
53 " cst.p %1,%M0 ,cc3,#1 \n"
54 " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
55 " beq icc3,#0,0b \n"
56 : "+U"(v->counter), "=&r"(val)
57 : "NPr"(i)
58 : "memory", "cc7", "cc3", "icc3"
59 );
60
61 return val;
62}
63
64static inline int atomic_sub_return(int i, atomic_t *v)
65{
66 unsigned long val;
67
68 asm("0: \n"
69 " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
70 " ckeq icc3,cc7 \n"
71 " ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
72 " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
73 " sub%I2 %1,%2,%1 \n"
74 " cst.p %1,%M0 ,cc3,#1 \n"
75 " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
76 " beq icc3,#0,0b \n"
77 : "+U"(v->counter), "=&r"(val)
78 : "NPr"(i)
79 : "memory", "cc7", "cc3", "icc3"
80 );
81
82 return val;
83}
84
85#else
86
87extern int atomic_add_return(int i, atomic_t *v);
88extern int atomic_sub_return(int i, atomic_t *v);
89
90#endif
91
92static inline int atomic_add_negative(int i, atomic_t *v)
93{
94 return atomic_add_return(i, v) < 0;
95}
96
97static inline void atomic_add(int i, atomic_t *v)
98{
99 atomic_add_return(i, v);
100}
101
102static inline void atomic_sub(int i, atomic_t *v)
103{
104 atomic_sub_return(i, v);
105}
106
107static inline void atomic_inc(atomic_t *v)
108{
109 atomic_add_return(1, v);
110}
111
112static inline void atomic_dec(atomic_t *v)
113{
114 atomic_sub_return(1, v);
115}
116
117#define atomic_dec_return(v) atomic_sub_return(1, (v))
118#define atomic_inc_return(v) atomic_add_return(1, (v))
119
120#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
121#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
122#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
123
124/*****************************************************************************/
125/*
126 * exchange value with memory
127 */
128#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
129
130#define xchg(ptr, x) \
131({ \
132 __typeof__(ptr) __xg_ptr = (ptr); \
133 __typeof__(*(ptr)) __xg_orig; \
134 \
135 switch (sizeof(__xg_orig)) { \
136 case 4: \
137 asm volatile( \
138 "swap%I0 %M0,%1" \
139 : "+m"(*__xg_ptr), "=r"(__xg_orig) \
140 : "1"(x) \
141 : "memory" \
142 ); \
143 break; \
144 \
145 default: \
146 __xg_orig = (__typeof__(__xg_orig))0; \
147 asm volatile("break"); \
148 break; \
149 } \
150 \
151 __xg_orig; \
152})
153
154#else
155
156extern uint32_t __xchg_32(uint32_t i, volatile void *v);
157
158#define xchg(ptr, x) \
159({ \
160 __typeof__(ptr) __xg_ptr = (ptr); \
161 __typeof__(*(ptr)) __xg_orig; \
162 \
163 switch (sizeof(__xg_orig)) { \
164 case 4: __xg_orig = (__typeof__(*(ptr))) __xchg_32((uint32_t) x, __xg_ptr); break; \
165 default: \
166 __xg_orig = (__typeof__(__xg_orig))0; \
167 asm volatile("break"); \
168 break; \
169 } \
170 __xg_orig; \
171})
172
173#endif
174
175#define tas(ptr) (xchg((ptr), 1))
176
177#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
178#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
179
180static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
181{
182 int c, old;
183 c = atomic_read(v);
184 for (;;) {
185 if (unlikely(c == (u)))
186 break;
187 old = atomic_cmpxchg((v), c, c + (a));
188 if (likely(old == c))
189 break;
190 c = old;
191 }
192 return c != (u);
193}
194
195#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
196
197#include <asm-generic/atomic.h>
198#endif /* _ASM_ATOMIC_H */
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