diff options
Diffstat (limited to 'arch/cris')
| -rw-r--r-- | arch/cris/arch-v10/drivers/pcf8563.c | 2 | ||||
| -rw-r--r-- | arch/cris/arch-v32/drivers/pcf8563.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/cris/arch-v10/drivers/pcf8563.c b/arch/cris/arch-v10/drivers/pcf8563.c index 1de0026bb94e..c263b8232dbc 100644 --- a/arch/cris/arch-v10/drivers/pcf8563.c +++ b/arch/cris/arch-v10/drivers/pcf8563.c | |||
| @@ -4,7 +4,7 @@ | |||
| 4 | * From Phillips' datasheet: | 4 | * From Phillips' datasheet: |
| 5 | * | 5 | * |
| 6 | * The PCF8563 is a CMOS real-time clock/calendar optimized for low power | 6 | * The PCF8563 is a CMOS real-time clock/calendar optimized for low power |
| 7 | * consumption. A programmable clock output, interupt output and voltage | 7 | * consumption. A programmable clock output, interrupt output and voltage |
| 8 | * low detector are also provided. All address and data are transferred | 8 | * low detector are also provided. All address and data are transferred |
| 9 | * serially via two-line bidirectional I2C-bus. Maximum bus speed is | 9 | * serially via two-line bidirectional I2C-bus. Maximum bus speed is |
| 10 | * 400 kbits/s. The built-in word address register is incremented | 10 | * 400 kbits/s. The built-in word address register is incremented |
diff --git a/arch/cris/arch-v32/drivers/pcf8563.c b/arch/cris/arch-v32/drivers/pcf8563.c index da479a14f836..6dbd700d3d66 100644 --- a/arch/cris/arch-v32/drivers/pcf8563.c +++ b/arch/cris/arch-v32/drivers/pcf8563.c | |||
| @@ -4,7 +4,7 @@ | |||
| 4 | * From Phillips' datasheet: | 4 | * From Phillips' datasheet: |
| 5 | * | 5 | * |
| 6 | * The PCF8563 is a CMOS real-time clock/calendar optimized for low power | 6 | * The PCF8563 is a CMOS real-time clock/calendar optimized for low power |
| 7 | * consumption. A programmable clock output, interupt output and voltage | 7 | * consumption. A programmable clock output, interrupt output and voltage |
| 8 | * low detector are also provided. All address and data are transferred | 8 | * low detector are also provided. All address and data are transferred |
| 9 | * serially via two-line bidirectional I2C-bus. Maximum bus speed is | 9 | * serially via two-line bidirectional I2C-bus. Maximum bus speed is |
| 10 | * 400 kbits/s. The built-in word address register is incremented | 10 | * 400 kbits/s. The built-in word address register is incremented |