9 files changed, 114 insertions, 34 deletions

diff --git a/arch/cris/include/asm/Kbuild b/arch/cris/include/asm/Kbuild
index d5b631935ec8..956eea246b97 100644
--- a/arch/cris/include/asm/Kbuild
+++ b/arch/cris/include/asm/Kbuild
@@ -4,8 +4,7 @@ header-y += arch-v10/
 header-y += arch-v32/
 
 header-y += ethernet.h
+header-y += etraxgpio.h
+header-y += rs485.h
 header-y += rtc.h
 header-y += sync_serial.h
-
-unifdef-y += etraxgpio.h
-unifdef-y += rs485.h
diff --git a/arch/cris/include/asm/dma-mapping.h b/arch/cris/include/asm/dma-mapping.h
index da8ef8e8f842..8588b2ccf854 100644
--- a/arch/cris/include/asm/dma-mapping.h
+++ b/arch/cris/include/asm/dma-mapping.h
@@ -152,14 +152,6 @@ dma_set_mask(struct device *dev, u64 mask)
         return 0;
 }
 
-static inline int
-dma_get_cache_alignment(void)
-{
-        return (1 << INTERNODE_CACHE_SHIFT);
-}
-
-#define dma_is_consistent(d, h) (1)
-
 static inline void
 dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                enum dma_data_direction direction)
diff --git a/arch/cris/include/asm/etraxgpio.h b/arch/cris/include/asm/etraxgpio.h
index 38f1c8e1770c..d474818a537e 100644
--- a/arch/cris/include/asm/etraxgpio.h
+++ b/arch/cris/include/asm/etraxgpio.h
@@ -21,31 +21,35 @@
  * /dev/leds   minor 2, Access to leds depending on kernelconfig
  *
  * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3):
- * /dev/gpioa  minor 0,  8 bit GPIO, each bit can change direction
- * /dev/gpiob  minor 1, 18 bit GPIO, each bit can change direction
- * /dev/gpioc  minor 3, 18 bit GPIO, each bit can change direction
- * /dev/gpiod  minor 4, 18 bit GPIO, each bit can change direction
+ * /dev/gpioa  minor 0, 32 bit GPIO, each bit can change direction
+ * /dev/gpiob  minor 1, 32 bit GPIO, each bit can change direction
+ * /dev/gpioc  minor 3, 16 bit GPIO, each bit can change direction
+ * /dev/gpiod  minor 4, 32 bit GPIO, input only
  * /dev/leds   minor 2, Access to leds depending on kernelconfig
  * /dev/pwm0   minor 16, PWM channel 0 on PA30
  * /dev/pwm1   minor 17, PWM channel 1 on PA31
  * /dev/pwm2   minor 18, PWM channel 2 on PB26
+ * /dev/ppwm   minor 19, PPWM channel
  *
  */
 #ifndef _ASM_ETRAXGPIO_H
 #define _ASM_ETRAXGPIO_H
 
+#define GPIO_MINOR_FIRST 0
+
+#define ETRAXGPIO_IOCTYPE 43
+
 /* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
 #ifdef CONFIG_ETRAX_ARCH_V10
-#define ETRAXGPIO_IOCTYPE 43
 #define GPIO_MINOR_A 0
 #define GPIO_MINOR_B 1
 #define GPIO_MINOR_LEDS 2
 #define GPIO_MINOR_G 3
 #define GPIO_MINOR_LAST 3
+#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
 #endif
 
 #ifdef CONFIG_ETRAXFS
-#define ETRAXGPIO_IOCTYPE 43
 #define GPIO_MINOR_A 0
 #define GPIO_MINOR_B 1
 #define GPIO_MINOR_LEDS 2
@@ -58,10 +62,10 @@
 #else
 #define GPIO_MINOR_LAST 5
 #endif
+#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
 #endif
 
 #ifdef CONFIG_CRIS_MACH_ARTPEC3
-#define ETRAXGPIO_IOCTYPE 43
 #define GPIO_MINOR_A 0
 #define GPIO_MINOR_B 1
 #define GPIO_MINOR_LEDS 2
@@ -73,12 +77,17 @@
 #else
 #define GPIO_MINOR_LAST 4
 #endif
-#define GPIO_MINOR_PWM0 16
-#define GPIO_MINOR_PWM1 17
-#define GPIO_MINOR_PWM2 18
-#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2
+#define GPIO_MINOR_FIRST_PWM 16
+#define GPIO_MINOR_PWM0 (GPIO_MINOR_FIRST_PWM+0)
+#define GPIO_MINOR_PWM1 (GPIO_MINOR_FIRST_PWM+1)
+#define GPIO_MINOR_PWM2 (GPIO_MINOR_FIRST_PWM+2)
+#define GPIO_MINOR_PPWM (GPIO_MINOR_FIRST_PWM+3)
+#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PPWM
+#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST_PWM
 #endif
 
+
+
 /* supported ioctl _IOC_NR's */
 
 #define IO_READBITS  0x1  /* read and return current port bits (obsolete) */
@@ -125,12 +134,10 @@
  */
 #define IO_READ_INBITS   0x10 /* *arg is result of reading the input pins */
 #define IO_READ_OUTBITS  0x11 /* *arg is result of reading the output shadow */
-#define IO_SETGET_INPUT  0x12 /* bits set in *arg is set to input,
-                               * *arg updated with current input pins.
-                               */
-#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output,
-                               * *arg updated with current output pins.
-                               */
+#define IO_SETGET_INPUT  0x12 /* bits set in *arg is set to input, */
+                              /* *arg updated with current input pins. */
+#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */
+                              /* *arg updated with current output pins. */
 
 /* The following ioctl's are applicable to the PWM channels only */
 
@@ -140,7 +147,8 @@ enum io_pwm_mode {
         PWM_OFF = 0,            /* disabled, deallocated */
         PWM_STANDARD = 1,       /* 390 kHz, duty cycle 0..255/256 */
         PWM_FAST = 2,           /* variable freq, w/ 10ns active pulse len */
-        PWM_VARFREQ = 3         /* individually configurable high/low periods */
+        PWM_VARFREQ = 3,        /* individually configurable high/low periods */
+        PWM_SOFT = 4            /* software generated */
 };
 
 struct io_pwm_set_mode {
@@ -176,4 +184,56 @@ struct io_pwm_set_duty {
         int duty;               /* 0..255 */
 };
 
+/* Returns information about the latest PWM pulse.
+ * lo: Length of the latest low period, in units of 10ns.
+ * hi: Length of the latest high period, in units of 10ns.
+ * cnt: Time since last detected edge, in units of 10ns.
+ *
+ * The input source to PWM is decied by IO_PWM_SET_INPUT_SRC.
+ *
+ * NOTE: All PWM devices is connected to the same input source.
+ */
+#define IO_PWM_GET_PERIOD   0x23
+
+struct io_pwm_get_period {
+        unsigned int lo;
+        unsigned int hi;
+        unsigned int cnt;
+};
+
+/* Sets the input source for the PWM input. For the src value see the
+ * register description for gio:rw_pwm_in_cfg.
+ *
+ * NOTE: All PWM devices is connected to the same input source.
+ */
+#define IO_PWM_SET_INPUT_SRC   0x24
+struct io_pwm_set_input_src {
+        unsigned int src;       /* 0..7 */
+};
+
+/* Sets the duty cycles in steps of 1/256, 0 = 0%, 255 = 100% duty cycle */
+#define IO_PPWM_SET_DUTY     0x25
+
+struct io_ppwm_set_duty {
+        int duty;               /* 0..255 */
+};
+
+/* Configuraton struct for the IO_PWMCLK_SET_CONFIG ioctl to configure
+ * PWM capable gpio pins:
+ */
+#define IO_PWMCLK_SETGET_CONFIG 0x26
+struct gpio_pwmclk_conf {
+  unsigned int gpiopin; /* The pin number based on the opened device */
+  unsigned int baseclk; /* The base clock to use, or sw will select one close*/
+  unsigned int low;     /* The number of low periods of the baseclk */
+  unsigned int high;    /* The number of high periods of the baseclk */
+};
+
+/* Examples:
+ * To get a symmetric 12 MHz clock without knowing anything about the hardware:
+ * baseclk = 12000000, low = 0, high = 0
+ * To just get info of current setting:
+ * baseclk = 0, low = 0, high = 0, the values will be updated by driver.
+ */
+
 #endif
diff --git a/arch/cris/include/asm/ioctls.h b/arch/cris/include/asm/ioctls.h
index 35bbc181598a..c9129ed37443 100644
--- a/arch/cris/include/asm/ioctls.h
+++ b/arch/cris/include/asm/ioctls.h
@@ -54,6 +54,7 @@
 #define TCSETSF2        _IOW('T',0x2D, struct termios2)
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+#define TIOCSIG         _IOW('T',0x36, int)  /* Generate signal on Pty slave */
 
 #define FIONCLEX        0x5450  /* these numbers need to be adjusted. */
 #define FIOCLEX         0x5451
@@ -70,13 +71,12 @@
 
 #define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
 #define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
-#define TIOCGHAYESESP   0x545E  /* Get Hayes ESP configuration */
-#define TIOCSHAYESESP   0x545F  /* Set Hayes ESP configuration */
 #define FIOQSIZE        0x5460
 
 #define TIOCSERSETRS485 0x5461  /* enable rs-485 (deprecated) */
 #define TIOCSERWRRS485  0x5462  /* write rs-485 */
 #define TIOCSRS485      0x5463  /* enable rs-485 */
+#define TIOCGRS485      0x542E  /* get rs-485 */
 
 /* Used for packet mode */
 #define TIOCPKT_DATA             0
@@ -86,6 +86,7 @@
 #define TIOCPKT_START            8
 #define TIOCPKT_NOSTOP          16
 #define TIOCPKT_DOSTOP          32
+#define TIOCPKT_IOCTL           64
 
 #define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
 
diff --git a/arch/cris/include/asm/local64.h b/arch/cris/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/cris/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/cris/include/asm/pgtable.h b/arch/cris/include/asm/pgtable.h
index 99ea6cd1b143..f63d6fccbc6c 100644
--- a/arch/cris/include/asm/pgtable.h
+++ b/arch/cris/include/asm/pgtable.h
@@ -260,6 +260,9 @@ static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long addre
 #define pgd_ERROR(e) \
         printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
 
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
+                remap_pfn_range(vma, vaddr, pfn, size, prot)
+
 
 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
 
diff --git a/arch/cris/include/asm/scatterlist.h b/arch/cris/include/asm/scatterlist.h
index 249a7842ff5f..f11f8f40ec4a 100644
--- a/arch/cris/include/asm/scatterlist.h
+++ b/arch/cris/include/asm/scatterlist.h
@@ -3,6 +3,4 @@
 
 #include <asm-generic/scatterlist.h>
 
-#define ISA_DMA_THRESHOLD (0x1fffffff)
-
 #endif /* !(__ASM_CRIS_SCATTERLIST_H) */
diff --git a/arch/cris/include/asm/sync_serial.h b/arch/cris/include/asm/sync_serial.h
index d87c24df2b38..7f827fea30e7 100644
--- a/arch/cris/include/asm/sync_serial.h
+++ b/arch/cris/include/asm/sync_serial.h
@@ -19,6 +19,7 @@
 #define SSP_OPOLARITY  _IOR('S', 4, unsigned int)
 #define SSP_SPI        _IOR('S', 5, unsigned int)
 #define SSP_INBUFCHUNK _IOR('S', 6, unsigned int)
+#define SSP_INPUT      _IOR('S', 7, unsigned int)
 
 /* Values for SSP_SPEED */
 #define SSP150        0
@@ -37,6 +38,7 @@
 #define SSP921600    13
 #define SSP3125000   14
 #define CODEC        15
+#define CODEC_f32768 16
 
 #define FREQ_4MHz   0
 #define FREQ_2MHz   1
@@ -46,9 +48,14 @@
 #define FREQ_128kHz 5
 #define FREQ_64kHz  6
 #define FREQ_32kHz  7
+/* FREQ_* with values where bit (value & 0x10) is set are */
+/* used for CODEC_f32768 */
+#define FREQ_4096kHz 16 /* CODEC_f32768 */
 
 /* Used by application to set CODEC divider, word rate and frame rate */
-#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) (CODEC | (freq << 8) | (clk_per_sync << 16) | (sync_per_frame << 28))
+#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) \
+        ((CODEC + ((freq & 0x10) >> 4)) | (freq << 8) | \
+                   (clk_per_sync << 16) | (sync_per_frame << 28))
 
 /* Used by driver to extract speed */
 #define GET_SPEED(x) (x & 0xff)
@@ -68,6 +75,7 @@
 #define NORMAL_SYNC                1
 #define EARLY_SYNC                 2
 #define SECOND_WORD_SYNC     0x40000
+#define LATE_SYNC            0x80000
 
 #define BIT_SYNC                   4
 #define WORD_SYNC                  8
@@ -104,4 +112,21 @@
 /* Values for SSP_INBUFCHUNK */
 /* plain integer with the size of DMA chunks */
 
+/* To ensure that the timestamps are aligned with the data being read
+ * the read length MUST be a multiple of the length of the DMA buffers.
+ *
+ * Use a multiple of SSP_INPUT_CHUNK_SIZE defined below.
+ */
+#define SSP_INPUT_CHUNK_SIZE  256
+
+/* Request struct to pass through the ioctl interface to read
+ * data with timestamps.
+ */
+struct ssp_request {
+        char __user *buf;       /* Where to put the data. */
+        size_t len;             /* Size of buf. MUST be a multiple of */
+                                /* SSP_INPUT_CHUNK_SIZE! */
+        struct timespec ts;     /* The time the data was sampled. */
+};
+
 #endif
diff --git a/arch/cris/include/asm/termbits.h b/arch/cris/include/asm/termbits.h
index 66e1a7492a0c..1c43bc874ccf 100644
--- a/arch/cris/include/asm/termbits.h
+++ b/arch/cris/include/asm/termbits.h
@@ -214,6 +214,7 @@ struct ktermios {
 #define FLUSHO  0010000
 #define PENDIN  0040000
 #define IEXTEN  0100000
+#define EXTPROC 0200000
 
 /* tcflow() and TCXONC use these */
 #define TCOOFF          0