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Diffstat (limited to 'arch/cris/arch-v32/kernel/time.c')
-rw-r--r-- | arch/cris/arch-v32/kernel/time.c | 341 |
1 files changed, 341 insertions, 0 deletions
diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c new file mode 100644 index 000000000000..d48e397f5fa4 --- /dev/null +++ b/arch/cris/arch-v32/kernel/time.c | |||
@@ -0,0 +1,341 @@ | |||
1 | /* $Id: time.c,v 1.19 2005/04/29 05:40:09 starvik Exp $ | ||
2 | * | ||
3 | * linux/arch/cris/arch-v32/kernel/time.c | ||
4 | * | ||
5 | * Copyright (C) 2003 Axis Communications AB | ||
6 | * | ||
7 | */ | ||
8 | |||
9 | #include <linux/config.h> | ||
10 | #include <linux/timex.h> | ||
11 | #include <linux/time.h> | ||
12 | #include <linux/jiffies.h> | ||
13 | #include <linux/interrupt.h> | ||
14 | #include <linux/swap.h> | ||
15 | #include <linux/sched.h> | ||
16 | #include <linux/init.h> | ||
17 | #include <linux/threads.h> | ||
18 | #include <asm/types.h> | ||
19 | #include <asm/signal.h> | ||
20 | #include <asm/io.h> | ||
21 | #include <asm/delay.h> | ||
22 | #include <asm/rtc.h> | ||
23 | #include <asm/irq.h> | ||
24 | |||
25 | #include <asm/arch/hwregs/reg_map.h> | ||
26 | #include <asm/arch/hwregs/reg_rdwr.h> | ||
27 | #include <asm/arch/hwregs/timer_defs.h> | ||
28 | #include <asm/arch/hwregs/intr_vect_defs.h> | ||
29 | |||
30 | /* Watchdog defines */ | ||
31 | #define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */ | ||
32 | #define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */ | ||
33 | #define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1) /* Number of 763 counts before watchdog bites */ | ||
34 | |||
35 | unsigned long timer_regs[NR_CPUS] = | ||
36 | { | ||
37 | regi_timer, | ||
38 | #ifdef CONFIG_SMP | ||
39 | regi_timer2 | ||
40 | #endif | ||
41 | }; | ||
42 | |||
43 | extern void update_xtime_from_cmos(void); | ||
44 | extern int set_rtc_mmss(unsigned long nowtime); | ||
45 | extern int setup_irq(int, struct irqaction *); | ||
46 | extern int have_rtc; | ||
47 | |||
48 | unsigned long get_ns_in_jiffie(void) | ||
49 | { | ||
50 | reg_timer_r_tmr0_data data; | ||
51 | unsigned long ns; | ||
52 | |||
53 | data = REG_RD(timer, regi_timer, r_tmr0_data); | ||
54 | ns = (TIMER0_DIV - data) * 10; | ||
55 | return ns; | ||
56 | } | ||
57 | |||
58 | unsigned long do_slow_gettimeoffset(void) | ||
59 | { | ||
60 | unsigned long count; | ||
61 | unsigned long usec_count = 0; | ||
62 | |||
63 | static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */ | ||
64 | static unsigned long jiffies_p = 0; | ||
65 | |||
66 | /* | ||
67 | * cache volatile jiffies temporarily; we have IRQs turned off. | ||
68 | */ | ||
69 | unsigned long jiffies_t; | ||
70 | |||
71 | /* The timer interrupt comes from Etrax timer 0. In order to get | ||
72 | * better precision, we check the current value. It might have | ||
73 | * underflowed already though. | ||
74 | */ | ||
75 | |||
76 | count = REG_RD(timer, regi_timer, r_tmr0_data); | ||
77 | jiffies_t = jiffies; | ||
78 | |||
79 | /* | ||
80 | * avoiding timer inconsistencies (they are rare, but they happen)... | ||
81 | * there are one problem that must be avoided here: | ||
82 | * 1. the timer counter underflows | ||
83 | */ | ||
84 | if( jiffies_t == jiffies_p ) { | ||
85 | if( count > count_p ) { | ||
86 | /* Timer wrapped, use new count and prescale | ||
87 | * increase the time corresponding to one jiffie | ||
88 | */ | ||
89 | usec_count = 1000000/HZ; | ||
90 | } | ||
91 | } else | ||
92 | jiffies_p = jiffies_t; | ||
93 | count_p = count; | ||
94 | /* Convert timer value to usec */ | ||
95 | /* 100 MHz timer, divide by 100 to get usec */ | ||
96 | usec_count += (TIMER0_DIV - count) / 100; | ||
97 | return usec_count; | ||
98 | } | ||
99 | |||
100 | /* From timer MDS describing the hardware watchdog: | ||
101 | * 4.3.1 Watchdog Operation | ||
102 | * The watchdog timer is an 8-bit timer with a configurable start value. | ||
103 | * Once started the whatchdog counts downwards with a frequency of 763 Hz | ||
104 | * (100/131072 MHz). When the watchdog counts down to 1, it generates an | ||
105 | * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the | ||
106 | * chip. | ||
107 | */ | ||
108 | /* This gives us 1.3 ms to do something useful when the NMI comes */ | ||
109 | |||
110 | /* right now, starting the watchdog is the same as resetting it */ | ||
111 | #define start_watchdog reset_watchdog | ||
112 | |||
113 | #if defined(CONFIG_ETRAX_WATCHDOG) | ||
114 | static short int watchdog_key = 42; /* arbitrary 7 bit number */ | ||
115 | #endif | ||
116 | |||
117 | /* number of pages to consider "out of memory". it is normal that the memory | ||
118 | * is used though, so put this really low. | ||
119 | */ | ||
120 | |||
121 | #define WATCHDOG_MIN_FREE_PAGES 8 | ||
122 | |||
123 | void | ||
124 | reset_watchdog(void) | ||
125 | { | ||
126 | #if defined(CONFIG_ETRAX_WATCHDOG) | ||
127 | reg_timer_rw_wd_ctrl wd_ctrl = { 0 }; | ||
128 | |||
129 | /* only keep watchdog happy as long as we have memory left! */ | ||
130 | if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) { | ||
131 | /* reset the watchdog with the inverse of the old key */ | ||
132 | watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */ | ||
133 | wd_ctrl.cnt = ETRAX_WD_CNT; | ||
134 | wd_ctrl.cmd = regk_timer_start; | ||
135 | wd_ctrl.key = watchdog_key; | ||
136 | REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl); | ||
137 | } | ||
138 | #endif | ||
139 | } | ||
140 | |||
141 | /* stop the watchdog - we still need the correct key */ | ||
142 | |||
143 | void | ||
144 | stop_watchdog(void) | ||
145 | { | ||
146 | #if defined(CONFIG_ETRAX_WATCHDOG) | ||
147 | reg_timer_rw_wd_ctrl wd_ctrl = { 0 }; | ||
148 | watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */ | ||
149 | wd_ctrl.cnt = ETRAX_WD_CNT; | ||
150 | wd_ctrl.cmd = regk_timer_stop; | ||
151 | wd_ctrl.key = watchdog_key; | ||
152 | REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl); | ||
153 | #endif | ||
154 | } | ||
155 | |||
156 | extern void show_registers(struct pt_regs *regs); | ||
157 | |||
158 | void | ||
159 | handle_watchdog_bite(struct pt_regs* regs) | ||
160 | { | ||
161 | #if defined(CONFIG_ETRAX_WATCHDOG) | ||
162 | extern int cause_of_death; | ||
163 | |||
164 | raw_printk("Watchdog bite\n"); | ||
165 | |||
166 | /* Check if forced restart or unexpected watchdog */ | ||
167 | if (cause_of_death == 0xbedead) { | ||
168 | while(1); | ||
169 | } | ||
170 | |||
171 | /* Unexpected watchdog, stop the watchdog and dump registers*/ | ||
172 | stop_watchdog(); | ||
173 | raw_printk("Oops: bitten by watchdog\n"); | ||
174 | show_registers(regs); | ||
175 | #ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY | ||
176 | reset_watchdog(); | ||
177 | #endif | ||
178 | while(1) /* nothing */; | ||
179 | #endif | ||
180 | } | ||
181 | |||
182 | /* last time the cmos clock got updated */ | ||
183 | static long last_rtc_update = 0; | ||
184 | |||
185 | /* | ||
186 | * timer_interrupt() needs to keep up the real-time clock, | ||
187 | * as well as call the "do_timer()" routine every clocktick | ||
188 | */ | ||
189 | |||
190 | //static unsigned short myjiff; /* used by our debug routine print_timestamp */ | ||
191 | |||
192 | extern void cris_do_profile(struct pt_regs *regs); | ||
193 | |||
194 | static inline irqreturn_t | ||
195 | timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) | ||
196 | { | ||
197 | int cpu = smp_processor_id(); | ||
198 | reg_timer_r_masked_intr masked_intr; | ||
199 | reg_timer_rw_ack_intr ack_intr = { 0 }; | ||
200 | |||
201 | /* Check if the timer interrupt is for us (a tmr0 int) */ | ||
202 | masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr); | ||
203 | if (!masked_intr.tmr0) | ||
204 | return IRQ_NONE; | ||
205 | |||
206 | /* acknowledge the timer irq */ | ||
207 | ack_intr.tmr0 = 1; | ||
208 | REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr); | ||
209 | |||
210 | /* reset watchdog otherwise it resets us! */ | ||
211 | reset_watchdog(); | ||
212 | |||
213 | /* Update statistics. */ | ||
214 | update_process_times(user_mode(regs)); | ||
215 | |||
216 | cris_do_profile(regs); /* Save profiling information */ | ||
217 | |||
218 | /* The master CPU is responsible for the time keeping. */ | ||
219 | if (cpu != 0) | ||
220 | return IRQ_HANDLED; | ||
221 | |||
222 | /* call the real timer interrupt handler */ | ||
223 | do_timer(regs); | ||
224 | |||
225 | /* | ||
226 | * If we have an externally synchronized Linux clock, then update | ||
227 | * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be | ||
228 | * called as close as possible to 500 ms before the new second starts. | ||
229 | * | ||
230 | * The division here is not time critical since it will run once in | ||
231 | * 11 minutes | ||
232 | */ | ||
233 | if ((time_status & STA_UNSYNC) == 0 && | ||
234 | xtime.tv_sec > last_rtc_update + 660 && | ||
235 | (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 && | ||
236 | (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) { | ||
237 | if (set_rtc_mmss(xtime.tv_sec) == 0) | ||
238 | last_rtc_update = xtime.tv_sec; | ||
239 | else | ||
240 | last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */ | ||
241 | } | ||
242 | return IRQ_HANDLED; | ||
243 | } | ||
244 | |||
245 | /* timer is SA_SHIRQ so drivers can add stuff to the timer irq chain | ||
246 | * it needs to be SA_INTERRUPT to make the jiffies update work properly | ||
247 | */ | ||
248 | |||
249 | static struct irqaction irq_timer = { timer_interrupt, SA_SHIRQ | SA_INTERRUPT, | ||
250 | CPU_MASK_NONE, "timer", NULL, NULL}; | ||
251 | |||
252 | void __init | ||
253 | cris_timer_init(void) | ||
254 | { | ||
255 | int cpu = smp_processor_id(); | ||
256 | reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 }; | ||
257 | reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV; | ||
258 | reg_timer_rw_intr_mask timer_intr_mask; | ||
259 | |||
260 | /* Setup the etrax timers | ||
261 | * Base frequency is 100MHz, divider 1000000 -> 100 HZ | ||
262 | * We use timer0, so timer1 is free. | ||
263 | * The trig timer is used by the fasttimer API if enabled. | ||
264 | */ | ||
265 | |||
266 | tmr0_ctrl.op = regk_timer_ld; | ||
267 | tmr0_ctrl.freq = regk_timer_f100; | ||
268 | REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div); | ||
269 | REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */ | ||
270 | tmr0_ctrl.op = regk_timer_run; | ||
271 | REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */ | ||
272 | |||
273 | /* enable the timer irq */ | ||
274 | timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask); | ||
275 | timer_intr_mask.tmr0 = 1; | ||
276 | REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask); | ||
277 | } | ||
278 | |||
279 | void __init | ||
280 | time_init(void) | ||
281 | { | ||
282 | reg_intr_vect_rw_mask intr_mask; | ||
283 | |||
284 | /* probe for the RTC and read it if it exists | ||
285 | * Before the RTC can be probed the loops_per_usec variable needs | ||
286 | * to be initialized to make usleep work. A better value for | ||
287 | * loops_per_usec is calculated by the kernel later once the | ||
288 | * clock has started. | ||
289 | */ | ||
290 | loops_per_usec = 50; | ||
291 | |||
292 | if(RTC_INIT() < 0) { | ||
293 | /* no RTC, start at 1980 */ | ||
294 | xtime.tv_sec = 0; | ||
295 | xtime.tv_nsec = 0; | ||
296 | have_rtc = 0; | ||
297 | } else { | ||
298 | /* get the current time */ | ||
299 | have_rtc = 1; | ||
300 | update_xtime_from_cmos(); | ||
301 | } | ||
302 | |||
303 | /* | ||
304 | * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the | ||
305 | * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC). | ||
306 | */ | ||
307 | set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec); | ||
308 | |||
309 | /* Start CPU local timer */ | ||
310 | cris_timer_init(); | ||
311 | |||
312 | /* enable the timer irq in global config */ | ||
313 | intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); | ||
314 | intr_mask.timer = 1; | ||
315 | REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); | ||
316 | |||
317 | /* now actually register the timer irq handler that calls timer_interrupt() */ | ||
318 | |||
319 | setup_irq(TIMER_INTR_VECT, &irq_timer); | ||
320 | |||
321 | /* enable watchdog if we should use one */ | ||
322 | |||
323 | #if defined(CONFIG_ETRAX_WATCHDOG) | ||
324 | printk("Enabling watchdog...\n"); | ||
325 | start_watchdog(); | ||
326 | |||
327 | /* If we use the hardware watchdog, we want to trap it as an NMI | ||
328 | and dump registers before it resets us. For this to happen, we | ||
329 | must set the "m" NMI enable flag (which once set, is unset only | ||
330 | when an NMI is taken). | ||
331 | |||
332 | The same goes for the external NMI, but that doesn't have any | ||
333 | driver or infrastructure support yet. */ | ||
334 | { | ||
335 | unsigned long flags; | ||
336 | local_save_flags(flags); | ||
337 | flags |= (1<<30); /* NMI M flag is at bit 30 */ | ||
338 | local_irq_restore(flags); | ||
339 | } | ||
340 | #endif | ||
341 | } | ||