1 files changed, 131 insertions, 0 deletions
diff --git a/arch/cris/arch-v32/drivers/pci/bios.c b/arch/cris/arch-v32/drivers/pci/bios.c
new file mode 100644
index 000000000000..24bc149889b6
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/pci/bios.c
@@ -0,0 +1,131 @@
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <asm/arch/hwregs/intr_vect.h>
+void __devinit  pcibios_fixup_bus(struct pci_bus *b)
+{
+}
+char * __devinit  pcibios_setup(char *str)
+{
+        return NULL;
+}
+void pcibios_set_master(struct pci_dev *dev)
+{
+        u8 lat;
+        pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
+        printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
+        pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
+}
+int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+                        enum pci_mmap_state mmap_state, int write_combine)
+{
+        unsigned long prot;
+        /* Leave vm_pgoff as-is, the PCI space address is the physical
+         * address on this platform.
+         */
+        vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO);
+        prot = pgprot_val(vma->vm_page_prot);
+        vma->vm_page_prot = __pgprot(prot);
+        /* Write-combine setting is ignored, it is changed via the mtrr
+         * interfaces on this platform.
+         */
+        if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+                             vma->vm_end - vma->vm_start,
+                             vma->vm_page_prot))
+                return -EAGAIN;
+        return 0;
+}
+void
+pcibios_align_resource(void *data, struct resource *res,
+                       unsigned long size, unsigned long align)
+{
+        if (res->flags & IORESOURCE_IO) {
+                unsigned long start = res->start;
+                if (start & 0x300) {
+                        start = (start + 0x3ff) & ~0x3ff;
+                        res->start = start;
+                }
+        }
+}
+int pcibios_enable_resources(struct pci_dev *dev, int mask)
+{
+        u16 cmd, old_cmd;
+        int idx;
+        struct resource *r;
+        pci_read_config_word(dev, PCI_COMMAND, &cmd);
+        old_cmd = cmd;
+        for(idx=0; idx<6; idx++) {
+                /* Only set up the requested stuff */
+                if (!(mask & (1<<idx)))
+                        continue;
+                r = &dev->resource[idx];
+                if (!r->start && r->end) {
+                        printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
+                        return -EINVAL;
+                }
+                if (r->flags & IORESOURCE_IO)
+                        cmd |= PCI_COMMAND_IO;
+                if (r->flags & IORESOURCE_MEM)
+                        cmd |= PCI_COMMAND_MEMORY;
+        }
+        if (dev->resource[PCI_ROM_RESOURCE].start)
+                cmd |= PCI_COMMAND_MEMORY;
+        if (cmd != old_cmd) {
+                printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
+                pci_write_config_word(dev, PCI_COMMAND, cmd);
+        }
+        return 0;
+}
+int pcibios_enable_irq(struct pci_dev *dev)
+{
+        dev->irq = EXT_INTR_VECT;
+        return 0;
+}
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+        int err;
+        if ((err = pcibios_enable_resources(dev, mask)) < 0)
+                return err;
+        return pcibios_enable_irq(dev);
+}
+int pcibios_assign_resources(void)
+{
+        struct pci_dev *dev = NULL;
+        int idx;
+        struct resource *r;
+        while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
+                int class = dev->class >> 8;
+                /* Don't touch classless devices and host bridges */
+                if (!class || class == PCI_CLASS_BRIDGE_HOST)
+                        continue;
+                for(idx=0; idx<6; idx++) {
+                        r = &dev->resource[idx];
+                        if (!r->start && r->end)
+                                pci_assign_resource(dev, idx);
+                }
+        }
+        return 0;
+}
+EXPORT_SYMBOL(pcibios_assign_resources);

diff --git a/arch/cris/arch-v32/drivers/pci/bios.c b/arch/cris/arch-v32/drivers/pci/bios.c new file mode 100644 index 000000000000..24bc149889b6 --- /dev/null +++ b/arch/cris/arch-v32/drivers/pci/bios.c
@@ -0,0 +1,131 @@
	1	#include <linux/pci.h>
	2	#include <linux/kernel.h>
	3	#include <asm/arch/hwregs/intr_vect.h>
	4
	5	void __devinit pcibios_fixup_bus(struct pci_bus *b)
	6	{
	7	}
	8
	9	char * __devinit pcibios_setup(char *str)
	10	{
	11	return NULL;
	12	}
	13
	14	void pcibios_set_master(struct pci_dev *dev)
	15	{
	16	u8 lat;
	17	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	18	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
	19	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
	20	}
	21
	22	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	23	enum pci_mmap_state mmap_state, int write_combine)
	24	{
	25	unsigned long prot;
	26
	27	/* Leave vm_pgoff as-is, the PCI space address is the physical
	28	* address on this platform.
	29	*/
	30	vma->vm_flags \|= (VM_SHM \| VM_LOCKED \| VM_IO);
	31
	32	prot = pgprot_val(vma->vm_page_prot);
	33	vma->vm_page_prot = __pgprot(prot);
	34
	35	/* Write-combine setting is ignored, it is changed via the mtrr
	36	* interfaces on this platform.
	37	*/
	38	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
	39	vma->vm_end - vma->vm_start,
	40	vma->vm_page_prot))
	41	return -EAGAIN;
	42
	43	return 0;
	44	}
	45
	46	void
	47	pcibios_align_resource(void data, struct resource res,
	48	unsigned long size, unsigned long align)
	49	{
	50	if (res->flags & IORESOURCE_IO) {
	51	unsigned long start = res->start;
	52
	53	if (start & 0x300) {
	54	start = (start + 0x3ff) & ~0x3ff;
	55	res->start = start;
	56	}
	57	}
	58	}
	59
	60	int pcibios_enable_resources(struct pci_dev *dev, int mask)
	61	{
	62	u16 cmd, old_cmd;
	63	int idx;
	64	struct resource *r;
	65
	66	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	67	old_cmd = cmd;
	68	for(idx=0; idx<6; idx++) {
	69	/* Only set up the requested stuff */
	70	if (!(mask & (1<<idx)))
	71	continue;
	72
	73	r = &dev->resource[idx];
	74	if (!r->start && r->end) {
	75	printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
	76	return -EINVAL;
	77	}
	78	if (r->flags & IORESOURCE_IO)
	79	cmd \|= PCI_COMMAND_IO;
	80	if (r->flags & IORESOURCE_MEM)
	81	cmd \|= PCI_COMMAND_MEMORY;
	82	}
	83	if (dev->resource[PCI_ROM_RESOURCE].start)
	84	cmd \|= PCI_COMMAND_MEMORY;
	85	if (cmd != old_cmd) {
	86	printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
	87	pci_write_config_word(dev, PCI_COMMAND, cmd);
	88	}
	89	return 0;
	90	}
	91
	92	int pcibios_enable_irq(struct pci_dev *dev)
	93	{
	94	dev->irq = EXT_INTR_VECT;
	95	return 0;
	96	}
	97
	98	int pcibios_enable_device(struct pci_dev *dev, int mask)
	99	{
	100	int err;
	101
	102	if ((err = pcibios_enable_resources(dev, mask)) < 0)
	103	return err;
	104
	105	return pcibios_enable_irq(dev);
	106	}
	107
	108	int pcibios_assign_resources(void)
	109	{
	110	struct pci_dev *dev = NULL;
	111	int idx;
	112	struct resource *r;
	113
	114	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
	115	int class = dev->class >> 8;
	116
	117	/* Don't touch classless devices and host bridges */
	118	if (!class \|\| class == PCI_CLASS_BRIDGE_HOST)
	119	continue;
	120
	121	for(idx=0; idx<6; idx++) {
	122	r = &dev->resource[idx];
	123
	124	if (!r->start && r->end)
	125	pci_assign_resource(dev, idx);
	126	}
	127	}
	128	return 0;
	129	}
	130
	131	EXPORT_SYMBOL(pcibios_assign_resources);