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-rw-r--r--arch/cris/arch-v10/drivers/Kconfig181
-rw-r--r--arch/cris/arch-v10/drivers/Makefile12
-rw-r--r--arch/cris/arch-v10/drivers/axisflashmap.c181
-rw-r--r--arch/cris/arch-v10/drivers/ds1302.c4
-rw-r--r--arch/cris/arch-v10/drivers/eeprom.c75
-rw-r--r--arch/cris/arch-v10/drivers/gpio.c634
-rw-r--r--arch/cris/arch-v10/drivers/i2c.c81
-rw-r--r--arch/cris/arch-v10/drivers/pcf8563.c393
-rw-r--r--arch/cris/arch-v10/drivers/sync_serial.c1441
9 files changed, 1961 insertions, 1041 deletions
diff --git a/arch/cris/arch-v10/drivers/Kconfig b/arch/cris/arch-v10/drivers/Kconfig
index 96740ef497d4..58f5864a6680 100644
--- a/arch/cris/arch-v10/drivers/Kconfig
+++ b/arch/cris/arch-v10/drivers/Kconfig
@@ -9,37 +9,6 @@ config ETRAX_ETHERNET
9 This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet 9 This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet
10 controller. 10 controller.
11 11
12choice
13 prompt "Network LED behavior"
14 depends on ETRAX_ETHERNET
15 default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
16
17config ETRAX_NETWORK_LED_ON_WHEN_LINK
18 bool "LED_on_when_link"
19 help
20 Selecting LED_on_when_link will light the LED when there is a
21 connection and will flash off when there is activity.
22
23 Selecting LED_on_when_activity will light the LED only when
24 there is activity.
25
26 This setting will also affect the behaviour of other activity LEDs
27 e.g. Bluetooth.
28
29config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
30 bool "LED_on_when_activity"
31 help
32 Selecting LED_on_when_link will light the LED when there is a
33 connection and will flash off when there is activity.
34
35 Selecting LED_on_when_activity will light the LED only when
36 there is activity.
37
38 This setting will also affect the behaviour of other activity LEDs
39 e.g. Bluetooth.
40
41endchoice
42
43config ETRAX_SERIAL 12config ETRAX_SERIAL
44 bool "Serial-port support" 13 bool "Serial-port support"
45 depends on ETRAX_ARCH_V10 14 depends on ETRAX_ARCH_V10
@@ -84,32 +53,6 @@ config ETRAX_SERIAL_PORT0
84 the same DMA channels. 53 the same DMA channels.
85 54
86choice 55choice
87 prompt "Ser0 DMA out assignment"
88 depends on ETRAX_SERIAL_PORT0
89 default ETRAX_SERIAL_PORT0_DMA6_OUT
90
91config ETRAX_SERIAL_PORT0_NO_DMA_OUT
92 bool "No DMA out"
93
94config ETRAX_SERIAL_PORT0_DMA6_OUT
95 bool "DMA 6"
96
97endchoice
98
99choice
100 prompt "Ser0 DMA in assignment"
101 depends on ETRAX_SERIAL_PORT0
102 default ETRAX_SERIAL_PORT0_DMA7_IN
103
104config ETRAX_SERIAL_PORT0_NO_DMA_IN
105 bool "No DMA in"
106
107config ETRAX_SERIAL_PORT0_DMA7_IN
108 bool "DMA 7"
109
110endchoice
111
112choice
113 prompt "Ser0 DTR, RI, DSR and CD assignment" 56 prompt "Ser0 DTR, RI, DSR and CD assignment"
114 depends on ETRAX_SERIAL_PORT0 57 depends on ETRAX_SERIAL_PORT0
115 default ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE 58 default ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE
@@ -198,32 +141,6 @@ config ETRAX_SERIAL_PORT1
198 Enables the ETRAX 100 serial driver for ser1 (ttyS1). 141 Enables the ETRAX 100 serial driver for ser1 (ttyS1).
199 142
200choice 143choice
201 prompt "Ser1 DMA out assignment"
202 depends on ETRAX_SERIAL_PORT1
203 default ETRAX_SERIAL_PORT1_DMA8_OUT
204
205config ETRAX_SERIAL_PORT1_NO_DMA_OUT
206 bool "No DMA out"
207
208config ETRAX_SERIAL_PORT1_DMA8_OUT
209 bool "DMA 8"
210
211endchoice
212
213choice
214 prompt "Ser1 DMA in assignment"
215 depends on ETRAX_SERIAL_PORT1
216 default ETRAX_SERIAL_PORT1_DMA9_IN
217
218config ETRAX_SERIAL_PORT1_NO_DMA_IN
219 bool "No DMA in"
220
221config ETRAX_SERIAL_PORT1_DMA9_IN
222 bool "DMA 9"
223
224endchoice
225
226choice
227 prompt "Ser1 DTR, RI, DSR and CD assignment" 144 prompt "Ser1 DTR, RI, DSR and CD assignment"
228 depends on ETRAX_SERIAL_PORT1 145 depends on ETRAX_SERIAL_PORT1
229 default ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE 146 default ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE
@@ -315,32 +232,6 @@ config ETRAX_SERIAL_PORT2
315 Enables the ETRAX 100 serial driver for ser2 (ttyS2). 232 Enables the ETRAX 100 serial driver for ser2 (ttyS2).
316 233
317choice 234choice
318 prompt "Ser2 DMA out assignment"
319 depends on ETRAX_SERIAL_PORT2
320 default ETRAX_SERIAL_PORT2_DMA2_OUT
321
322config ETRAX_SERIAL_PORT2_NO_DMA_OUT
323 bool "No DMA out"
324
325config ETRAX_SERIAL_PORT2_DMA2_OUT
326 bool "DMA 2"
327
328endchoice
329
330choice
331 prompt "Ser2 DMA in assignment"
332 depends on ETRAX_SERIAL_PORT2
333 default ETRAX_SERIAL_PORT2_DMA3_IN
334
335config ETRAX_SERIAL_PORT2_NO_DMA_IN
336 bool "No DMA in"
337
338config ETRAX_SERIAL_PORT2_DMA3_IN
339 bool "DMA 3"
340
341endchoice
342
343choice
344 prompt "Ser2 DTR, RI, DSR and CD assignment" 235 prompt "Ser2 DTR, RI, DSR and CD assignment"
345 depends on ETRAX_SERIAL_PORT2 236 depends on ETRAX_SERIAL_PORT2
346 default ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE 237 default ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE
@@ -429,32 +320,6 @@ config ETRAX_SERIAL_PORT3
429 Enables the ETRAX 100 serial driver for ser3 (ttyS3). 320 Enables the ETRAX 100 serial driver for ser3 (ttyS3).
430 321
431choice 322choice
432 prompt "Ser3 DMA out assignment"
433 depends on ETRAX_SERIAL_PORT3
434 default ETRAX_SERIAL_PORT3_DMA4_OUT
435
436config ETRAX_SERIAL_PORT3_NO_DMA_OUT
437 bool "No DMA out"
438
439config ETRAX_SERIAL_PORT3_DMA4_OUT
440 bool "DMA 4"
441
442endchoice
443
444choice
445 prompt "Ser3 DMA in assignment"
446 depends on ETRAX_SERIAL_PORT3
447 default ETRAX_SERIAL_PORT3_DMA5_IN
448
449config ETRAX_SERIAL_PORT3_NO_DMA_IN
450 bool "No DMA in"
451
452config ETRAX_SERIAL_PORT3_DMA5_IN
453 bool "DMA 5"
454
455endchoice
456
457choice
458 prompt "Ser3 DTR, RI, DSR and CD assignment" 323 prompt "Ser3 DTR, RI, DSR and CD assignment"
459 depends on ETRAX_SERIAL_PORT3 324 depends on ETRAX_SERIAL_PORT3
460 default ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE 325 default ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE
@@ -563,21 +428,6 @@ config ETRAX_USB_HOST_PORT2
563 depends on ETRAX_USB_HOST 428 depends on ETRAX_USB_HOST
564 default n 429 default n
565 430
566config ETRAX_AXISFLASHMAP
567 bool "Axis flash-map support"
568 depends on ETRAX_ARCH_V10
569 select MTD
570 select MTD_CFI
571 select MTD_CFI_AMDSTD
572 select MTD_CHAR
573 select MTD_BLOCK
574 select MTD_PARTITIONS
575 select MTD_CONCAT
576 select MTD_COMPLEX_MAPPINGS
577 help
578 This option enables MTD mapping of flash devices. Needed to use
579 flash memories. If unsure, say Y.
580
581config ETRAX_PTABLE_SECTOR 431config ETRAX_PTABLE_SECTOR
582 int "Byte-offset of partition table sector" 432 int "Byte-offset of partition table sector"
583 depends on ETRAX_AXISFLASHMAP 433 depends on ETRAX_AXISFLASHMAP
@@ -731,37 +581,6 @@ config ETRAX_PB_CHANGEABLE_BITS
731 Bit set = changeable. 581 Bit set = changeable.
732 You probably want 00 here. 582 You probably want 00 here.
733 583
734config ETRAX_RTC
735 bool "Real Time Clock support"
736 depends on ETRAX_ARCH_V10
737 help
738 Enables drivers for the Real-Time Clock battery-backed chips on
739 some products. The kernel reads the time when booting, and
740 the date can be set using ioctl(fd, RTC_SET_TIME, &rt) with rt a
741 rtc_time struct (see <file:include/asm-cris/rtc.h>) on the /dev/rtc
742 device, major 121. You can check the time with cat /proc/rtc, but
743 normal time reading should be done using libc function time and
744 friends.
745
746choice
747 prompt "RTC chip"
748 depends on ETRAX_RTC
749 default ETRAX_DS1302
750
751config ETRAX_DS1302
752 bool "DS1302"
753 help
754 Enables the driver for the DS1302 Real-Time Clock battery-backed
755 chip on some products.
756
757config ETRAX_PCF8563
758 bool "PCF8563"
759 help
760 Enables the driver for the PCF8563 Real-Time Clock battery-backed
761 chip on some products.
762
763endchoice
764
765config ETRAX_DS1302_RST_ON_GENERIC_PORT 584config ETRAX_DS1302_RST_ON_GENERIC_PORT
766 bool "DS1302 RST on Generic Port" 585 bool "DS1302 RST on Generic Port"
767 depends on ETRAX_DS1302 586 depends on ETRAX_DS1302
diff --git a/arch/cris/arch-v10/drivers/Makefile b/arch/cris/arch-v10/drivers/Makefile
index 20258e36f384..44bf2e88c26e 100644
--- a/arch/cris/arch-v10/drivers/Makefile
+++ b/arch/cris/arch-v10/drivers/Makefile
@@ -2,11 +2,11 @@
2# Makefile for Etrax-specific drivers 2# Makefile for Etrax-specific drivers
3# 3#
4 4
5obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o 5obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o
6obj-$(CONFIG_ETRAX_I2C) += i2c.o 6obj-$(CONFIG_ETRAX_I2C) += i2c.o
7obj-$(CONFIG_ETRAX_I2C_EEPROM) += eeprom.o 7obj-$(CONFIG_ETRAX_I2C_EEPROM) += eeprom.o
8obj-$(CONFIG_ETRAX_GPIO) += gpio.o 8obj-$(CONFIG_ETRAX_GPIO) += gpio.o
9obj-$(CONFIG_ETRAX_DS1302) += ds1302.o 9obj-$(CONFIG_ETRAX_DS1302) += ds1302.o
10obj-$(CONFIG_ETRAX_PCF8563) += pcf8563.o 10obj-$(CONFIG_ETRAX_PCF8563) += pcf8563.o
11 11obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o
12 12
diff --git a/arch/cris/arch-v10/drivers/axisflashmap.c b/arch/cris/arch-v10/drivers/axisflashmap.c
index ea3cf2e39a14..b3bdda93ffef 100644
--- a/arch/cris/arch-v10/drivers/axisflashmap.c
+++ b/arch/cris/arch-v10/drivers/axisflashmap.c
@@ -10,129 +10,6 @@
10 * tells us what other partitions to define. If there isn't, we use a default 10 * tells us what other partitions to define. If there isn't, we use a default
11 * partition split defined below. 11 * partition split defined below.
12 * 12 *
13 * $Log: axisflashmap.c,v $
14 * Revision 1.11 2004/11/15 10:27:14 starvik
15 * Corrected typo (Thanks to Milton Miller <miltonm@bga.com>).
16 *
17 * Revision 1.10 2004/08/16 12:37:22 starvik
18 * Merge of Linux 2.6.8
19 *
20 * Revision 1.8 2004/05/14 07:58:03 starvik
21 * Merge of changes from 2.4
22 *
23 * Revision 1.6 2003/07/04 08:27:37 starvik
24 * Merge of Linux 2.5.74
25 *
26 * Revision 1.5 2002/12/11 13:13:57 starvik
27 * Added arch/ to v10 specific includes
28 * Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
29 *
30 * Revision 1.4 2002/11/20 11:56:10 starvik
31 * Merge of Linux 2.5.48
32 *
33 * Revision 1.3 2002/11/13 14:54:13 starvik
34 * Copied from linux 2.4
35 *
36 * Revision 1.28 2002/10/01 08:08:43 jonashg
37 * The first partition ends at the start of the partition table.
38 *
39 * Revision 1.27 2002/08/21 09:23:13 jonashg
40 * Speling.
41 *
42 * Revision 1.26 2002/08/21 08:35:20 jonashg
43 * Cosmetic change to printouts.
44 *
45 * Revision 1.25 2002/08/21 08:15:42 jonashg
46 * Made it compile even without CONFIG_MTD_CONCAT defined.
47 *
48 * Revision 1.24 2002/08/20 13:12:35 jonashg
49 * * New approach to probing. Probe cse0 and cse1 separately and (mtd)concat
50 * the results.
51 * * Removed compile time tests concerning how the mtdram driver has been
52 * configured. The user will know about the misconfiguration at runtime
53 * instead. (The old approach made it impossible to use mtdram for anything
54 * else than RAM boot).
55 *
56 * Revision 1.23 2002/05/13 12:12:28 johana
57 * Allow compile without CONFIG_MTD_MTDRAM but warn at compiletime and
58 * be informative at runtime.
59 *
60 * Revision 1.22 2002/05/13 10:24:44 johana
61 * Added #if checks on MTDRAM CONFIG
62 *
63 * Revision 1.21 2002/05/06 16:05:20 johana
64 * Removed debug printout.
65 *
66 * Revision 1.20 2002/05/06 16:03:00 johana
67 * No more cramfs as root hack in generic code.
68 * It's handled by axisflashmap using mtdram.
69 *
70 * Revision 1.19 2002/03/15 17:10:28 bjornw
71 * Changed comment about cached access since we changed this before
72 *
73 * Revision 1.18 2002/03/05 17:06:15 jonashg
74 * Try amd_flash probe before cfi_probe since amd_flash driver can handle two
75 * (or more) flash chips of different model and the cfi driver cannot.
76 *
77 * Revision 1.17 2001/11/12 19:42:38 pkj
78 * Fixed compiler warnings.
79 *
80 * Revision 1.16 2001/11/08 11:18:58 jonashg
81 * Always read from uncached address to avoid problems with flushing
82 * cachelines after write and MTD-erase. No performance loss have been
83 * seen yet.
84 *
85 * Revision 1.15 2001/10/19 12:41:04 jonashg
86 * Name of probe has changed in MTD.
87 *
88 * Revision 1.14 2001/09/21 07:14:10 jonashg
89 * Made root filesystem (cramfs) use mtdblock driver when booting from flash.
90 *
91 * Revision 1.13 2001/08/15 13:57:35 jonashg
92 * Entire MTD updated to the linux 2.4.7 version.
93 *
94 * Revision 1.12 2001/06/11 09:50:30 jonashg
95 * Oops, 2MB is 0x200000 bytes.
96 *
97 * Revision 1.11 2001/06/08 11:39:44 jonashg
98 * Changed sizes and offsets in axis_default_partitions to use
99 * CONFIG_ETRAX_PTABLE_SECTOR.
100 *
101 * Revision 1.10 2001/05/29 09:42:03 jonashg
102 * Use macro for end marker length instead of sizeof.
103 *
104 * Revision 1.9 2001/05/29 08:52:52 jonashg
105 * Gave names to the magic fours (size of the ptable end marker).
106 *
107 * Revision 1.8 2001/05/28 15:36:20 jonashg
108 * * Removed old comment about ptable location in flash (it's a CONFIG_ option).
109 * * Variable ptable was initialized twice to the same value.
110 *
111 * Revision 1.7 2001/04/05 13:41:46 markusl
112 * Updated according to review remarks
113 *
114 * Revision 1.6 2001/03/07 09:21:21 bjornw
115 * No need to waste .data
116 *
117 * Revision 1.5 2001/03/06 16:27:01 jonashg
118 * Probe the entire flash area for flash devices.
119 *
120 * Revision 1.4 2001/02/23 12:47:15 bjornw
121 * Uncached flash in LOW_MAP moved from 0xe to 0x8
122 *
123 * Revision 1.3 2001/02/16 12:11:45 jonashg
124 * MTD driver amd_flash is now included in MTD CVS repository.
125 * (It's now in drivers/mtd).
126 *
127 * Revision 1.2 2001/02/09 11:12:22 jonashg
128 * Support for AMD compatible non-CFI flash chips.
129 * Only tested with Toshiba TC58FVT160 so far.
130 *
131 * Revision 1.1 2001/01/12 17:01:18 bjornw
132 * * Added axisflashmap.c, a physical mapping for MTD that reads and understands
133 * Axis partition-table format.
134 *
135 *
136 */ 13 */
137 14
138#include <linux/module.h> 15#include <linux/module.h>
@@ -235,7 +112,7 @@ static struct map_info map_cse1 = {
235}; 112};
236 113
237/* If no partition-table was found, we use this default-set. */ 114/* If no partition-table was found, we use this default-set. */
238#define MAX_PARTITIONS 7 115#define MAX_PARTITIONS 7
239#define NUM_DEFAULT_PARTITIONS 3 116#define NUM_DEFAULT_PARTITIONS 3
240 117
241/* 118/*
@@ -300,6 +177,15 @@ static struct mtd_partition axis_partitions[MAX_PARTITIONS] = {
300 }, 177 },
301}; 178};
302 179
180#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
181/* Main flash device */
182static struct mtd_partition main_partition = {
183 .name = "main",
184 .size = 0,
185 .offset = 0
186};
187#endif
188
303/* 189/*
304 * Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash 190 * Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash
305 * chips in that order (because the amd_flash-driver is faster). 191 * chips in that order (because the amd_flash-driver is faster).
@@ -316,15 +202,14 @@ static struct mtd_info *probe_cs(struct map_info *map_cs)
316 mtd_cs = do_map_probe("cfi_probe", map_cs); 202 mtd_cs = do_map_probe("cfi_probe", map_cs);
317#endif 203#endif
318#ifdef CONFIG_MTD_JEDECPROBE 204#ifdef CONFIG_MTD_JEDECPROBE
319 if (!mtd_cs) { 205 if (!mtd_cs)
320 mtd_cs = do_map_probe("jedec_probe", map_cs); 206 mtd_cs = do_map_probe("jedec_probe", map_cs);
321 }
322#endif 207#endif
323 208
324 return mtd_cs; 209 return mtd_cs;
325} 210}
326 211
327/* 212/*
328 * Probe each chip select individually for flash chips. If there are chips on 213 * Probe each chip select individually for flash chips. If there are chips on
329 * both cse0 and cse1, the mtd_info structs will be concatenated to one struct 214 * both cse0 and cse1, the mtd_info structs will be concatenated to one struct
330 * so that MTD partitions can cross chip boundries. 215 * so that MTD partitions can cross chip boundries.
@@ -351,7 +236,7 @@ static struct mtd_info *flash_probe(void)
351 if (mtd_cse0 && mtd_cse1) { 236 if (mtd_cse0 && mtd_cse1) {
352#ifdef CONFIG_MTD_CONCAT 237#ifdef CONFIG_MTD_CONCAT
353 struct mtd_info *mtds[] = { mtd_cse0, mtd_cse1 }; 238 struct mtd_info *mtds[] = { mtd_cse0, mtd_cse1 };
354 239
355 /* Since the concatenation layer adds a small overhead we 240 /* Since the concatenation layer adds a small overhead we
356 * could try to figure out if the chips in cse0 and cse1 are 241 * could try to figure out if the chips in cse0 and cse1 are
357 * identical and reprobe the whole cse0+cse1 window. But since 242 * identical and reprobe the whole cse0+cse1 window. But since
@@ -372,7 +257,7 @@ static struct mtd_info *flash_probe(void)
372 257
373 /* The best we can do now is to only use what we found 258 /* The best we can do now is to only use what we found
374 * at cse0. 259 * at cse0.
375 */ 260 */
376 mtd_cse = mtd_cse0; 261 mtd_cse = mtd_cse0;
377 map_destroy(mtd_cse1); 262 map_destroy(mtd_cse1);
378 } 263 }
@@ -395,7 +280,7 @@ static int __init init_axis_flash(void)
395 struct partitiontable_head *ptable_head = NULL; 280 struct partitiontable_head *ptable_head = NULL;
396 struct partitiontable_entry *ptable; 281 struct partitiontable_entry *ptable;
397 int use_default_ptable = 1; /* Until proven otherwise. */ 282 int use_default_ptable = 1; /* Until proven otherwise. */
398 const char *pmsg = " /dev/flash%d at 0x%08x, size 0x%08x\n"; 283 const char pmsg[] = " /dev/flash%d at 0x%08x, size 0x%08x\n";
399 284
400 if (!(mymtd = flash_probe())) { 285 if (!(mymtd = flash_probe())) {
401 /* There's no reason to use this module if no flash chip can 286 /* There's no reason to use this module if no flash chip can
@@ -435,7 +320,7 @@ static int __init init_axis_flash(void)
435 unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR; 320 unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR;
436 unsigned char *p; 321 unsigned char *p;
437 unsigned long csum = 0; 322 unsigned long csum = 0;
438 323
439 ptable = (struct partitiontable_entry *) 324 ptable = (struct partitiontable_entry *)
440 ((unsigned long)ptable_head + sizeof(*ptable_head)); 325 ((unsigned long)ptable_head + sizeof(*ptable_head));
441 326
@@ -490,6 +375,16 @@ static int __init init_axis_flash(void)
490 pidx++; 375 pidx++;
491 } 376 }
492 377
378#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
379 if (mymtd) {
380 main_partition.size = mymtd->size;
381 err = add_mtd_partitions(mymtd, &main_partition, 1);
382 if (err)
383 panic("axisflashmap: Could not initialize "
384 "partition for whole main mtd device!\n");
385 }
386#endif
387
493 if (mymtd) { 388 if (mymtd) {
494 if (use_default_ptable) { 389 if (use_default_ptable) {
495 printk(KERN_INFO " Using default partition table.\n"); 390 printk(KERN_INFO " Using default partition table.\n");
@@ -499,9 +394,8 @@ static int __init init_axis_flash(void)
499 err = add_mtd_partitions(mymtd, axis_partitions, pidx); 394 err = add_mtd_partitions(mymtd, axis_partitions, pidx);
500 } 395 }
501 396
502 if (err) { 397 if (err)
503 panic("axisflashmap could not add MTD partitions!\n"); 398 panic("axisflashmap could not add MTD partitions!\n");
504 }
505 } 399 }
506 400
507 if (!romfs_in_flash) { 401 if (!romfs_in_flash) {
@@ -515,25 +409,24 @@ static int __init init_axis_flash(void)
515#else 409#else
516 struct mtd_info *mtd_ram; 410 struct mtd_info *mtd_ram;
517 411
518 mtd_ram = kmalloc(sizeof(struct mtd_info), 412 mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
519 GFP_KERNEL); 413 if (!mtd_ram)
520 if (!mtd_ram) {
521 panic("axisflashmap couldn't allocate memory for " 414 panic("axisflashmap couldn't allocate memory for "
522 "mtd_info!\n"); 415 "mtd_info!\n");
523 }
524 416
525 printk(KERN_INFO " Adding RAM partition for romfs image:\n"); 417 printk(KERN_INFO " Adding RAM partition for romfs image:\n");
526 printk(pmsg, pidx, romfs_start, romfs_length); 418 printk(pmsg, pidx, (unsigned)romfs_start,
527 419 (unsigned)romfs_length);
528 err = mtdram_init_device(mtd_ram, (void*)romfs_start, 420
529 romfs_length, "romfs"); 421 err = mtdram_init_device(mtd_ram,
530 if (err) { 422 (void *)romfs_start,
423 romfs_length,
424 "romfs");
425 if (err)
531 panic("axisflashmap could not initialize MTD RAM " 426 panic("axisflashmap could not initialize MTD RAM "
532 "device!\n"); 427 "device!\n");
533 }
534#endif 428#endif
535 } 429 }
536
537 return err; 430 return err;
538} 431}
539 432
diff --git a/arch/cris/arch-v10/drivers/ds1302.c b/arch/cris/arch-v10/drivers/ds1302.c
index 1d1936a18133..c9aa3904be05 100644
--- a/arch/cris/arch-v10/drivers/ds1302.c
+++ b/arch/cris/arch-v10/drivers/ds1302.c
@@ -333,7 +333,7 @@ rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
333 ds1302_writereg(RTC_TRICKLECHARGER, tcs_val); 333 ds1302_writereg(RTC_TRICKLECHARGER, tcs_val);
334 return 0; 334 return 0;
335 } 335 }
336 case RTC_VLOW_RD: 336 case RTC_VL_READ:
337 { 337 {
338 /* TODO: 338 /* TODO:
339 * Implement voltage low detection support 339 * Implement voltage low detection support
@@ -342,7 +342,7 @@ rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
342 " is not supported\n"); 342 " is not supported\n");
343 return 0; 343 return 0;
344 } 344 }
345 case RTC_VLOW_SET: 345 case RTC_VL_CLR:
346 { 346 {
347 /* TODO: 347 /* TODO:
348 * Nothing to do since Voltage Low detection is not supported 348 * Nothing to do since Voltage Low detection is not supported
diff --git a/arch/cris/arch-v10/drivers/eeprom.c b/arch/cris/arch-v10/drivers/eeprom.c
index be35a70798aa..f1cac9dc75b8 100644
--- a/arch/cris/arch-v10/drivers/eeprom.c
+++ b/arch/cris/arch-v10/drivers/eeprom.c
@@ -19,77 +19,6 @@
19*! Sep 03 1999 Edgar Iglesias Added bail-out stuff if we get interrupted 19*! Sep 03 1999 Edgar Iglesias Added bail-out stuff if we get interrupted
20*! in the spin-lock. 20*! in the spin-lock.
21*! 21*!
22*! $Log: eeprom.c,v $
23*! Revision 1.12 2005/06/19 17:06:46 starvik
24*! Merge of Linux 2.6.12.
25*!
26*! Revision 1.11 2005/01/26 07:14:46 starvik
27*! Applied diff from kernel janitors (Nish Aravamudan).
28*!
29*! Revision 1.10 2003/09/11 07:29:48 starvik
30*! Merge of Linux 2.6.0-test5
31*!
32*! Revision 1.9 2003/07/04 08:27:37 starvik
33*! Merge of Linux 2.5.74
34*!
35*! Revision 1.8 2003/04/09 05:20:47 starvik
36*! Merge of Linux 2.5.67
37*!
38*! Revision 1.6 2003/02/10 07:19:28 starvik
39*! Removed misplaced ;
40*!
41*! Revision 1.5 2002/12/11 13:13:57 starvik
42*! Added arch/ to v10 specific includes
43*! Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
44*!
45*! Revision 1.4 2002/11/20 11:56:10 starvik
46*! Merge of Linux 2.5.48
47*!
48*! Revision 1.3 2002/11/18 13:16:06 starvik
49*! Linux 2.5 port of latest 2.4 drivers
50*!
51*! Revision 1.8 2001/06/15 13:24:29 jonashg
52*! * Added verification of pointers from userspace in read and write.
53*! * Made busy counter volatile.
54*! * Added define for initial write delay.
55*! * Removed warnings by using loff_t instead of unsigned long.
56*!
57*! Revision 1.7 2001/06/14 15:26:54 jonashg
58*! Removed test because condition is always true.
59*!
60*! Revision 1.6 2001/06/14 15:18:20 jonashg
61*! Kb -> kB (makes quite a difference if you don't know if you have 2k or 16k).
62*!
63*! Revision 1.5 2001/06/14 14:39:51 jonashg
64*! Forgot to use name when registering the driver.
65*!
66*! Revision 1.4 2001/06/14 14:35:47 jonashg
67*! * Gave driver a name and used it in printk's.
68*! * Cleanup.
69*!
70*! Revision 1.3 2001/03/19 16:04:46 markusl
71*! Fixed init of fops struct
72*!
73*! Revision 1.2 2001/03/19 10:35:07 markusl
74*! 2.4 port of eeprom driver
75*!
76*! Revision 1.8 2000/05/18 10:42:25 edgar
77*! Make sure to end write cycle on _every_ write
78*!
79*! Revision 1.7 2000/01/17 17:41:01 johana
80*! Adjusted probing and return -ENOSPC when writing outside EEPROM
81*!
82*! Revision 1.6 2000/01/17 15:50:36 johana
83*! Added adaptive timing adjustments and fixed autoprobing for 2k and 16k(?)
84*! EEPROMs
85*!
86*! Revision 1.5 1999/09/03 15:07:37 edgar
87*! Added bail-out check to the spinlock
88*!
89*! Revision 1.4 1999/09/03 12:11:17 bjornw
90*! Proper atomicity (need to use spinlocks, not if's). users -> busy.
91*!
92*!
93*! (c) 1999 Axis Communications AB, Lund, Sweden 22*! (c) 1999 Axis Communications AB, Lund, Sweden
94*!*****************************************************************************/ 23*!*****************************************************************************/
95 24
@@ -103,10 +32,10 @@
103#include <asm/uaccess.h> 32#include <asm/uaccess.h>
104#include "i2c.h" 33#include "i2c.h"
105 34
106#define D(x) 35#define D(x)
107 36
108/* If we should use adaptive timing or not: */ 37/* If we should use adaptive timing or not: */
109//#define EEPROM_ADAPTIVE_TIMING 38/* #define EEPROM_ADAPTIVE_TIMING */
110 39
111#define EEPROM_MAJOR_NR 122 /* use a LOCAL/EXPERIMENTAL major for now */ 40#define EEPROM_MAJOR_NR 122 /* use a LOCAL/EXPERIMENTAL major for now */
112#define EEPROM_MINOR_NR 0 41#define EEPROM_MINOR_NR 0
diff --git a/arch/cris/arch-v10/drivers/gpio.c b/arch/cris/arch-v10/drivers/gpio.c
index 0d347a705835..68a998bd1069 100644
--- a/arch/cris/arch-v10/drivers/gpio.c
+++ b/arch/cris/arch-v10/drivers/gpio.c
@@ -1,138 +1,11 @@
1/* $Id: gpio.c,v 1.17 2005/06/19 17:06:46 starvik Exp $ 1/*
2 *
3 * Etrax general port I/O device 2 * Etrax general port I/O device
4 * 3 *
5 * Copyright (c) 1999, 2000, 2001, 2002 Axis Communications AB 4 * Copyright (c) 1999-2007 Axis Communications AB
6 * 5 *
7 * Authors: Bjorn Wesen (initial version) 6 * Authors: Bjorn Wesen (initial version)
8 * Ola Knutsson (LED handling) 7 * Ola Knutsson (LED handling)
9 * Johan Adolfsson (read/set directions, write, port G) 8 * Johan Adolfsson (read/set directions, write, port G)
10 *
11 * $Log: gpio.c,v $
12 * Revision 1.17 2005/06/19 17:06:46 starvik
13 * Merge of Linux 2.6.12.
14 *
15 * Revision 1.16 2005/03/07 13:02:29 starvik
16 * Protect driver global states with spinlock
17 *
18 * Revision 1.15 2005/01/05 06:08:55 starvik
19 * No need to do local_irq_disable after local_irq_save.
20 *
21 * Revision 1.14 2004/12/13 12:21:52 starvik
22 * Added I/O and DMA allocators from Linux 2.4
23 *
24 * Revision 1.12 2004/08/24 07:19:59 starvik
25 * Whitespace cleanup
26 *
27 * Revision 1.11 2004/05/14 07:58:03 starvik
28 * Merge of changes from 2.4
29 *
30 * Revision 1.9 2003/09/11 07:29:48 starvik
31 * Merge of Linux 2.6.0-test5
32 *
33 * Revision 1.8 2003/07/04 08:27:37 starvik
34 * Merge of Linux 2.5.74
35 *
36 * Revision 1.7 2003/01/10 07:44:07 starvik
37 * init_ioremap is now called by kernel before drivers are initialized
38 *
39 * Revision 1.6 2002/12/11 13:13:57 starvik
40 * Added arch/ to v10 specific includes
41 * Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
42 *
43 * Revision 1.5 2002/11/20 11:56:11 starvik
44 * Merge of Linux 2.5.48
45 *
46 * Revision 1.4 2002/11/18 10:10:05 starvik
47 * Linux 2.5 port of latest gpio.c from Linux 2.4
48 *
49 * Revision 1.20 2002/10/16 21:16:24 johana
50 * Added support for PA high level interrupt.
51 * That gives 2ms response time with iodtest for high levels and 2-12 ms
52 * response time on low levels if the check is not made in
53 * process.c:cpu_idle() as well.
54 *
55 * Revision 1.19 2002/10/14 18:27:33 johana
56 * Implemented alarm handling so select() now works.
57 * Latency is around 6-9 ms with a etrax_gpio_wake_up_check() in
58 * cpu_idle().
59 * Otherwise I get 15-18 ms (same as doing the poll in userspace -
60 * but less overhead).
61 * TODO? Perhaps we should add the check in IMMEDIATE_BH (or whatever it
62 * is in 2.4) as well?
63 * TODO? Perhaps call request_irq()/free_irq() only when needed?
64 * Increased version to 2.5
65 *
66 * Revision 1.18 2002/10/11 15:02:00 johana
67 * Mask inverted 8 bit value in setget_input().
68 *
69 * Revision 1.17 2002/06/17 15:53:01 johana
70 * Added IO_READ_INBITS, IO_READ_OUTBITS, IO_SETGET_INPUT and IO_SETGET_OUTPUT
71 * that take a pointer as argument and thus can handle 32 bit ports (G)
72 * correctly.
73 * These should be used instead of IO_READBITS, IO_SETINPUT and IO_SETOUTPUT.
74 * (especially if Port G bit 31 is used)
75 *
76 * Revision 1.16 2002/06/17 09:59:51 johana
77 * Returning 32 bit values in the ioctl return value doesn't work if bit
78 * 31 is set (could happen for port G), so mask it of with 0x7FFFFFFF.
79 * A new set of ioctl's will be added.
80 *
81 * Revision 1.15 2002/05/06 13:19:13 johana
82 * IO_SETINPUT returns mask with bit set = inputs for PA and PB as well.
83 *
84 * Revision 1.14 2002/04/12 12:01:53 johana
85 * Use global r_port_g_data_shadow.
86 * Moved gpio_init_port_g() closer to gpio_init() and marked it __init.
87 *
88 * Revision 1.13 2002/04/10 12:03:55 johana
89 * Added support for port G /dev/gpiog (minor 3).
90 * Changed indentation on switch cases.
91 * Fixed other spaces to tabs.
92 *
93 * Revision 1.12 2001/11/12 19:42:15 pkj
94 * * Corrected return values from gpio_leds_ioctl().
95 * * Fixed compiler warnings.
96 *
97 * Revision 1.11 2001/10/30 14:39:12 johana
98 * Added D() around gpio_write printk.
99 *
100 * Revision 1.10 2001/10/25 10:24:42 johana
101 * Added IO_CFG_WRITE_MODE ioctl and write method that can do fast
102 * bittoggling in the kernel. (This speeds up programming an FPGA with 450kB
103 * from ~60 seconds to 4 seconds).
104 * Added save_flags/cli/restore_flags in ioctl.
105 *
106 * Revision 1.9 2001/05/04 14:16:07 matsfg
107 * Corrected spelling error
108 *
109 * Revision 1.8 2001/04/27 13:55:26 matsfg
110 * Moved initioremap.
111 * Turns off all LEDS on init.
112 * Added support for shutdown and powerbutton.
113 *
114 * Revision 1.7 2001/04/04 13:30:08 matsfg
115 * Added bitset and bitclear for leds. Calls init_ioremap to set up memmapping
116 *
117 * Revision 1.6 2001/03/26 16:03:06 bjornw
118 * Needs linux/config.h
119 *
120 * Revision 1.5 2001/03/26 14:22:03 bjornw
121 * Namechange of some config options
122 *
123 * Revision 1.4 2001/02/27 13:52:48 bjornw
124 * malloc.h -> slab.h
125 *
126 * Revision 1.3 2001/01/24 15:06:48 bjornw
127 * gpio_wq correct type
128 *
129 * Revision 1.2 2001/01/18 16:07:30 bjornw
130 * 2.4 port
131 *
132 * Revision 1.1 2001/01/18 15:55:16 bjornw
133 * Verbatim copy of etraxgpio.c from elinux 2.0 added
134 *
135 *
136 */ 9 */
137 10
138 11
@@ -165,7 +38,7 @@ static int dp_cnt;
165#else 38#else
166#define DP(x) 39#define DP(x)
167#endif 40#endif
168 41
169static char gpio_name[] = "etrax gpio"; 42static char gpio_name[] = "etrax gpio";
170 43
171#if 0 44#if 0
@@ -173,9 +46,9 @@ static wait_queue_head_t *gpio_wq;
173#endif 46#endif
174 47
175static int gpio_ioctl(struct inode *inode, struct file *file, 48static int gpio_ioctl(struct inode *inode, struct file *file,
176 unsigned int cmd, unsigned long arg); 49 unsigned int cmd, unsigned long arg);
177static ssize_t gpio_write(struct file * file, const char * buf, size_t count, 50static ssize_t gpio_write(struct file *file, const char __user *buf,
178 loff_t *off); 51 size_t count, loff_t *off);
179static int gpio_open(struct inode *inode, struct file *filp); 52static int gpio_open(struct inode *inode, struct file *filp);
180static int gpio_release(struct inode *inode, struct file *filp); 53static int gpio_release(struct inode *inode, struct file *filp);
181static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait); 54static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait);
@@ -201,22 +74,22 @@ struct gpio_private {
201 74
202/* linked list of alarms to check for */ 75/* linked list of alarms to check for */
203 76
204static struct gpio_private *alarmlist = 0; 77static struct gpio_private *alarmlist;
205 78
206static int gpio_some_alarms = 0; /* Set if someone uses alarm */ 79static int gpio_some_alarms; /* Set if someone uses alarm */
207static unsigned long gpio_pa_irq_enabled_mask = 0; 80static unsigned long gpio_pa_irq_enabled_mask;
208 81
209static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */ 82static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */
210 83
211/* Port A and B use 8 bit access, but Port G is 32 bit */ 84/* Port A and B use 8 bit access, but Port G is 32 bit */
212#define NUM_PORTS (GPIO_MINOR_B+1) 85#define NUM_PORTS (GPIO_MINOR_B+1)
213 86
214static volatile unsigned char *ports[NUM_PORTS] = { 87static volatile unsigned char *ports[NUM_PORTS] = {
215 R_PORT_PA_DATA, 88 R_PORT_PA_DATA,
216 R_PORT_PB_DATA, 89 R_PORT_PB_DATA,
217}; 90};
218static volatile unsigned char *shads[NUM_PORTS] = { 91static volatile unsigned char *shads[NUM_PORTS] = {
219 &port_pa_data_shadow, 92 &port_pa_data_shadow,
220 &port_pb_data_shadow 93 &port_pb_data_shadow
221}; 94};
222 95
@@ -236,29 +109,29 @@ static volatile unsigned char *shads[NUM_PORTS] = {
236#endif 109#endif
237 110
238 111
239static unsigned char changeable_dir[NUM_PORTS] = { 112static unsigned char changeable_dir[NUM_PORTS] = {
240 CONFIG_ETRAX_PA_CHANGEABLE_DIR, 113 CONFIG_ETRAX_PA_CHANGEABLE_DIR,
241 CONFIG_ETRAX_PB_CHANGEABLE_DIR 114 CONFIG_ETRAX_PB_CHANGEABLE_DIR
242}; 115};
243static unsigned char changeable_bits[NUM_PORTS] = { 116static unsigned char changeable_bits[NUM_PORTS] = {
244 CONFIG_ETRAX_PA_CHANGEABLE_BITS, 117 CONFIG_ETRAX_PA_CHANGEABLE_BITS,
245 CONFIG_ETRAX_PB_CHANGEABLE_BITS 118 CONFIG_ETRAX_PB_CHANGEABLE_BITS
246}; 119};
247 120
248static volatile unsigned char *dir[NUM_PORTS] = { 121static volatile unsigned char *dir[NUM_PORTS] = {
249 R_PORT_PA_DIR, 122 R_PORT_PA_DIR,
250 R_PORT_PB_DIR 123 R_PORT_PB_DIR
251}; 124};
252 125
253static volatile unsigned char *dir_shadow[NUM_PORTS] = { 126static volatile unsigned char *dir_shadow[NUM_PORTS] = {
254 &port_pa_dir_shadow, 127 &port_pa_dir_shadow,
255 &port_pb_dir_shadow 128 &port_pb_dir_shadow
256}; 129};
257 130
258/* All bits in port g that can change dir. */ 131/* All bits in port g that can change dir. */
259static const unsigned long int changeable_dir_g_mask = 0x01FFFF01; 132static const unsigned long int changeable_dir_g_mask = 0x01FFFF01;
260 133
261/* Port G is 32 bit, handle it special, some bits are both inputs 134/* Port G is 32 bit, handle it special, some bits are both inputs
262 and outputs at the same time, only some of the bits can change direction 135 and outputs at the same time, only some of the bits can change direction
263 and some of them in groups of 8 bit. */ 136 and some of them in groups of 8 bit. */
264static unsigned long changeable_dir_g; 137static unsigned long changeable_dir_g;
@@ -269,18 +142,17 @@ static unsigned long dir_g_shadow; /* 1=output */
269#define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B) 142#define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B)
270 143
271 144
272 145static unsigned int gpio_poll(struct file *file, poll_table *wait)
273static unsigned int
274gpio_poll(struct file *file,
275 poll_table *wait)
276{ 146{
277 unsigned int mask = 0; 147 unsigned int mask = 0;
278 struct gpio_private *priv = (struct gpio_private *)file->private_data; 148 struct gpio_private *priv = file->private_data;
279 unsigned long data; 149 unsigned long data;
280 spin_lock(&gpio_lock); 150 unsigned long flags;
151
152 spin_lock_irqsave(&gpio_lock, flags);
153
281 poll_wait(file, &priv->alarm_wq, wait); 154 poll_wait(file, &priv->alarm_wq, wait);
282 if (priv->minor == GPIO_MINOR_A) { 155 if (priv->minor == GPIO_MINOR_A) {
283 unsigned long flags;
284 unsigned long tmp; 156 unsigned long tmp;
285 data = *R_PORT_PA_DATA; 157 data = *R_PORT_PA_DATA;
286 /* PA has support for high level interrupt - 158 /* PA has support for high level interrupt -
@@ -288,27 +160,25 @@ gpio_poll(struct file *file,
288 */ 160 */
289 tmp = ~data & priv->highalarm & 0xFF; 161 tmp = ~data & priv->highalarm & 0xFF;
290 tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR); 162 tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR);
291 local_irq_save(flags); 163
292 gpio_pa_irq_enabled_mask |= tmp; 164 gpio_pa_irq_enabled_mask |= tmp;
293 *R_IRQ_MASK1_SET = tmp; 165 *R_IRQ_MASK1_SET = tmp;
294 local_irq_restore(flags);
295
296 } else if (priv->minor == GPIO_MINOR_B) 166 } else if (priv->minor == GPIO_MINOR_B)
297 data = *R_PORT_PB_DATA; 167 data = *R_PORT_PB_DATA;
298 else if (priv->minor == GPIO_MINOR_G) 168 else if (priv->minor == GPIO_MINOR_G)
299 data = *R_PORT_G_DATA; 169 data = *R_PORT_G_DATA;
300 else { 170 else {
301 spin_unlock(&gpio_lock); 171 mask = 0;
302 return 0; 172 goto out;
303 } 173 }
304 174
305 if ((data & priv->highalarm) || 175 if ((data & priv->highalarm) ||
306 (~data & priv->lowalarm)) { 176 (~data & priv->lowalarm)) {
307 mask = POLLIN|POLLRDNORM; 177 mask = POLLIN|POLLRDNORM;
308 } 178 }
309 179
310 spin_unlock(&gpio_lock); 180out:
311 181 spin_unlock_irqrestore(&gpio_lock, flags);
312 DP(printk("gpio_poll ready: mask 0x%08X\n", mask)); 182 DP(printk("gpio_poll ready: mask 0x%08X\n", mask));
313 183
314 return mask; 184 return mask;
@@ -316,16 +186,19 @@ gpio_poll(struct file *file,
316 186
317int etrax_gpio_wake_up_check(void) 187int etrax_gpio_wake_up_check(void)
318{ 188{
319 struct gpio_private *priv = alarmlist; 189 struct gpio_private *priv;
320 unsigned long data = 0; 190 unsigned long data = 0;
321 int ret = 0; 191 int ret = 0;
322 spin_lock(&gpio_lock); 192 unsigned long flags;
193
194 spin_lock_irqsave(&gpio_lock, flags);
195 priv = alarmlist;
323 while (priv) { 196 while (priv) {
324 if (USE_PORTS(priv)) { 197 if (USE_PORTS(priv))
325 data = *priv->port; 198 data = *priv->port;
326 } else if (priv->minor == GPIO_MINOR_G) { 199 else if (priv->minor == GPIO_MINOR_G)
327 data = *R_PORT_G_DATA; 200 data = *R_PORT_G_DATA;
328 } 201
329 if ((data & priv->highalarm) || 202 if ((data & priv->highalarm) ||
330 (~data & priv->lowalarm)) { 203 (~data & priv->lowalarm)) {
331 DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor)); 204 DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor));
@@ -334,12 +207,12 @@ int etrax_gpio_wake_up_check(void)
334 } 207 }
335 priv = priv->next; 208 priv = priv->next;
336 } 209 }
337 spin_unlock(&gpio_lock); 210 spin_unlock_irqrestore(&gpio_lock, flags);
338 return ret; 211 return ret;
339} 212}
340 213
341static irqreturn_t 214static irqreturn_t
342gpio_poll_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) 215gpio_poll_timer_interrupt(int irq, void *dev_id)
343{ 216{
344 if (gpio_some_alarms) { 217 if (gpio_some_alarms) {
345 etrax_gpio_wake_up_check(); 218 etrax_gpio_wake_up_check();
@@ -349,10 +222,13 @@ gpio_poll_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
349} 222}
350 223
351static irqreturn_t 224static irqreturn_t
352gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs) 225gpio_interrupt(int irq, void *dev_id)
353{ 226{
354 unsigned long tmp; 227 unsigned long tmp;
355 spin_lock(&gpio_lock); 228 unsigned long flags;
229
230 spin_lock_irqsave(&gpio_lock, flags);
231
356 /* Find what PA interrupts are active */ 232 /* Find what PA interrupts are active */
357 tmp = (*R_IRQ_READ1); 233 tmp = (*R_IRQ_READ1);
358 234
@@ -363,75 +239,70 @@ gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs)
363 *R_IRQ_MASK1_CLR = tmp; 239 *R_IRQ_MASK1_CLR = tmp;
364 gpio_pa_irq_enabled_mask &= ~tmp; 240 gpio_pa_irq_enabled_mask &= ~tmp;
365 241
366 spin_unlock(&gpio_lock); 242 spin_unlock_irqrestore(&gpio_lock, flags);
367 243
368 if (gpio_some_alarms) { 244 if (gpio_some_alarms)
369 return IRQ_RETVAL(etrax_gpio_wake_up_check()); 245 return IRQ_RETVAL(etrax_gpio_wake_up_check());
370 } 246
371 return IRQ_NONE; 247 return IRQ_NONE;
372} 248}
373 249
250static void gpio_write_bit(struct gpio_private *priv,
251 unsigned char data, int bit)
252{
253 *priv->port = *priv->shadow &= ~(priv->clk_mask);
254 if (data & 1 << bit)
255 *priv->port = *priv->shadow |= priv->data_mask;
256 else
257 *priv->port = *priv->shadow &= ~(priv->data_mask);
258
259 /* For FPGA: min 5.0ns (DCC) before CCLK high */
260 *priv->port = *priv->shadow |= priv->clk_mask;
261}
374 262
375static ssize_t gpio_write(struct file * file, const char * buf, size_t count, 263static void gpio_write_byte(struct gpio_private *priv, unsigned char data)
376 loff_t *off)
377{ 264{
378 struct gpio_private *priv = (struct gpio_private *)file->private_data; 265 int i;
379 unsigned char data, clk_mask, data_mask, write_msb;
380 unsigned long flags;
381 266
382 spin_lock(&gpio_lock); 267 if (priv->write_msb)
268 for (i = 7; i >= 0; i--)
269 gpio_write_bit(priv, data, i);
270 else
271 for (i = 0; i <= 7; i++)
272 gpio_write_bit(priv, data, i);
273}
383 274
275static ssize_t gpio_write(struct file *file, const char __user *buf,
276 size_t count, loff_t *off)
277{
278 struct gpio_private *priv = file->private_data;
279 unsigned long flags;
384 ssize_t retval = count; 280 ssize_t retval = count;
385 if (priv->minor !=GPIO_MINOR_A && priv->minor != GPIO_MINOR_B) { 281
386 retval = -EFAULT; 282 if (priv->minor != GPIO_MINOR_A && priv->minor != GPIO_MINOR_B)
387 goto out; 283 return -EFAULT;
388 } 284
389 285 if (!access_ok(VERIFY_READ, buf, count))
390 if (!access_ok(VERIFY_READ, buf, count)) { 286 return -EFAULT;
391 retval = -EFAULT; 287
392 goto out; 288 spin_lock_irqsave(&gpio_lock, flags);
393 } 289
394 clk_mask = priv->clk_mask;
395 data_mask = priv->data_mask;
396 /* It must have been configured using the IO_CFG_WRITE_MODE */ 290 /* It must have been configured using the IO_CFG_WRITE_MODE */
397 /* Perhaps a better error code? */ 291 /* Perhaps a better error code? */
398 if (clk_mask == 0 || data_mask == 0) { 292 if (priv->clk_mask == 0 || priv->data_mask == 0) {
399 retval = -EPERM; 293 retval = -EPERM;
400 goto out; 294 goto out;
401 } 295 }
402 write_msb = priv->write_msb; 296
403 D(printk("gpio_write: %lu to data 0x%02X clk 0x%02X msb: %i\n",count, data_mask, clk_mask, write_msb)); 297 D(printk(KERN_DEBUG "gpio_write: %02X to data 0x%02X "
404 while (count--) { 298 "clk 0x%02X msb: %i\n",
405 int i; 299 count, priv->data_mask, priv->clk_mask, priv->write_msb));
406 data = *buf++; 300
407 if (priv->write_msb) { 301 while (count--)
408 for (i = 7; i >= 0;i--) { 302 gpio_write_byte(priv, *buf++);
409 local_irq_save(flags); 303
410 *priv->port = *priv->shadow &= ~clk_mask;
411 if (data & 1<<i)
412 *priv->port = *priv->shadow |= data_mask;
413 else
414 *priv->port = *priv->shadow &= ~data_mask;
415 /* For FPGA: min 5.0ns (DCC) before CCLK high */
416 *priv->port = *priv->shadow |= clk_mask;
417 local_irq_restore(flags);
418 }
419 } else {
420 for (i = 0; i <= 7;i++) {
421 local_irq_save(flags);
422 *priv->port = *priv->shadow &= ~clk_mask;
423 if (data & 1<<i)
424 *priv->port = *priv->shadow |= data_mask;
425 else
426 *priv->port = *priv->shadow &= ~data_mask;
427 /* For FPGA: min 5.0ns (DCC) before CCLK high */
428 *priv->port = *priv->shadow |= clk_mask;
429 local_irq_restore(flags);
430 }
431 }
432 }
433out: 304out:
434 spin_unlock(&gpio_lock); 305 spin_unlock_irqrestore(&gpio_lock, flags);
435 return retval; 306 return retval;
436} 307}
437 308
@@ -442,22 +313,20 @@ gpio_open(struct inode *inode, struct file *filp)
442{ 313{
443 struct gpio_private *priv; 314 struct gpio_private *priv;
444 int p = iminor(inode); 315 int p = iminor(inode);
316 unsigned long flags;
445 317
446 if (p > GPIO_MINOR_LAST) 318 if (p > GPIO_MINOR_LAST)
447 return -EINVAL; 319 return -EINVAL;
448 320
449 priv = kmalloc(sizeof(struct gpio_private), 321 priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL);
450 GFP_KERNEL);
451 322
452 if (!priv) 323 if (!priv)
453 return -ENOMEM; 324 return -ENOMEM;
454 325
455 priv->minor = p; 326 priv->minor = p;
456 327
457 /* initialize the io/alarm struct and link it into our alarmlist */ 328 /* initialize the io/alarm struct */
458 329
459 priv->next = alarmlist;
460 alarmlist = priv;
461 if (USE_PORTS(priv)) { /* A and B */ 330 if (USE_PORTS(priv)) { /* A and B */
462 priv->port = ports[p]; 331 priv->port = ports[p];
463 priv->shadow = shads[p]; 332 priv->shadow = shads[p];
@@ -480,7 +349,13 @@ gpio_open(struct inode *inode, struct file *filp)
480 priv->data_mask = 0; 349 priv->data_mask = 0;
481 init_waitqueue_head(&priv->alarm_wq); 350 init_waitqueue_head(&priv->alarm_wq);
482 351
483 filp->private_data = (void *)priv; 352 filp->private_data = priv;
353
354 /* link it into our alarmlist */
355 spin_lock_irqsave(&gpio_lock, flags);
356 priv->next = alarmlist;
357 alarmlist = priv;
358 spin_unlock_irqrestore(&gpio_lock, flags);
484 359
485 return 0; 360 return 0;
486} 361}
@@ -490,11 +365,12 @@ gpio_release(struct inode *inode, struct file *filp)
490{ 365{
491 struct gpio_private *p; 366 struct gpio_private *p;
492 struct gpio_private *todel; 367 struct gpio_private *todel;
368 unsigned long flags;
493 369
494 spin_lock(&gpio_lock); 370 spin_lock_irqsave(&gpio_lock, flags);
495 371
496 p = alarmlist; 372 p = alarmlist;
497 todel = (struct gpio_private *)filp->private_data; 373 todel = filp->private_data;
498 374
499 /* unlink from alarmlist and free the private structure */ 375 /* unlink from alarmlist and free the private structure */
500 376
@@ -512,123 +388,114 @@ gpio_release(struct inode *inode, struct file *filp)
512 while (p) { 388 while (p) {
513 if (p->highalarm | p->lowalarm) { 389 if (p->highalarm | p->lowalarm) {
514 gpio_some_alarms = 1; 390 gpio_some_alarms = 1;
515 spin_unlock(&gpio_lock); 391 goto out;
516 return 0;
517 } 392 }
518 p = p->next; 393 p = p->next;
519 } 394 }
520 gpio_some_alarms = 0; 395 gpio_some_alarms = 0;
521 spin_unlock(&gpio_lock); 396out:
397 spin_unlock_irqrestore(&gpio_lock, flags);
522 return 0; 398 return 0;
523} 399}
524 400
525/* Main device API. ioctl's to read/set/clear bits, as well as to 401/* Main device API. ioctl's to read/set/clear bits, as well as to
526 * set alarms to wait for using a subsequent select(). 402 * set alarms to wait for using a subsequent select().
527 */ 403 */
528
529unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg) 404unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg)
530{ 405{
531 /* Set direction 0=unchanged 1=input, 406 /* Set direction 0=unchanged 1=input,
532 * return mask with 1=input 407 * return mask with 1=input */
533 */
534 unsigned long flags;
535 if (USE_PORTS(priv)) { 408 if (USE_PORTS(priv)) {
536 local_irq_save(flags); 409 *priv->dir = *priv->dir_shadow &=
537 *priv->dir = *priv->dir_shadow &=
538 ~((unsigned char)arg & priv->changeable_dir); 410 ~((unsigned char)arg & priv->changeable_dir);
539 local_irq_restore(flags);
540 return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */ 411 return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */
541 } else if (priv->minor == GPIO_MINOR_G) { 412 }
542 /* We must fiddle with R_GEN_CONFIG to change dir */ 413
543 local_irq_save(flags); 414 if (priv->minor != GPIO_MINOR_G)
544 if (((arg & dir_g_in_bits) != arg) && 415 return 0;
545 (arg & changeable_dir_g)) { 416
546 arg &= changeable_dir_g; 417 /* We must fiddle with R_GEN_CONFIG to change dir */
547 /* Clear bits in genconfig to set to input */ 418 if (((arg & dir_g_in_bits) != arg) &&
548 if (arg & (1<<0)) { 419 (arg & changeable_dir_g)) {
549 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g0dir); 420 arg &= changeable_dir_g;
550 dir_g_in_bits |= (1<<0); 421 /* Clear bits in genconfig to set to input */
551 dir_g_out_bits &= ~(1<<0); 422 if (arg & (1<<0)) {
552 } 423 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g0dir);
553 if ((arg & 0x0000FF00) == 0x0000FF00) { 424 dir_g_in_bits |= (1<<0);
554 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g8_15dir); 425 dir_g_out_bits &= ~(1<<0);
555 dir_g_in_bits |= 0x0000FF00;
556 dir_g_out_bits &= ~0x0000FF00;
557 }
558 if ((arg & 0x00FF0000) == 0x00FF0000) {
559 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g16_23dir);
560 dir_g_in_bits |= 0x00FF0000;
561 dir_g_out_bits &= ~0x00FF0000;
562 }
563 if (arg & (1<<24)) {
564 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g24dir);
565 dir_g_in_bits |= (1<<24);
566 dir_g_out_bits &= ~(1<<24);
567 }
568 D(printk(KERN_INFO "gpio: SETINPUT on port G set "
569 "genconfig to 0x%08lX "
570 "in_bits: 0x%08lX "
571 "out_bits: 0x%08lX\n",
572 (unsigned long)genconfig_shadow,
573 dir_g_in_bits, dir_g_out_bits));
574 *R_GEN_CONFIG = genconfig_shadow;
575 /* Must be a >120 ns delay before writing this again */
576
577 } 426 }
578 local_irq_restore(flags); 427 if ((arg & 0x0000FF00) == 0x0000FF00) {
579 return dir_g_in_bits; 428 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g8_15dir);
429 dir_g_in_bits |= 0x0000FF00;
430 dir_g_out_bits &= ~0x0000FF00;
431 }
432 if ((arg & 0x00FF0000) == 0x00FF0000) {
433 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g16_23dir);
434 dir_g_in_bits |= 0x00FF0000;
435 dir_g_out_bits &= ~0x00FF0000;
436 }
437 if (arg & (1<<24)) {
438 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g24dir);
439 dir_g_in_bits |= (1<<24);
440 dir_g_out_bits &= ~(1<<24);
441 }
442 D(printk(KERN_DEBUG "gpio: SETINPUT on port G set "
443 "genconfig to 0x%08lX "
444 "in_bits: 0x%08lX "
445 "out_bits: 0x%08lX\n",
446 (unsigned long)genconfig_shadow,
447 dir_g_in_bits, dir_g_out_bits));
448 *R_GEN_CONFIG = genconfig_shadow;
449 /* Must be a >120 ns delay before writing this again */
450
580 } 451 }
581 return 0; 452 return dir_g_in_bits;
582} /* setget_input */ 453} /* setget_input */
583 454
584unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg) 455unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg)
585{ 456{
586 unsigned long flags;
587 if (USE_PORTS(priv)) { 457 if (USE_PORTS(priv)) {
588 local_irq_save(flags); 458 *priv->dir = *priv->dir_shadow |=
589 *priv->dir = *priv->dir_shadow |= 459 ((unsigned char)arg & priv->changeable_dir);
590 ((unsigned char)arg & priv->changeable_dir);
591 local_irq_restore(flags);
592 return *priv->dir_shadow; 460 return *priv->dir_shadow;
593 } else if (priv->minor == GPIO_MINOR_G) { 461 }
594 /* We must fiddle with R_GEN_CONFIG to change dir */ 462 if (priv->minor != GPIO_MINOR_G)
595 local_irq_save(flags); 463 return 0;
596 if (((arg & dir_g_out_bits) != arg) && 464
597 (arg & changeable_dir_g)) { 465 /* We must fiddle with R_GEN_CONFIG to change dir */
598 /* Set bits in genconfig to set to output */ 466 if (((arg & dir_g_out_bits) != arg) &&
599 if (arg & (1<<0)) { 467 (arg & changeable_dir_g)) {
600 genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g0dir); 468 /* Set bits in genconfig to set to output */
601 dir_g_out_bits |= (1<<0); 469 if (arg & (1<<0)) {
602 dir_g_in_bits &= ~(1<<0); 470 genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g0dir);
603 } 471 dir_g_out_bits |= (1<<0);
604 if ((arg & 0x0000FF00) == 0x0000FF00) { 472 dir_g_in_bits &= ~(1<<0);
605 genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g8_15dir);
606 dir_g_out_bits |= 0x0000FF00;
607 dir_g_in_bits &= ~0x0000FF00;
608 }
609 if ((arg & 0x00FF0000) == 0x00FF0000) {
610 genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g16_23dir);
611 dir_g_out_bits |= 0x00FF0000;
612 dir_g_in_bits &= ~0x00FF0000;
613 }
614 if (arg & (1<<24)) {
615 genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g24dir);
616 dir_g_out_bits |= (1<<24);
617 dir_g_in_bits &= ~(1<<24);
618 }
619 D(printk(KERN_INFO "gpio: SETOUTPUT on port G set "
620 "genconfig to 0x%08lX "
621 "in_bits: 0x%08lX "
622 "out_bits: 0x%08lX\n",
623 (unsigned long)genconfig_shadow,
624 dir_g_in_bits, dir_g_out_bits));
625 *R_GEN_CONFIG = genconfig_shadow;
626 /* Must be a >120 ns delay before writing this again */
627 } 473 }
628 local_irq_restore(flags); 474 if ((arg & 0x0000FF00) == 0x0000FF00) {
629 return dir_g_out_bits & 0x7FFFFFFF; 475 genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g8_15dir);
476 dir_g_out_bits |= 0x0000FF00;
477 dir_g_in_bits &= ~0x0000FF00;
478 }
479 if ((arg & 0x00FF0000) == 0x00FF0000) {
480 genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g16_23dir);
481 dir_g_out_bits |= 0x00FF0000;
482 dir_g_in_bits &= ~0x00FF0000;
483 }
484 if (arg & (1<<24)) {
485 genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g24dir);
486 dir_g_out_bits |= (1<<24);
487 dir_g_in_bits &= ~(1<<24);
488 }
489 D(printk(KERN_INFO "gpio: SETOUTPUT on port G set "
490 "genconfig to 0x%08lX "
491 "in_bits: 0x%08lX "
492 "out_bits: 0x%08lX\n",
493 (unsigned long)genconfig_shadow,
494 dir_g_in_bits, dir_g_out_bits));
495 *R_GEN_CONFIG = genconfig_shadow;
496 /* Must be a >120 ns delay before writing this again */
630 } 497 }
631 return 0; 498 return dir_g_out_bits & 0x7FFFFFFF;
632} /* setget_output */ 499} /* setget_output */
633 500
634static int 501static int
@@ -642,12 +509,11 @@ gpio_ioctl(struct inode *inode, struct file *file,
642 unsigned long val; 509 unsigned long val;
643 int ret = 0; 510 int ret = 0;
644 511
645 struct gpio_private *priv = (struct gpio_private *)file->private_data; 512 struct gpio_private *priv = file->private_data;
646 if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) { 513 if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
647 return -EINVAL; 514 return -EINVAL;
648 }
649 515
650 spin_lock(&gpio_lock); 516 spin_lock_irqsave(&gpio_lock, flags);
651 517
652 switch (_IOC_NR(cmd)) { 518 switch (_IOC_NR(cmd)) {
653 case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */ 519 case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
@@ -659,7 +525,6 @@ gpio_ioctl(struct inode *inode, struct file *file,
659 } 525 }
660 break; 526 break;
661 case IO_SETBITS: 527 case IO_SETBITS:
662 local_irq_save(flags);
663 // set changeable bits with a 1 in arg 528 // set changeable bits with a 1 in arg
664 if (USE_PORTS(priv)) { 529 if (USE_PORTS(priv)) {
665 *priv->port = *priv->shadow |= 530 *priv->port = *priv->shadow |=
@@ -667,10 +532,8 @@ gpio_ioctl(struct inode *inode, struct file *file,
667 } else if (priv->minor == GPIO_MINOR_G) { 532 } else if (priv->minor == GPIO_MINOR_G) {
668 *R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits); 533 *R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits);
669 } 534 }
670 local_irq_restore(flags);
671 break; 535 break;
672 case IO_CLRBITS: 536 case IO_CLRBITS:
673 local_irq_save(flags);
674 // clear changeable bits with a 1 in arg 537 // clear changeable bits with a 1 in arg
675 if (USE_PORTS(priv)) { 538 if (USE_PORTS(priv)) {
676 *priv->port = *priv->shadow &= 539 *priv->port = *priv->shadow &=
@@ -678,7 +541,6 @@ gpio_ioctl(struct inode *inode, struct file *file,
678 } else if (priv->minor == GPIO_MINOR_G) { 541 } else if (priv->minor == GPIO_MINOR_G) {
679 *R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits); 542 *R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits);
680 } 543 }
681 local_irq_restore(flags);
682 break; 544 break;
683 case IO_HIGHALARM: 545 case IO_HIGHALARM:
684 // set alarm when bits with 1 in arg go high 546 // set alarm when bits with 1 in arg go high
@@ -698,6 +560,8 @@ gpio_ioctl(struct inode *inode, struct file *file,
698 /* Must update gpio_some_alarms */ 560 /* Must update gpio_some_alarms */
699 struct gpio_private *p = alarmlist; 561 struct gpio_private *p = alarmlist;
700 int some_alarms; 562 int some_alarms;
563 spin_lock_irq(&gpio_lock);
564 p = alarmlist;
701 some_alarms = 0; 565 some_alarms = 0;
702 while (p) { 566 while (p) {
703 if (p->highalarm | p->lowalarm) { 567 if (p->highalarm | p->lowalarm) {
@@ -707,6 +571,7 @@ gpio_ioctl(struct inode *inode, struct file *file,
707 p = p->next; 571 p = p->next;
708 } 572 }
709 gpio_some_alarms = some_alarms; 573 gpio_some_alarms = some_alarms;
574 spin_unlock_irq(&gpio_lock);
710 } 575 }
711 break; 576 break;
712 case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */ 577 case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
@@ -766,7 +631,7 @@ gpio_ioctl(struct inode *inode, struct file *file,
766 } else if (priv->minor == GPIO_MINOR_G) { 631 } else if (priv->minor == GPIO_MINOR_G) {
767 val = *R_PORT_G_DATA; 632 val = *R_PORT_G_DATA;
768 } 633 }
769 if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) 634 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
770 ret = -EFAULT; 635 ret = -EFAULT;
771 break; 636 break;
772 case IO_READ_OUTBITS: 637 case IO_READ_OUTBITS:
@@ -776,33 +641,32 @@ gpio_ioctl(struct inode *inode, struct file *file,
776 } else if (priv->minor == GPIO_MINOR_G) { 641 } else if (priv->minor == GPIO_MINOR_G) {
777 val = port_g_data_shadow; 642 val = port_g_data_shadow;
778 } 643 }
779 if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) 644 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
780 ret = -EFAULT; 645 ret = -EFAULT;
781 break; 646 break;
782 case IO_SETGET_INPUT: 647 case IO_SETGET_INPUT:
783 /* bits set in *arg is set to input, 648 /* bits set in *arg is set to input,
784 * *arg updated with current input pins. 649 * *arg updated with current input pins.
785 */ 650 */
786 if (copy_from_user(&val, (unsigned long*)arg, sizeof(val))) 651 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
787 { 652 {
788 ret = -EFAULT; 653 ret = -EFAULT;
789 break; 654 break;
790 } 655 }
791 val = setget_input(priv, val); 656 val = setget_input(priv, val);
792 if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) 657 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
793 ret = -EFAULT; 658 ret = -EFAULT;
794 break; 659 break;
795 case IO_SETGET_OUTPUT: 660 case IO_SETGET_OUTPUT:
796 /* bits set in *arg is set to output, 661 /* bits set in *arg is set to output,
797 * *arg updated with current output pins. 662 * *arg updated with current output pins.
798 */ 663 */
799 if (copy_from_user(&val, (unsigned long*)arg, sizeof(val))) 664 if (copy_from_user(&val, (void __user *)arg, sizeof(val))) {
800 {
801 ret = -EFAULT; 665 ret = -EFAULT;
802 break; 666 break;
803 } 667 }
804 val = setget_output(priv, val); 668 val = setget_output(priv, val);
805 if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) 669 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
806 ret = -EFAULT; 670 ret = -EFAULT;
807 break; 671 break;
808 default: 672 default:
@@ -812,7 +676,7 @@ gpio_ioctl(struct inode *inode, struct file *file,
812 ret = -EINVAL; 676 ret = -EINVAL;
813 } /* switch */ 677 } /* switch */
814 678
815 spin_unlock(&gpio_lock); 679 spin_unlock_irqrestore(&gpio_lock, flags);
816 return ret; 680 return ret;
817} 681}
818 682
@@ -824,18 +688,18 @@ gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
824 688
825 switch (_IOC_NR(cmd)) { 689 switch (_IOC_NR(cmd)) {
826 case IO_LEDACTIVE_SET: 690 case IO_LEDACTIVE_SET:
827 green = ((unsigned char) arg) & 1; 691 green = ((unsigned char)arg) & 1;
828 red = (((unsigned char) arg) >> 1) & 1; 692 red = (((unsigned char)arg) >> 1) & 1;
829 LED_ACTIVE_SET_G(green); 693 CRIS_LED_ACTIVE_SET_G(green);
830 LED_ACTIVE_SET_R(red); 694 CRIS_LED_ACTIVE_SET_R(red);
831 break; 695 break;
832 696
833 case IO_LED_SETBIT: 697 case IO_LED_SETBIT:
834 LED_BIT_SET(arg); 698 CRIS_LED_BIT_SET(arg);
835 break; 699 break;
836 700
837 case IO_LED_CLRBIT: 701 case IO_LED_CLRBIT:
838 LED_BIT_CLR(arg); 702 CRIS_LED_BIT_CLR(arg);
839 break; 703 break;
840 704
841 default: 705 default:
@@ -845,7 +709,7 @@ gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
845 return 0; 709 return 0;
846} 710}
847 711
848const struct file_operations gpio_fops = { 712static const struct file_operations gpio_fops = {
849 .owner = THIS_MODULE, 713 .owner = THIS_MODULE,
850 .poll = gpio_poll, 714 .poll = gpio_poll,
851 .ioctl = gpio_ioctl, 715 .ioctl = gpio_ioctl,
@@ -854,16 +718,18 @@ const struct file_operations gpio_fops = {
854 .release = gpio_release, 718 .release = gpio_release,
855}; 719};
856 720
857 721static void ioif_watcher(const unsigned int gpio_in_available,
858void ioif_watcher(const unsigned int gpio_in_available, 722 const unsigned int gpio_out_available,
859 const unsigned int gpio_out_available, 723 const unsigned char pa_available,
860 const unsigned char pa_available, 724 const unsigned char pb_available)
861 const unsigned char pb_available)
862{ 725{
863 unsigned long int flags; 726 unsigned long int flags;
864 D(printk("gpio.c: ioif_watcher called\n")); 727
865 D(printk("gpio.c: G in: 0x%08x G out: 0x%08x PA: 0x%02x PB: 0x%02x\n", 728 D(printk(KERN_DEBUG "gpio.c: ioif_watcher called\n"));
866 gpio_in_available, gpio_out_available, pa_available, pb_available)); 729 D(printk(KERN_DEBUG "gpio.c: G in: 0x%08x G out: 0x%08x "
730 "PA: 0x%02x PB: 0x%02x\n",
731 gpio_in_available, gpio_out_available,
732 pa_available, pb_available));
867 733
868 spin_lock_irqsave(&gpio_lock, flags); 734 spin_lock_irqsave(&gpio_lock, flags);
869 735
@@ -872,7 +738,7 @@ void ioif_watcher(const unsigned int gpio_in_available,
872 738
873 /* Initialise the dir_g_shadow etc. depending on genconfig */ 739 /* Initialise the dir_g_shadow etc. depending on genconfig */
874 /* 0=input 1=output */ 740 /* 0=input 1=output */
875 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out)) 741 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out))
876 dir_g_shadow |= (1 << 0); 742 dir_g_shadow |= (1 << 0);
877 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out)) 743 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out))
878 dir_g_shadow |= 0x0000FF00; 744 dir_g_shadow |= 0x0000FF00;
@@ -884,7 +750,8 @@ void ioif_watcher(const unsigned int gpio_in_available,
884 changeable_dir_g = changeable_dir_g_mask; 750 changeable_dir_g = changeable_dir_g_mask;
885 changeable_dir_g &= dir_g_out_bits; 751 changeable_dir_g &= dir_g_out_bits;
886 changeable_dir_g &= dir_g_in_bits; 752 changeable_dir_g &= dir_g_in_bits;
887 /* Correct the bits that can change direction */ 753
754 /* Correct the bits that can change direction */
888 dir_g_out_bits &= ~changeable_dir_g; 755 dir_g_out_bits &= ~changeable_dir_g;
889 dir_g_out_bits |= dir_g_shadow; 756 dir_g_out_bits |= dir_g_shadow;
890 dir_g_in_bits &= ~changeable_dir_g; 757 dir_g_in_bits &= ~changeable_dir_g;
@@ -892,7 +759,8 @@ void ioif_watcher(const unsigned int gpio_in_available,
892 759
893 spin_unlock_irqrestore(&gpio_lock, flags); 760 spin_unlock_irqrestore(&gpio_lock, flags);
894 761
895 printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX val: %08lX\n", 762 printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX "
763 "val: %08lX\n",
896 dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA); 764 dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA);
897 printk(KERN_INFO "GPIO port G: dir: %08lX changeable: %08lX\n", 765 printk(KERN_INFO "GPIO port G: dir: %08lX changeable: %08lX\n",
898 dir_g_shadow, changeable_dir_g); 766 dir_g_shadow, changeable_dir_g);
@@ -900,16 +768,12 @@ void ioif_watcher(const unsigned int gpio_in_available,
900 768
901/* main driver initialization routine, called from mem.c */ 769/* main driver initialization routine, called from mem.c */
902 770
903static __init int 771static int __init gpio_init(void)
904gpio_init(void)
905{ 772{
906 int res; 773 int res;
907#if defined (CONFIG_ETRAX_CSP0_LEDS) 774#if defined (CONFIG_ETRAX_CSP0_LEDS)
908 int i; 775 int i;
909#endif 776#endif
910 printk("gpio init\n");
911
912 /* do the formalities */
913 777
914 res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops); 778 res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
915 if (res < 0) { 779 if (res < 0) {
@@ -919,43 +783,45 @@ gpio_init(void)
919 783
920 /* Clear all leds */ 784 /* Clear all leds */
921#if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS) 785#if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS)
922 LED_NETWORK_SET(0); 786 CRIS_LED_NETWORK_SET(0);
923 LED_ACTIVE_SET(0); 787 CRIS_LED_ACTIVE_SET(0);
924 LED_DISK_READ(0); 788 CRIS_LED_DISK_READ(0);
925 LED_DISK_WRITE(0); 789 CRIS_LED_DISK_WRITE(0);
926 790
927#if defined (CONFIG_ETRAX_CSP0_LEDS) 791#if defined (CONFIG_ETRAX_CSP0_LEDS)
928 for (i = 0; i < 32; i++) { 792 for (i = 0; i < 32; i++)
929 LED_BIT_SET(i); 793 CRIS_LED_BIT_SET(i);
930 }
931#endif 794#endif
932 795
933#endif 796#endif
934 /* The I/O interface allocation watcher will be called when 797 /* The I/O interface allocation watcher will be called when
935 * registering it. */ 798 * registering it. */
936 if (cris_io_interface_register_watcher(ioif_watcher)){ 799 if (cris_io_interface_register_watcher(ioif_watcher)){
937 printk(KERN_WARNING "gpio_init: Failed to install IO if allocator watcher\n"); 800 printk(KERN_WARNING "gpio_init: Failed to install IO "
801 "if allocator watcher\n");
938 } 802 }
939 803
940 printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001, 2002, 2003, 2004 Axis Communications AB\n"); 804 printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001-2008 "
805 "Axis Communications AB\n");
941 /* We call etrax_gpio_wake_up_check() from timer interrupt and 806 /* We call etrax_gpio_wake_up_check() from timer interrupt and
942 * from cpu_idle() in kernel/process.c 807 * from cpu_idle() in kernel/process.c
943 * The check in cpu_idle() reduces latency from ~15 ms to ~6 ms 808 * The check in cpu_idle() reduces latency from ~15 ms to ~6 ms
944 * in some tests. 809 * in some tests.
945 */ 810 */
946 if (request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt, 811 res = request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt,
947 IRQF_SHARED | IRQF_DISABLED,"gpio poll", NULL)) { 812 IRQF_SHARED | IRQF_DISABLED, "gpio poll", gpio_name);
813 if (res) {
948 printk(KERN_CRIT "err: timer0 irq for gpio\n"); 814 printk(KERN_CRIT "err: timer0 irq for gpio\n");
815 return res;
949 } 816 }
950 if (request_irq(PA_IRQ_NBR, gpio_pa_interrupt, 817 res = request_irq(PA_IRQ_NBR, gpio_interrupt,
951 IRQF_SHARED | IRQF_DISABLED,"gpio PA", NULL)) { 818 IRQF_SHARED | IRQF_DISABLED, "gpio PA", gpio_name);
819 if (res)
952 printk(KERN_CRIT "err: PA irq for gpio\n"); 820 printk(KERN_CRIT "err: PA irq for gpio\n");
953 }
954
955 821
956 return res; 822 return res;
957} 823}
958 824
959/* this makes sure that gpio_init is called during kernel boot */ 825/* this makes sure that gpio_init is called during kernel boot */
960
961module_init(gpio_init); 826module_init(gpio_init);
827
diff --git a/arch/cris/arch-v10/drivers/i2c.c b/arch/cris/arch-v10/drivers/i2c.c
index aca81ddaf60f..d6d22067d0c8 100644
--- a/arch/cris/arch-v10/drivers/i2c.c
+++ b/arch/cris/arch-v10/drivers/i2c.c
@@ -6,85 +6,9 @@
6*! kernel modules (i2c_writereg/readreg) and from userspace using 6*! kernel modules (i2c_writereg/readreg) and from userspace using
7*! ioctl()'s 7*! ioctl()'s
8*! 8*!
9*! Nov 30 1998 Torbjorn Eliasson Initial version. 9*! (C) Copyright 1999-2007 Axis Communications AB, LUND, SWEDEN
10*! Bjorn Wesen Elinux kernel version.
11*! Jan 14 2000 Johan Adolfsson Fixed PB shadow register stuff -
12*! don't use PB_I2C if DS1302 uses same bits,
13*! use PB.
14*! $Log: i2c.c,v $
15*! Revision 1.13 2005/03/07 13:13:07 starvik
16*! Added spinlocks to protect states etc
17*!
18*! Revision 1.12 2005/01/05 06:11:22 starvik
19*! No need to do local_irq_disable after local_irq_save.
20*!
21*! Revision 1.11 2004/12/13 12:21:52 starvik
22*! Added I/O and DMA allocators from Linux 2.4
23*!
24*! Revision 1.9 2004/08/24 06:49:14 starvik
25*! Whitespace cleanup
26*!
27*! Revision 1.8 2004/06/08 08:48:26 starvik
28*! Removed unused code
29*!
30*! Revision 1.7 2004/05/28 09:26:59 starvik
31*! Modified I2C initialization to work in 2.6.
32*!
33*! Revision 1.6 2004/05/14 07:58:03 starvik
34*! Merge of changes from 2.4
35*!
36*! Revision 1.4 2002/12/11 13:13:57 starvik
37*! Added arch/ to v10 specific includes
38*! Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
39*!
40*! Revision 1.3 2002/11/20 11:56:11 starvik
41*! Merge of Linux 2.5.48
42*!
43*! Revision 1.2 2002/11/18 13:16:06 starvik
44*! Linux 2.5 port of latest 2.4 drivers
45*!
46*! Revision 1.9 2002/10/31 15:32:26 starvik
47*! Update Port B register and shadow even when running with hardware support
48*! to avoid glitches when reading bits
49*! Never set direction to out in i2c_inbyte
50*! Removed incorrect clock toggling at end of i2c_inbyte
51*!
52*! Revision 1.8 2002/08/13 06:31:53 starvik
53*! Made SDA and SCL line configurable
54*! Modified i2c_inbyte to work with PCF8563
55*!
56*! Revision 1.7 2001/04/04 13:11:36 markusl
57*! Updated according to review remarks
58*!
59*! Revision 1.6 2001/03/19 12:43:00 markusl
60*! Made some symbols unstatic (used by the eeprom driver)
61*!
62*! Revision 1.5 2001/02/27 13:52:48 bjornw
63*! malloc.h -> slab.h
64*!
65*! Revision 1.4 2001/02/15 07:17:40 starvik
66*! Corrected usage if port_pb_i2c_shadow
67*!
68*! Revision 1.3 2001/01/26 17:55:13 bjornw
69*! * Made I2C_USES_PB_NOT_PB_I2C a CONFIG option instead of assigning it
70*! magically. Config.in needs to set it for the options that need it, like
71*! Dallas 1302 support. Actually, it should be default since it screws up
72*! the PB bits even if you don't use I2C..
73*! * Include linux/config.h to get the above
74*!
75*! Revision 1.2 2001/01/18 15:49:30 bjornw
76*! 2.4 port of I2C including some cleanups (untested of course)
77*!
78*! Revision 1.1 2001/01/18 15:35:25 bjornw
79*! Verbatim copy of the Etrax i2c driver, 2.0 elinux version
80*!
81*!
82*! ---------------------------------------------------------------------------
83*!
84*! (C) Copyright 1999-2002 Axis Communications AB, LUND, SWEDEN
85*! 10*!
86*!***************************************************************************/ 11*!***************************************************************************/
87/* $Id: i2c.c,v 1.13 2005/03/07 13:13:07 starvik Exp $ */
88 12
89/****************** INCLUDE FILES SECTION ***********************************/ 13/****************** INCLUDE FILES SECTION ***********************************/
90 14
@@ -622,7 +546,7 @@ i2c_readreg(unsigned char theSlave, unsigned char theReg)
622 * last received byte needs to be nacked 546 * last received byte needs to be nacked
623 * instead of acked 547 * instead of acked
624 */ 548 */
625 i2c_sendack(); 549 i2c_sendnack();
626 /* 550 /*
627 * end sequence 551 * end sequence
628 */ 552 */
@@ -708,6 +632,7 @@ i2c_init(void)
708 if (!first) { 632 if (!first) {
709 return res; 633 return res;
710 } 634 }
635 first = 0;
711 636
712 /* Setup and enable the Port B I2C interface */ 637 /* Setup and enable the Port B I2C interface */
713 638
diff --git a/arch/cris/arch-v10/drivers/pcf8563.c b/arch/cris/arch-v10/drivers/pcf8563.c
index c263b8232dbc..52103d16dc6c 100644
--- a/arch/cris/arch-v10/drivers/pcf8563.c
+++ b/arch/cris/arch-v10/drivers/pcf8563.c
@@ -8,14 +8,13 @@
8 * low detector are also provided. All address and data are transferred 8 * low detector are also provided. All address and data are transferred
9 * serially via two-line bidirectional I2C-bus. Maximum bus speed is 9 * serially via two-line bidirectional I2C-bus. Maximum bus speed is
10 * 400 kbits/s. The built-in word address register is incremented 10 * 400 kbits/s. The built-in word address register is incremented
11 * automatically after each written or read bute. 11 * automatically after each written or read byte.
12 * 12 *
13 * Copyright (c) 2002, Axis Communications AB 13 * Copyright (c) 2002-2007, Axis Communications AB
14 * All rights reserved. 14 * All rights reserved.
15 * 15 *
16 * Author: Tobias Anderberg <tobiasa@axis.com>. 16 * Author: Tobias Anderberg <tobiasa@axis.com>.
17 * 17 *
18 * $Id: pcf8563.c,v 1.11 2005/03/07 13:13:07 starvik Exp $
19 */ 18 */
20 19
21#include <linux/module.h> 20#include <linux/module.h>
@@ -27,19 +26,19 @@
27#include <linux/ioctl.h> 26#include <linux/ioctl.h>
28#include <linux/delay.h> 27#include <linux/delay.h>
29#include <linux/bcd.h> 28#include <linux/bcd.h>
30#include <linux/capability.h> 29#include <linux/mutex.h>
31 30
32#include <asm/uaccess.h> 31#include <asm/uaccess.h>
33#include <asm/system.h> 32#include <asm/system.h>
34#include <asm/io.h> 33#include <asm/io.h>
35#include <asm/arch/svinto.h>
36#include <asm/rtc.h> 34#include <asm/rtc.h>
35
37#include "i2c.h" 36#include "i2c.h"
38 37
39#define PCF8563_MAJOR 121 /* Local major number. */ 38#define PCF8563_MAJOR 121 /* Local major number. */
40#define DEVICE_NAME "rtc" /* Name which is registered in /proc/devices. */ 39#define DEVICE_NAME "rtc" /* Name which is registered in /proc/devices. */
41#define PCF8563_NAME "PCF8563" 40#define PCF8563_NAME "PCF8563"
42#define DRIVER_VERSION "$Revision: 1.11 $" 41#define DRIVER_VERSION "$Revision: 1.24 $"
43 42
44/* I2C bus slave registers. */ 43/* I2C bus slave registers. */
45#define RTC_I2C_READ 0xa3 44#define RTC_I2C_READ 0xa3
@@ -49,71 +48,88 @@
49#define rtc_read(x) i2c_readreg(RTC_I2C_READ, x) 48#define rtc_read(x) i2c_readreg(RTC_I2C_READ, x)
50#define rtc_write(x,y) i2c_writereg(RTC_I2C_WRITE, x, y) 49#define rtc_write(x,y) i2c_writereg(RTC_I2C_WRITE, x, y)
51 50
52static DEFINE_SPINLOCK(rtc_lock); /* Protect state etc */ 51static DEFINE_MUTEX(rtc_lock); /* Protect state etc */
53 52
54static const unsigned char days_in_month[] = 53static const unsigned char days_in_month[] =
55 { 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; 54 { 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
56 55
57int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long); 56int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
58 57
58/* Cache VL bit value read at driver init since writing the RTC_SECOND
59 * register clears the VL status.
60 */
61static int voltage_low;
62
59static const struct file_operations pcf8563_fops = { 63static const struct file_operations pcf8563_fops = {
60 .owner = THIS_MODULE, 64 .owner = THIS_MODULE,
61 .ioctl = pcf8563_ioctl, 65 .ioctl = pcf8563_ioctl,
62}; 66};
63 67
64unsigned char 68unsigned char
65pcf8563_readreg(int reg) 69pcf8563_readreg(int reg)
66{ 70{
67 unsigned char res = i2c_readreg(RTC_I2C_READ, reg); 71 unsigned char res = rtc_read(reg);
68 72
69 /* The PCF8563 does not return 0 for unimplemented bits */ 73 /* The PCF8563 does not return 0 for unimplemented bits. */
70 switch(reg) 74 switch (reg) {
71 { 75 case RTC_SECONDS:
72 case RTC_SECONDS: 76 case RTC_MINUTES:
73 case RTC_MINUTES: 77 res &= 0x7F;
74 res &= 0x7f; 78 break;
75 break; 79 case RTC_HOURS:
76 case RTC_HOURS: 80 case RTC_DAY_OF_MONTH:
77 case RTC_DAY_OF_MONTH: 81 res &= 0x3F;
78 res &= 0x3f; 82 break;
79 break; 83 case RTC_WEEKDAY:
80 case RTC_MONTH: 84 res &= 0x07;
81 res = (res & 0x1f) - 1; /* PCF8563 returns month in range 1-12 */ 85 break;
82 break; 86 case RTC_MONTH:
87 res &= 0x1F;
88 break;
89 case RTC_CONTROL1:
90 res &= 0xA8;
91 break;
92 case RTC_CONTROL2:
93 res &= 0x1F;
94 break;
95 case RTC_CLOCKOUT_FREQ:
96 case RTC_TIMER_CONTROL:
97 res &= 0x83;
98 break;
83 } 99 }
84 return res; 100 return res;
85} 101}
86 102
87void 103void
88pcf8563_writereg(int reg, unsigned char val) 104pcf8563_writereg(int reg, unsigned char val)
89{ 105{
90#ifdef CONFIG_ETRAX_RTC_READONLY
91 if (reg == RTC_CONTROL1 || (reg >= RTC_SECONDS && reg <= RTC_YEAR))
92 return;
93#endif
94
95 rtc_write(reg, val); 106 rtc_write(reg, val);
96} 107}
97 108
98void 109void
99get_rtc_time(struct rtc_time *tm) 110get_rtc_time(struct rtc_time *tm)
100{ 111{
101 tm->tm_sec = rtc_read(RTC_SECONDS); 112 tm->tm_sec = rtc_read(RTC_SECONDS);
102 tm->tm_min = rtc_read(RTC_MINUTES); 113 tm->tm_min = rtc_read(RTC_MINUTES);
103 tm->tm_hour = rtc_read(RTC_HOURS); 114 tm->tm_hour = rtc_read(RTC_HOURS);
104 tm->tm_mday = rtc_read(RTC_DAY_OF_MONTH); 115 tm->tm_mday = rtc_read(RTC_DAY_OF_MONTH);
105 tm->tm_mon = rtc_read(RTC_MONTH); 116 tm->tm_wday = rtc_read(RTC_WEEKDAY);
117 tm->tm_mon = rtc_read(RTC_MONTH);
106 tm->tm_year = rtc_read(RTC_YEAR); 118 tm->tm_year = rtc_read(RTC_YEAR);
107 119
108 if (tm->tm_sec & 0x80) 120 if (tm->tm_sec & 0x80) {
109 printk(KERN_WARNING "%s: RTC Low Voltage - date/time is not reliable!\n", PCF8563_NAME); 121 printk(KERN_ERR "%s: RTC Voltage Low - reliable date/time "
122 "information is no longer guaranteed!\n", PCF8563_NAME);
123 }
110 124
111 tm->tm_year = BCD_TO_BIN(tm->tm_year) + ((tm->tm_mon & 0x80) ? 100 : 0); 125 tm->tm_year = BCD_TO_BIN(tm->tm_year) +
112 tm->tm_sec &= 0x7f; 126 ((tm->tm_mon & 0x80) ? 100 : 0);
113 tm->tm_min &= 0x7f; 127 tm->tm_sec &= 0x7F;
114 tm->tm_hour &= 0x3f; 128 tm->tm_min &= 0x7F;
115 tm->tm_mday &= 0x3f; 129 tm->tm_hour &= 0x3F;
116 tm->tm_mon &= 0x1f; 130 tm->tm_mday &= 0x3F;
131 tm->tm_wday &= 0x07; /* Not coded in BCD. */
132 tm->tm_mon &= 0x1F;
117 133
118 BCD_TO_BIN(tm->tm_sec); 134 BCD_TO_BIN(tm->tm_sec);
119 BCD_TO_BIN(tm->tm_min); 135 BCD_TO_BIN(tm->tm_min);
@@ -126,17 +142,24 @@ get_rtc_time(struct rtc_time *tm)
126int __init 142int __init
127pcf8563_init(void) 143pcf8563_init(void)
128{ 144{
129 int ret; 145 static int res;
130 146 static int first = 1;
131 if ((ret = i2c_init())) { 147
132 printk(KERN_CRIT "pcf8563_init: failed to init i2c\n"); 148 if (!first)
133 return ret; 149 return res;
150 first = 0;
151
152 /* Initiate the i2c protocol. */
153 res = i2c_init();
154 if (res < 0) {
155 printk(KERN_CRIT "pcf8563_init: Failed to init i2c.\n");
156 return res;
134 } 157 }
135 158
136 /* 159 /*
137 * First of all we need to reset the chip. This is done by 160 * First of all we need to reset the chip. This is done by
138 * clearing control1, control2 and clk freq, clear the 161 * clearing control1, control2 and clk freq and resetting
139 * Voltage Low bit, and resetting all alarms. 162 * all alarms.
140 */ 163 */
141 if (rtc_write(RTC_CONTROL1, 0x00) < 0) 164 if (rtc_write(RTC_CONTROL1, 0x00) < 0)
142 goto err; 165 goto err;
@@ -147,34 +170,36 @@ pcf8563_init(void)
147 if (rtc_write(RTC_CLOCKOUT_FREQ, 0x00) < 0) 170 if (rtc_write(RTC_CLOCKOUT_FREQ, 0x00) < 0)
148 goto err; 171 goto err;
149 172
150 /* Clear the VL bit in the seconds register. */ 173 if (rtc_write(RTC_TIMER_CONTROL, 0x03) < 0)
151 ret = rtc_read(RTC_SECONDS);
152
153 if (rtc_write(RTC_SECONDS, (ret & 0x7f)) < 0)
154 goto err; 174 goto err;
155 175
156 /* Reset the alarms. */ 176 /* Reset the alarms. */
157 if (rtc_write(RTC_MINUTE_ALARM, 0x00) < 0) 177 if (rtc_write(RTC_MINUTE_ALARM, 0x80) < 0)
158 goto err; 178 goto err;
159 179
160 if (rtc_write(RTC_HOUR_ALARM, 0x00) < 0) 180 if (rtc_write(RTC_HOUR_ALARM, 0x80) < 0)
161 goto err; 181 goto err;
162 182
163 if (rtc_write(RTC_DAY_ALARM, 0x00) < 0) 183 if (rtc_write(RTC_DAY_ALARM, 0x80) < 0)
164 goto err; 184 goto err;
165 185
166 if (rtc_write(RTC_WEEKDAY_ALARM, 0x00) < 0) 186 if (rtc_write(RTC_WEEKDAY_ALARM, 0x80) < 0)
167 goto err; 187 goto err;
168 188
169 /* Check for low voltage, and warn about it.. */ 189 /* Check for low voltage, and warn about it. */
170 if (rtc_read(RTC_SECONDS) & 0x80) 190 if (rtc_read(RTC_SECONDS) & 0x80) {
171 printk(KERN_WARNING "%s: RTC Low Voltage - date/time is not reliable!\n", PCF8563_NAME); 191 voltage_low = 1;
172 192 printk(KERN_WARNING "%s: RTC Voltage Low - reliable "
173 return 0; 193 "date/time information is no longer guaranteed!\n",
194 PCF8563_NAME);
195 }
196
197 return res;
174 198
175err: 199err:
176 printk(KERN_INFO "%s: Error initializing chip.\n", PCF8563_NAME); 200 printk(KERN_INFO "%s: Error initializing chip.\n", PCF8563_NAME);
177 return -1; 201 res = -1;
202 return res;
178} 203}
179 204
180void __exit 205void __exit
@@ -187,8 +212,8 @@ pcf8563_exit(void)
187 * ioctl calls for this driver. Why return -ENOTTY upon error? Because 212 * ioctl calls for this driver. Why return -ENOTTY upon error? Because
188 * POSIX says so! 213 * POSIX says so!
189 */ 214 */
190int 215int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
191pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) 216 unsigned long arg)
192{ 217{
193 /* Some sanity checks. */ 218 /* Some sanity checks. */
194 if (_IOC_TYPE(cmd) != RTC_MAGIC) 219 if (_IOC_TYPE(cmd) != RTC_MAGIC)
@@ -198,124 +223,146 @@ pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned
198 return -ENOTTY; 223 return -ENOTTY;
199 224
200 switch (cmd) { 225 switch (cmd) {
201 case RTC_RD_TIME: 226 case RTC_RD_TIME:
202 { 227 {
203 struct rtc_time tm; 228 struct rtc_time tm;
204
205 spin_lock(&rtc_lock);
206 get_rtc_time(&tm);
207
208 if (copy_to_user((struct rtc_time *) arg, &tm, sizeof(struct rtc_time))) {
209 spin_unlock(&rtc_lock);
210 return -EFAULT;
211 }
212
213 spin_unlock(&rtc_lock);
214 return 0;
215 }
216 break;
217 case RTC_SET_TIME:
218 {
219#ifdef CONFIG_ETRAX_RTC_READONLY
220 return -EPERM;
221#else
222 int leap;
223 int century;
224 struct rtc_time tm;
225
226 memset(&tm, 0, sizeof (struct rtc_time));
227 if (!capable(CAP_SYS_TIME))
228 return -EPERM;
229
230 if (copy_from_user(&tm, (struct rtc_time *) arg, sizeof(struct rtc_time)))
231 return -EFAULT;
232
233 /* Convert from struct tm to struct rtc_time. */
234 tm.tm_year += 1900;
235 tm.tm_mon += 1;
236
237 leap = ((tm.tm_mon == 2) && ((tm.tm_year % 4) == 0)) ? 1 : 0;
238
239 /* Perform some sanity checks. */
240 if ((tm.tm_year < 1970) ||
241 (tm.tm_mon > 12) ||
242 (tm.tm_mday == 0) ||
243 (tm.tm_mday > days_in_month[tm.tm_mon] + leap) ||
244 (tm.tm_hour >= 24) ||
245 (tm.tm_min >= 60) ||
246 (tm.tm_sec >= 60))
247 return -EINVAL;
248
249 century = (tm.tm_year >= 2000) ? 0x80 : 0;
250 tm.tm_year = tm.tm_year % 100;
251
252 BIN_TO_BCD(tm.tm_year);
253 BIN_TO_BCD(tm.tm_mday);
254 BIN_TO_BCD(tm.tm_hour);
255 BIN_TO_BCD(tm.tm_min);
256 BIN_TO_BCD(tm.tm_sec);
257 tm.tm_mon |= century;
258
259 spin_lock(&rtc_lock);
260
261 rtc_write(RTC_YEAR, tm.tm_year);
262 rtc_write(RTC_MONTH, tm.tm_mon);
263 rtc_write(RTC_DAY_OF_MONTH, tm.tm_mday);
264 rtc_write(RTC_HOURS, tm.tm_hour);
265 rtc_write(RTC_MINUTES, tm.tm_min);
266 rtc_write(RTC_SECONDS, tm.tm_sec);
267
268 spin_unlock(&rtc_lock);
269
270 return 0;
271#endif /* !CONFIG_ETRAX_RTC_READONLY */
272 }
273
274 case RTC_VLOW_RD:
275 {
276 int vl_bit = 0;
277
278 if (rtc_read(RTC_SECONDS) & 0x80) {
279 vl_bit = 1;
280 printk(KERN_WARNING "%s: RTC Voltage Low - reliable "
281 "date/time information is no longer guaranteed!\n",
282 PCF8563_NAME);
283 }
284 if (copy_to_user((int *) arg, &vl_bit, sizeof(int)))
285 return -EFAULT;
286
287 return 0;
288 }
289 229
290 case RTC_VLOW_SET: 230 mutex_lock(&rtc_lock);
291 { 231 memset(&tm, 0, sizeof tm);
292 /* Clear the VL bit in the seconds register */ 232 get_rtc_time(&tm);
293 int ret = rtc_read(RTC_SECONDS);
294 233
295 rtc_write(RTC_SECONDS, (ret & 0x7F)); 234 if (copy_to_user((struct rtc_time *) arg, &tm,
235 sizeof tm)) {
236 spin_unlock(&rtc_lock);
237 return -EFAULT;
238 }
239
240 mutex_unlock(&rtc_lock);
296 241
297 return 0; 242 return 0;
243 }
244 case RTC_SET_TIME:
245 {
246 int leap;
247 int year;
248 int century;
249 struct rtc_time tm;
250
251 memset(&tm, 0, sizeof tm);
252 if (!capable(CAP_SYS_TIME))
253 return -EPERM;
254
255 if (copy_from_user(&tm, (struct rtc_time *) arg, sizeof tm))
256 return -EFAULT;
257
258 /* Convert from struct tm to struct rtc_time. */
259 tm.tm_year += 1900;
260 tm.tm_mon += 1;
261
262 /*
263 * Check if tm.tm_year is a leap year. A year is a leap
264 * year if it is divisible by 4 but not 100, except
265 * that years divisible by 400 _are_ leap years.
266 */
267 year = tm.tm_year;
268 leap = (tm.tm_mon == 2) &&
269 ((year % 4 == 0 && year % 100 != 0) || year % 400 == 0);
270
271 /* Perform some sanity checks. */
272 if ((tm.tm_year < 1970) ||
273 (tm.tm_mon > 12) ||
274 (tm.tm_mday == 0) ||
275 (tm.tm_mday > days_in_month[tm.tm_mon] + leap) ||
276 (tm.tm_wday >= 7) ||
277 (tm.tm_hour >= 24) ||
278 (tm.tm_min >= 60) ||
279 (tm.tm_sec >= 60))
280 return -EINVAL;
281
282 century = (tm.tm_year >= 2000) ? 0x80 : 0;
283 tm.tm_year = tm.tm_year % 100;
284
285 BIN_TO_BCD(tm.tm_year);
286 BIN_TO_BCD(tm.tm_mon);
287 BIN_TO_BCD(tm.tm_mday);
288 BIN_TO_BCD(tm.tm_hour);
289 BIN_TO_BCD(tm.tm_min);
290 BIN_TO_BCD(tm.tm_sec);
291 tm.tm_mon |= century;
292
293 mutex_lock(&rtc_lock);
294
295 rtc_write(RTC_YEAR, tm.tm_year);
296 rtc_write(RTC_MONTH, tm.tm_mon);
297 rtc_write(RTC_WEEKDAY, tm.tm_wday); /* Not coded in BCD. */
298 rtc_write(RTC_DAY_OF_MONTH, tm.tm_mday);
299 rtc_write(RTC_HOURS, tm.tm_hour);
300 rtc_write(RTC_MINUTES, tm.tm_min);
301 rtc_write(RTC_SECONDS, tm.tm_sec);
302
303 mutex_unlock(&rtc_lock);
304
305 return 0;
306 }
307 case RTC_VL_READ:
308 if (voltage_low) {
309 printk(KERN_ERR "%s: RTC Voltage Low - "
310 "reliable date/time information is no "
311 "longer guaranteed!\n", PCF8563_NAME);
298 } 312 }
299 313
300 default: 314 if (copy_to_user((int *) arg, &voltage_low, sizeof(int)))
301 return -ENOTTY; 315 return -EFAULT;
316 return 0;
317
318 case RTC_VL_CLR:
319 {
320 /* Clear the VL bit in the seconds register in case
321 * the time has not been set already (which would
322 * have cleared it). This does not really matter
323 * because of the cached voltage_low value but do it
324 * anyway for consistency. */
325
326 int ret = rtc_read(RTC_SECONDS);
327
328 rtc_write(RTC_SECONDS, (ret & 0x7F));
329
330 /* Clear the cached value. */
331 voltage_low = 0;
332
333 return 0;
334 }
335 default:
336 return -ENOTTY;
302 } 337 }
303 338
304 return 0; 339 return 0;
305} 340}
306 341
307static int __init 342static int __init pcf8563_register(void)
308pcf8563_register(void)
309{ 343{
310 pcf8563_init(); 344 if (pcf8563_init() < 0) {
345 printk(KERN_INFO "%s: Unable to initialize Real-Time Clock "
346 "Driver, %s\n", PCF8563_NAME, DRIVER_VERSION);
347 return -1;
348 }
349
311 if (register_chrdev(PCF8563_MAJOR, DEVICE_NAME, &pcf8563_fops) < 0) { 350 if (register_chrdev(PCF8563_MAJOR, DEVICE_NAME, &pcf8563_fops) < 0) {
312 printk(KERN_INFO "%s: Unable to get major number %d for RTC device.\n", 351 printk(KERN_INFO "%s: Unable to get major number %d for RTC device.\n",
313 PCF8563_NAME, PCF8563_MAJOR); 352 PCF8563_NAME, PCF8563_MAJOR);
314 return -1; 353 return -1;
315 } 354 }
316 355
317 printk(KERN_INFO "%s Real-Time Clock Driver, %s\n", PCF8563_NAME, DRIVER_VERSION); 356 printk(KERN_INFO "%s Real-Time Clock Driver, %s\n", PCF8563_NAME,
318 return 0; 357 DRIVER_VERSION);
358
359 /* Check for low voltage, and warn about it. */
360 if (voltage_low) {
361 printk(KERN_WARNING "%s: RTC Voltage Low - reliable date/time "
362 "information is no longer guaranteed!\n", PCF8563_NAME);
363 }
364
365 return 0;
319} 366}
320 367
321module_init(pcf8563_register); 368module_init(pcf8563_register);
diff --git a/arch/cris/arch-v10/drivers/sync_serial.c b/arch/cris/arch-v10/drivers/sync_serial.c
new file mode 100644
index 000000000000..069546e342c5
--- /dev/null
+++ b/arch/cris/arch-v10/drivers/sync_serial.c
@@ -0,0 +1,1441 @@
1/*
2 * Simple synchronous serial port driver for ETRAX 100LX.
3 *
4 * Synchronous serial ports are used for continuous streamed data like audio.
5 * The default setting for this driver is compatible with the STA 013 MP3
6 * decoder. The driver can easily be tuned to fit other audio encoder/decoders
7 * and SPI
8 *
9 * Copyright (c) 2001-2008 Axis Communications AB
10 *
11 * Author: Mikael Starvik, Johan Adolfsson
12 *
13 */
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/errno.h>
18#include <linux/major.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/interrupt.h>
22#include <linux/poll.h>
23#include <linux/init.h>
24#include <linux/timer.h>
25#include <asm/irq.h>
26#include <asm/dma.h>
27#include <asm/io.h>
28#include <asm/arch/svinto.h>
29#include <asm/uaccess.h>
30#include <asm/system.h>
31#include <asm/sync_serial.h>
32#include <asm/arch/io_interface_mux.h>
33
34/* The receiver is a bit tricky beacuse of the continuous stream of data.*/
35/* */
36/* Three DMA descriptors are linked together. Each DMA descriptor is */
37/* responsible for port->bufchunk of a common buffer. */
38/* */
39/* +---------------------------------------------+ */
40/* | +----------+ +----------+ +----------+ | */
41/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */
42/* +----------+ +----------+ +----------+ */
43/* | | | */
44/* v v v */
45/* +-------------------------------------+ */
46/* | BUFFER | */
47/* +-------------------------------------+ */
48/* |<- data_avail ->| */
49/* readp writep */
50/* */
51/* If the application keeps up the pace readp will be right after writep.*/
52/* If the application can't keep the pace we have to throw away data. */
53/* The idea is that readp should be ready with the data pointed out by */
54/* Descr[i] when the DMA has filled in Descr[i+1]. */
55/* Otherwise we will discard */
56/* the rest of the data pointed out by Descr1 and set readp to the start */
57/* of Descr2 */
58
59#define SYNC_SERIAL_MAJOR 125
60
61/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */
62/* words can be handled */
63#define IN_BUFFER_SIZE 12288
64#define IN_DESCR_SIZE 256
65#define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE)
66#define OUT_BUFFER_SIZE 4096
67
68#define DEFAULT_FRAME_RATE 0
69#define DEFAULT_WORD_RATE 7
70
71/* NOTE: Enabling some debug will likely cause overrun or underrun,
72 * especially if manual mode is use.
73 */
74#define DEBUG(x)
75#define DEBUGREAD(x)
76#define DEBUGWRITE(x)
77#define DEBUGPOLL(x)
78#define DEBUGRXINT(x)
79#define DEBUGTXINT(x)
80
81/* Define some macros to access ETRAX 100 registers */
82#define SETF(var, reg, field, val) \
83 do { \
84 var = (var & ~IO_MASK_(reg##_, field##_)) | \
85 IO_FIELD_(reg##_, field##_, val); \
86 } while (0)
87
88#define SETS(var, reg, field, val) \
89 do { \
90 var = (var & ~IO_MASK_(reg##_, field##_)) | \
91 IO_STATE_(reg##_, field##_, _##val); \
92 } while (0)
93
94struct sync_port {
95 /* Etrax registers and bits*/
96 const volatile unsigned *const status;
97 volatile unsigned *const ctrl_data;
98 volatile unsigned *const output_dma_first;
99 volatile unsigned char *const output_dma_cmd;
100 volatile unsigned char *const output_dma_clr_irq;
101 volatile unsigned *const input_dma_first;
102 volatile unsigned char *const input_dma_cmd;
103 volatile unsigned *const input_dma_descr;
104 /* 8*4 */
105 volatile unsigned char *const input_dma_clr_irq;
106 volatile unsigned *const data_out;
107 const volatile unsigned *const data_in;
108 char data_avail_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
109 char transmitter_ready_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
110 char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */
111
112 char output_dma_bit; /* In R_IRQ_MASK2_RD */
113 /* End of fields initialised in array */
114 char started; /* 1 if port has been started */
115 char port_nbr; /* Port 0 or 1 */
116 char busy; /* 1 if port is busy */
117
118 char enabled; /* 1 if port is enabled */
119 char use_dma; /* 1 if port uses dma */
120 char tr_running;
121
122 char init_irqs;
123
124 /* Register shadow */
125 unsigned int ctrl_data_shadow;
126 /* Remaining bytes for current transfer */
127 volatile unsigned int out_count;
128 /* Current position in out_buffer */
129 unsigned char *outp;
130 /* 16*4 */
131 /* Next byte to be read by application */
132 volatile unsigned char *volatile readp;
133 /* Next byte to be written by etrax */
134 volatile unsigned char *volatile writep;
135
136 unsigned int in_buffer_size;
137 unsigned int inbufchunk;
138 struct etrax_dma_descr out_descr __attribute__ ((aligned(32)));
139 struct etrax_dma_descr in_descr[NUM_IN_DESCR] __attribute__ ((aligned(32)));
140 unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32)));
141 unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32)));
142 unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32)));
143 struct etrax_dma_descr *next_rx_desc;
144 struct etrax_dma_descr *prev_rx_desc;
145 int full;
146
147 wait_queue_head_t out_wait_q;
148 wait_queue_head_t in_wait_q;
149};
150
151
152static int etrax_sync_serial_init(void);
153static void initialize_port(int portnbr);
154static inline int sync_data_avail(struct sync_port *port);
155
156static int sync_serial_open(struct inode *inode, struct file *file);
157static int sync_serial_release(struct inode *inode, struct file *file);
158static unsigned int sync_serial_poll(struct file *filp, poll_table *wait);
159
160static int sync_serial_ioctl(struct inode *inode, struct file *file,
161 unsigned int cmd, unsigned long arg);
162static ssize_t sync_serial_write(struct file *file, const char *buf,
163 size_t count, loff_t *ppos);
164static ssize_t sync_serial_read(struct file *file, char *buf,
165 size_t count, loff_t *ppos);
166
167#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
168 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
169 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
170 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
171#define SYNC_SER_DMA
172#endif
173
174static void send_word(struct sync_port *port);
175static void start_dma(struct sync_port *port, const char *data, int count);
176static void start_dma_in(struct sync_port *port);
177#ifdef SYNC_SER_DMA
178static irqreturn_t tr_interrupt(int irq, void *dev_id);
179static irqreturn_t rx_interrupt(int irq, void *dev_id);
180#endif
181#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
182 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
183 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
184 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
185#define SYNC_SER_MANUAL
186#endif
187#ifdef SYNC_SER_MANUAL
188static irqreturn_t manual_interrupt(int irq, void *dev_id);
189#endif
190
191/* The ports */
192static struct sync_port ports[] = {
193 {
194 .status = R_SYNC_SERIAL1_STATUS,
195 .ctrl_data = R_SYNC_SERIAL1_CTRL,
196 .output_dma_first = R_DMA_CH8_FIRST,
197 .output_dma_cmd = R_DMA_CH8_CMD,
198 .output_dma_clr_irq = R_DMA_CH8_CLR_INTR,
199 .input_dma_first = R_DMA_CH9_FIRST,
200 .input_dma_cmd = R_DMA_CH9_CMD,
201 .input_dma_descr = R_DMA_CH9_DESCR,
202 .input_dma_clr_irq = R_DMA_CH9_CLR_INTR,
203 .data_out = R_SYNC_SERIAL1_TR_DATA,
204 .data_in = R_SYNC_SERIAL1_REC_DATA,
205 .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_data),
206 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_ready),
207 .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma9_descr),
208 .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma8_eop),
209 .init_irqs = 1,
210#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
211 .use_dma = 1,
212#else
213 .use_dma = 0,
214#endif
215 },
216 {
217 .status = R_SYNC_SERIAL3_STATUS,
218 .ctrl_data = R_SYNC_SERIAL3_CTRL,
219 .output_dma_first = R_DMA_CH4_FIRST,
220 .output_dma_cmd = R_DMA_CH4_CMD,
221 .output_dma_clr_irq = R_DMA_CH4_CLR_INTR,
222 .input_dma_first = R_DMA_CH5_FIRST,
223 .input_dma_cmd = R_DMA_CH5_CMD,
224 .input_dma_descr = R_DMA_CH5_DESCR,
225 .input_dma_clr_irq = R_DMA_CH5_CLR_INTR,
226 .data_out = R_SYNC_SERIAL3_TR_DATA,
227 .data_in = R_SYNC_SERIAL3_REC_DATA,
228 .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_data),
229 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_ready),
230 .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma5_descr),
231 .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma4_eop),
232 .init_irqs = 1,
233#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
234 .use_dma = 1,
235#else
236 .use_dma = 0,
237#endif
238 }
239};
240
241/* Register shadows */
242static unsigned sync_serial_prescale_shadow;
243
244#define NUMBER_OF_PORTS 2
245
246static struct file_operations sync_serial_fops = {
247 .owner = THIS_MODULE,
248 .write = sync_serial_write,
249 .read = sync_serial_read,
250 .poll = sync_serial_poll,
251 .ioctl = sync_serial_ioctl,
252 .open = sync_serial_open,
253 .release = sync_serial_release
254};
255
256static int __init etrax_sync_serial_init(void)
257{
258 ports[0].enabled = 0;
259 ports[1].enabled = 0;
260
261#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
262 if (cris_request_io_interface(if_sync_serial_1, "sync_ser1")) {
263 printk(KERN_CRIT "ETRAX100LX sync_serial: "
264 "Could not allocate IO group for port %d\n", 0);
265 return -EBUSY;
266 }
267#endif
268#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
269 if (cris_request_io_interface(if_sync_serial_3, "sync_ser3")) {
270#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
271 cris_free_io_interface(if_sync_serial_1);
272#endif
273 printk(KERN_CRIT "ETRAX100LX sync_serial: "
274 "Could not allocate IO group for port %d\n", 1);
275 return -EBUSY;
276 }
277#endif
278
279 if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial",
280 &sync_serial_fops) < 0) {
281#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
282 cris_free_io_interface(if_sync_serial_3);
283#endif
284#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
285 cris_free_io_interface(if_sync_serial_1);
286#endif
287 printk("unable to get major for synchronous serial port\n");
288 return -EBUSY;
289 }
290
291 /* Deselect synchronous serial ports while configuring. */
292 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
293 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
294 *R_GEN_CONFIG_II = gen_config_ii_shadow;
295
296 /* Initialize Ports */
297#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
298 ports[0].enabled = 1;
299 SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra);
300 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
301#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
302 ports[0].use_dma = 1;
303#else
304 ports[0].use_dma = 0;
305#endif
306 initialize_port(0);
307#endif
308
309#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
310 ports[1].enabled = 1;
311 SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra);
312 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
313#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
314 ports[1].use_dma = 1;
315#else
316 ports[1].use_dma = 0;
317#endif
318 initialize_port(1);
319#endif
320
321 *R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */
322
323 /* Set up timing */
324 *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = (
325 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) |
326 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) |
327 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) |
328 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) |
329 IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) |
330 IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate,
331 DEFAULT_FRAME_RATE) |
332 IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) |
333 IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal));
334
335 /* Select synchronous ports */
336 *R_GEN_CONFIG_II = gen_config_ii_shadow;
337
338 printk(KERN_INFO "ETRAX 100LX synchronous serial port driver\n");
339 return 0;
340}
341
342static void __init initialize_port(int portnbr)
343{
344 struct sync_port *port = &ports[portnbr];
345
346 DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr));
347
348 port->started = 0;
349 port->port_nbr = portnbr;
350 port->busy = 0;
351 port->tr_running = 0;
352
353 port->out_count = 0;
354 port->outp = port->out_buffer;
355
356 port->readp = port->flip;
357 port->writep = port->flip;
358 port->in_buffer_size = IN_BUFFER_SIZE;
359 port->inbufchunk = IN_DESCR_SIZE;
360 port->next_rx_desc = &port->in_descr[0];
361 port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1];
362 port->prev_rx_desc->ctrl = d_eol;
363
364 init_waitqueue_head(&port->out_wait_q);
365 init_waitqueue_head(&port->in_wait_q);
366
367 port->ctrl_data_shadow =
368 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz) |
369 IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) |
370 IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore) |
371 IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) |
372 IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal) |
373 IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word) |
374 IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on) |
375 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal) |
376 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped) |
377 IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb) |
378 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable) |
379 IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit) |
380 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8) |
381 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8) |
382 IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled) |
383 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg) |
384 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)|
385 IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)|
386 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal) |
387 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) |
388 IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)|
389 IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high);
390
391 if (port->use_dma)
392 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
393 dma_enable, on);
394 else
395 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
396 dma_enable, off);
397
398 *port->ctrl_data = port->ctrl_data_shadow;
399}
400
401static inline int sync_data_avail(struct sync_port *port)
402{
403 int avail;
404 unsigned char *start;
405 unsigned char *end;
406
407 start = (unsigned char *)port->readp; /* cast away volatile */
408 end = (unsigned char *)port->writep; /* cast away volatile */
409 /* 0123456789 0123456789
410 * ----- - -----
411 * ^rp ^wp ^wp ^rp
412 */
413 if (end >= start)
414 avail = end - start;
415 else
416 avail = port->in_buffer_size - (start - end);
417 return avail;
418}
419
420static inline int sync_data_avail_to_end(struct sync_port *port)
421{
422 int avail;
423 unsigned char *start;
424 unsigned char *end;
425
426 start = (unsigned char *)port->readp; /* cast away volatile */
427 end = (unsigned char *)port->writep; /* cast away volatile */
428 /* 0123456789 0123456789
429 * ----- -----
430 * ^rp ^wp ^wp ^rp
431 */
432
433 if (end >= start)
434 avail = end - start;
435 else
436 avail = port->flip + port->in_buffer_size - start;
437 return avail;
438}
439
440
441static int sync_serial_open(struct inode *inode, struct file *file)
442{
443 int dev = MINOR(inode->i_rdev);
444 struct sync_port *port;
445 int mode;
446
447 DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev));
448
449 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
450 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
451 return -ENODEV;
452 }
453 port = &ports[dev];
454 /* Allow open this device twice (assuming one reader and one writer) */
455 if (port->busy == 2) {
456 DEBUG(printk(KERN_DEBUG "Device is busy.. \n"));
457 return -EBUSY;
458 }
459 if (port->init_irqs) {
460 if (port->use_dma) {
461 if (port == &ports[0]) {
462#ifdef SYNC_SER_DMA
463 if (request_irq(24, tr_interrupt, 0,
464 "synchronous serial 1 dma tr",
465 &ports[0])) {
466 printk(KERN_CRIT "Can't alloc "
467 "sync serial port 1 IRQ");
468 return -EBUSY;
469 } else if (request_irq(25, rx_interrupt, 0,
470 "synchronous serial 1 dma rx",
471 &ports[0])) {
472 free_irq(24, &port[0]);
473 printk(KERN_CRIT "Can't alloc "
474 "sync serial port 1 IRQ");
475 return -EBUSY;
476 } else if (cris_request_dma(8,
477 "synchronous serial 1 dma tr",
478 DMA_VERBOSE_ON_ERROR,
479 dma_ser1)) {
480 free_irq(24, &port[0]);
481 free_irq(25, &port[0]);
482 printk(KERN_CRIT "Can't alloc "
483 "sync serial port 1 "
484 "TX DMA channel");
485 return -EBUSY;
486 } else if (cris_request_dma(9,
487 "synchronous serial 1 dma rec",
488 DMA_VERBOSE_ON_ERROR,
489 dma_ser1)) {
490 cris_free_dma(8, NULL);
491 free_irq(24, &port[0]);
492 free_irq(25, &port[0]);
493 printk(KERN_CRIT "Can't alloc "
494 "sync serial port 1 "
495 "RX DMA channel");
496 return -EBUSY;
497 }
498#endif
499 RESET_DMA(8); WAIT_DMA(8);
500 RESET_DMA(9); WAIT_DMA(9);
501 *R_DMA_CH8_CLR_INTR =
502 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop,
503 do) |
504 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr,
505 do);
506 *R_DMA_CH9_CLR_INTR =
507 IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop,
508 do) |
509 IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr,
510 do);
511 *R_IRQ_MASK2_SET =
512 IO_STATE(R_IRQ_MASK2_SET, dma8_eop,
513 set) |
514 IO_STATE(R_IRQ_MASK2_SET, dma9_descr,
515 set);
516 } else if (port == &ports[1]) {
517#ifdef SYNC_SER_DMA
518 if (request_irq(20, tr_interrupt, 0,
519 "synchronous serial 3 dma tr",
520 &ports[1])) {
521 printk(KERN_CRIT "Can't alloc "
522 "sync serial port 3 IRQ");
523 return -EBUSY;
524 } else if (request_irq(21, rx_interrupt, 0,
525 "synchronous serial 3 dma rx",
526 &ports[1])) {
527 free_irq(20, &ports[1]);
528 printk(KERN_CRIT "Can't alloc "
529 "sync serial port 3 IRQ");
530 return -EBUSY;
531 } else if (cris_request_dma(4,
532 "synchronous serial 3 dma tr",
533 DMA_VERBOSE_ON_ERROR,
534 dma_ser3)) {
535 free_irq(21, &ports[1]);
536 free_irq(20, &ports[1]);
537 printk(KERN_CRIT "Can't alloc "
538 "sync serial port 3 "
539 "TX DMA channel");
540 return -EBUSY;
541 } else if (cris_request_dma(5,
542 "synchronous serial 3 dma rec",
543 DMA_VERBOSE_ON_ERROR,
544 dma_ser3)) {
545 cris_free_dma(4, NULL);
546 free_irq(21, &ports[1]);
547 free_irq(20, &ports[1]);
548 printk(KERN_CRIT "Can't alloc "
549 "sync serial port 3 "
550 "RX DMA channel");
551 return -EBUSY;
552 }
553#endif
554 RESET_DMA(4); WAIT_DMA(4);
555 RESET_DMA(5); WAIT_DMA(5);
556 *R_DMA_CH4_CLR_INTR =
557 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop,
558 do) |
559 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr,
560 do);
561 *R_DMA_CH5_CLR_INTR =
562 IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop,
563 do) |
564 IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr,
565 do);
566 *R_IRQ_MASK2_SET =
567 IO_STATE(R_IRQ_MASK2_SET, dma4_eop,
568 set) |
569 IO_STATE(R_IRQ_MASK2_SET, dma5_descr,
570 set);
571 }
572 start_dma_in(port);
573 port->init_irqs = 0;
574 } else { /* !port->use_dma */
575#ifdef SYNC_SER_MANUAL
576 if (port == &ports[0]) {
577 if (request_irq(8,
578 manual_interrupt,
579 IRQF_SHARED | IRQF_DISABLED,
580 "synchronous serial manual irq",
581 &ports[0])) {
582 printk(KERN_CRIT "Can't alloc "
583 "sync serial manual irq");
584 return -EBUSY;
585 }
586 } else if (port == &ports[1]) {
587 if (request_irq(8,
588 manual_interrupt,
589 IRQF_SHARED | IRQF_DISABLED,
590 "synchronous serial manual irq",
591 &ports[1])) {
592 printk(KERN_CRIT "Can't alloc "
593 "sync serial manual irq");
594 return -EBUSY;
595 }
596 }
597 port->init_irqs = 0;
598#else
599 panic("sync_serial: Manual mode not supported.\n");
600#endif /* SYNC_SER_MANUAL */
601 }
602 } /* port->init_irqs */
603
604 port->busy++;
605 /* Start port if we use it as input */
606 mode = IO_EXTRACT(R_SYNC_SERIAL1_CTRL, mode, port->ctrl_data_shadow);
607 if (mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_input) ||
608 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_input) ||
609 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_bidir) ||
610 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_bidir)) {
611 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
612 running);
613 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
614 enable);
615 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
616 enable);
617 port->started = 1;
618 *port->ctrl_data = port->ctrl_data_shadow;
619 if (!port->use_dma)
620 *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
621 DEBUG(printk(KERN_DEBUG "sser%d rec started\n", dev));
622 }
623 return 0;
624}
625
626static int sync_serial_release(struct inode *inode, struct file *file)
627{
628 int dev = MINOR(inode->i_rdev);
629 struct sync_port *port;
630
631 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
632 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
633 return -ENODEV;
634 }
635 port = &ports[dev];
636 if (port->busy)
637 port->busy--;
638 if (!port->busy)
639 *R_IRQ_MASK1_CLR = ((1 << port->data_avail_bit) |
640 (1 << port->transmitter_ready_bit));
641
642 return 0;
643}
644
645
646
647static unsigned int sync_serial_poll(struct file *file, poll_table *wait)
648{
649 int dev = MINOR(file->f_dentry->d_inode->i_rdev);
650 unsigned int mask = 0;
651 struct sync_port *port;
652 DEBUGPOLL(static unsigned int prev_mask = 0);
653
654 port = &ports[dev];
655 poll_wait(file, &port->out_wait_q, wait);
656 poll_wait(file, &port->in_wait_q, wait);
657 /* Some room to write */
658 if (port->out_count < OUT_BUFFER_SIZE)
659 mask |= POLLOUT | POLLWRNORM;
660 /* At least an inbufchunk of data */
661 if (sync_data_avail(port) >= port->inbufchunk)
662 mask |= POLLIN | POLLRDNORM;
663
664 DEBUGPOLL(if (mask != prev_mask)
665 printk(KERN_DEBUG "sync_serial_poll: mask 0x%08X %s %s\n",
666 mask,
667 mask & POLLOUT ? "POLLOUT" : "",
668 mask & POLLIN ? "POLLIN" : "");
669 prev_mask = mask;
670 );
671 return mask;
672}
673
674static int sync_serial_ioctl(struct inode *inode, struct file *file,
675 unsigned int cmd, unsigned long arg)
676{
677 int return_val = 0;
678 unsigned long flags;
679
680 int dev = MINOR(file->f_dentry->d_inode->i_rdev);
681 struct sync_port *port;
682
683 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
684 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
685 return -1;
686 }
687 port = &ports[dev];
688
689 local_irq_save(flags);
690 /* Disable port while changing config */
691 if (dev) {
692 if (port->use_dma) {
693 RESET_DMA(4); WAIT_DMA(4);
694 port->tr_running = 0;
695 port->out_count = 0;
696 port->outp = port->out_buffer;
697 *R_DMA_CH4_CLR_INTR =
698 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) |
699 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do);
700 }
701 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
702 } else {
703 if (port->use_dma) {
704 RESET_DMA(8); WAIT_DMA(8);
705 port->tr_running = 0;
706 port->out_count = 0;
707 port->outp = port->out_buffer;
708 *R_DMA_CH8_CLR_INTR =
709 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) |
710 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do);
711 }
712 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
713 }
714 *R_GEN_CONFIG_II = gen_config_ii_shadow;
715 local_irq_restore(flags);
716
717 switch (cmd) {
718 case SSP_SPEED:
719 if (GET_SPEED(arg) == CODEC) {
720 if (dev)
721 SETS(sync_serial_prescale_shadow,
722 R_SYNC_SERIAL_PRESCALE, clk_sel_u3,
723 codec);
724 else
725 SETS(sync_serial_prescale_shadow,
726 R_SYNC_SERIAL_PRESCALE, clk_sel_u1,
727 codec);
728
729 SETF(sync_serial_prescale_shadow,
730 R_SYNC_SERIAL_PRESCALE, prescaler,
731 GET_FREQ(arg));
732 SETF(sync_serial_prescale_shadow,
733 R_SYNC_SERIAL_PRESCALE, frame_rate,
734 GET_FRAME_RATE(arg));
735 SETF(sync_serial_prescale_shadow,
736 R_SYNC_SERIAL_PRESCALE, word_rate,
737 GET_WORD_RATE(arg));
738 } else {
739 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
740 tr_baud, GET_SPEED(arg));
741 if (dev)
742 SETS(sync_serial_prescale_shadow,
743 R_SYNC_SERIAL_PRESCALE, clk_sel_u3,
744 baudrate);
745 else
746 SETS(sync_serial_prescale_shadow,
747 R_SYNC_SERIAL_PRESCALE, clk_sel_u1,
748 baudrate);
749 }
750 break;
751 case SSP_MODE:
752 if (arg > 5)
753 return -EINVAL;
754 if (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT)
755 *R_IRQ_MASK1_CLR = 1 << port->data_avail_bit;
756 else if (!port->use_dma)
757 *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
758 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, arg);
759 break;
760 case SSP_FRAME_SYNC:
761 if (arg & NORMAL_SYNC)
762 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
763 f_synctype, normal);
764 else if (arg & EARLY_SYNC)
765 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
766 f_synctype, early);
767
768 if (arg & BIT_SYNC)
769 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
770 f_syncsize, bit);
771 else if (arg & WORD_SYNC)
772 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
773 f_syncsize, word);
774 else if (arg & EXTENDED_SYNC)
775 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
776 f_syncsize, extended);
777
778 if (arg & SYNC_ON)
779 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
780 f_sync, on);
781 else if (arg & SYNC_OFF)
782 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
783 f_sync, off);
784
785 if (arg & WORD_SIZE_8)
786 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
787 wordsize, size8bit);
788 else if (arg & WORD_SIZE_12)
789 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
790 wordsize, size12bit);
791 else if (arg & WORD_SIZE_16)
792 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
793 wordsize, size16bit);
794 else if (arg & WORD_SIZE_24)
795 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
796 wordsize, size24bit);
797 else if (arg & WORD_SIZE_32)
798 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
799 wordsize, size32bit);
800
801 if (arg & BIT_ORDER_MSB)
802 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
803 bitorder, msb);
804 else if (arg & BIT_ORDER_LSB)
805 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
806 bitorder, lsb);
807
808 if (arg & FLOW_CONTROL_ENABLE)
809 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
810 flow_ctrl, enabled);
811 else if (arg & FLOW_CONTROL_DISABLE)
812 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
813 flow_ctrl, disabled);
814
815 if (arg & CLOCK_NOT_GATED)
816 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
817 clk_mode, normal);
818 else if (arg & CLOCK_GATED)
819 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
820 clk_mode, gated);
821
822 break;
823 case SSP_IPOLARITY:
824 /* NOTE!! negedge is considered NORMAL */
825 if (arg & CLOCK_NORMAL)
826 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
827 clk_polarity, neg);
828 else if (arg & CLOCK_INVERT)
829 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
830 clk_polarity, pos);
831
832 if (arg & FRAME_NORMAL)
833 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
834 frame_polarity, normal);
835 else if (arg & FRAME_INVERT)
836 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
837 frame_polarity, inverted);
838
839 if (arg & STATUS_NORMAL)
840 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
841 status_polarity, normal);
842 else if (arg & STATUS_INVERT)
843 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
844 status_polarity, inverted);
845 break;
846 case SSP_OPOLARITY:
847 if (arg & CLOCK_NORMAL)
848 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
849 clk_driver, normal);
850 else if (arg & CLOCK_INVERT)
851 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
852 clk_driver, inverted);
853
854 if (arg & FRAME_NORMAL)
855 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
856 frame_driver, normal);
857 else if (arg & FRAME_INVERT)
858 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
859 frame_driver, inverted);
860
861 if (arg & STATUS_NORMAL)
862 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
863 status_driver, normal);
864 else if (arg & STATUS_INVERT)
865 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
866 status_driver, inverted);
867 break;
868 case SSP_SPI:
869 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl,
870 disabled);
871 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder,
872 msb);
873 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize,
874 size8bit);
875 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on);
876 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize,
877 word);
878 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype,
879 normal);
880 if (arg & SPI_SLAVE) {
881 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
882 frame_polarity, inverted);
883 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
884 clk_polarity, neg);
885 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
886 mode, SLAVE_INPUT);
887 } else {
888 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
889 frame_driver, inverted);
890 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
891 clk_driver, inverted);
892 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
893 mode, MASTER_OUTPUT);
894 }
895 break;
896 case SSP_INBUFCHUNK:
897#if 0
898 if (arg > port->in_buffer_size/NUM_IN_DESCR)
899 return -EINVAL;
900 port->inbufchunk = arg;
901 /* Make sure in_buffer_size is a multiple of inbufchunk */
902 port->in_buffer_size =
903 (port->in_buffer_size/port->inbufchunk) *
904 port->inbufchunk;
905 DEBUG(printk(KERN_DEBUG "inbufchunk %i in_buffer_size: %i\n",
906 port->inbufchunk, port->in_buffer_size));
907 if (port->use_dma) {
908 if (port->port_nbr == 0) {
909 RESET_DMA(9);
910 WAIT_DMA(9);
911 } else {
912 RESET_DMA(5);
913 WAIT_DMA(5);
914 }
915 start_dma_in(port);
916 }
917#endif
918 break;
919 default:
920 return_val = -1;
921 }
922 /* Make sure we write the config without interruption */
923 local_irq_save(flags);
924 /* Set config and enable port */
925 *port->ctrl_data = port->ctrl_data_shadow;
926 nop(); nop(); nop(); nop();
927 *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow;
928 nop(); nop(); nop(); nop();
929 if (dev)
930 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
931 else
932 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
933
934 *R_GEN_CONFIG_II = gen_config_ii_shadow;
935 /* Reset DMA. At readout from serial port the data could be shifted
936 * one byte if not resetting DMA.
937 */
938 if (port->use_dma) {
939 if (port->port_nbr == 0) {
940 RESET_DMA(9);
941 WAIT_DMA(9);
942 } else {
943 RESET_DMA(5);
944 WAIT_DMA(5);
945 }
946 start_dma_in(port);
947 }
948 local_irq_restore(flags);
949 return return_val;
950}
951
952
953static ssize_t sync_serial_write(struct file *file, const char *buf,
954 size_t count, loff_t *ppos)
955{
956 int dev = MINOR(file->f_dentry->d_inode->i_rdev);
957 DECLARE_WAITQUEUE(wait, current);
958 struct sync_port *port;
959 unsigned long flags;
960 unsigned long c, c1;
961 unsigned long free_outp;
962 unsigned long outp;
963 unsigned long out_buffer;
964
965 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
966 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
967 return -ENODEV;
968 }
969 port = &ports[dev];
970
971 DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu (%d/%d)\n",
972 port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE));
973 /* Space to end of buffer */
974 /*
975 * out_buffer <c1>012345<- c ->OUT_BUFFER_SIZE
976 * outp^ +out_count
977 * ^free_outp
978 * out_buffer 45<- c ->0123OUT_BUFFER_SIZE
979 * +out_count outp^
980 * free_outp
981 *
982 */
983
984 /* Read variables that may be updated by interrupts */
985 local_irq_save(flags);
986 if (count > OUT_BUFFER_SIZE - port->out_count)
987 count = OUT_BUFFER_SIZE - port->out_count;
988
989 outp = (unsigned long)port->outp;
990 free_outp = outp + port->out_count;
991 local_irq_restore(flags);
992 out_buffer = (unsigned long)port->out_buffer;
993
994 /* Find out where and how much to write */
995 if (free_outp >= out_buffer + OUT_BUFFER_SIZE)
996 free_outp -= OUT_BUFFER_SIZE;
997 if (free_outp >= outp)
998 c = out_buffer + OUT_BUFFER_SIZE - free_outp;
999 else
1000 c = outp - free_outp;
1001 if (c > count)
1002 c = count;
1003
1004 DEBUGWRITE(printk(KERN_DEBUG "w op %08lX fop %08lX c %lu\n",
1005 outp, free_outp, c));
1006 if (copy_from_user((void *)free_outp, buf, c))
1007 return -EFAULT;
1008
1009 if (c != count) {
1010 buf += c;
1011 c1 = count - c;
1012 DEBUGWRITE(printk(KERN_DEBUG "w2 fi %lu c %lu c1 %lu\n",
1013 free_outp-out_buffer, c, c1));
1014 if (copy_from_user((void *)out_buffer, buf, c1))
1015 return -EFAULT;
1016 }
1017 local_irq_save(flags);
1018 port->out_count += count;
1019 local_irq_restore(flags);
1020
1021 /* Make sure transmitter/receiver is running */
1022 if (!port->started) {
1023 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
1024 running);
1025 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
1026 enable);
1027 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
1028 enable);
1029 port->started = 1;
1030 }
1031
1032 *port->ctrl_data = port->ctrl_data_shadow;
1033
1034 if (file->f_flags & O_NONBLOCK) {
1035 local_irq_save(flags);
1036 if (!port->tr_running) {
1037 if (!port->use_dma) {
1038 /* Start sender by writing data */
1039 send_word(port);
1040 /* and enable transmitter ready IRQ */
1041 *R_IRQ_MASK1_SET = 1 <<
1042 port->transmitter_ready_bit;
1043 } else
1044 start_dma(port,
1045 (unsigned char *volatile)port->outp, c);
1046 }
1047 local_irq_restore(flags);
1048 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu NB\n",
1049 port->port_nbr, count));
1050 return count;
1051 }
1052
1053 /* Sleep until all sent */
1054 add_wait_queue(&port->out_wait_q, &wait);
1055 set_current_state(TASK_INTERRUPTIBLE);
1056 local_irq_save(flags);
1057 if (!port->tr_running) {
1058 if (!port->use_dma) {
1059 /* Start sender by writing data */
1060 send_word(port);
1061 /* and enable transmitter ready IRQ */
1062 *R_IRQ_MASK1_SET = 1 << port->transmitter_ready_bit;
1063 } else
1064 start_dma(port, port->outp, c);
1065 }
1066 local_irq_restore(flags);
1067 schedule();
1068 set_current_state(TASK_RUNNING);
1069 remove_wait_queue(&port->out_wait_q, &wait);
1070 if (signal_pending(current))
1071 return -EINTR;
1072
1073 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n", port->port_nbr, count));
1074 return count;
1075}
1076
1077static ssize_t sync_serial_read(struct file *file, char *buf,
1078 size_t count, loff_t *ppos)
1079{
1080 int dev = MINOR(file->f_dentry->d_inode->i_rdev);
1081 int avail;
1082 struct sync_port *port;
1083 unsigned char *start;
1084 unsigned char *end;
1085 unsigned long flags;
1086
1087 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
1088 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
1089 return -ENODEV;
1090 }
1091 port = &ports[dev];
1092
1093 DEBUGREAD(printk(KERN_DEBUG "R%d c %d ri %lu wi %lu /%lu\n",
1094 dev, count, port->readp - port->flip,
1095 port->writep - port->flip, port->in_buffer_size));
1096
1097 if (!port->started) {
1098 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
1099 running);
1100 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
1101 enable);
1102 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
1103 enable);
1104 port->started = 1;
1105 }
1106 *port->ctrl_data = port->ctrl_data_shadow;
1107
1108 /* Calculate number of available bytes */
1109 /* Save pointers to avoid that they are modified by interrupt */
1110 local_irq_save(flags);
1111 start = (unsigned char *)port->readp; /* cast away volatile */
1112 end = (unsigned char *)port->writep; /* cast away volatile */
1113 local_irq_restore(flags);
1114 while (start == end && !port->full) {
1115 /* No data */
1116 if (file->f_flags & O_NONBLOCK)
1117 return -EAGAIN;
1118
1119 interruptible_sleep_on(&port->in_wait_q);
1120 if (signal_pending(current))
1121 return -EINTR;
1122
1123 local_irq_save(flags);
1124 start = (unsigned char *)port->readp; /* cast away volatile */
1125 end = (unsigned char *)port->writep; /* cast away volatile */
1126 local_irq_restore(flags);
1127 }
1128
1129 /* Lazy read, never return wrapped data. */
1130 if (port->full)
1131 avail = port->in_buffer_size;
1132 else if (end > start)
1133 avail = end - start;
1134 else
1135 avail = port->flip + port->in_buffer_size - start;
1136
1137 count = count > avail ? avail : count;
1138 if (copy_to_user(buf, start, count))
1139 return -EFAULT;
1140 /* Disable interrupts while updating readp */
1141 local_irq_save(flags);
1142 port->readp += count;
1143 if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */
1144 port->readp = port->flip;
1145 port->full = 0;
1146 local_irq_restore(flags);
1147 DEBUGREAD(printk(KERN_DEBUG "r %d\n", count));
1148 return count;
1149}
1150
1151static void send_word(struct sync_port *port)
1152{
1153 switch (IO_EXTRACT(R_SYNC_SERIAL1_CTRL, wordsize,
1154 port->ctrl_data_shadow)) {
1155 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
1156 port->out_count--;
1157 *port->data_out = *port->outp++;
1158 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1159 port->outp = port->out_buffer;
1160 break;
1161 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
1162 {
1163 int data = (*port->outp++) << 8;
1164 data |= *port->outp++;
1165 port->out_count -= 2;
1166 *port->data_out = data;
1167 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1168 port->outp = port->out_buffer;
1169 break;
1170 }
1171 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
1172 port->out_count -= 2;
1173 *port->data_out = *(unsigned short *)port->outp;
1174 port->outp += 2;
1175 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1176 port->outp = port->out_buffer;
1177 break;
1178 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
1179 port->out_count -= 3;
1180 *port->data_out = *(unsigned int *)port->outp;
1181 port->outp += 3;
1182 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1183 port->outp = port->out_buffer;
1184 break;
1185 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
1186 port->out_count -= 4;
1187 *port->data_out = *(unsigned int *)port->outp;
1188 port->outp += 4;
1189 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1190 port->outp = port->out_buffer;
1191 break;
1192 }
1193}
1194
1195
1196static void start_dma(struct sync_port *port, const char *data, int count)
1197{
1198 port->tr_running = 1;
1199 port->out_descr.hw_len = 0;
1200 port->out_descr.next = 0;
1201 port->out_descr.ctrl = d_eol | d_eop; /* No d_wait to avoid glitches */
1202 port->out_descr.sw_len = count;
1203 port->out_descr.buf = virt_to_phys(data);
1204 port->out_descr.status = 0;
1205
1206 *port->output_dma_first = virt_to_phys(&port->out_descr);
1207 *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
1208 DEBUGTXINT(printk(KERN_DEBUG "dma %08lX c %d\n",
1209 (unsigned long)data, count));
1210}
1211
1212static void start_dma_in(struct sync_port *port)
1213{
1214 int i;
1215 unsigned long buf;
1216 port->writep = port->flip;
1217
1218 if (port->writep > port->flip + port->in_buffer_size) {
1219 panic("Offset too large in sync serial driver\n");
1220 return;
1221 }
1222 buf = virt_to_phys(port->in_buffer);
1223 for (i = 0; i < NUM_IN_DESCR; i++) {
1224 port->in_descr[i].sw_len = port->inbufchunk;
1225 port->in_descr[i].ctrl = d_int;
1226 port->in_descr[i].next = virt_to_phys(&port->in_descr[i+1]);
1227 port->in_descr[i].buf = buf;
1228 port->in_descr[i].hw_len = 0;
1229 port->in_descr[i].status = 0;
1230 port->in_descr[i].fifo_len = 0;
1231 buf += port->inbufchunk;
1232 prepare_rx_descriptor(&port->in_descr[i]);
1233 }
1234 /* Link the last descriptor to the first */
1235 port->in_descr[i-1].next = virt_to_phys(&port->in_descr[0]);
1236 port->in_descr[i-1].ctrl |= d_eol;
1237 port->next_rx_desc = &port->in_descr[0];
1238 port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1];
1239 *port->input_dma_first = virt_to_phys(port->next_rx_desc);
1240 *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
1241}
1242
1243#ifdef SYNC_SER_DMA
1244static irqreturn_t tr_interrupt(int irq, void *dev_id)
1245{
1246 unsigned long ireg = *R_IRQ_MASK2_RD;
1247 struct etrax_dma_descr *descr;
1248 unsigned int sentl;
1249 int handled = 0;
1250 int i;
1251
1252 for (i = 0; i < NUMBER_OF_PORTS; i++) {
1253 struct sync_port *port = &ports[i];
1254 if (!port->enabled || !port->use_dma)
1255 continue;
1256
1257 /* IRQ active for the port? */
1258 if (!(ireg & (1 << port->output_dma_bit)))
1259 continue;
1260
1261 handled = 1;
1262
1263 /* Clear IRQ */
1264 *port->output_dma_clr_irq =
1265 IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) |
1266 IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do);
1267
1268 descr = &port->out_descr;
1269 if (!(descr->status & d_stop))
1270 sentl = descr->sw_len;
1271 else
1272 /* Otherwise find amount of data sent here */
1273 sentl = descr->hw_len;
1274
1275 port->out_count -= sentl;
1276 port->outp += sentl;
1277 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1278 port->outp = port->out_buffer;
1279 if (port->out_count) {
1280 int c = port->out_buffer + OUT_BUFFER_SIZE - port->outp;
1281 if (c > port->out_count)
1282 c = port->out_count;
1283 DEBUGTXINT(printk(KERN_DEBUG
1284 "tx_int DMAWRITE %i %i\n", sentl, c));
1285 start_dma(port, port->outp, c);
1286 } else {
1287 DEBUGTXINT(printk(KERN_DEBUG
1288 "tx_int DMA stop %i\n", sentl));
1289 port->tr_running = 0;
1290 }
1291 /* wake up the waiting process */
1292 wake_up_interruptible(&port->out_wait_q);
1293 }
1294 return IRQ_RETVAL(handled);
1295} /* tr_interrupt */
1296
1297static irqreturn_t rx_interrupt(int irq, void *dev_id)
1298{
1299 unsigned long ireg = *R_IRQ_MASK2_RD;
1300 int i;
1301 int handled = 0;
1302
1303 for (i = 0; i < NUMBER_OF_PORTS; i++) {
1304 struct sync_port *port = &ports[i];
1305
1306 if (!port->enabled || !port->use_dma)
1307 continue;
1308
1309 if (!(ireg & (1 << port->input_dma_descr_bit)))
1310 continue;
1311
1312 /* Descriptor interrupt */
1313 handled = 1;
1314 while (*port->input_dma_descr !=
1315 virt_to_phys(port->next_rx_desc)) {
1316 if (port->writep + port->inbufchunk > port->flip +
1317 port->in_buffer_size) {
1318 int first_size = port->flip +
1319 port->in_buffer_size - port->writep;
1320 memcpy(port->writep,
1321 phys_to_virt(port->next_rx_desc->buf),
1322 first_size);
1323 memcpy(port->flip,
1324 phys_to_virt(port->next_rx_desc->buf +
1325 first_size),
1326 port->inbufchunk - first_size);
1327 port->writep = port->flip +
1328 port->inbufchunk - first_size;
1329 } else {
1330 memcpy(port->writep,
1331 phys_to_virt(port->next_rx_desc->buf),
1332 port->inbufchunk);
1333 port->writep += port->inbufchunk;
1334 if (port->writep >= port->flip
1335 + port->in_buffer_size)
1336 port->writep = port->flip;
1337 }
1338 if (port->writep == port->readp)
1339 port->full = 1;
1340 prepare_rx_descriptor(port->next_rx_desc);
1341 port->next_rx_desc->ctrl |= d_eol;
1342 port->prev_rx_desc->ctrl &= ~d_eol;
1343 port->prev_rx_desc = phys_to_virt((unsigned)
1344 port->next_rx_desc);
1345 port->next_rx_desc = phys_to_virt((unsigned)
1346 port->next_rx_desc->next);
1347 /* Wake up the waiting process */
1348 wake_up_interruptible(&port->in_wait_q);
1349 *port->input_dma_cmd = IO_STATE(R_DMA_CH1_CMD,
1350 cmd, restart);
1351 /* DMA has reached end of descriptor */
1352 *port->input_dma_clr_irq = IO_STATE(R_DMA_CH0_CLR_INTR,
1353 clr_descr, do);
1354 }
1355 }
1356 return IRQ_RETVAL(handled);
1357} /* rx_interrupt */
1358#endif /* SYNC_SER_DMA */
1359
1360#ifdef SYNC_SER_MANUAL
1361static irqreturn_t manual_interrupt(int irq, void *dev_id)
1362{
1363 int i;
1364 int handled = 0;
1365
1366 for (i = 0; i < NUMBER_OF_PORTS; i++) {
1367 struct sync_port *port = &ports[i];
1368
1369 if (!port->enabled || port->use_dma)
1370 continue;
1371
1372 /* Data received? */
1373 if (*R_IRQ_MASK1_RD & (1 << port->data_avail_bit)) {
1374 handled = 1;
1375 /* Read data */
1376 switch (port->ctrl_data_shadow &
1377 IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize)) {
1378 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
1379 *port->writep++ =
1380 *(volatile char *)port->data_in;
1381 break;
1382 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
1383 {
1384 int data = *(unsigned short *)port->data_in;
1385 *port->writep = (data & 0x0ff0) >> 4;
1386 *(port->writep + 1) = data & 0x0f;
1387 port->writep += 2;
1388 break;
1389 }
1390 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
1391 *(unsigned short *)port->writep =
1392 *(volatile unsigned short *)port->data_in;
1393 port->writep += 2;
1394 break;
1395 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
1396 *(unsigned int *)port->writep = *port->data_in;
1397 port->writep += 3;
1398 break;
1399 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
1400 *(unsigned int *)port->writep = *port->data_in;
1401 port->writep += 4;
1402 break;
1403 }
1404
1405 /* Wrap? */
1406 if (port->writep >= port->flip + port->in_buffer_size)
1407 port->writep = port->flip;
1408 if (port->writep == port->readp) {
1409 /* Receive buffer overrun, discard oldest */
1410 port->readp++;
1411 /* Wrap? */
1412 if (port->readp >= port->flip +
1413 port->in_buffer_size)
1414 port->readp = port->flip;
1415 }
1416 if (sync_data_avail(port) >= port->inbufchunk) {
1417 /* Wake up application */
1418 wake_up_interruptible(&port->in_wait_q);
1419 }
1420 }
1421
1422 /* Transmitter ready? */
1423 if (*R_IRQ_MASK1_RD & (1 << port->transmitter_ready_bit)) {
1424 if (port->out_count > 0) {
1425 /* More data to send */
1426 send_word(port);
1427 } else {
1428 /* Transmission finished */
1429 /* Turn off IRQ */
1430 *R_IRQ_MASK1_CLR = 1 <<
1431 port->transmitter_ready_bit;
1432 /* Wake up application */
1433 wake_up_interruptible(&port->out_wait_q);
1434 }
1435 }
1436 }
1437 return IRQ_RETVAL(handled);
1438}
1439#endif
1440
1441module_init(etrax_sync_serial_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 11:34:09 -0500