diff options
Diffstat (limited to 'arch/blackfin')
185 files changed, 3909 insertions, 4252 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 3640cdc38aac..8ea0d942cdea 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig | |||
| @@ -6,59 +6,65 @@ | |||
| 6 | mainmenu "Blackfin Kernel Configuration" | 6 | mainmenu "Blackfin Kernel Configuration" |
| 7 | 7 | ||
| 8 | config MMU | 8 | config MMU |
| 9 | bool | 9 | def_bool n |
| 10 | default n | ||
| 11 | 10 | ||
| 12 | config FPU | 11 | config FPU |
| 13 | bool | 12 | def_bool n |
| 14 | default n | ||
| 15 | 13 | ||
| 16 | config RWSEM_GENERIC_SPINLOCK | 14 | config RWSEM_GENERIC_SPINLOCK |
| 17 | bool | 15 | def_bool y |
| 18 | default y | ||
| 19 | 16 | ||
| 20 | config RWSEM_XCHGADD_ALGORITHM | 17 | config RWSEM_XCHGADD_ALGORITHM |
| 21 | bool | 18 | def_bool n |
| 22 | default n | ||
| 23 | 19 | ||
| 24 | config BLACKFIN | 20 | config BLACKFIN |
| 25 | bool | 21 | def_bool y |
| 26 | default y | 22 | select HAVE_FUNCTION_GRAPH_TRACER |
| 23 | select HAVE_FUNCTION_TRACER | ||
| 27 | select HAVE_IDE | 24 | select HAVE_IDE |
| 25 | select HAVE_KERNEL_GZIP | ||
| 26 | select HAVE_KERNEL_BZIP2 | ||
| 27 | select HAVE_KERNEL_LZMA | ||
| 28 | select HAVE_OPROFILE | 28 | select HAVE_OPROFILE |
| 29 | select ARCH_WANT_OPTIONAL_GPIOLIB | 29 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 30 | 30 | ||
| 31 | config GENERIC_BUG | ||
| 32 | def_bool y | ||
| 33 | depends on BUG | ||
| 34 | |||
| 31 | config ZONE_DMA | 35 | config ZONE_DMA |
| 32 | bool | 36 | def_bool y |
| 33 | default y | ||
| 34 | 37 | ||
| 35 | config GENERIC_FIND_NEXT_BIT | 38 | config GENERIC_FIND_NEXT_BIT |
| 36 | bool | 39 | def_bool y |
| 37 | default y | ||
| 38 | 40 | ||
| 39 | config GENERIC_HWEIGHT | 41 | config GENERIC_HWEIGHT |
| 40 | bool | 42 | def_bool y |
| 41 | default y | ||
| 42 | 43 | ||
| 43 | config GENERIC_HARDIRQS | 44 | config GENERIC_HARDIRQS |
| 44 | bool | 45 | def_bool y |
| 45 | default y | ||
| 46 | 46 | ||
| 47 | config GENERIC_IRQ_PROBE | 47 | config GENERIC_IRQ_PROBE |
| 48 | bool | 48 | def_bool y |
| 49 | default y | ||
| 50 | 49 | ||
| 51 | config GENERIC_GPIO | 50 | config GENERIC_GPIO |
| 52 | bool | 51 | def_bool y |
| 53 | default y | ||
| 54 | 52 | ||
| 55 | config FORCE_MAX_ZONEORDER | 53 | config FORCE_MAX_ZONEORDER |
| 56 | int | 54 | int |
| 57 | default "14" | 55 | default "14" |
| 58 | 56 | ||
| 59 | config GENERIC_CALIBRATE_DELAY | 57 | config GENERIC_CALIBRATE_DELAY |
| 60 | bool | 58 | def_bool y |
| 61 | default y | 59 | |
| 60 | config LOCKDEP_SUPPORT | ||
| 61 | def_bool y | ||
| 62 | |||
| 63 | config STACKTRACE_SUPPORT | ||
| 64 | def_bool y | ||
| 65 | |||
| 66 | config TRACE_IRQFLAGS_SUPPORT | ||
| 67 | def_bool y | ||
| 62 | 68 | ||
| 63 | source "init/Kconfig" | 69 | source "init/Kconfig" |
| 64 | 70 | ||
| @@ -223,6 +229,7 @@ endchoice | |||
| 223 | 229 | ||
| 224 | config SMP | 230 | config SMP |
| 225 | depends on BF561 | 231 | depends on BF561 |
| 232 | select GENERIC_TIME | ||
| 226 | bool "Symmetric multi-processing support" | 233 | bool "Symmetric multi-processing support" |
| 227 | ---help--- | 234 | ---help--- |
| 228 | This enables support for systems with more than one CPU, | 235 | This enables support for systems with more than one CPU, |
| @@ -241,12 +248,6 @@ config IRQ_PER_CPU | |||
| 241 | depends on SMP | 248 | depends on SMP |
| 242 | default y | 249 | default y |
| 243 | 250 | ||
| 244 | config TICK_SOURCE_SYSTMR0 | ||
| 245 | bool | ||
| 246 | select BFIN_GPTIMERS | ||
| 247 | depends on SMP | ||
| 248 | default y | ||
| 249 | |||
| 250 | config BF_REV_MIN | 251 | config BF_REV_MIN |
| 251 | int | 252 | int |
| 252 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) | 253 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
| @@ -263,8 +264,8 @@ config BF_REV_MAX | |||
| 263 | 264 | ||
| 264 | choice | 265 | choice |
| 265 | prompt "Silicon Rev" | 266 | prompt "Silicon Rev" |
| 266 | default BF_REV_0_1 if (BF51x || BF52x || (BF54x && !BF54xM)) | 267 | default BF_REV_0_0 if (BF51x || BF52x) |
| 267 | default BF_REV_0_2 if (BF534 || BF536 || BF537) | 268 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) |
| 268 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) | 269 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
| 269 | 270 | ||
| 270 | config BF_REV_0_0 | 271 | config BF_REV_0_0 |
| @@ -413,12 +414,12 @@ comment "Clock/PLL Setup" | |||
| 413 | 414 | ||
| 414 | config CLKIN_HZ | 415 | config CLKIN_HZ |
| 415 | int "Frequency of the crystal on the board in Hz" | 416 | int "Frequency of the crystal on the board in Hz" |
| 417 | default "10000000" if BFIN532_IP0X | ||
| 416 | default "11059200" if BFIN533_STAMP | 418 | default "11059200" if BFIN533_STAMP |
| 419 | default "24576000" if PNAV10 | ||
| 420 | default "25000000" # most people use this | ||
| 417 | default "27000000" if BFIN533_EZKIT | 421 | default "27000000" if BFIN533_EZKIT |
| 418 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD) | ||
| 419 | default "30000000" if BFIN561_EZKIT | 422 | default "30000000" if BFIN561_EZKIT |
| 420 | default "24576000" if PNAV10 | ||
| 421 | default "10000000" if BFIN532_IP0X | ||
| 422 | help | 423 | help |
| 423 | The frequency of CLKIN crystal oscillator on the board in Hz. | 424 | The frequency of CLKIN crystal oscillator on the board in Hz. |
| 424 | Warning: This value should match the crystal on the board. Otherwise, | 425 | Warning: This value should match the crystal on the board. Otherwise, |
| @@ -607,7 +608,6 @@ source kernel/Kconfig.hz | |||
| 607 | 608 | ||
| 608 | config GENERIC_TIME | 609 | config GENERIC_TIME |
| 609 | bool "Generic time" | 610 | bool "Generic time" |
| 610 | depends on !SMP | ||
| 611 | default y | 611 | default y |
| 612 | 612 | ||
| 613 | config GENERIC_CLOCKEVENTS | 613 | config GENERIC_CLOCKEVENTS |
| @@ -615,12 +615,26 @@ config GENERIC_CLOCKEVENTS | |||
| 615 | depends on GENERIC_TIME | 615 | depends on GENERIC_TIME |
| 616 | default y | 616 | default y |
| 617 | 617 | ||
| 618 | choice | ||
| 619 | prompt "Kernel Tick Source" | ||
| 620 | depends on GENERIC_CLOCKEVENTS | ||
| 621 | default TICKSOURCE_CORETMR | ||
| 622 | |||
| 623 | config TICKSOURCE_GPTMR0 | ||
| 624 | bool "Gptimer0 (SCLK domain)" | ||
| 625 | select BFIN_GPTIMERS | ||
| 626 | depends on !IPIPE | ||
| 627 | |||
| 628 | config TICKSOURCE_CORETMR | ||
| 629 | bool "Core timer (CCLK domain)" | ||
| 630 | |||
| 631 | endchoice | ||
| 632 | |||
| 618 | config CYCLES_CLOCKSOURCE | 633 | config CYCLES_CLOCKSOURCE |
| 619 | bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)" | 634 | bool "Use 'CYCLES' as a clocksource" |
| 620 | depends on EXPERIMENTAL | ||
| 621 | depends on GENERIC_CLOCKEVENTS | 635 | depends on GENERIC_CLOCKEVENTS |
| 622 | depends on !BFIN_SCRATCH_REG_CYCLES | 636 | depends on !BFIN_SCRATCH_REG_CYCLES |
| 623 | default n | 637 | depends on !SMP |
| 624 | help | 638 | help |
| 625 | If you say Y here, you will enable support for using the 'cycles' | 639 | If you say Y here, you will enable support for using the 'cycles' |
| 626 | registers as a clock source. Doing so means you will be unable to | 640 | registers as a clock source. Doing so means you will be unable to |
| @@ -628,6 +642,11 @@ config CYCLES_CLOCKSOURCE | |||
| 628 | still be able to read it (such as for performance monitoring), but | 642 | still be able to read it (such as for performance monitoring), but |
| 629 | writing the registers will most likely crash the kernel. | 643 | writing the registers will most likely crash the kernel. |
| 630 | 644 | ||
| 645 | config GPTMR0_CLOCKSOURCE | ||
| 646 | bool "Use GPTimer0 as a clocksource (higher rating)" | ||
| 647 | depends on GENERIC_CLOCKEVENTS | ||
| 648 | depends on !TICKSOURCE_GPTMR0 | ||
| 649 | |||
| 631 | source kernel/time/Kconfig | 650 | source kernel/time/Kconfig |
| 632 | 651 | ||
| 633 | comment "Misc" | 652 | comment "Misc" |
| @@ -808,7 +827,7 @@ config APP_STACK_L1 | |||
| 808 | config EXCEPTION_L1_SCRATCH | 827 | config EXCEPTION_L1_SCRATCH |
| 809 | bool "Locate exception stack in L1 Scratch Memory" | 828 | bool "Locate exception stack in L1 Scratch Memory" |
| 810 | default n | 829 | default n |
| 811 | depends on !APP_STACK_L1 && !SYSCALL_TAB_L1 | 830 | depends on !APP_STACK_L1 |
| 812 | help | 831 | help |
| 813 | Whenever an exception occurs, use the L1 Scratch memory for | 832 | Whenever an exception occurs, use the L1 Scratch memory for |
| 814 | stack storage. You cannot place the stacks of FLAT binaries | 833 | stack storage. You cannot place the stacks of FLAT binaries |
| @@ -872,7 +891,7 @@ config BFIN_GPTIMERS | |||
| 872 | are unsure, say N. | 891 | are unsure, say N. |
| 873 | 892 | ||
| 874 | To compile this driver as a module, choose M here: the module | 893 | To compile this driver as a module, choose M here: the module |
| 875 | will be called gptimers.ko. | 894 | will be called gptimers. |
| 876 | 895 | ||
| 877 | choice | 896 | choice |
| 878 | prompt "Uncached DMA region" | 897 | prompt "Uncached DMA region" |
| @@ -901,7 +920,7 @@ config BFIN_ICACHE_LOCK | |||
| 901 | bool "Enable Instruction Cache Locking" | 920 | bool "Enable Instruction Cache Locking" |
| 902 | 921 | ||
| 903 | choice | 922 | choice |
| 904 | prompt "Policy" | 923 | prompt "External memory cache policy" |
| 905 | depends on BFIN_DCACHE | 924 | depends on BFIN_DCACHE |
| 906 | default BFIN_WB if !SMP | 925 | default BFIN_WB if !SMP |
| 907 | default BFIN_WT if SMP | 926 | default BFIN_WT if SMP |
| @@ -942,12 +961,22 @@ config BFIN_WT | |||
| 942 | 961 | ||
| 943 | endchoice | 962 | endchoice |
| 944 | 963 | ||
| 945 | config BFIN_L2_CACHEABLE | 964 | choice |
| 946 | bool "Cache L2 SRAM" | 965 | prompt "L2 SRAM cache policy" |
| 947 | depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP)) | 966 | depends on (BF54x || BF561) |
| 948 | default n | 967 | default BFIN_L2_WT |
| 949 | help | 968 | config BFIN_L2_WB |
| 950 | Select to make L2 SRAM cacheable in L1 data and instruction cache. | 969 | bool "Write back" |
| 970 | depends on !SMP | ||
| 971 | |||
| 972 | config BFIN_L2_WT | ||
| 973 | bool "Write through" | ||
| 974 | depends on !SMP | ||
| 975 | |||
| 976 | config BFIN_L2_NOT_CACHED | ||
| 977 | bool "Not cached" | ||
| 978 | |||
| 979 | endchoice | ||
| 951 | 980 | ||
| 952 | config MPU | 981 | config MPU |
| 953 | bool "Enable the memory protection unit (EXPERIMENTAL)" | 982 | bool "Enable the memory protection unit (EXPERIMENTAL)" |
| @@ -1011,21 +1040,34 @@ endmenu | |||
| 1011 | 1040 | ||
| 1012 | menu "EBIU_AMBCTL Control" | 1041 | menu "EBIU_AMBCTL Control" |
| 1013 | config BANK_0 | 1042 | config BANK_0 |
| 1014 | hex "Bank 0" | 1043 | hex "Bank 0 (AMBCTL0.L)" |
| 1015 | default 0x7BB0 | 1044 | default 0x7BB0 |
| 1045 | help | ||
| 1046 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | ||
| 1047 | used to control the Asynchronous Memory Bank 0 settings. | ||
| 1016 | 1048 | ||
| 1017 | config BANK_1 | 1049 | config BANK_1 |
| 1018 | hex "Bank 1" | 1050 | hex "Bank 1 (AMBCTL0.H)" |
| 1019 | default 0x7BB0 | 1051 | default 0x7BB0 |
| 1020 | default 0x5558 if BF54x | 1052 | default 0x5558 if BF54x |
| 1053 | help | ||
| 1054 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | ||
| 1055 | used to control the Asynchronous Memory Bank 1 settings. | ||
| 1021 | 1056 | ||
| 1022 | config BANK_2 | 1057 | config BANK_2 |
| 1023 | hex "Bank 2" | 1058 | hex "Bank 2 (AMBCTL1.L)" |
| 1024 | default 0x7BB0 | 1059 | default 0x7BB0 |
| 1060 | help | ||
| 1061 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | ||
| 1062 | used to control the Asynchronous Memory Bank 2 settings. | ||
| 1025 | 1063 | ||
| 1026 | config BANK_3 | 1064 | config BANK_3 |
| 1027 | hex "Bank 3" | 1065 | hex "Bank 3 (AMBCTL1.H)" |
| 1028 | default 0x99B3 | 1066 | default 0x99B3 |
| 1067 | help | ||
| 1068 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | ||
| 1069 | used to control the Asynchronous Memory Bank 3 settings. | ||
| 1070 | |||
| 1029 | endmenu | 1071 | endmenu |
| 1030 | 1072 | ||
| 1031 | config EBIU_MBSCTLVAL | 1073 | config EBIU_MBSCTLVAL |
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug index 79e7e63ab709..1fc4981d486f 100644 --- a/arch/blackfin/Kconfig.debug +++ b/arch/blackfin/Kconfig.debug | |||
| @@ -54,6 +54,19 @@ config DEBUG_HWERR | |||
| 54 | hardware error interrupts and need to know where they are coming | 54 | hardware error interrupts and need to know where they are coming |
| 55 | from. | 55 | from. |
| 56 | 56 | ||
| 57 | config EXACT_HWERR | ||
| 58 | bool "Try to make Hardware errors exact" | ||
| 59 | depends on DEBUG_HWERR | ||
| 60 | help | ||
| 61 | By default, the Blackfin hardware errors are not exact - the error | ||
| 62 | be reported multiple cycles after the error happens. This delay | ||
| 63 | can cause the wrong application, or even the kernel to receive a | ||
| 64 | signal to be killed. If you are getting HW errors in your system, | ||
| 65 | try turning this on to ensure they are at least comming from the | ||
| 66 | proper thread. | ||
| 67 | |||
| 68 | On production systems, it is safe (and a small optimization) to say N. | ||
| 69 | |||
| 57 | config DEBUG_DOUBLEFAULT | 70 | config DEBUG_DOUBLEFAULT |
| 58 | bool "Debug Double Faults" | 71 | bool "Debug Double Faults" |
| 59 | default n | 72 | default n |
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile index d54c8283825c..6f9533c3d752 100644 --- a/arch/blackfin/Makefile +++ b/arch/blackfin/Makefile | |||
| @@ -137,7 +137,7 @@ archclean: | |||
| 137 | 137 | ||
| 138 | INSTALL_PATH ?= /tftpboot | 138 | INSTALL_PATH ?= /tftpboot |
| 139 | boot := arch/$(ARCH)/boot | 139 | boot := arch/$(ARCH)/boot |
| 140 | BOOT_TARGETS = vmImage | 140 | BOOT_TARGETS = vmImage vmImage.bz2 vmImage.gz vmImage.lzma |
| 141 | PHONY += $(BOOT_TARGETS) install | 141 | PHONY += $(BOOT_TARGETS) install |
| 142 | KBUILD_IMAGE := $(boot)/vmImage | 142 | KBUILD_IMAGE := $(boot)/vmImage |
| 143 | 143 | ||
| @@ -150,7 +150,10 @@ install: | |||
| 150 | $(Q)$(MAKE) $(build)=$(boot) BOOTIMAGE=$(KBUILD_IMAGE) install | 150 | $(Q)$(MAKE) $(build)=$(boot) BOOTIMAGE=$(KBUILD_IMAGE) install |
| 151 | 151 | ||
| 152 | define archhelp | 152 | define archhelp |
| 153 | echo '* vmImage - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage)' | 153 | echo '* vmImage - Alias to selected kernel format (vmImage.gz by default)' |
| 154 | echo ' vmImage.bz2 - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)' | ||
| 155 | echo '* vmImage.gz - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)' | ||
| 156 | echo ' vmImage.lzma - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)' | ||
| 154 | echo ' install - Install kernel using' | 157 | echo ' install - Install kernel using' |
| 155 | echo ' (your) ~/bin/$(CROSS_COMPILE)installkernel or' | 158 | echo ' (your) ~/bin/$(CROSS_COMPILE)installkernel or' |
| 156 | echo ' (distribution) PATH: $(CROSS_COMPILE)installkernel or' | 159 | echo ' (distribution) PATH: $(CROSS_COMPILE)installkernel or' |
diff --git a/arch/blackfin/boot/.gitignore b/arch/blackfin/boot/.gitignore index 3ae03994b88d..229e50808677 100644 --- a/arch/blackfin/boot/.gitignore +++ b/arch/blackfin/boot/.gitignore | |||
| @@ -1 +1,2 @@ | |||
| 1 | +vmImage | 1 | vmImage* |
| 2 | vmlinux* | ||
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile index e028d13481a9..3ab6f23561dd 100644 --- a/arch/blackfin/boot/Makefile +++ b/arch/blackfin/boot/Makefile | |||
| @@ -8,24 +8,41 @@ | |||
| 8 | 8 | ||
| 9 | MKIMAGE := $(srctree)/scripts/mkuboot.sh | 9 | MKIMAGE := $(srctree)/scripts/mkuboot.sh |
| 10 | 10 | ||
| 11 | targets := vmImage | 11 | targets := vmImage vmImage.bz2 vmImage.gz vmImage.lzma |
| 12 | extra-y += vmlinux.bin vmlinux.gz | 12 | extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma |
| 13 | 13 | ||
| 14 | quiet_cmd_uimage = UIMAGE $@ | 14 | quiet_cmd_uimage = UIMAGE $@ |
| 15 | cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \ | 15 | cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \ |
| 16 | -C gzip -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \ | 16 | -C $(2) -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \ |
| 17 | -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \ | 17 | -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \ |
| 18 | -d $< $@ | 18 | -d $< $@ |
| 19 | 19 | ||
| 20 | $(obj)/vmlinux.bin: vmlinux FORCE | 20 | $(obj)/vmlinux.bin: vmlinux FORCE |
| 21 | $(call if_changed,objcopy) | 21 | $(call if_changed,objcopy) |
| 22 | 22 | ||
| 23 | $(obj)/vmlinux.gz: $(obj)/vmlinux.bin FORCE | 23 | $(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE |
| 24 | $(call if_changed,gzip) | 24 | $(call if_changed,gzip) |
| 25 | 25 | ||
| 26 | $(obj)/vmImage: $(obj)/vmlinux.gz | 26 | $(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE |
| 27 | $(call if_changed,uimage) | 27 | $(call if_changed,bzip2) |
| 28 | @$(kecho) 'Kernel: $@ is ready' | 28 | |
| 29 | $(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE | ||
| 30 | $(call if_changed,lzma) | ||
| 31 | |||
| 32 | $(obj)/vmImage.bz2: $(obj)/vmlinux.bin.bz2 | ||
| 33 | $(call if_changed,uimage,bzip2) | ||
| 34 | |||
| 35 | $(obj)/vmImage.gz: $(obj)/vmlinux.bin.gz | ||
| 36 | $(call if_changed,uimage,gzip) | ||
| 37 | |||
| 38 | $(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma | ||
| 39 | $(call if_changed,uimage,lzma) | ||
| 40 | |||
| 41 | suffix-$(CONFIG_KERNEL_GZIP) := gz | ||
| 42 | suffix-$(CONFIG_KERNEL_BZIP2) := bz2 | ||
| 43 | suffix-$(CONFIG_KERNEL_LZMA) := lzma | ||
| 44 | $(obj)/vmImage: $(obj)/vmImage.$(suffix-y) | ||
| 45 | @ln -sf $(notdir $<) $@ | ||
| 29 | 46 | ||
| 30 | install: | 47 | install: |
| 31 | sh $(srctree)/$(src)/install.sh $(KERNELRELEASE) $(BOOTIMAGE) System.map "$(INSTALL_PATH)" | 48 | sh $(srctree)/$(src)/install.sh $(KERNELRELEASE) $(BOOTIMAGE) System.map "$(INSTALL_PATH)" |
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig index c121d6e6e2b8..baec1337f282 100644 --- a/arch/blackfin/configs/BF518F-EZBRD_defconfig +++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28.7 | 3 | # Linux kernel version: 2.6.28.10 |
| 4 | # Thu May 21 05:50:01 2009 | ||
| 4 | # | 5 | # |
| 5 | # CONFIG_MMU is not set | 6 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 7 | # CONFIG_FPU is not set |
| @@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 42 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 43 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 44 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 45 | # CONFIG_SYSCTL is not set | 46 | CONFIG_SYSCTL=y |
| 47 | CONFIG_ANON_INODES=y | ||
| 46 | CONFIG_EMBEDDED=y | 48 | CONFIG_EMBEDDED=y |
| 47 | CONFIG_UID16=y | 49 | CONFIG_UID16=y |
| 48 | CONFIG_SYSCTL_SYSCALL=y | 50 | # CONFIG_SYSCTL_SYSCALL is not set |
| 49 | CONFIG_KALLSYMS=y | 51 | CONFIG_KALLSYMS=y |
| 50 | # CONFIG_KALLSYMS_ALL is not set | 52 | # CONFIG_KALLSYMS_ALL is not set |
| 51 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 53 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| @@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y | |||
| 53 | CONFIG_PRINTK=y | 55 | CONFIG_PRINTK=y |
| 54 | CONFIG_BUG=y | 56 | CONFIG_BUG=y |
| 55 | # CONFIG_ELF_CORE is not set | 57 | # CONFIG_ELF_CORE is not set |
| 56 | CONFIG_COMPAT_BRK=y | ||
| 57 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 58 | # CONFIG_FUTEX is not set | 59 | # CONFIG_FUTEX is not set |
| 59 | CONFIG_ANON_INODES=y | ||
| 60 | CONFIG_EPOLL=y | 60 | CONFIG_EPOLL=y |
| 61 | CONFIG_SIGNALFD=y | 61 | # CONFIG_SIGNALFD is not set |
| 62 | CONFIG_TIMERFD=y | 62 | # CONFIG_TIMERFD is not set |
| 63 | CONFIG_EVENTFD=y | 63 | # CONFIG_EVENTFD is not set |
| 64 | # CONFIG_AIO is not set | 64 | # CONFIG_AIO is not set |
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 65 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_COMPAT_BRK=y | ||
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| @@ -71,7 +72,6 @@ CONFIG_SLAB=y | |||
| 71 | CONFIG_HAVE_OPROFILE=y | 72 | CONFIG_HAVE_OPROFILE=y |
| 72 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 73 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 74 | CONFIG_RT_MUTEXES=y | ||
| 75 | CONFIG_TINY_SHMEM=y | 75 | CONFIG_TINY_SHMEM=y |
| 76 | CONFIG_BASE_SMALL=0 | 76 | CONFIG_BASE_SMALL=0 |
| 77 | CONFIG_MODULES=y | 77 | CONFIG_MODULES=y |
| @@ -259,7 +259,10 @@ CONFIG_HZ=250 | |||
| 259 | # CONFIG_SCHED_HRTICK is not set | 259 | # CONFIG_SCHED_HRTICK is not set |
| 260 | CONFIG_GENERIC_TIME=y | 260 | CONFIG_GENERIC_TIME=y |
| 261 | CONFIG_GENERIC_CLOCKEVENTS=y | 261 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 262 | # CONFIG_TICKSOURCE_GPTMR0 is not set | ||
| 263 | CONFIG_TICKSOURCE_CORETMR=y | ||
| 262 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 264 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 265 | # CONFIG_GPTMR0_CLOCKSOURCE is not set | ||
| 263 | # CONFIG_NO_HZ is not set | 266 | # CONFIG_NO_HZ is not set |
| 264 | # CONFIG_HIGH_RES_TIMERS is not set | 267 | # CONFIG_HIGH_RES_TIMERS is not set |
| 265 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 268 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| @@ -404,7 +407,7 @@ CONFIG_IP_PNP=y | |||
| 404 | # CONFIG_NET_IPIP is not set | 407 | # CONFIG_NET_IPIP is not set |
| 405 | # CONFIG_NET_IPGRE is not set | 408 | # CONFIG_NET_IPGRE is not set |
| 406 | # CONFIG_ARPD is not set | 409 | # CONFIG_ARPD is not set |
| 407 | CONFIG_SYN_COOKIES=y | 410 | # CONFIG_SYN_COOKIES is not set |
| 408 | # CONFIG_INET_AH is not set | 411 | # CONFIG_INET_AH is not set |
| 409 | # CONFIG_INET_ESP is not set | 412 | # CONFIG_INET_ESP is not set |
| 410 | # CONFIG_INET_IPCOMP is not set | 413 | # CONFIG_INET_IPCOMP is not set |
| @@ -688,14 +691,14 @@ CONFIG_INPUT_MISC=y | |||
| 688 | # Character devices | 691 | # Character devices |
| 689 | # | 692 | # |
| 690 | # CONFIG_AD9960 is not set | 693 | # CONFIG_AD9960 is not set |
| 691 | # CONFIG_SPI_ADC_BF533 is not set | 694 | CONFIG_BFIN_DMA_INTERFACE=m |
| 692 | # CONFIG_BF5xx_PPIFCD is not set | 695 | # CONFIG_BFIN_PPI is not set |
| 696 | # CONFIG_BFIN_PPIFCD is not set | ||
| 693 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 697 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 694 | # CONFIG_BF5xx_PPI is not set | 698 | # CONFIG_BFIN_SPI_ADC is not set |
| 695 | # CONFIG_BFIN_SPORT is not set | 699 | # CONFIG_BFIN_SPORT is not set |
| 696 | # CONFIG_BFIN_TIMER_LATENCY is not set | 700 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 697 | # CONFIG_TWI_LCD is not set | 701 | # CONFIG_BFIN_TWI_LCD is not set |
| 698 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 699 | CONFIG_SIMPLE_GPIO=m | 702 | CONFIG_SIMPLE_GPIO=m |
| 700 | CONFIG_VT=y | 703 | CONFIG_VT=y |
| 701 | CONFIG_CONSOLE_TRANSLATIONS=y | 704 | CONFIG_CONSOLE_TRANSLATIONS=y |
| @@ -802,7 +805,30 @@ CONFIG_SPI_BFIN=y | |||
| 802 | # CONFIG_SPI_SPIDEV is not set | 805 | # CONFIG_SPI_SPIDEV is not set |
| 803 | # CONFIG_SPI_TLE62X0 is not set | 806 | # CONFIG_SPI_TLE62X0 is not set |
| 804 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | 807 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 805 | # CONFIG_GPIOLIB is not set | 808 | CONFIG_GPIOLIB=y |
| 809 | # CONFIG_DEBUG_GPIO is not set | ||
| 810 | CONFIG_GPIO_SYSFS=y | ||
| 811 | |||
| 812 | # | ||
| 813 | # Memory mapped GPIO expanders: | ||
| 814 | # | ||
| 815 | |||
| 816 | # | ||
| 817 | # I2C GPIO expanders: | ||
| 818 | # | ||
| 819 | # CONFIG_GPIO_MAX732X is not set | ||
| 820 | # CONFIG_GPIO_PCA953X is not set | ||
| 821 | # CONFIG_GPIO_PCF857X is not set | ||
| 822 | |||
| 823 | # | ||
| 824 | # PCI GPIO expanders: | ||
| 825 | # | ||
| 826 | |||
| 827 | # | ||
| 828 | # SPI GPIO expanders: | ||
| 829 | # | ||
| 830 | # CONFIG_GPIO_MAX7301 is not set | ||
| 831 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 806 | # CONFIG_W1 is not set | 832 | # CONFIG_W1 is not set |
| 807 | # CONFIG_POWER_SUPPLY is not set | 833 | # CONFIG_POWER_SUPPLY is not set |
| 808 | # CONFIG_HWMON is not set | 834 | # CONFIG_HWMON is not set |
| @@ -831,6 +857,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 831 | # CONFIG_HTC_PASIC3 is not set | 857 | # CONFIG_HTC_PASIC3 is not set |
| 832 | # CONFIG_MFD_TMIO is not set | 858 | # CONFIG_MFD_TMIO is not set |
| 833 | # CONFIG_PMIC_DA903X is not set | 859 | # CONFIG_PMIC_DA903X is not set |
| 860 | # CONFIG_PMIC_ADP5520 is not set | ||
| 834 | # CONFIG_MFD_WM8400 is not set | 861 | # CONFIG_MFD_WM8400 is not set |
| 835 | # CONFIG_MFD_WM8350_I2C is not set | 862 | # CONFIG_MFD_WM8350_I2C is not set |
| 836 | # CONFIG_REGULATOR is not set | 863 | # CONFIG_REGULATOR is not set |
| @@ -962,7 +989,8 @@ CONFIG_RTC_DRV_BFIN=y | |||
| 962 | # | 989 | # |
| 963 | # File systems | 990 | # File systems |
| 964 | # | 991 | # |
| 965 | # CONFIG_EXT2_FS is not set | 992 | CONFIG_EXT2_FS=m |
| 993 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 966 | # CONFIG_EXT3_FS is not set | 994 | # CONFIG_EXT3_FS is not set |
| 967 | # CONFIG_EXT4_FS is not set | 995 | # CONFIG_EXT4_FS is not set |
| 968 | # CONFIG_REISERFS_FS is not set | 996 | # CONFIG_REISERFS_FS is not set |
| @@ -988,8 +1016,11 @@ CONFIG_INOTIFY_USER=y | |||
| 988 | # | 1016 | # |
| 989 | # DOS/FAT/NT Filesystems | 1017 | # DOS/FAT/NT Filesystems |
| 990 | # | 1018 | # |
| 1019 | CONFIG_FAT_FS=m | ||
| 991 | # CONFIG_MSDOS_FS is not set | 1020 | # CONFIG_MSDOS_FS is not set |
| 992 | # CONFIG_VFAT_FS is not set | 1021 | CONFIG_VFAT_FS=m |
| 1022 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1023 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 993 | # CONFIG_NTFS_FS is not set | 1024 | # CONFIG_NTFS_FS is not set |
| 994 | 1025 | ||
| 995 | # | 1026 | # |
| @@ -1012,8 +1043,8 @@ CONFIG_SYSFS=y | |||
| 1012 | # CONFIG_BEFS_FS is not set | 1043 | # CONFIG_BEFS_FS is not set |
| 1013 | # CONFIG_BFS_FS is not set | 1044 | # CONFIG_BFS_FS is not set |
| 1014 | # CONFIG_EFS_FS is not set | 1045 | # CONFIG_EFS_FS is not set |
| 1015 | # CONFIG_YAFFS_FS is not set | ||
| 1016 | # CONFIG_JFFS2_FS is not set | 1046 | # CONFIG_JFFS2_FS is not set |
| 1047 | # CONFIG_YAFFS_FS is not set | ||
| 1017 | # CONFIG_CRAMFS is not set | 1048 | # CONFIG_CRAMFS is not set |
| 1018 | # CONFIG_VXFS_FS is not set | 1049 | # CONFIG_VXFS_FS is not set |
| 1019 | # CONFIG_MINIX_FS is not set | 1050 | # CONFIG_MINIX_FS is not set |
| @@ -1048,9 +1079,9 @@ CONFIG_SMB_FS=m | |||
| 1048 | # | 1079 | # |
| 1049 | # CONFIG_PARTITION_ADVANCED is not set | 1080 | # CONFIG_PARTITION_ADVANCED is not set |
| 1050 | CONFIG_MSDOS_PARTITION=y | 1081 | CONFIG_MSDOS_PARTITION=y |
| 1051 | CONFIG_NLS=y | 1082 | CONFIG_NLS=m |
| 1052 | CONFIG_NLS_DEFAULT="iso8859-1" | 1083 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 1053 | CONFIG_NLS_CODEPAGE_437=y | 1084 | CONFIG_NLS_CODEPAGE_437=m |
| 1054 | # CONFIG_NLS_CODEPAGE_737 is not set | 1085 | # CONFIG_NLS_CODEPAGE_737 is not set |
| 1055 | # CONFIG_NLS_CODEPAGE_775 is not set | 1086 | # CONFIG_NLS_CODEPAGE_775 is not set |
| 1056 | # CONFIG_NLS_CODEPAGE_850 is not set | 1087 | # CONFIG_NLS_CODEPAGE_850 is not set |
| @@ -1065,7 +1096,7 @@ CONFIG_NLS_CODEPAGE_437=y | |||
| 1065 | # CONFIG_NLS_CODEPAGE_865 is not set | 1096 | # CONFIG_NLS_CODEPAGE_865 is not set |
| 1066 | # CONFIG_NLS_CODEPAGE_866 is not set | 1097 | # CONFIG_NLS_CODEPAGE_866 is not set |
| 1067 | # CONFIG_NLS_CODEPAGE_869 is not set | 1098 | # CONFIG_NLS_CODEPAGE_869 is not set |
| 1068 | # CONFIG_NLS_CODEPAGE_936 is not set | 1099 | CONFIG_NLS_CODEPAGE_936=m |
| 1069 | # CONFIG_NLS_CODEPAGE_950 is not set | 1100 | # CONFIG_NLS_CODEPAGE_950 is not set |
| 1070 | # CONFIG_NLS_CODEPAGE_932 is not set | 1101 | # CONFIG_NLS_CODEPAGE_932 is not set |
| 1071 | # CONFIG_NLS_CODEPAGE_949 is not set | 1102 | # CONFIG_NLS_CODEPAGE_949 is not set |
| @@ -1074,7 +1105,7 @@ CONFIG_NLS_CODEPAGE_437=y | |||
| 1074 | # CONFIG_NLS_CODEPAGE_1250 is not set | 1105 | # CONFIG_NLS_CODEPAGE_1250 is not set |
| 1075 | # CONFIG_NLS_CODEPAGE_1251 is not set | 1106 | # CONFIG_NLS_CODEPAGE_1251 is not set |
| 1076 | # CONFIG_NLS_ASCII is not set | 1107 | # CONFIG_NLS_ASCII is not set |
| 1077 | CONFIG_NLS_ISO8859_1=y | 1108 | CONFIG_NLS_ISO8859_1=m |
| 1078 | # CONFIG_NLS_ISO8859_2 is not set | 1109 | # CONFIG_NLS_ISO8859_2 is not set |
| 1079 | # CONFIG_NLS_ISO8859_3 is not set | 1110 | # CONFIG_NLS_ISO8859_3 is not set |
| 1080 | # CONFIG_NLS_ISO8859_4 is not set | 1111 | # CONFIG_NLS_ISO8859_4 is not set |
| @@ -1087,7 +1118,7 @@ CONFIG_NLS_ISO8859_1=y | |||
| 1087 | # CONFIG_NLS_ISO8859_15 is not set | 1118 | # CONFIG_NLS_ISO8859_15 is not set |
| 1088 | # CONFIG_NLS_KOI8_R is not set | 1119 | # CONFIG_NLS_KOI8_R is not set |
| 1089 | # CONFIG_NLS_KOI8_U is not set | 1120 | # CONFIG_NLS_KOI8_U is not set |
| 1090 | # CONFIG_NLS_UTF8 is not set | 1121 | CONFIG_NLS_UTF8=m |
| 1091 | # CONFIG_DLM is not set | 1122 | # CONFIG_DLM is not set |
| 1092 | 1123 | ||
| 1093 | # | 1124 | # |
| @@ -1102,7 +1133,7 @@ CONFIG_FRAME_WARN=1024 | |||
| 1102 | CONFIG_DEBUG_FS=y | 1133 | CONFIG_DEBUG_FS=y |
| 1103 | # CONFIG_HEADERS_CHECK is not set | 1134 | # CONFIG_HEADERS_CHECK is not set |
| 1104 | CONFIG_DEBUG_KERNEL=y | 1135 | CONFIG_DEBUG_KERNEL=y |
| 1105 | # CONFIG_DEBUG_SHIRQ is not set | 1136 | CONFIG_DEBUG_SHIRQ=y |
| 1106 | CONFIG_DETECT_SOFTLOCKUP=y | 1137 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1107 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | 1138 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set |
| 1108 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | 1139 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 |
| @@ -1111,8 +1142,6 @@ CONFIG_SCHED_DEBUG=y | |||
| 1111 | # CONFIG_TIMER_STATS is not set | 1142 | # CONFIG_TIMER_STATS is not set |
| 1112 | # CONFIG_DEBUG_OBJECTS is not set | 1143 | # CONFIG_DEBUG_OBJECTS is not set |
| 1113 | # CONFIG_DEBUG_SLAB is not set | 1144 | # CONFIG_DEBUG_SLAB is not set |
| 1114 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1115 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1116 | # CONFIG_DEBUG_SPINLOCK is not set | 1145 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1117 | # CONFIG_DEBUG_MUTEXES is not set | 1146 | # CONFIG_DEBUG_MUTEXES is not set |
| 1118 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1147 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| @@ -1132,7 +1161,6 @@ CONFIG_DEBUG_INFO=y | |||
| 1132 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1161 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1133 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 1162 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
| 1134 | # CONFIG_FAULT_INJECTION is not set | 1163 | # CONFIG_FAULT_INJECTION is not set |
| 1135 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 1136 | 1164 | ||
| 1137 | # | 1165 | # |
| 1138 | # Tracers | 1166 | # Tracers |
| @@ -1148,16 +1176,20 @@ CONFIG_HAVE_ARCH_KGDB=y | |||
| 1148 | # CONFIG_DEBUG_STACK_USAGE is not set | 1176 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1149 | CONFIG_DEBUG_VERBOSE=y | 1177 | CONFIG_DEBUG_VERBOSE=y |
| 1150 | CONFIG_DEBUG_MMRS=y | 1178 | CONFIG_DEBUG_MMRS=y |
| 1151 | # CONFIG_DEBUG_HWERR is not set | 1179 | CONFIG_DEBUG_HWERR=y |
| 1152 | # CONFIG_DEBUG_DOUBLEFAULT is not set | 1180 | CONFIG_EXACT_HWERR=y |
| 1181 | CONFIG_DEBUG_DOUBLEFAULT=y | ||
| 1182 | CONFIG_DEBUG_DOUBLEFAULT_PRINT=y | ||
| 1183 | # CONFIG_DEBUG_DOUBLEFAULT_RESET is not set | ||
| 1184 | # CONFIG_DEBUG_ICACHE_CHECK is not set | ||
| 1153 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1185 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1154 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1186 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1155 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1187 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set |
| 1156 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set | 1188 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y |
| 1157 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set | 1189 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set |
| 1158 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 | 1190 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1 |
| 1159 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set | 1191 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set |
| 1160 | # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set | 1192 | CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y |
| 1161 | CONFIG_EARLY_PRINTK=y | 1193 | CONFIG_EARLY_PRINTK=y |
| 1162 | CONFIG_CPLB_INFO=y | 1194 | CONFIG_CPLB_INFO=y |
| 1163 | CONFIG_ACCESS_CHECK=y | 1195 | CONFIG_ACCESS_CHECK=y |
| @@ -1269,7 +1301,6 @@ CONFIG_CRC32=y | |||
| 1269 | # CONFIG_CRC7 is not set | 1301 | # CONFIG_CRC7 is not set |
| 1270 | # CONFIG_LIBCRC32C is not set | 1302 | # CONFIG_LIBCRC32C is not set |
| 1271 | CONFIG_ZLIB_INFLATE=y | 1303 | CONFIG_ZLIB_INFLATE=y |
| 1272 | CONFIG_PLIST=y | ||
| 1273 | CONFIG_HAS_IOMEM=y | 1304 | CONFIG_HAS_IOMEM=y |
| 1274 | CONFIG_HAS_IOPORT=y | 1305 | CONFIG_HAS_IOPORT=y |
| 1275 | CONFIG_HAS_DMA=y | 1306 | CONFIG_HAS_DMA=y |
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig index 3e562b2775d4..c06262e41f7c 100644 --- a/arch/blackfin/configs/BF526-EZBRD_defconfig +++ b/arch/blackfin/configs/BF526-EZBRD_defconfig | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28.7 | 3 | # Linux kernel version: 2.6.28.10 |
| 4 | # Thu May 21 05:50:01 2009 | ||
| 4 | # | 5 | # |
| 5 | # CONFIG_MMU is not set | 6 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 7 | # CONFIG_FPU is not set |
| @@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 42 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 43 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 44 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 45 | # CONFIG_SYSCTL is not set | 46 | CONFIG_SYSCTL=y |
| 47 | CONFIG_ANON_INODES=y | ||
| 46 | CONFIG_EMBEDDED=y | 48 | CONFIG_EMBEDDED=y |
| 47 | CONFIG_UID16=y | 49 | CONFIG_UID16=y |
| 48 | CONFIG_SYSCTL_SYSCALL=y | 50 | # CONFIG_SYSCTL_SYSCALL is not set |
| 49 | CONFIG_KALLSYMS=y | 51 | CONFIG_KALLSYMS=y |
| 50 | # CONFIG_KALLSYMS_ALL is not set | 52 | # CONFIG_KALLSYMS_ALL is not set |
| 51 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 53 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| @@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y | |||
| 53 | CONFIG_PRINTK=y | 55 | CONFIG_PRINTK=y |
| 54 | CONFIG_BUG=y | 56 | CONFIG_BUG=y |
| 55 | # CONFIG_ELF_CORE is not set | 57 | # CONFIG_ELF_CORE is not set |
| 56 | CONFIG_COMPAT_BRK=y | ||
| 57 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 58 | # CONFIG_FUTEX is not set | 59 | # CONFIG_FUTEX is not set |
| 59 | CONFIG_ANON_INODES=y | ||
| 60 | CONFIG_EPOLL=y | 60 | CONFIG_EPOLL=y |
| 61 | CONFIG_SIGNALFD=y | 61 | # CONFIG_SIGNALFD is not set |
| 62 | CONFIG_TIMERFD=y | 62 | # CONFIG_TIMERFD is not set |
| 63 | CONFIG_EVENTFD=y | 63 | # CONFIG_EVENTFD is not set |
| 64 | # CONFIG_AIO is not set | 64 | # CONFIG_AIO is not set |
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 65 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_COMPAT_BRK=y | ||
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| @@ -71,7 +72,6 @@ CONFIG_SLAB=y | |||
| 71 | CONFIG_HAVE_OPROFILE=y | 72 | CONFIG_HAVE_OPROFILE=y |
| 72 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 73 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 74 | CONFIG_RT_MUTEXES=y | ||
| 75 | CONFIG_TINY_SHMEM=y | 75 | CONFIG_TINY_SHMEM=y |
| 76 | CONFIG_BASE_SMALL=0 | 76 | CONFIG_BASE_SMALL=0 |
| 77 | CONFIG_MODULES=y | 77 | CONFIG_MODULES=y |
| @@ -144,8 +144,8 @@ CONFIG_BF526=y | |||
| 144 | # CONFIG_BF561 is not set | 144 | # CONFIG_BF561 is not set |
| 145 | CONFIG_BF_REV_MIN=0 | 145 | CONFIG_BF_REV_MIN=0 |
| 146 | CONFIG_BF_REV_MAX=2 | 146 | CONFIG_BF_REV_MAX=2 |
| 147 | # CONFIG_BF_REV_0_0 is not set | 147 | CONFIG_BF_REV_0_0=y |
| 148 | CONFIG_BF_REV_0_1=y | 148 | # CONFIG_BF_REV_0_1 is not set |
| 149 | # CONFIG_BF_REV_0_2 is not set | 149 | # CONFIG_BF_REV_0_2 is not set |
| 150 | # CONFIG_BF_REV_0_3 is not set | 150 | # CONFIG_BF_REV_0_3 is not set |
| 151 | # CONFIG_BF_REV_0_4 is not set | 151 | # CONFIG_BF_REV_0_4 is not set |
| @@ -264,7 +264,10 @@ CONFIG_HZ=250 | |||
| 264 | # CONFIG_SCHED_HRTICK is not set | 264 | # CONFIG_SCHED_HRTICK is not set |
| 265 | CONFIG_GENERIC_TIME=y | 265 | CONFIG_GENERIC_TIME=y |
| 266 | CONFIG_GENERIC_CLOCKEVENTS=y | 266 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 267 | # CONFIG_TICKSOURCE_GPTMR0 is not set | ||
| 268 | CONFIG_TICKSOURCE_CORETMR=y | ||
| 267 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 269 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 270 | # CONFIG_GPTMR0_CLOCKSOURCE is not set | ||
| 268 | # CONFIG_NO_HZ is not set | 271 | # CONFIG_NO_HZ is not set |
| 269 | # CONFIG_HIGH_RES_TIMERS is not set | 272 | # CONFIG_HIGH_RES_TIMERS is not set |
| 270 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 273 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| @@ -409,7 +412,7 @@ CONFIG_IP_PNP=y | |||
| 409 | # CONFIG_NET_IPIP is not set | 412 | # CONFIG_NET_IPIP is not set |
| 410 | # CONFIG_NET_IPGRE is not set | 413 | # CONFIG_NET_IPGRE is not set |
| 411 | # CONFIG_ARPD is not set | 414 | # CONFIG_ARPD is not set |
| 412 | CONFIG_SYN_COOKIES=y | 415 | # CONFIG_SYN_COOKIES is not set |
| 413 | # CONFIG_INET_AH is not set | 416 | # CONFIG_INET_AH is not set |
| 414 | # CONFIG_INET_ESP is not set | 417 | # CONFIG_INET_ESP is not set |
| 415 | # CONFIG_INET_IPCOMP is not set | 418 | # CONFIG_INET_IPCOMP is not set |
| @@ -491,7 +494,7 @@ CONFIG_MTD_PARTITIONS=y | |||
| 491 | # | 494 | # |
| 492 | # User Modules And Translation Layers | 495 | # User Modules And Translation Layers |
| 493 | # | 496 | # |
| 494 | CONFIG_MTD_CHAR=m | 497 | CONFIG_MTD_CHAR=y |
| 495 | CONFIG_MTD_BLKDEVS=y | 498 | CONFIG_MTD_BLKDEVS=y |
| 496 | CONFIG_MTD_BLOCK=y | 499 | CONFIG_MTD_BLOCK=y |
| 497 | # CONFIG_FTL is not set | 500 | # CONFIG_FTL is not set |
| @@ -504,9 +507,9 @@ CONFIG_MTD_BLOCK=y | |||
| 504 | # | 507 | # |
| 505 | # RAM/ROM/Flash chip drivers | 508 | # RAM/ROM/Flash chip drivers |
| 506 | # | 509 | # |
| 507 | # CONFIG_MTD_CFI is not set | 510 | CONFIG_MTD_CFI=y |
| 508 | CONFIG_MTD_JEDECPROBE=m | 511 | # CONFIG_MTD_JEDECPROBE is not set |
| 509 | CONFIG_MTD_GEN_PROBE=m | 512 | CONFIG_MTD_GEN_PROBE=y |
| 510 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | 513 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set |
| 511 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | 514 | CONFIG_MTD_MAP_BANK_WIDTH_1=y |
| 512 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | 515 | CONFIG_MTD_MAP_BANK_WIDTH_2=y |
| @@ -518,9 +521,10 @@ CONFIG_MTD_CFI_I1=y | |||
| 518 | CONFIG_MTD_CFI_I2=y | 521 | CONFIG_MTD_CFI_I2=y |
| 519 | # CONFIG_MTD_CFI_I4 is not set | 522 | # CONFIG_MTD_CFI_I4 is not set |
| 520 | # CONFIG_MTD_CFI_I8 is not set | 523 | # CONFIG_MTD_CFI_I8 is not set |
| 521 | # CONFIG_MTD_CFI_INTELEXT is not set | 524 | CONFIG_MTD_CFI_INTELEXT=y |
| 522 | # CONFIG_MTD_CFI_AMDSTD is not set | 525 | # CONFIG_MTD_CFI_AMDSTD is not set |
| 523 | # CONFIG_MTD_CFI_STAA is not set | 526 | # CONFIG_MTD_CFI_STAA is not set |
| 527 | CONFIG_MTD_CFI_UTIL=y | ||
| 524 | CONFIG_MTD_RAM=y | 528 | CONFIG_MTD_RAM=y |
| 525 | CONFIG_MTD_ROM=m | 529 | CONFIG_MTD_ROM=m |
| 526 | # CONFIG_MTD_ABSENT is not set | 530 | # CONFIG_MTD_ABSENT is not set |
| @@ -529,7 +533,8 @@ CONFIG_MTD_ROM=m | |||
| 529 | # Mapping drivers for chip access | 533 | # Mapping drivers for chip access |
| 530 | # | 534 | # |
| 531 | CONFIG_MTD_COMPLEX_MAPPINGS=y | 535 | CONFIG_MTD_COMPLEX_MAPPINGS=y |
| 532 | # CONFIG_MTD_PHYSMAP is not set | 536 | CONFIG_MTD_PHYSMAP=y |
| 537 | # CONFIG_MTD_PHYSMAP_COMPAT is not set | ||
| 533 | # CONFIG_MTD_GPIO_ADDR is not set | 538 | # CONFIG_MTD_GPIO_ADDR is not set |
| 534 | # CONFIG_MTD_UCLINUX is not set | 539 | # CONFIG_MTD_UCLINUX is not set |
| 535 | # CONFIG_MTD_PLATRAM is not set | 540 | # CONFIG_MTD_PLATRAM is not set |
| @@ -597,9 +602,42 @@ CONFIG_HAVE_IDE=y | |||
| 597 | # SCSI device support | 602 | # SCSI device support |
| 598 | # | 603 | # |
| 599 | # CONFIG_RAID_ATTRS is not set | 604 | # CONFIG_RAID_ATTRS is not set |
| 600 | # CONFIG_SCSI is not set | 605 | CONFIG_SCSI=y |
| 601 | # CONFIG_SCSI_DMA is not set | 606 | CONFIG_SCSI_DMA=y |
| 607 | # CONFIG_SCSI_TGT is not set | ||
| 602 | # CONFIG_SCSI_NETLINK is not set | 608 | # CONFIG_SCSI_NETLINK is not set |
| 609 | # CONFIG_SCSI_PROC_FS is not set | ||
| 610 | |||
| 611 | # | ||
| 612 | # SCSI support type (disk, tape, CD-ROM) | ||
| 613 | # | ||
| 614 | CONFIG_BLK_DEV_SD=y | ||
| 615 | # CONFIG_CHR_DEV_ST is not set | ||
| 616 | # CONFIG_CHR_DEV_OSST is not set | ||
| 617 | CONFIG_BLK_DEV_SR=m | ||
| 618 | # CONFIG_BLK_DEV_SR_VENDOR is not set | ||
| 619 | # CONFIG_CHR_DEV_SG is not set | ||
| 620 | # CONFIG_CHR_DEV_SCH is not set | ||
| 621 | |||
| 622 | # | ||
| 623 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 624 | # | ||
| 625 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 626 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 627 | # CONFIG_SCSI_LOGGING is not set | ||
| 628 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 629 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 630 | |||
| 631 | # | ||
| 632 | # SCSI Transports | ||
| 633 | # | ||
| 634 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 635 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 636 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 637 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 638 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 639 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 640 | # CONFIG_SCSI_DH is not set | ||
| 603 | # CONFIG_ATA is not set | 641 | # CONFIG_ATA is not set |
| 604 | # CONFIG_MD is not set | 642 | # CONFIG_MD is not set |
| 605 | CONFIG_NETDEVICES=y | 643 | CONFIG_NETDEVICES=y |
| @@ -644,9 +682,8 @@ CONFIG_BFIN_MAC_RMII=y | |||
| 644 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | 682 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set |
| 645 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | 683 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set |
| 646 | # CONFIG_B44 is not set | 684 | # CONFIG_B44 is not set |
| 647 | CONFIG_NETDEV_1000=y | 685 | # CONFIG_NETDEV_1000 is not set |
| 648 | # CONFIG_AX88180 is not set | 686 | # CONFIG_NETDEV_10000 is not set |
| 649 | CONFIG_NETDEV_10000=y | ||
| 650 | 687 | ||
| 651 | # | 688 | # |
| 652 | # Wireless LAN | 689 | # Wireless LAN |
| @@ -715,14 +752,14 @@ CONFIG_INPUT_MISC=y | |||
| 715 | # Character devices | 752 | # Character devices |
| 716 | # | 753 | # |
| 717 | # CONFIG_AD9960 is not set | 754 | # CONFIG_AD9960 is not set |
| 718 | # CONFIG_SPI_ADC_BF533 is not set | 755 | CONFIG_BFIN_DMA_INTERFACE=m |
| 719 | # CONFIG_BF5xx_PPIFCD is not set | 756 | # CONFIG_BFIN_PPI is not set |
| 757 | # CONFIG_BFIN_PPIFCD is not set | ||
| 720 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 758 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 721 | # CONFIG_BF5xx_PPI is not set | 759 | # CONFIG_BFIN_SPI_ADC is not set |
| 722 | # CONFIG_BFIN_SPORT is not set | 760 | # CONFIG_BFIN_SPORT is not set |
| 723 | # CONFIG_BFIN_TIMER_LATENCY is not set | 761 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 724 | # CONFIG_TWI_LCD is not set | 762 | # CONFIG_BFIN_TWI_LCD is not set |
| 725 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 726 | CONFIG_SIMPLE_GPIO=m | 763 | CONFIG_SIMPLE_GPIO=m |
| 727 | CONFIG_VT=y | 764 | CONFIG_VT=y |
| 728 | CONFIG_CONSOLE_TRANSLATIONS=y | 765 | CONFIG_CONSOLE_TRANSLATIONS=y |
| @@ -832,11 +869,35 @@ CONFIG_SPI_BFIN=y | |||
| 832 | # CONFIG_SPI_SPIDEV is not set | 869 | # CONFIG_SPI_SPIDEV is not set |
| 833 | # CONFIG_SPI_TLE62X0 is not set | 870 | # CONFIG_SPI_TLE62X0 is not set |
| 834 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | 871 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 835 | # CONFIG_GPIOLIB is not set | 872 | CONFIG_GPIOLIB=y |
| 873 | # CONFIG_DEBUG_GPIO is not set | ||
| 874 | CONFIG_GPIO_SYSFS=y | ||
| 875 | |||
| 876 | # | ||
| 877 | # Memory mapped GPIO expanders: | ||
| 878 | # | ||
| 879 | |||
| 880 | # | ||
| 881 | # I2C GPIO expanders: | ||
| 882 | # | ||
| 883 | # CONFIG_GPIO_MAX732X is not set | ||
| 884 | # CONFIG_GPIO_PCA953X is not set | ||
| 885 | # CONFIG_GPIO_PCF857X is not set | ||
| 886 | |||
| 887 | # | ||
| 888 | # PCI GPIO expanders: | ||
| 889 | # | ||
| 890 | |||
| 891 | # | ||
| 892 | # SPI GPIO expanders: | ||
| 893 | # | ||
| 894 | # CONFIG_GPIO_MAX7301 is not set | ||
| 895 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 836 | # CONFIG_W1 is not set | 896 | # CONFIG_W1 is not set |
| 837 | # CONFIG_POWER_SUPPLY is not set | 897 | # CONFIG_POWER_SUPPLY is not set |
| 838 | CONFIG_HWMON=y | 898 | CONFIG_HWMON=y |
| 839 | # CONFIG_HWMON_VID is not set | 899 | # CONFIG_HWMON_VID is not set |
| 900 | # CONFIG_SENSORS_AD5252 is not set | ||
| 840 | # CONFIG_SENSORS_AD7414 is not set | 901 | # CONFIG_SENSORS_AD7414 is not set |
| 841 | # CONFIG_SENSORS_AD7418 is not set | 902 | # CONFIG_SENSORS_AD7418 is not set |
| 842 | # CONFIG_SENSORS_ADCXX is not set | 903 | # CONFIG_SENSORS_ADCXX is not set |
| @@ -920,6 +981,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 920 | # CONFIG_HTC_PASIC3 is not set | 981 | # CONFIG_HTC_PASIC3 is not set |
| 921 | # CONFIG_MFD_TMIO is not set | 982 | # CONFIG_MFD_TMIO is not set |
| 922 | # CONFIG_PMIC_DA903X is not set | 983 | # CONFIG_PMIC_DA903X is not set |
| 984 | # CONFIG_PMIC_ADP5520 is not set | ||
| 923 | # CONFIG_MFD_WM8400 is not set | 985 | # CONFIG_MFD_WM8400 is not set |
| 924 | # CONFIG_MFD_WM8350_I2C is not set | 986 | # CONFIG_MFD_WM8350_I2C is not set |
| 925 | # CONFIG_REGULATOR is not set | 987 | # CONFIG_REGULATOR is not set |
| @@ -1008,8 +1070,8 @@ CONFIG_USB=y | |||
| 1008 | # | 1070 | # |
| 1009 | # Miscellaneous USB options | 1071 | # Miscellaneous USB options |
| 1010 | # | 1072 | # |
| 1011 | # CONFIG_USB_DEVICEFS is not set | 1073 | CONFIG_USB_DEVICEFS=y |
| 1012 | CONFIG_USB_DEVICE_CLASS=y | 1074 | # CONFIG_USB_DEVICE_CLASS is not set |
| 1013 | # CONFIG_USB_DYNAMIC_MINORS is not set | 1075 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 1014 | # CONFIG_USB_OTG is not set | 1076 | # CONFIG_USB_OTG is not set |
| 1015 | # CONFIG_USB_OTG_WHITELIST is not set | 1077 | # CONFIG_USB_OTG_WHITELIST is not set |
| @@ -1037,10 +1099,10 @@ CONFIG_USB_MUSB_SOC=y | |||
| 1037 | CONFIG_USB_MUSB_HOST=y | 1099 | CONFIG_USB_MUSB_HOST=y |
| 1038 | # CONFIG_USB_MUSB_PERIPHERAL is not set | 1100 | # CONFIG_USB_MUSB_PERIPHERAL is not set |
| 1039 | # CONFIG_USB_MUSB_OTG is not set | 1101 | # CONFIG_USB_MUSB_OTG is not set |
| 1040 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 1041 | CONFIG_USB_MUSB_HDRC_HCD=y | 1102 | CONFIG_USB_MUSB_HDRC_HCD=y |
| 1042 | CONFIG_MUSB_PIO_ONLY=y | 1103 | # CONFIG_MUSB_PIO_ONLY is not set |
| 1043 | CONFIG_MUSB_DMA_POLL=y | 1104 | CONFIG_USB_INVENTRA_DMA=y |
| 1105 | # CONFIG_USB_TI_CPPI_DMA is not set | ||
| 1044 | # CONFIG_USB_MUSB_DEBUG is not set | 1106 | # CONFIG_USB_MUSB_DEBUG is not set |
| 1045 | 1107 | ||
| 1046 | # | 1108 | # |
| @@ -1058,7 +1120,7 @@ CONFIG_MUSB_DMA_POLL=y | |||
| 1058 | # | 1120 | # |
| 1059 | # see USB_STORAGE Help for more information | 1121 | # see USB_STORAGE Help for more information |
| 1060 | # | 1122 | # |
| 1061 | CONFIG_USB_STORAGE=m | 1123 | CONFIG_USB_STORAGE=y |
| 1062 | # CONFIG_USB_STORAGE_DEBUG is not set | 1124 | # CONFIG_USB_STORAGE_DEBUG is not set |
| 1063 | # CONFIG_USB_STORAGE_DATAFAB is not set | 1125 | # CONFIG_USB_STORAGE_DATAFAB is not set |
| 1064 | # CONFIG_USB_STORAGE_FREECOM is not set | 1126 | # CONFIG_USB_STORAGE_FREECOM is not set |
| @@ -1107,33 +1169,10 @@ CONFIG_USB_STORAGE=m | |||
| 1107 | # CONFIG_USB_LD is not set | 1169 | # CONFIG_USB_LD is not set |
| 1108 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1170 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 1109 | # CONFIG_USB_IOWARRIOR is not set | 1171 | # CONFIG_USB_IOWARRIOR is not set |
| 1172 | # CONFIG_USB_TEST is not set | ||
| 1110 | # CONFIG_USB_ISIGHTFW is not set | 1173 | # CONFIG_USB_ISIGHTFW is not set |
| 1111 | # CONFIG_USB_VST is not set | 1174 | # CONFIG_USB_VST is not set |
| 1112 | # CONFIG_USB_GADGET is not set | 1175 | # CONFIG_USB_GADGET is not set |
| 1113 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 1114 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 1115 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 1116 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 1117 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 1118 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1119 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 1120 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 1121 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1122 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1123 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1124 | # CONFIG_USB_GADGET_NET2272 is not set | ||
| 1125 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1126 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1127 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 1128 | # CONFIG_USB_ZERO is not set | ||
| 1129 | # CONFIG_USB_AUDIO is not set | ||
| 1130 | # CONFIG_USB_ETH is not set | ||
| 1131 | # CONFIG_USB_GADGETFS is not set | ||
| 1132 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 1133 | # CONFIG_USB_G_SERIAL is not set | ||
| 1134 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 1135 | # CONFIG_USB_G_PRINTER is not set | ||
| 1136 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 1137 | # CONFIG_MMC is not set | 1176 | # CONFIG_MMC is not set |
| 1138 | # CONFIG_MEMSTICK is not set | 1177 | # CONFIG_MEMSTICK is not set |
| 1139 | # CONFIG_NEW_LEDS is not set | 1178 | # CONFIG_NEW_LEDS is not set |
| @@ -1206,7 +1245,8 @@ CONFIG_RTC_DRV_BFIN=y | |||
| 1206 | # | 1245 | # |
| 1207 | # File systems | 1246 | # File systems |
| 1208 | # | 1247 | # |
| 1209 | # CONFIG_EXT2_FS is not set | 1248 | CONFIG_EXT2_FS=m |
| 1249 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1210 | # CONFIG_EXT3_FS is not set | 1250 | # CONFIG_EXT3_FS is not set |
| 1211 | # CONFIG_EXT4_FS is not set | 1251 | # CONFIG_EXT4_FS is not set |
| 1212 | # CONFIG_REISERFS_FS is not set | 1252 | # CONFIG_REISERFS_FS is not set |
| @@ -1226,14 +1266,19 @@ CONFIG_INOTIFY_USER=y | |||
| 1226 | # | 1266 | # |
| 1227 | # CD-ROM/DVD Filesystems | 1267 | # CD-ROM/DVD Filesystems |
| 1228 | # | 1268 | # |
| 1229 | # CONFIG_ISO9660_FS is not set | 1269 | CONFIG_ISO9660_FS=m |
| 1270 | CONFIG_JOLIET=y | ||
| 1271 | # CONFIG_ZISOFS is not set | ||
| 1230 | # CONFIG_UDF_FS is not set | 1272 | # CONFIG_UDF_FS is not set |
| 1231 | 1273 | ||
| 1232 | # | 1274 | # |
| 1233 | # DOS/FAT/NT Filesystems | 1275 | # DOS/FAT/NT Filesystems |
| 1234 | # | 1276 | # |
| 1277 | CONFIG_FAT_FS=m | ||
| 1235 | # CONFIG_MSDOS_FS is not set | 1278 | # CONFIG_MSDOS_FS is not set |
| 1236 | # CONFIG_VFAT_FS is not set | 1279 | CONFIG_VFAT_FS=m |
| 1280 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1281 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1237 | # CONFIG_NTFS_FS is not set | 1282 | # CONFIG_NTFS_FS is not set |
| 1238 | 1283 | ||
| 1239 | # | 1284 | # |
| @@ -1256,16 +1301,6 @@ CONFIG_SYSFS=y | |||
| 1256 | # CONFIG_BEFS_FS is not set | 1301 | # CONFIG_BEFS_FS is not set |
| 1257 | # CONFIG_BFS_FS is not set | 1302 | # CONFIG_BFS_FS is not set |
| 1258 | # CONFIG_EFS_FS is not set | 1303 | # CONFIG_EFS_FS is not set |
| 1259 | CONFIG_YAFFS_FS=m | ||
| 1260 | CONFIG_YAFFS_YAFFS1=y | ||
| 1261 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1262 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1263 | CONFIG_YAFFS_YAFFS2=y | ||
| 1264 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1265 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1266 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1267 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1268 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1269 | CONFIG_JFFS2_FS=m | 1304 | CONFIG_JFFS2_FS=m |
| 1270 | CONFIG_JFFS2_FS_DEBUG=0 | 1305 | CONFIG_JFFS2_FS_DEBUG=0 |
| 1271 | CONFIG_JFFS2_FS_WRITEBUFFER=y | 1306 | CONFIG_JFFS2_FS_WRITEBUFFER=y |
| @@ -1277,6 +1312,16 @@ CONFIG_JFFS2_ZLIB=y | |||
| 1277 | # CONFIG_JFFS2_LZO is not set | 1312 | # CONFIG_JFFS2_LZO is not set |
| 1278 | CONFIG_JFFS2_RTIME=y | 1313 | CONFIG_JFFS2_RTIME=y |
| 1279 | # CONFIG_JFFS2_RUBIN is not set | 1314 | # CONFIG_JFFS2_RUBIN is not set |
| 1315 | CONFIG_YAFFS_FS=m | ||
| 1316 | CONFIG_YAFFS_YAFFS1=y | ||
| 1317 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1318 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1319 | CONFIG_YAFFS_YAFFS2=y | ||
| 1320 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1321 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1322 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1323 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1324 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1280 | # CONFIG_CRAMFS is not set | 1325 | # CONFIG_CRAMFS is not set |
| 1281 | # CONFIG_VXFS_FS is not set | 1326 | # CONFIG_VXFS_FS is not set |
| 1282 | # CONFIG_MINIX_FS is not set | 1327 | # CONFIG_MINIX_FS is not set |
| @@ -1313,7 +1358,7 @@ CONFIG_SMB_FS=m | |||
| 1313 | CONFIG_MSDOS_PARTITION=y | 1358 | CONFIG_MSDOS_PARTITION=y |
| 1314 | CONFIG_NLS=m | 1359 | CONFIG_NLS=m |
| 1315 | CONFIG_NLS_DEFAULT="iso8859-1" | 1360 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 1316 | # CONFIG_NLS_CODEPAGE_437 is not set | 1361 | CONFIG_NLS_CODEPAGE_437=m |
| 1317 | # CONFIG_NLS_CODEPAGE_737 is not set | 1362 | # CONFIG_NLS_CODEPAGE_737 is not set |
| 1318 | # CONFIG_NLS_CODEPAGE_775 is not set | 1363 | # CONFIG_NLS_CODEPAGE_775 is not set |
| 1319 | # CONFIG_NLS_CODEPAGE_850 is not set | 1364 | # CONFIG_NLS_CODEPAGE_850 is not set |
| @@ -1328,7 +1373,7 @@ CONFIG_NLS_DEFAULT="iso8859-1" | |||
| 1328 | # CONFIG_NLS_CODEPAGE_865 is not set | 1373 | # CONFIG_NLS_CODEPAGE_865 is not set |
| 1329 | # CONFIG_NLS_CODEPAGE_866 is not set | 1374 | # CONFIG_NLS_CODEPAGE_866 is not set |
| 1330 | # CONFIG_NLS_CODEPAGE_869 is not set | 1375 | # CONFIG_NLS_CODEPAGE_869 is not set |
| 1331 | # CONFIG_NLS_CODEPAGE_936 is not set | 1376 | CONFIG_NLS_CODEPAGE_936=m |
| 1332 | # CONFIG_NLS_CODEPAGE_950 is not set | 1377 | # CONFIG_NLS_CODEPAGE_950 is not set |
| 1333 | # CONFIG_NLS_CODEPAGE_932 is not set | 1378 | # CONFIG_NLS_CODEPAGE_932 is not set |
| 1334 | # CONFIG_NLS_CODEPAGE_949 is not set | 1379 | # CONFIG_NLS_CODEPAGE_949 is not set |
| @@ -1337,7 +1382,7 @@ CONFIG_NLS_DEFAULT="iso8859-1" | |||
| 1337 | # CONFIG_NLS_CODEPAGE_1250 is not set | 1382 | # CONFIG_NLS_CODEPAGE_1250 is not set |
| 1338 | # CONFIG_NLS_CODEPAGE_1251 is not set | 1383 | # CONFIG_NLS_CODEPAGE_1251 is not set |
| 1339 | # CONFIG_NLS_ASCII is not set | 1384 | # CONFIG_NLS_ASCII is not set |
| 1340 | # CONFIG_NLS_ISO8859_1 is not set | 1385 | CONFIG_NLS_ISO8859_1=m |
| 1341 | # CONFIG_NLS_ISO8859_2 is not set | 1386 | # CONFIG_NLS_ISO8859_2 is not set |
| 1342 | # CONFIG_NLS_ISO8859_3 is not set | 1387 | # CONFIG_NLS_ISO8859_3 is not set |
| 1343 | # CONFIG_NLS_ISO8859_4 is not set | 1388 | # CONFIG_NLS_ISO8859_4 is not set |
| @@ -1350,7 +1395,7 @@ CONFIG_NLS_DEFAULT="iso8859-1" | |||
| 1350 | # CONFIG_NLS_ISO8859_15 is not set | 1395 | # CONFIG_NLS_ISO8859_15 is not set |
| 1351 | # CONFIG_NLS_KOI8_R is not set | 1396 | # CONFIG_NLS_KOI8_R is not set |
| 1352 | # CONFIG_NLS_KOI8_U is not set | 1397 | # CONFIG_NLS_KOI8_U is not set |
| 1353 | # CONFIG_NLS_UTF8 is not set | 1398 | CONFIG_NLS_UTF8=m |
| 1354 | # CONFIG_DLM is not set | 1399 | # CONFIG_DLM is not set |
| 1355 | 1400 | ||
| 1356 | # | 1401 | # |
| @@ -1365,7 +1410,7 @@ CONFIG_FRAME_WARN=1024 | |||
| 1365 | CONFIG_DEBUG_FS=y | 1410 | CONFIG_DEBUG_FS=y |
| 1366 | # CONFIG_HEADERS_CHECK is not set | 1411 | # CONFIG_HEADERS_CHECK is not set |
| 1367 | CONFIG_DEBUG_KERNEL=y | 1412 | CONFIG_DEBUG_KERNEL=y |
| 1368 | # CONFIG_DEBUG_SHIRQ is not set | 1413 | CONFIG_DEBUG_SHIRQ=y |
| 1369 | CONFIG_DETECT_SOFTLOCKUP=y | 1414 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1370 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | 1415 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set |
| 1371 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | 1416 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 |
| @@ -1374,8 +1419,6 @@ CONFIG_SCHED_DEBUG=y | |||
| 1374 | # CONFIG_TIMER_STATS is not set | 1419 | # CONFIG_TIMER_STATS is not set |
| 1375 | # CONFIG_DEBUG_OBJECTS is not set | 1420 | # CONFIG_DEBUG_OBJECTS is not set |
| 1376 | # CONFIG_DEBUG_SLAB is not set | 1421 | # CONFIG_DEBUG_SLAB is not set |
| 1377 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1378 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1379 | # CONFIG_DEBUG_SPINLOCK is not set | 1422 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1380 | # CONFIG_DEBUG_MUTEXES is not set | 1423 | # CONFIG_DEBUG_MUTEXES is not set |
| 1381 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1424 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| @@ -1395,7 +1438,6 @@ CONFIG_DEBUG_INFO=y | |||
| 1395 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1438 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1396 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 1439 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
| 1397 | # CONFIG_FAULT_INJECTION is not set | 1440 | # CONFIG_FAULT_INJECTION is not set |
| 1398 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 1399 | 1441 | ||
| 1400 | # | 1442 | # |
| 1401 | # Tracers | 1443 | # Tracers |
| @@ -1411,16 +1453,20 @@ CONFIG_HAVE_ARCH_KGDB=y | |||
| 1411 | # CONFIG_DEBUG_STACK_USAGE is not set | 1453 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1412 | CONFIG_DEBUG_VERBOSE=y | 1454 | CONFIG_DEBUG_VERBOSE=y |
| 1413 | CONFIG_DEBUG_MMRS=y | 1455 | CONFIG_DEBUG_MMRS=y |
| 1414 | # CONFIG_DEBUG_HWERR is not set | 1456 | CONFIG_DEBUG_HWERR=y |
| 1415 | # CONFIG_DEBUG_DOUBLEFAULT is not set | 1457 | CONFIG_EXACT_HWERR=y |
| 1458 | CONFIG_DEBUG_DOUBLEFAULT=y | ||
| 1459 | CONFIG_DEBUG_DOUBLEFAULT_PRINT=y | ||
| 1460 | # CONFIG_DEBUG_DOUBLEFAULT_RESET is not set | ||
| 1461 | # CONFIG_DEBUG_ICACHE_CHECK is not set | ||
| 1416 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1462 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1417 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1463 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1418 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1464 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set |
| 1419 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set | 1465 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y |
| 1420 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set | 1466 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set |
| 1421 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 | 1467 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1 |
| 1422 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set | 1468 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set |
| 1423 | # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set | 1469 | CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y |
| 1424 | CONFIG_EARLY_PRINTK=y | 1470 | CONFIG_EARLY_PRINTK=y |
| 1425 | CONFIG_CPLB_INFO=y | 1471 | CONFIG_CPLB_INFO=y |
| 1426 | CONFIG_ACCESS_CHECK=y | 1472 | CONFIG_ACCESS_CHECK=y |
| @@ -1534,7 +1580,6 @@ CONFIG_CRC32=y | |||
| 1534 | # CONFIG_LIBCRC32C is not set | 1580 | # CONFIG_LIBCRC32C is not set |
| 1535 | CONFIG_ZLIB_INFLATE=y | 1581 | CONFIG_ZLIB_INFLATE=y |
| 1536 | CONFIG_ZLIB_DEFLATE=m | 1582 | CONFIG_ZLIB_DEFLATE=m |
| 1537 | CONFIG_PLIST=y | ||
| 1538 | CONFIG_HAS_IOMEM=y | 1583 | CONFIG_HAS_IOMEM=y |
| 1539 | CONFIG_HAS_IOPORT=y | 1584 | CONFIG_HAS_IOPORT=y |
| 1540 | CONFIG_HAS_DMA=y | 1585 | CONFIG_HAS_DMA=y |
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig index 911b5dba1dbc..e9175c608aa7 100644 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT_defconfig | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28.7 | 3 | # Linux kernel version: 2.6.28.10 |
| 4 | # Thu May 21 05:50:01 2009 | ||
| 4 | # | 5 | # |
| 5 | # CONFIG_MMU is not set | 6 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 7 | # CONFIG_FPU is not set |
| @@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 42 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 43 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 44 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 45 | # CONFIG_SYSCTL is not set | 46 | CONFIG_SYSCTL=y |
| 47 | CONFIG_ANON_INODES=y | ||
| 46 | CONFIG_EMBEDDED=y | 48 | CONFIG_EMBEDDED=y |
| 47 | CONFIG_UID16=y | 49 | CONFIG_UID16=y |
| 48 | CONFIG_SYSCTL_SYSCALL=y | 50 | # CONFIG_SYSCTL_SYSCALL is not set |
| 49 | CONFIG_KALLSYMS=y | 51 | CONFIG_KALLSYMS=y |
| 50 | # CONFIG_KALLSYMS_ALL is not set | 52 | # CONFIG_KALLSYMS_ALL is not set |
| 51 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 53 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| @@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y | |||
| 53 | CONFIG_PRINTK=y | 55 | CONFIG_PRINTK=y |
| 54 | CONFIG_BUG=y | 56 | CONFIG_BUG=y |
| 55 | # CONFIG_ELF_CORE is not set | 57 | # CONFIG_ELF_CORE is not set |
| 56 | CONFIG_COMPAT_BRK=y | ||
| 57 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 58 | # CONFIG_FUTEX is not set | 59 | # CONFIG_FUTEX is not set |
| 59 | CONFIG_ANON_INODES=y | ||
| 60 | CONFIG_EPOLL=y | 60 | CONFIG_EPOLL=y |
| 61 | CONFIG_SIGNALFD=y | 61 | # CONFIG_SIGNALFD is not set |
| 62 | CONFIG_TIMERFD=y | 62 | # CONFIG_TIMERFD is not set |
| 63 | CONFIG_EVENTFD=y | 63 | # CONFIG_EVENTFD is not set |
| 64 | # CONFIG_AIO is not set | 64 | # CONFIG_AIO is not set |
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 65 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_COMPAT_BRK=y | ||
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| @@ -71,7 +72,6 @@ CONFIG_SLAB=y | |||
| 71 | CONFIG_HAVE_OPROFILE=y | 72 | CONFIG_HAVE_OPROFILE=y |
| 72 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 73 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 74 | CONFIG_RT_MUTEXES=y | ||
| 75 | CONFIG_TINY_SHMEM=y | 75 | CONFIG_TINY_SHMEM=y |
| 76 | CONFIG_BASE_SMALL=0 | 76 | CONFIG_BASE_SMALL=0 |
| 77 | CONFIG_MODULES=y | 77 | CONFIG_MODULES=y |
| @@ -145,8 +145,8 @@ CONFIG_BF527=y | |||
| 145 | CONFIG_BF_REV_MIN=0 | 145 | CONFIG_BF_REV_MIN=0 |
| 146 | CONFIG_BF_REV_MAX=2 | 146 | CONFIG_BF_REV_MAX=2 |
| 147 | # CONFIG_BF_REV_0_0 is not set | 147 | # CONFIG_BF_REV_0_0 is not set |
| 148 | CONFIG_BF_REV_0_1=y | 148 | # CONFIG_BF_REV_0_1 is not set |
| 149 | # CONFIG_BF_REV_0_2 is not set | 149 | CONFIG_BF_REV_0_2=y |
| 150 | # CONFIG_BF_REV_0_3 is not set | 150 | # CONFIG_BF_REV_0_3 is not set |
| 151 | # CONFIG_BF_REV_0_4 is not set | 151 | # CONFIG_BF_REV_0_4 is not set |
| 152 | # CONFIG_BF_REV_0_5 is not set | 152 | # CONFIG_BF_REV_0_5 is not set |
| @@ -264,7 +264,10 @@ CONFIG_HZ=250 | |||
| 264 | # CONFIG_SCHED_HRTICK is not set | 264 | # CONFIG_SCHED_HRTICK is not set |
| 265 | CONFIG_GENERIC_TIME=y | 265 | CONFIG_GENERIC_TIME=y |
| 266 | CONFIG_GENERIC_CLOCKEVENTS=y | 266 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 267 | # CONFIG_TICKSOURCE_GPTMR0 is not set | ||
| 268 | CONFIG_TICKSOURCE_CORETMR=y | ||
| 267 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 269 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 270 | # CONFIG_GPTMR0_CLOCKSOURCE is not set | ||
| 268 | # CONFIG_NO_HZ is not set | 271 | # CONFIG_NO_HZ is not set |
| 269 | # CONFIG_HIGH_RES_TIMERS is not set | 272 | # CONFIG_HIGH_RES_TIMERS is not set |
| 270 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 273 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| @@ -318,7 +321,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 | |||
| 318 | # CONFIG_PHYS_ADDR_T_64BIT is not set | 321 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 319 | CONFIG_ZONE_DMA_FLAG=1 | 322 | CONFIG_ZONE_DMA_FLAG=1 |
| 320 | CONFIG_VIRT_TO_BUS=y | 323 | CONFIG_VIRT_TO_BUS=y |
| 321 | CONFIG_BFIN_GPTIMERS=m | 324 | CONFIG_BFIN_GPTIMERS=y |
| 322 | # CONFIG_DMA_UNCACHED_4M is not set | 325 | # CONFIG_DMA_UNCACHED_4M is not set |
| 323 | # CONFIG_DMA_UNCACHED_2M is not set | 326 | # CONFIG_DMA_UNCACHED_2M is not set |
| 324 | CONFIG_DMA_UNCACHED_1M=y | 327 | CONFIG_DMA_UNCACHED_1M=y |
| @@ -409,7 +412,7 @@ CONFIG_IP_PNP=y | |||
| 409 | # CONFIG_NET_IPIP is not set | 412 | # CONFIG_NET_IPIP is not set |
| 410 | # CONFIG_NET_IPGRE is not set | 413 | # CONFIG_NET_IPGRE is not set |
| 411 | # CONFIG_ARPD is not set | 414 | # CONFIG_ARPD is not set |
| 412 | CONFIG_SYN_COOKIES=y | 415 | # CONFIG_SYN_COOKIES is not set |
| 413 | # CONFIG_INET_AH is not set | 416 | # CONFIG_INET_AH is not set |
| 414 | # CONFIG_INET_ESP is not set | 417 | # CONFIG_INET_ESP is not set |
| 415 | # CONFIG_INET_IPCOMP is not set | 418 | # CONFIG_INET_IPCOMP is not set |
| @@ -639,9 +642,42 @@ CONFIG_HAVE_IDE=y | |||
| 639 | # SCSI device support | 642 | # SCSI device support |
| 640 | # | 643 | # |
| 641 | # CONFIG_RAID_ATTRS is not set | 644 | # CONFIG_RAID_ATTRS is not set |
| 642 | # CONFIG_SCSI is not set | 645 | CONFIG_SCSI=y |
| 643 | # CONFIG_SCSI_DMA is not set | 646 | CONFIG_SCSI_DMA=y |
| 647 | # CONFIG_SCSI_TGT is not set | ||
| 644 | # CONFIG_SCSI_NETLINK is not set | 648 | # CONFIG_SCSI_NETLINK is not set |
| 649 | # CONFIG_SCSI_PROC_FS is not set | ||
| 650 | |||
| 651 | # | ||
| 652 | # SCSI support type (disk, tape, CD-ROM) | ||
| 653 | # | ||
| 654 | CONFIG_BLK_DEV_SD=y | ||
| 655 | # CONFIG_CHR_DEV_ST is not set | ||
| 656 | # CONFIG_CHR_DEV_OSST is not set | ||
| 657 | CONFIG_BLK_DEV_SR=m | ||
| 658 | # CONFIG_BLK_DEV_SR_VENDOR is not set | ||
| 659 | # CONFIG_CHR_DEV_SG is not set | ||
| 660 | # CONFIG_CHR_DEV_SCH is not set | ||
| 661 | |||
| 662 | # | ||
| 663 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 664 | # | ||
| 665 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 666 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 667 | # CONFIG_SCSI_LOGGING is not set | ||
| 668 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 669 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 670 | |||
| 671 | # | ||
| 672 | # SCSI Transports | ||
| 673 | # | ||
| 674 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 675 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 676 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 677 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 678 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 679 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 680 | # CONFIG_SCSI_DH is not set | ||
| 645 | # CONFIG_ATA is not set | 681 | # CONFIG_ATA is not set |
| 646 | # CONFIG_MD is not set | 682 | # CONFIG_MD is not set |
| 647 | CONFIG_NETDEVICES=y | 683 | CONFIG_NETDEVICES=y |
| @@ -687,9 +723,8 @@ CONFIG_BFIN_MAC_RMII=y | |||
| 687 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | 723 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set |
| 688 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | 724 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set |
| 689 | # CONFIG_B44 is not set | 725 | # CONFIG_B44 is not set |
| 690 | CONFIG_NETDEV_1000=y | 726 | # CONFIG_NETDEV_1000 is not set |
| 691 | # CONFIG_AX88180 is not set | 727 | # CONFIG_NETDEV_10000 is not set |
| 692 | CONFIG_NETDEV_10000=y | ||
| 693 | 728 | ||
| 694 | # | 729 | # |
| 695 | # Wireless LAN | 730 | # Wireless LAN |
| @@ -758,14 +793,14 @@ CONFIG_INPUT_MISC=y | |||
| 758 | # Character devices | 793 | # Character devices |
| 759 | # | 794 | # |
| 760 | # CONFIG_AD9960 is not set | 795 | # CONFIG_AD9960 is not set |
| 761 | # CONFIG_SPI_ADC_BF533 is not set | 796 | CONFIG_BFIN_DMA_INTERFACE=m |
| 762 | # CONFIG_BF5xx_PPIFCD is not set | 797 | # CONFIG_BFIN_PPI is not set |
| 798 | # CONFIG_BFIN_PPIFCD is not set | ||
| 763 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 799 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 764 | CONFIG_BF5xx_PPI=m | 800 | # CONFIG_BFIN_SPI_ADC is not set |
| 765 | CONFIG_BFIN_SPORT=m | 801 | CONFIG_BFIN_SPORT=m |
| 766 | # CONFIG_BFIN_TIMER_LATENCY is not set | 802 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 767 | # CONFIG_TWI_LCD is not set | 803 | # CONFIG_BFIN_TWI_LCD is not set |
| 768 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 769 | CONFIG_SIMPLE_GPIO=m | 804 | CONFIG_SIMPLE_GPIO=m |
| 770 | CONFIG_VT=y | 805 | CONFIG_VT=y |
| 771 | CONFIG_CONSOLE_TRANSLATIONS=y | 806 | CONFIG_CONSOLE_TRANSLATIONS=y |
| @@ -875,7 +910,30 @@ CONFIG_SPI_BFIN=y | |||
| 875 | # CONFIG_SPI_SPIDEV is not set | 910 | # CONFIG_SPI_SPIDEV is not set |
| 876 | # CONFIG_SPI_TLE62X0 is not set | 911 | # CONFIG_SPI_TLE62X0 is not set |
| 877 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | 912 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 878 | # CONFIG_GPIOLIB is not set | 913 | CONFIG_GPIOLIB=y |
| 914 | # CONFIG_DEBUG_GPIO is not set | ||
| 915 | CONFIG_GPIO_SYSFS=y | ||
| 916 | |||
| 917 | # | ||
| 918 | # Memory mapped GPIO expanders: | ||
| 919 | # | ||
| 920 | |||
| 921 | # | ||
| 922 | # I2C GPIO expanders: | ||
| 923 | # | ||
| 924 | # CONFIG_GPIO_MAX732X is not set | ||
| 925 | # CONFIG_GPIO_PCA953X is not set | ||
| 926 | # CONFIG_GPIO_PCF857X is not set | ||
| 927 | |||
| 928 | # | ||
| 929 | # PCI GPIO expanders: | ||
| 930 | # | ||
| 931 | |||
| 932 | # | ||
| 933 | # SPI GPIO expanders: | ||
| 934 | # | ||
| 935 | # CONFIG_GPIO_MAX7301 is not set | ||
| 936 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 879 | # CONFIG_W1 is not set | 937 | # CONFIG_W1 is not set |
| 880 | # CONFIG_POWER_SUPPLY is not set | 938 | # CONFIG_POWER_SUPPLY is not set |
| 881 | # CONFIG_HWMON is not set | 939 | # CONFIG_HWMON is not set |
| @@ -909,6 +967,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 909 | # CONFIG_HTC_PASIC3 is not set | 967 | # CONFIG_HTC_PASIC3 is not set |
| 910 | # CONFIG_MFD_TMIO is not set | 968 | # CONFIG_MFD_TMIO is not set |
| 911 | # CONFIG_PMIC_DA903X is not set | 969 | # CONFIG_PMIC_DA903X is not set |
| 970 | # CONFIG_PMIC_ADP5520 is not set | ||
| 912 | # CONFIG_MFD_WM8400 is not set | 971 | # CONFIG_MFD_WM8400 is not set |
| 913 | # CONFIG_MFD_WM8350_I2C is not set | 972 | # CONFIG_MFD_WM8350_I2C is not set |
| 914 | # CONFIG_REGULATOR is not set | 973 | # CONFIG_REGULATOR is not set |
| @@ -1091,8 +1150,8 @@ CONFIG_USB=y | |||
| 1091 | # | 1150 | # |
| 1092 | # Miscellaneous USB options | 1151 | # Miscellaneous USB options |
| 1093 | # | 1152 | # |
| 1094 | # CONFIG_USB_DEVICEFS is not set | 1153 | CONFIG_USB_DEVICEFS=y |
| 1095 | CONFIG_USB_DEVICE_CLASS=y | 1154 | # CONFIG_USB_DEVICE_CLASS is not set |
| 1096 | # CONFIG_USB_DYNAMIC_MINORS is not set | 1155 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 1097 | # CONFIG_USB_OTG is not set | 1156 | # CONFIG_USB_OTG is not set |
| 1098 | # CONFIG_USB_OTG_WHITELIST is not set | 1157 | # CONFIG_USB_OTG_WHITELIST is not set |
| @@ -1120,10 +1179,10 @@ CONFIG_USB_MUSB_SOC=y | |||
| 1120 | CONFIG_USB_MUSB_HOST=y | 1179 | CONFIG_USB_MUSB_HOST=y |
| 1121 | # CONFIG_USB_MUSB_PERIPHERAL is not set | 1180 | # CONFIG_USB_MUSB_PERIPHERAL is not set |
| 1122 | # CONFIG_USB_MUSB_OTG is not set | 1181 | # CONFIG_USB_MUSB_OTG is not set |
| 1123 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 1124 | CONFIG_USB_MUSB_HDRC_HCD=y | 1182 | CONFIG_USB_MUSB_HDRC_HCD=y |
| 1125 | CONFIG_MUSB_PIO_ONLY=y | 1183 | # CONFIG_MUSB_PIO_ONLY is not set |
| 1126 | CONFIG_MUSB_DMA_POLL=y | 1184 | CONFIG_USB_INVENTRA_DMA=y |
| 1185 | # CONFIG_USB_TI_CPPI_DMA is not set | ||
| 1127 | # CONFIG_USB_MUSB_DEBUG is not set | 1186 | # CONFIG_USB_MUSB_DEBUG is not set |
| 1128 | 1187 | ||
| 1129 | # | 1188 | # |
| @@ -1141,7 +1200,7 @@ CONFIG_MUSB_DMA_POLL=y | |||
| 1141 | # | 1200 | # |
| 1142 | # see USB_STORAGE Help for more information | 1201 | # see USB_STORAGE Help for more information |
| 1143 | # | 1202 | # |
| 1144 | CONFIG_USB_STORAGE=m | 1203 | CONFIG_USB_STORAGE=y |
| 1145 | # CONFIG_USB_STORAGE_DEBUG is not set | 1204 | # CONFIG_USB_STORAGE_DEBUG is not set |
| 1146 | # CONFIG_USB_STORAGE_DATAFAB is not set | 1205 | # CONFIG_USB_STORAGE_DATAFAB is not set |
| 1147 | # CONFIG_USB_STORAGE_FREECOM is not set | 1206 | # CONFIG_USB_STORAGE_FREECOM is not set |
| @@ -1190,33 +1249,10 @@ CONFIG_USB_STORAGE=m | |||
| 1190 | # CONFIG_USB_LD is not set | 1249 | # CONFIG_USB_LD is not set |
| 1191 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1250 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 1192 | # CONFIG_USB_IOWARRIOR is not set | 1251 | # CONFIG_USB_IOWARRIOR is not set |
| 1252 | # CONFIG_USB_TEST is not set | ||
| 1193 | # CONFIG_USB_ISIGHTFW is not set | 1253 | # CONFIG_USB_ISIGHTFW is not set |
| 1194 | # CONFIG_USB_VST is not set | 1254 | # CONFIG_USB_VST is not set |
| 1195 | # CONFIG_USB_GADGET is not set | 1255 | # CONFIG_USB_GADGET is not set |
| 1196 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 1197 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 1198 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 1199 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 1200 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 1201 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1202 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 1203 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 1204 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1205 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1206 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1207 | # CONFIG_USB_GADGET_NET2272 is not set | ||
| 1208 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1209 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1210 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 1211 | # CONFIG_USB_ZERO is not set | ||
| 1212 | # CONFIG_USB_AUDIO is not set | ||
| 1213 | # CONFIG_USB_ETH is not set | ||
| 1214 | # CONFIG_USB_GADGETFS is not set | ||
| 1215 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 1216 | # CONFIG_USB_G_SERIAL is not set | ||
| 1217 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 1218 | # CONFIG_USB_G_PRINTER is not set | ||
| 1219 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 1220 | # CONFIG_MMC is not set | 1256 | # CONFIG_MMC is not set |
| 1221 | # CONFIG_MEMSTICK is not set | 1257 | # CONFIG_MEMSTICK is not set |
| 1222 | # CONFIG_NEW_LEDS is not set | 1258 | # CONFIG_NEW_LEDS is not set |
| @@ -1289,7 +1325,8 @@ CONFIG_RTC_DRV_BFIN=y | |||
| 1289 | # | 1325 | # |
| 1290 | # File systems | 1326 | # File systems |
| 1291 | # | 1327 | # |
| 1292 | # CONFIG_EXT2_FS is not set | 1328 | CONFIG_EXT2_FS=m |
| 1329 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1293 | # CONFIG_EXT3_FS is not set | 1330 | # CONFIG_EXT3_FS is not set |
| 1294 | # CONFIG_EXT4_FS is not set | 1331 | # CONFIG_EXT4_FS is not set |
| 1295 | # CONFIG_REISERFS_FS is not set | 1332 | # CONFIG_REISERFS_FS is not set |
| @@ -1309,14 +1346,20 @@ CONFIG_INOTIFY_USER=y | |||
| 1309 | # | 1346 | # |
| 1310 | # CD-ROM/DVD Filesystems | 1347 | # CD-ROM/DVD Filesystems |
| 1311 | # | 1348 | # |
| 1312 | # CONFIG_ISO9660_FS is not set | 1349 | CONFIG_ISO9660_FS=m |
| 1313 | # CONFIG_UDF_FS is not set | 1350 | CONFIG_JOLIET=y |
| 1351 | # CONFIG_ZISOFS is not set | ||
| 1352 | CONFIG_UDF_FS=m | ||
| 1353 | CONFIG_UDF_NLS=y | ||
| 1314 | 1354 | ||
| 1315 | # | 1355 | # |
| 1316 | # DOS/FAT/NT Filesystems | 1356 | # DOS/FAT/NT Filesystems |
| 1317 | # | 1357 | # |
| 1358 | CONFIG_FAT_FS=m | ||
| 1318 | # CONFIG_MSDOS_FS is not set | 1359 | # CONFIG_MSDOS_FS is not set |
| 1319 | # CONFIG_VFAT_FS is not set | 1360 | CONFIG_VFAT_FS=m |
| 1361 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1362 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1320 | # CONFIG_NTFS_FS is not set | 1363 | # CONFIG_NTFS_FS is not set |
| 1321 | 1364 | ||
| 1322 | # | 1365 | # |
| @@ -1339,16 +1382,6 @@ CONFIG_SYSFS=y | |||
| 1339 | # CONFIG_BEFS_FS is not set | 1382 | # CONFIG_BEFS_FS is not set |
| 1340 | # CONFIG_BFS_FS is not set | 1383 | # CONFIG_BFS_FS is not set |
| 1341 | # CONFIG_EFS_FS is not set | 1384 | # CONFIG_EFS_FS is not set |
| 1342 | CONFIG_YAFFS_FS=m | ||
| 1343 | CONFIG_YAFFS_YAFFS1=y | ||
| 1344 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1345 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1346 | CONFIG_YAFFS_YAFFS2=y | ||
| 1347 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1348 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1349 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1350 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1351 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1352 | CONFIG_JFFS2_FS=m | 1385 | CONFIG_JFFS2_FS=m |
| 1353 | CONFIG_JFFS2_FS_DEBUG=0 | 1386 | CONFIG_JFFS2_FS_DEBUG=0 |
| 1354 | CONFIG_JFFS2_FS_WRITEBUFFER=y | 1387 | CONFIG_JFFS2_FS_WRITEBUFFER=y |
| @@ -1360,6 +1393,16 @@ CONFIG_JFFS2_ZLIB=y | |||
| 1360 | # CONFIG_JFFS2_LZO is not set | 1393 | # CONFIG_JFFS2_LZO is not set |
| 1361 | CONFIG_JFFS2_RTIME=y | 1394 | CONFIG_JFFS2_RTIME=y |
| 1362 | # CONFIG_JFFS2_RUBIN is not set | 1395 | # CONFIG_JFFS2_RUBIN is not set |
| 1396 | CONFIG_YAFFS_FS=m | ||
| 1397 | CONFIG_YAFFS_YAFFS1=y | ||
| 1398 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1399 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1400 | CONFIG_YAFFS_YAFFS2=y | ||
| 1401 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1402 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1403 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1404 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1405 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1363 | # CONFIG_CRAMFS is not set | 1406 | # CONFIG_CRAMFS is not set |
| 1364 | # CONFIG_VXFS_FS is not set | 1407 | # CONFIG_VXFS_FS is not set |
| 1365 | # CONFIG_MINIX_FS is not set | 1408 | # CONFIG_MINIX_FS is not set |
| @@ -1396,7 +1439,7 @@ CONFIG_SMB_FS=m | |||
| 1396 | CONFIG_MSDOS_PARTITION=y | 1439 | CONFIG_MSDOS_PARTITION=y |
| 1397 | CONFIG_NLS=m | 1440 | CONFIG_NLS=m |
| 1398 | CONFIG_NLS_DEFAULT="iso8859-1" | 1441 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 1399 | # CONFIG_NLS_CODEPAGE_437 is not set | 1442 | CONFIG_NLS_CODEPAGE_437=m |
| 1400 | # CONFIG_NLS_CODEPAGE_737 is not set | 1443 | # CONFIG_NLS_CODEPAGE_737 is not set |
| 1401 | # CONFIG_NLS_CODEPAGE_775 is not set | 1444 | # CONFIG_NLS_CODEPAGE_775 is not set |
| 1402 | # CONFIG_NLS_CODEPAGE_850 is not set | 1445 | # CONFIG_NLS_CODEPAGE_850 is not set |
| @@ -1411,7 +1454,7 @@ CONFIG_NLS_DEFAULT="iso8859-1" | |||
| 1411 | # CONFIG_NLS_CODEPAGE_865 is not set | 1454 | # CONFIG_NLS_CODEPAGE_865 is not set |
| 1412 | # CONFIG_NLS_CODEPAGE_866 is not set | 1455 | # CONFIG_NLS_CODEPAGE_866 is not set |
| 1413 | # CONFIG_NLS_CODEPAGE_869 is not set | 1456 | # CONFIG_NLS_CODEPAGE_869 is not set |
| 1414 | # CONFIG_NLS_CODEPAGE_936 is not set | 1457 | CONFIG_NLS_CODEPAGE_936=m |
| 1415 | # CONFIG_NLS_CODEPAGE_950 is not set | 1458 | # CONFIG_NLS_CODEPAGE_950 is not set |
| 1416 | # CONFIG_NLS_CODEPAGE_932 is not set | 1459 | # CONFIG_NLS_CODEPAGE_932 is not set |
| 1417 | # CONFIG_NLS_CODEPAGE_949 is not set | 1460 | # CONFIG_NLS_CODEPAGE_949 is not set |
| @@ -1420,7 +1463,7 @@ CONFIG_NLS_DEFAULT="iso8859-1" | |||
| 1420 | # CONFIG_NLS_CODEPAGE_1250 is not set | 1463 | # CONFIG_NLS_CODEPAGE_1250 is not set |
| 1421 | # CONFIG_NLS_CODEPAGE_1251 is not set | 1464 | # CONFIG_NLS_CODEPAGE_1251 is not set |
| 1422 | # CONFIG_NLS_ASCII is not set | 1465 | # CONFIG_NLS_ASCII is not set |
| 1423 | # CONFIG_NLS_ISO8859_1 is not set | 1466 | CONFIG_NLS_ISO8859_1=m |
| 1424 | # CONFIG_NLS_ISO8859_2 is not set | 1467 | # CONFIG_NLS_ISO8859_2 is not set |
| 1425 | # CONFIG_NLS_ISO8859_3 is not set | 1468 | # CONFIG_NLS_ISO8859_3 is not set |
| 1426 | # CONFIG_NLS_ISO8859_4 is not set | 1469 | # CONFIG_NLS_ISO8859_4 is not set |
| @@ -1433,7 +1476,7 @@ CONFIG_NLS_DEFAULT="iso8859-1" | |||
| 1433 | # CONFIG_NLS_ISO8859_15 is not set | 1476 | # CONFIG_NLS_ISO8859_15 is not set |
| 1434 | # CONFIG_NLS_KOI8_R is not set | 1477 | # CONFIG_NLS_KOI8_R is not set |
| 1435 | # CONFIG_NLS_KOI8_U is not set | 1478 | # CONFIG_NLS_KOI8_U is not set |
| 1436 | # CONFIG_NLS_UTF8 is not set | 1479 | CONFIG_NLS_UTF8=m |
| 1437 | # CONFIG_DLM is not set | 1480 | # CONFIG_DLM is not set |
| 1438 | 1481 | ||
| 1439 | # | 1482 | # |
| @@ -1448,7 +1491,7 @@ CONFIG_FRAME_WARN=1024 | |||
| 1448 | CONFIG_DEBUG_FS=y | 1491 | CONFIG_DEBUG_FS=y |
| 1449 | # CONFIG_HEADERS_CHECK is not set | 1492 | # CONFIG_HEADERS_CHECK is not set |
| 1450 | CONFIG_DEBUG_KERNEL=y | 1493 | CONFIG_DEBUG_KERNEL=y |
| 1451 | # CONFIG_DEBUG_SHIRQ is not set | 1494 | CONFIG_DEBUG_SHIRQ=y |
| 1452 | CONFIG_DETECT_SOFTLOCKUP=y | 1495 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1453 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | 1496 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set |
| 1454 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | 1497 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 |
| @@ -1457,8 +1500,6 @@ CONFIG_SCHED_DEBUG=y | |||
| 1457 | # CONFIG_TIMER_STATS is not set | 1500 | # CONFIG_TIMER_STATS is not set |
| 1458 | # CONFIG_DEBUG_OBJECTS is not set | 1501 | # CONFIG_DEBUG_OBJECTS is not set |
| 1459 | # CONFIG_DEBUG_SLAB is not set | 1502 | # CONFIG_DEBUG_SLAB is not set |
| 1460 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1461 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1462 | # CONFIG_DEBUG_SPINLOCK is not set | 1503 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1463 | # CONFIG_DEBUG_MUTEXES is not set | 1504 | # CONFIG_DEBUG_MUTEXES is not set |
| 1464 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1505 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| @@ -1478,7 +1519,6 @@ CONFIG_DEBUG_INFO=y | |||
| 1478 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1519 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1479 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 1520 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
| 1480 | # CONFIG_FAULT_INJECTION is not set | 1521 | # CONFIG_FAULT_INJECTION is not set |
| 1481 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1482 | 1522 | ||
| 1483 | # | 1523 | # |
| 1484 | # Tracers | 1524 | # Tracers |
| @@ -1494,16 +1534,20 @@ CONFIG_HAVE_ARCH_KGDB=y | |||
| 1494 | # CONFIG_DEBUG_STACK_USAGE is not set | 1534 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1495 | CONFIG_DEBUG_VERBOSE=y | 1535 | CONFIG_DEBUG_VERBOSE=y |
| 1496 | CONFIG_DEBUG_MMRS=y | 1536 | CONFIG_DEBUG_MMRS=y |
| 1497 | # CONFIG_DEBUG_HWERR is not set | 1537 | CONFIG_DEBUG_HWERR=y |
| 1498 | # CONFIG_DEBUG_DOUBLEFAULT is not set | 1538 | CONFIG_EXACT_HWERR=y |
| 1539 | CONFIG_DEBUG_DOUBLEFAULT=y | ||
| 1540 | CONFIG_DEBUG_DOUBLEFAULT_PRINT=y | ||
| 1541 | # CONFIG_DEBUG_DOUBLEFAULT_RESET is not set | ||
| 1542 | # CONFIG_DEBUG_ICACHE_CHECK is not set | ||
| 1499 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1543 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1500 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1544 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1501 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1545 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set |
| 1502 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set | 1546 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y |
| 1503 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set | 1547 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set |
| 1504 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 | 1548 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1 |
| 1505 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set | 1549 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set |
| 1506 | # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set | 1550 | CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y |
| 1507 | CONFIG_EARLY_PRINTK=y | 1551 | CONFIG_EARLY_PRINTK=y |
| 1508 | CONFIG_CPLB_INFO=y | 1552 | CONFIG_CPLB_INFO=y |
| 1509 | CONFIG_ACCESS_CHECK=y | 1553 | CONFIG_ACCESS_CHECK=y |
| @@ -1611,13 +1655,12 @@ CONFIG_BITREVERSE=y | |||
| 1611 | CONFIG_CRC_CCITT=m | 1655 | CONFIG_CRC_CCITT=m |
| 1612 | # CONFIG_CRC16 is not set | 1656 | # CONFIG_CRC16 is not set |
| 1613 | # CONFIG_CRC_T10DIF is not set | 1657 | # CONFIG_CRC_T10DIF is not set |
| 1614 | # CONFIG_CRC_ITU_T is not set | 1658 | CONFIG_CRC_ITU_T=m |
| 1615 | CONFIG_CRC32=y | 1659 | CONFIG_CRC32=y |
| 1616 | # CONFIG_CRC7 is not set | 1660 | # CONFIG_CRC7 is not set |
| 1617 | # CONFIG_LIBCRC32C is not set | 1661 | # CONFIG_LIBCRC32C is not set |
| 1618 | CONFIG_ZLIB_INFLATE=y | 1662 | CONFIG_ZLIB_INFLATE=y |
| 1619 | CONFIG_ZLIB_DEFLATE=m | 1663 | CONFIG_ZLIB_DEFLATE=m |
| 1620 | CONFIG_PLIST=y | ||
| 1621 | CONFIG_HAS_IOMEM=y | 1664 | CONFIG_HAS_IOMEM=y |
| 1622 | CONFIG_HAS_IOPORT=y | 1665 | CONFIG_HAS_IOPORT=y |
| 1623 | CONFIG_HAS_DMA=y | 1666 | CONFIG_HAS_DMA=y |
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig index 4c41e03efe0f..5aa63bafdd62 100644 --- a/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/arch/blackfin/configs/BF533-EZKIT_defconfig | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28.7 | 3 | # Linux kernel version: 2.6.28.10 |
| 4 | # Thu May 21 05:50:01 2009 | ||
| 4 | # | 5 | # |
| 5 | # CONFIG_MMU is not set | 6 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 7 | # CONFIG_FPU is not set |
| @@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 42 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 43 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 44 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 45 | # CONFIG_SYSCTL is not set | 46 | CONFIG_SYSCTL=y |
| 47 | CONFIG_ANON_INODES=y | ||
| 46 | CONFIG_EMBEDDED=y | 48 | CONFIG_EMBEDDED=y |
| 47 | CONFIG_UID16=y | 49 | CONFIG_UID16=y |
| 48 | CONFIG_SYSCTL_SYSCALL=y | 50 | # CONFIG_SYSCTL_SYSCALL is not set |
| 49 | CONFIG_KALLSYMS=y | 51 | CONFIG_KALLSYMS=y |
| 50 | # CONFIG_KALLSYMS_ALL is not set | 52 | # CONFIG_KALLSYMS_ALL is not set |
| 51 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 53 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| @@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y | |||
| 53 | CONFIG_PRINTK=y | 55 | CONFIG_PRINTK=y |
| 54 | CONFIG_BUG=y | 56 | CONFIG_BUG=y |
| 55 | # CONFIG_ELF_CORE is not set | 57 | # CONFIG_ELF_CORE is not set |
| 56 | CONFIG_COMPAT_BRK=y | ||
| 57 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 58 | # CONFIG_FUTEX is not set | 59 | # CONFIG_FUTEX is not set |
| 59 | CONFIG_ANON_INODES=y | ||
| 60 | CONFIG_EPOLL=y | 60 | CONFIG_EPOLL=y |
| 61 | CONFIG_SIGNALFD=y | 61 | # CONFIG_SIGNALFD is not set |
| 62 | CONFIG_TIMERFD=y | 62 | # CONFIG_TIMERFD is not set |
| 63 | CONFIG_EVENTFD=y | 63 | # CONFIG_EVENTFD is not set |
| 64 | # CONFIG_AIO is not set | 64 | # CONFIG_AIO is not set |
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 65 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_COMPAT_BRK=y | ||
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| @@ -71,7 +72,6 @@ CONFIG_SLAB=y | |||
| 71 | CONFIG_HAVE_OPROFILE=y | 72 | CONFIG_HAVE_OPROFILE=y |
| 72 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 73 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 74 | CONFIG_RT_MUTEXES=y | ||
| 75 | CONFIG_TINY_SHMEM=y | 75 | CONFIG_TINY_SHMEM=y |
| 76 | CONFIG_BASE_SMALL=0 | 76 | CONFIG_BASE_SMALL=0 |
| 77 | CONFIG_MODULES=y | 77 | CONFIG_MODULES=y |
| @@ -225,7 +225,10 @@ CONFIG_HZ=250 | |||
| 225 | CONFIG_SCHED_HRTICK=y | 225 | CONFIG_SCHED_HRTICK=y |
| 226 | CONFIG_GENERIC_TIME=y | 226 | CONFIG_GENERIC_TIME=y |
| 227 | CONFIG_GENERIC_CLOCKEVENTS=y | 227 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 228 | # CONFIG_TICKSOURCE_GPTMR0 is not set | ||
| 229 | CONFIG_TICKSOURCE_CORETMR=y | ||
| 228 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 230 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 231 | # CONFIG_GPTMR0_CLOCKSOURCE is not set | ||
| 229 | CONFIG_TICK_ONESHOT=y | 232 | CONFIG_TICK_ONESHOT=y |
| 230 | # CONFIG_NO_HZ is not set | 233 | # CONFIG_NO_HZ is not set |
| 231 | CONFIG_HIGH_RES_TIMERS=y | 234 | CONFIG_HIGH_RES_TIMERS=y |
| @@ -382,7 +385,7 @@ CONFIG_IP_PNP=y | |||
| 382 | # CONFIG_NET_IPIP is not set | 385 | # CONFIG_NET_IPIP is not set |
| 383 | # CONFIG_NET_IPGRE is not set | 386 | # CONFIG_NET_IPGRE is not set |
| 384 | # CONFIG_ARPD is not set | 387 | # CONFIG_ARPD is not set |
| 385 | CONFIG_SYN_COOKIES=y | 388 | # CONFIG_SYN_COOKIES is not set |
| 386 | # CONFIG_INET_AH is not set | 389 | # CONFIG_INET_AH is not set |
| 387 | # CONFIG_INET_ESP is not set | 390 | # CONFIG_INET_ESP is not set |
| 388 | # CONFIG_INET_IPCOMP is not set | 391 | # CONFIG_INET_IPCOMP is not set |
| @@ -613,9 +616,8 @@ CONFIG_SMC91X=y | |||
| 613 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | 616 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set |
| 614 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | 617 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set |
| 615 | # CONFIG_B44 is not set | 618 | # CONFIG_B44 is not set |
| 616 | CONFIG_NETDEV_1000=y | 619 | # CONFIG_NETDEV_1000 is not set |
| 617 | # CONFIG_AX88180 is not set | 620 | # CONFIG_NETDEV_10000 is not set |
| 618 | CONFIG_NETDEV_10000=y | ||
| 619 | 621 | ||
| 620 | # | 622 | # |
| 621 | # Wireless LAN | 623 | # Wireless LAN |
| @@ -667,13 +669,13 @@ CONFIG_INPUT_EVDEV=m | |||
| 667 | # Character devices | 669 | # Character devices |
| 668 | # | 670 | # |
| 669 | # CONFIG_AD9960 is not set | 671 | # CONFIG_AD9960 is not set |
| 670 | # CONFIG_SPI_ADC_BF533 is not set | 672 | CONFIG_BFIN_DMA_INTERFACE=m |
| 671 | # CONFIG_BF5xx_PPIFCD is not set | 673 | # CONFIG_BFIN_PPI is not set |
| 674 | # CONFIG_BFIN_PPIFCD is not set | ||
| 672 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 675 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 673 | # CONFIG_BF5xx_PPI is not set | 676 | # CONFIG_BFIN_SPI_ADC is not set |
| 674 | CONFIG_BFIN_SPORT=y | 677 | CONFIG_BFIN_SPORT=y |
| 675 | # CONFIG_BFIN_TIMER_LATENCY is not set | 678 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 676 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 677 | CONFIG_SIMPLE_GPIO=m | 679 | CONFIG_SIMPLE_GPIO=m |
| 678 | # CONFIG_VT is not set | 680 | # CONFIG_VT is not set |
| 679 | # CONFIG_DEVKMEM is not set | 681 | # CONFIG_DEVKMEM is not set |
| @@ -729,7 +731,30 @@ CONFIG_SPI_BFIN=y | |||
| 729 | # CONFIG_SPI_SPIDEV is not set | 731 | # CONFIG_SPI_SPIDEV is not set |
| 730 | # CONFIG_SPI_TLE62X0 is not set | 732 | # CONFIG_SPI_TLE62X0 is not set |
| 731 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | 733 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 732 | # CONFIG_GPIOLIB is not set | 734 | CONFIG_GPIOLIB=y |
| 735 | # CONFIG_DEBUG_GPIO is not set | ||
| 736 | CONFIG_GPIO_SYSFS=y | ||
| 737 | |||
| 738 | # | ||
| 739 | # Memory mapped GPIO expanders: | ||
| 740 | # | ||
| 741 | |||
| 742 | # | ||
| 743 | # I2C GPIO expanders: | ||
| 744 | # | ||
| 745 | # CONFIG_GPIO_MAX732X is not set | ||
| 746 | # CONFIG_GPIO_PCA953X is not set | ||
| 747 | # CONFIG_GPIO_PCF857X is not set | ||
| 748 | |||
| 749 | # | ||
| 750 | # PCI GPIO expanders: | ||
| 751 | # | ||
| 752 | |||
| 753 | # | ||
| 754 | # SPI GPIO expanders: | ||
| 755 | # | ||
| 756 | # CONFIG_GPIO_MAX7301 is not set | ||
| 757 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 733 | # CONFIG_W1 is not set | 758 | # CONFIG_W1 is not set |
| 734 | # CONFIG_POWER_SUPPLY is not set | 759 | # CONFIG_POWER_SUPPLY is not set |
| 735 | # CONFIG_HWMON is not set | 760 | # CONFIG_HWMON is not set |
| @@ -904,16 +929,6 @@ CONFIG_SYSFS=y | |||
| 904 | # CONFIG_BEFS_FS is not set | 929 | # CONFIG_BEFS_FS is not set |
| 905 | # CONFIG_BFS_FS is not set | 930 | # CONFIG_BFS_FS is not set |
| 906 | # CONFIG_EFS_FS is not set | 931 | # CONFIG_EFS_FS is not set |
| 907 | CONFIG_YAFFS_FS=m | ||
| 908 | CONFIG_YAFFS_YAFFS1=y | ||
| 909 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 910 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 911 | CONFIG_YAFFS_YAFFS2=y | ||
| 912 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 913 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 914 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 915 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 916 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 917 | CONFIG_JFFS2_FS=m | 932 | CONFIG_JFFS2_FS=m |
| 918 | CONFIG_JFFS2_FS_DEBUG=0 | 933 | CONFIG_JFFS2_FS_DEBUG=0 |
| 919 | CONFIG_JFFS2_FS_WRITEBUFFER=y | 934 | CONFIG_JFFS2_FS_WRITEBUFFER=y |
| @@ -925,6 +940,16 @@ CONFIG_JFFS2_ZLIB=y | |||
| 925 | # CONFIG_JFFS2_LZO is not set | 940 | # CONFIG_JFFS2_LZO is not set |
| 926 | CONFIG_JFFS2_RTIME=y | 941 | CONFIG_JFFS2_RTIME=y |
| 927 | # CONFIG_JFFS2_RUBIN is not set | 942 | # CONFIG_JFFS2_RUBIN is not set |
| 943 | CONFIG_YAFFS_FS=m | ||
| 944 | CONFIG_YAFFS_YAFFS1=y | ||
| 945 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 946 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 947 | CONFIG_YAFFS_YAFFS2=y | ||
| 948 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 949 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 950 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 951 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 952 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 928 | # CONFIG_CRAMFS is not set | 953 | # CONFIG_CRAMFS is not set |
| 929 | # CONFIG_VXFS_FS is not set | 954 | # CONFIG_VXFS_FS is not set |
| 930 | # CONFIG_MINIX_FS is not set | 955 | # CONFIG_MINIX_FS is not set |
| @@ -1013,7 +1038,7 @@ CONFIG_FRAME_WARN=1024 | |||
| 1013 | CONFIG_DEBUG_FS=y | 1038 | CONFIG_DEBUG_FS=y |
| 1014 | # CONFIG_HEADERS_CHECK is not set | 1039 | # CONFIG_HEADERS_CHECK is not set |
| 1015 | CONFIG_DEBUG_KERNEL=y | 1040 | CONFIG_DEBUG_KERNEL=y |
| 1016 | # CONFIG_DEBUG_SHIRQ is not set | 1041 | CONFIG_DEBUG_SHIRQ=y |
| 1017 | CONFIG_DETECT_SOFTLOCKUP=y | 1042 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1018 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | 1043 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set |
| 1019 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | 1044 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 |
| @@ -1022,8 +1047,6 @@ CONFIG_SCHED_DEBUG=y | |||
| 1022 | # CONFIG_TIMER_STATS is not set | 1047 | # CONFIG_TIMER_STATS is not set |
| 1023 | # CONFIG_DEBUG_OBJECTS is not set | 1048 | # CONFIG_DEBUG_OBJECTS is not set |
| 1024 | # CONFIG_DEBUG_SLAB is not set | 1049 | # CONFIG_DEBUG_SLAB is not set |
| 1025 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1026 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1027 | # CONFIG_DEBUG_SPINLOCK is not set | 1050 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1028 | # CONFIG_DEBUG_MUTEXES is not set | 1051 | # CONFIG_DEBUG_MUTEXES is not set |
| 1029 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1052 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| @@ -1043,7 +1066,6 @@ CONFIG_DEBUG_INFO=y | |||
| 1043 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1066 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1044 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 1067 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
| 1045 | # CONFIG_FAULT_INJECTION is not set | 1068 | # CONFIG_FAULT_INJECTION is not set |
| 1046 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1047 | 1069 | ||
| 1048 | # | 1070 | # |
| 1049 | # Tracers | 1071 | # Tracers |
| @@ -1059,16 +1081,20 @@ CONFIG_HAVE_ARCH_KGDB=y | |||
| 1059 | # CONFIG_DEBUG_STACK_USAGE is not set | 1081 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1060 | CONFIG_DEBUG_VERBOSE=y | 1082 | CONFIG_DEBUG_VERBOSE=y |
| 1061 | CONFIG_DEBUG_MMRS=y | 1083 | CONFIG_DEBUG_MMRS=y |
| 1062 | # CONFIG_DEBUG_HWERR is not set | 1084 | CONFIG_DEBUG_HWERR=y |
| 1063 | # CONFIG_DEBUG_DOUBLEFAULT is not set | 1085 | CONFIG_EXACT_HWERR=y |
| 1086 | CONFIG_DEBUG_DOUBLEFAULT=y | ||
| 1087 | CONFIG_DEBUG_DOUBLEFAULT_PRINT=y | ||
| 1088 | # CONFIG_DEBUG_DOUBLEFAULT_RESET is not set | ||
| 1089 | # CONFIG_DEBUG_ICACHE_CHECK is not set | ||
| 1064 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1090 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1065 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1091 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1066 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1092 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set |
| 1067 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set | 1093 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y |
| 1068 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set | 1094 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set |
| 1069 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 | 1095 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1 |
| 1070 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set | 1096 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set |
| 1071 | # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set | 1097 | CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y |
| 1072 | CONFIG_EARLY_PRINTK=y | 1098 | CONFIG_EARLY_PRINTK=y |
| 1073 | CONFIG_CPLB_INFO=y | 1099 | CONFIG_CPLB_INFO=y |
| 1074 | CONFIG_ACCESS_CHECK=y | 1100 | CONFIG_ACCESS_CHECK=y |
| @@ -1181,7 +1207,6 @@ CONFIG_CRC32=y | |||
| 1181 | # CONFIG_LIBCRC32C is not set | 1207 | # CONFIG_LIBCRC32C is not set |
| 1182 | CONFIG_ZLIB_INFLATE=y | 1208 | CONFIG_ZLIB_INFLATE=y |
| 1183 | CONFIG_ZLIB_DEFLATE=m | 1209 | CONFIG_ZLIB_DEFLATE=m |
| 1184 | CONFIG_PLIST=y | ||
| 1185 | CONFIG_HAS_IOMEM=y | 1210 | CONFIG_HAS_IOMEM=y |
| 1186 | CONFIG_HAS_IOPORT=y | 1211 | CONFIG_HAS_IOPORT=y |
| 1187 | CONFIG_HAS_DMA=y | 1212 | CONFIG_HAS_DMA=y |
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig index 9c482cd1b343..fed25329e13c 100644 --- a/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/arch/blackfin/configs/BF533-STAMP_defconfig | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28.7 | 3 | # Linux kernel version: 2.6.28.10 |
| 4 | # Thu May 21 05:50:01 2009 | ||
| 4 | # | 5 | # |
| 5 | # CONFIG_MMU is not set | 6 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 7 | # CONFIG_FPU is not set |
| @@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 42 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 43 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 44 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 45 | # CONFIG_SYSCTL is not set | 46 | CONFIG_SYSCTL=y |
| 47 | CONFIG_ANON_INODES=y | ||
| 46 | CONFIG_EMBEDDED=y | 48 | CONFIG_EMBEDDED=y |
| 47 | CONFIG_UID16=y | 49 | CONFIG_UID16=y |
| 48 | CONFIG_SYSCTL_SYSCALL=y | 50 | # CONFIG_SYSCTL_SYSCALL is not set |
| 49 | CONFIG_KALLSYMS=y | 51 | CONFIG_KALLSYMS=y |
| 50 | # CONFIG_KALLSYMS_ALL is not set | 52 | # CONFIG_KALLSYMS_ALL is not set |
| 51 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 53 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| @@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y | |||
| 53 | CONFIG_PRINTK=y | 55 | CONFIG_PRINTK=y |
| 54 | CONFIG_BUG=y | 56 | CONFIG_BUG=y |
| 55 | # CONFIG_ELF_CORE is not set | 57 | # CONFIG_ELF_CORE is not set |
| 56 | CONFIG_COMPAT_BRK=y | ||
| 57 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 58 | # CONFIG_FUTEX is not set | 59 | # CONFIG_FUTEX is not set |
| 59 | CONFIG_ANON_INODES=y | ||
| 60 | CONFIG_EPOLL=y | 60 | CONFIG_EPOLL=y |
| 61 | CONFIG_SIGNALFD=y | 61 | # CONFIG_SIGNALFD is not set |
| 62 | CONFIG_TIMERFD=y | 62 | # CONFIG_TIMERFD is not set |
| 63 | CONFIG_EVENTFD=y | 63 | # CONFIG_EVENTFD is not set |
| 64 | # CONFIG_AIO is not set | 64 | # CONFIG_AIO is not set |
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 65 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_COMPAT_BRK=y | ||
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| @@ -71,7 +72,6 @@ CONFIG_SLAB=y | |||
| 71 | CONFIG_HAVE_OPROFILE=y | 72 | CONFIG_HAVE_OPROFILE=y |
| 72 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 73 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 74 | CONFIG_RT_MUTEXES=y | ||
| 75 | CONFIG_TINY_SHMEM=y | 75 | CONFIG_TINY_SHMEM=y |
| 76 | CONFIG_BASE_SMALL=0 | 76 | CONFIG_BASE_SMALL=0 |
| 77 | CONFIG_MODULES=y | 77 | CONFIG_MODULES=y |
| @@ -225,7 +225,10 @@ CONFIG_HZ=250 | |||
| 225 | CONFIG_SCHED_HRTICK=y | 225 | CONFIG_SCHED_HRTICK=y |
| 226 | CONFIG_GENERIC_TIME=y | 226 | CONFIG_GENERIC_TIME=y |
| 227 | CONFIG_GENERIC_CLOCKEVENTS=y | 227 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 228 | # CONFIG_TICKSOURCE_GPTMR0 is not set | ||
| 229 | CONFIG_TICKSOURCE_CORETMR=y | ||
| 228 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 230 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 231 | # CONFIG_GPTMR0_CLOCKSOURCE is not set | ||
| 229 | CONFIG_TICK_ONESHOT=y | 232 | CONFIG_TICK_ONESHOT=y |
| 230 | # CONFIG_NO_HZ is not set | 233 | # CONFIG_NO_HZ is not set |
| 231 | CONFIG_HIGH_RES_TIMERS=y | 234 | CONFIG_HIGH_RES_TIMERS=y |
| @@ -382,7 +385,7 @@ CONFIG_IP_PNP=y | |||
| 382 | # CONFIG_NET_IPIP is not set | 385 | # CONFIG_NET_IPIP is not set |
| 383 | # CONFIG_NET_IPGRE is not set | 386 | # CONFIG_NET_IPGRE is not set |
| 384 | # CONFIG_ARPD is not set | 387 | # CONFIG_ARPD is not set |
| 385 | CONFIG_SYN_COOKIES=y | 388 | # CONFIG_SYN_COOKIES is not set |
| 386 | # CONFIG_INET_AH is not set | 389 | # CONFIG_INET_AH is not set |
| 387 | # CONFIG_INET_ESP is not set | 390 | # CONFIG_INET_ESP is not set |
| 388 | # CONFIG_INET_IPCOMP is not set | 391 | # CONFIG_INET_IPCOMP is not set |
| @@ -618,9 +621,8 @@ CONFIG_SMC91X=y | |||
| 618 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | 621 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set |
| 619 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | 622 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set |
| 620 | # CONFIG_B44 is not set | 623 | # CONFIG_B44 is not set |
| 621 | CONFIG_NETDEV_1000=y | 624 | # CONFIG_NETDEV_1000 is not set |
| 622 | # CONFIG_AX88180 is not set | 625 | # CONFIG_NETDEV_10000 is not set |
| 623 | CONFIG_NETDEV_10000=y | ||
| 624 | 626 | ||
| 625 | # | 627 | # |
| 626 | # Wireless LAN | 628 | # Wireless LAN |
| @@ -674,14 +676,14 @@ CONFIG_CONFIG_INPUT_PCF8574=m | |||
| 674 | # Character devices | 676 | # Character devices |
| 675 | # | 677 | # |
| 676 | # CONFIG_AD9960 is not set | 678 | # CONFIG_AD9960 is not set |
| 677 | # CONFIG_SPI_ADC_BF533 is not set | 679 | CONFIG_BFIN_DMA_INTERFACE=m |
| 678 | # CONFIG_BF5xx_PPIFCD is not set | 680 | # CONFIG_BFIN_PPI is not set |
| 681 | # CONFIG_BFIN_PPIFCD is not set | ||
| 679 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 682 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 680 | CONFIG_BF5xx_PPI=m | 683 | # CONFIG_BFIN_SPI_ADC is not set |
| 681 | CONFIG_BFIN_SPORT=m | 684 | CONFIG_BFIN_SPORT=m |
| 682 | # CONFIG_BFIN_TIMER_LATENCY is not set | 685 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 683 | # CONFIG_TWI_LCD is not set | 686 | # CONFIG_BFIN_TWI_LCD is not set |
| 684 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 685 | CONFIG_SIMPLE_GPIO=m | 687 | CONFIG_SIMPLE_GPIO=m |
| 686 | # CONFIG_VT is not set | 688 | # CONFIG_VT is not set |
| 687 | # CONFIG_DEVKMEM is not set | 689 | # CONFIG_DEVKMEM is not set |
| @@ -781,7 +783,30 @@ CONFIG_SPI_BFIN=y | |||
| 781 | # CONFIG_SPI_SPIDEV is not set | 783 | # CONFIG_SPI_SPIDEV is not set |
| 782 | # CONFIG_SPI_TLE62X0 is not set | 784 | # CONFIG_SPI_TLE62X0 is not set |
| 783 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | 785 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 784 | # CONFIG_GPIOLIB is not set | 786 | CONFIG_GPIOLIB=y |
| 787 | # CONFIG_DEBUG_GPIO is not set | ||
| 788 | CONFIG_GPIO_SYSFS=y | ||
| 789 | |||
| 790 | # | ||
| 791 | # Memory mapped GPIO expanders: | ||
| 792 | # | ||
| 793 | |||
| 794 | # | ||
| 795 | # I2C GPIO expanders: | ||
| 796 | # | ||
| 797 | # CONFIG_GPIO_MAX732X is not set | ||
| 798 | # CONFIG_GPIO_PCA953X is not set | ||
| 799 | # CONFIG_GPIO_PCF857X is not set | ||
| 800 | |||
| 801 | # | ||
| 802 | # PCI GPIO expanders: | ||
| 803 | # | ||
| 804 | |||
| 805 | # | ||
| 806 | # SPI GPIO expanders: | ||
| 807 | # | ||
| 808 | # CONFIG_GPIO_MAX7301 is not set | ||
| 809 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 785 | # CONFIG_W1 is not set | 810 | # CONFIG_W1 is not set |
| 786 | # CONFIG_POWER_SUPPLY is not set | 811 | # CONFIG_POWER_SUPPLY is not set |
| 787 | # CONFIG_HWMON is not set | 812 | # CONFIG_HWMON is not set |
| @@ -1068,16 +1093,6 @@ CONFIG_SYSFS=y | |||
| 1068 | # CONFIG_BEFS_FS is not set | 1093 | # CONFIG_BEFS_FS is not set |
| 1069 | # CONFIG_BFS_FS is not set | 1094 | # CONFIG_BFS_FS is not set |
| 1070 | # CONFIG_EFS_FS is not set | 1095 | # CONFIG_EFS_FS is not set |
| 1071 | CONFIG_YAFFS_FS=m | ||
| 1072 | CONFIG_YAFFS_YAFFS1=y | ||
| 1073 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1074 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1075 | CONFIG_YAFFS_YAFFS2=y | ||
| 1076 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1077 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1078 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1079 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1080 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1081 | CONFIG_JFFS2_FS=m | 1096 | CONFIG_JFFS2_FS=m |
| 1082 | CONFIG_JFFS2_FS_DEBUG=0 | 1097 | CONFIG_JFFS2_FS_DEBUG=0 |
| 1083 | CONFIG_JFFS2_FS_WRITEBUFFER=y | 1098 | CONFIG_JFFS2_FS_WRITEBUFFER=y |
| @@ -1089,6 +1104,16 @@ CONFIG_JFFS2_ZLIB=y | |||
| 1089 | # CONFIG_JFFS2_LZO is not set | 1104 | # CONFIG_JFFS2_LZO is not set |
| 1090 | CONFIG_JFFS2_RTIME=y | 1105 | CONFIG_JFFS2_RTIME=y |
| 1091 | # CONFIG_JFFS2_RUBIN is not set | 1106 | # CONFIG_JFFS2_RUBIN is not set |
| 1107 | CONFIG_YAFFS_FS=m | ||
| 1108 | CONFIG_YAFFS_YAFFS1=y | ||
| 1109 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1110 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1111 | CONFIG_YAFFS_YAFFS2=y | ||
| 1112 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1113 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1114 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1115 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1116 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1092 | # CONFIG_CRAMFS is not set | 1117 | # CONFIG_CRAMFS is not set |
| 1093 | # CONFIG_VXFS_FS is not set | 1118 | # CONFIG_VXFS_FS is not set |
| 1094 | # CONFIG_MINIX_FS is not set | 1119 | # CONFIG_MINIX_FS is not set |
| @@ -1177,7 +1202,7 @@ CONFIG_FRAME_WARN=1024 | |||
| 1177 | CONFIG_DEBUG_FS=y | 1202 | CONFIG_DEBUG_FS=y |
| 1178 | # CONFIG_HEADERS_CHECK is not set | 1203 | # CONFIG_HEADERS_CHECK is not set |
| 1179 | CONFIG_DEBUG_KERNEL=y | 1204 | CONFIG_DEBUG_KERNEL=y |
| 1180 | # CONFIG_DEBUG_SHIRQ is not set | 1205 | CONFIG_DEBUG_SHIRQ=y |
| 1181 | CONFIG_DETECT_SOFTLOCKUP=y | 1206 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1182 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | 1207 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set |
| 1183 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | 1208 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 |
| @@ -1186,8 +1211,6 @@ CONFIG_SCHED_DEBUG=y | |||
| 1186 | # CONFIG_TIMER_STATS is not set | 1211 | # CONFIG_TIMER_STATS is not set |
| 1187 | # CONFIG_DEBUG_OBJECTS is not set | 1212 | # CONFIG_DEBUG_OBJECTS is not set |
| 1188 | # CONFIG_DEBUG_SLAB is not set | 1213 | # CONFIG_DEBUG_SLAB is not set |
| 1189 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1190 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1191 | # CONFIG_DEBUG_SPINLOCK is not set | 1214 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1192 | # CONFIG_DEBUG_MUTEXES is not set | 1215 | # CONFIG_DEBUG_MUTEXES is not set |
| 1193 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1216 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| @@ -1207,7 +1230,6 @@ CONFIG_DEBUG_INFO=y | |||
| 1207 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1230 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1208 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 1231 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
| 1209 | # CONFIG_FAULT_INJECTION is not set | 1232 | # CONFIG_FAULT_INJECTION is not set |
| 1210 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1211 | 1233 | ||
| 1212 | # | 1234 | # |
| 1213 | # Tracers | 1235 | # Tracers |
| @@ -1223,16 +1245,20 @@ CONFIG_HAVE_ARCH_KGDB=y | |||
| 1223 | # CONFIG_DEBUG_STACK_USAGE is not set | 1245 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1224 | CONFIG_DEBUG_VERBOSE=y | 1246 | CONFIG_DEBUG_VERBOSE=y |
| 1225 | CONFIG_DEBUG_MMRS=y | 1247 | CONFIG_DEBUG_MMRS=y |
| 1226 | # CONFIG_DEBUG_HWERR is not set | 1248 | CONFIG_DEBUG_HWERR=y |
| 1227 | # CONFIG_DEBUG_DOUBLEFAULT is not set | 1249 | CONFIG_EXACT_HWERR=y |
| 1250 | CONFIG_DEBUG_DOUBLEFAULT=y | ||
| 1251 | CONFIG_DEBUG_DOUBLEFAULT_PRINT=y | ||
| 1252 | # CONFIG_DEBUG_DOUBLEFAULT_RESET is not set | ||
| 1253 | # CONFIG_DEBUG_ICACHE_CHECK is not set | ||
| 1228 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1254 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1229 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1255 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1230 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1256 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set |
| 1231 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set | 1257 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y |
| 1232 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set | 1258 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set |
| 1233 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 | 1259 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1 |
| 1234 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set | 1260 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set |
| 1235 | # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set | 1261 | CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y |
| 1236 | CONFIG_EARLY_PRINTK=y | 1262 | CONFIG_EARLY_PRINTK=y |
| 1237 | CONFIG_CPLB_INFO=y | 1263 | CONFIG_CPLB_INFO=y |
| 1238 | CONFIG_ACCESS_CHECK=y | 1264 | CONFIG_ACCESS_CHECK=y |
| @@ -1345,7 +1371,6 @@ CONFIG_CRC32=y | |||
| 1345 | # CONFIG_LIBCRC32C is not set | 1371 | # CONFIG_LIBCRC32C is not set |
| 1346 | CONFIG_ZLIB_INFLATE=y | 1372 | CONFIG_ZLIB_INFLATE=y |
| 1347 | CONFIG_ZLIB_DEFLATE=m | 1373 | CONFIG_ZLIB_DEFLATE=m |
| 1348 | CONFIG_PLIST=y | ||
| 1349 | CONFIG_HAS_IOMEM=y | 1374 | CONFIG_HAS_IOMEM=y |
| 1350 | CONFIG_HAS_IOPORT=y | 1375 | CONFIG_HAS_IOPORT=y |
| 1351 | CONFIG_HAS_DMA=y | 1376 | CONFIG_HAS_DMA=y |
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig index 591f6edda4f7..f9ac20d55799 100644 --- a/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/arch/blackfin/configs/BF537-STAMP_defconfig | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28.7 | 3 | # Linux kernel version: 2.6.28.10 |
| 4 | # Thu May 21 05:50:01 2009 | ||
| 4 | # | 5 | # |
| 5 | # CONFIG_MMU is not set | 6 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 7 | # CONFIG_FPU is not set |
| @@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 42 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 43 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 44 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 45 | # CONFIG_SYSCTL is not set | 46 | CONFIG_SYSCTL=y |
| 47 | CONFIG_ANON_INODES=y | ||
| 46 | CONFIG_EMBEDDED=y | 48 | CONFIG_EMBEDDED=y |
| 47 | CONFIG_UID16=y | 49 | CONFIG_UID16=y |
| 48 | CONFIG_SYSCTL_SYSCALL=y | 50 | # CONFIG_SYSCTL_SYSCALL is not set |
| 49 | CONFIG_KALLSYMS=y | 51 | CONFIG_KALLSYMS=y |
| 50 | # CONFIG_KALLSYMS_ALL is not set | 52 | # CONFIG_KALLSYMS_ALL is not set |
| 51 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 53 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| @@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y | |||
| 53 | CONFIG_PRINTK=y | 55 | CONFIG_PRINTK=y |
| 54 | CONFIG_BUG=y | 56 | CONFIG_BUG=y |
| 55 | # CONFIG_ELF_CORE is not set | 57 | # CONFIG_ELF_CORE is not set |
| 56 | CONFIG_COMPAT_BRK=y | ||
| 57 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 58 | # CONFIG_FUTEX is not set | 59 | # CONFIG_FUTEX is not set |
| 59 | CONFIG_ANON_INODES=y | ||
| 60 | CONFIG_EPOLL=y | 60 | CONFIG_EPOLL=y |
| 61 | CONFIG_SIGNALFD=y | 61 | # CONFIG_SIGNALFD is not set |
| 62 | CONFIG_TIMERFD=y | 62 | # CONFIG_TIMERFD is not set |
| 63 | CONFIG_EVENTFD=y | 63 | # CONFIG_EVENTFD is not set |
| 64 | # CONFIG_AIO is not set | 64 | # CONFIG_AIO is not set |
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 65 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_COMPAT_BRK=y | ||
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| @@ -71,7 +72,6 @@ CONFIG_SLAB=y | |||
| 71 | CONFIG_HAVE_OPROFILE=y | 72 | CONFIG_HAVE_OPROFILE=y |
| 72 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 73 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 74 | CONFIG_RT_MUTEXES=y | ||
| 75 | CONFIG_TINY_SHMEM=y | 75 | CONFIG_TINY_SHMEM=y |
| 76 | CONFIG_BASE_SMALL=0 | 76 | CONFIG_BASE_SMALL=0 |
| 77 | CONFIG_MODULES=y | 77 | CONFIG_MODULES=y |
| @@ -232,7 +232,10 @@ CONFIG_HZ=250 | |||
| 232 | CONFIG_SCHED_HRTICK=y | 232 | CONFIG_SCHED_HRTICK=y |
| 233 | CONFIG_GENERIC_TIME=y | 233 | CONFIG_GENERIC_TIME=y |
| 234 | CONFIG_GENERIC_CLOCKEVENTS=y | 234 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 235 | # CONFIG_TICKSOURCE_GPTMR0 is not set | ||
| 236 | CONFIG_TICKSOURCE_CORETMR=y | ||
| 235 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 237 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 238 | # CONFIG_GPTMR0_CLOCKSOURCE is not set | ||
| 236 | CONFIG_TICK_ONESHOT=y | 239 | CONFIG_TICK_ONESHOT=y |
| 237 | # CONFIG_NO_HZ is not set | 240 | # CONFIG_NO_HZ is not set |
| 238 | CONFIG_HIGH_RES_TIMERS=y | 241 | CONFIG_HIGH_RES_TIMERS=y |
| @@ -390,7 +393,7 @@ CONFIG_IP_PNP=y | |||
| 390 | # CONFIG_NET_IPIP is not set | 393 | # CONFIG_NET_IPIP is not set |
| 391 | # CONFIG_NET_IPGRE is not set | 394 | # CONFIG_NET_IPGRE is not set |
| 392 | # CONFIG_ARPD is not set | 395 | # CONFIG_ARPD is not set |
| 393 | CONFIG_SYN_COOKIES=y | 396 | # CONFIG_SYN_COOKIES is not set |
| 394 | # CONFIG_INET_AH is not set | 397 | # CONFIG_INET_AH is not set |
| 395 | # CONFIG_INET_ESP is not set | 398 | # CONFIG_INET_ESP is not set |
| 396 | # CONFIG_INET_IPCOMP is not set | 399 | # CONFIG_INET_IPCOMP is not set |
| @@ -548,9 +551,7 @@ CONFIG_MTD_ROM=m | |||
| 548 | # | 551 | # |
| 549 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 552 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 550 | CONFIG_MTD_PHYSMAP=m | 553 | CONFIG_MTD_PHYSMAP=m |
| 551 | CONFIG_MTD_PHYSMAP_START=0x20000000 | 554 | # CONFIG_MTD_PHYSMAP_COMPAT is not set |
| 552 | CONFIG_MTD_PHYSMAP_LEN=0x0 | ||
| 553 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 554 | # CONFIG_MTD_UCLINUX is not set | 555 | # CONFIG_MTD_UCLINUX is not set |
| 555 | # CONFIG_MTD_PLATRAM is not set | 556 | # CONFIG_MTD_PLATRAM is not set |
| 556 | 557 | ||
| @@ -649,9 +650,8 @@ CONFIG_BFIN_RX_DESC_NUM=20 | |||
| 649 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | 650 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set |
| 650 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | 651 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set |
| 651 | # CONFIG_B44 is not set | 652 | # CONFIG_B44 is not set |
| 652 | CONFIG_NETDEV_1000=y | 653 | # CONFIG_NETDEV_1000 is not set |
| 653 | # CONFIG_AX88180 is not set | 654 | # CONFIG_NETDEV_10000 is not set |
| 654 | CONFIG_NETDEV_10000=y | ||
| 655 | 655 | ||
| 656 | # | 656 | # |
| 657 | # Wireless LAN | 657 | # Wireless LAN |
| @@ -708,14 +708,14 @@ CONFIG_SERIO_LIBPS2=y | |||
| 708 | # Character devices | 708 | # Character devices |
| 709 | # | 709 | # |
| 710 | # CONFIG_AD9960 is not set | 710 | # CONFIG_AD9960 is not set |
| 711 | # CONFIG_SPI_ADC_BF533 is not set | 711 | CONFIG_BFIN_DMA_INTERFACE=m |
| 712 | # CONFIG_BF5xx_PPIFCD is not set | 712 | # CONFIG_BFIN_PPI is not set |
| 713 | # CONFIG_BFIN_PPIFCD is not set | ||
| 713 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 714 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 714 | CONFIG_BF5xx_PPI=m | 715 | # CONFIG_BFIN_SPI_ADC is not set |
| 715 | CONFIG_BFIN_SPORT=m | 716 | CONFIG_BFIN_SPORT=m |
| 716 | # CONFIG_BFIN_TIMER_LATENCY is not set | 717 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 717 | # CONFIG_TWI_LCD is not set | 718 | # CONFIG_BFIN_TWI_LCD is not set |
| 718 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 719 | CONFIG_SIMPLE_GPIO=m | 719 | CONFIG_SIMPLE_GPIO=m |
| 720 | # CONFIG_VT is not set | 720 | # CONFIG_VT is not set |
| 721 | # CONFIG_DEVKMEM is not set | 721 | # CONFIG_DEVKMEM is not set |
| @@ -823,7 +823,30 @@ CONFIG_SPI_BFIN=y | |||
| 823 | # CONFIG_SPI_SPIDEV is not set | 823 | # CONFIG_SPI_SPIDEV is not set |
| 824 | # CONFIG_SPI_TLE62X0 is not set | 824 | # CONFIG_SPI_TLE62X0 is not set |
| 825 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | 825 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 826 | # CONFIG_GPIOLIB is not set | 826 | CONFIG_GPIOLIB=y |
| 827 | # CONFIG_DEBUG_GPIO is not set | ||
| 828 | CONFIG_GPIO_SYSFS=y | ||
| 829 | |||
| 830 | # | ||
| 831 | # Memory mapped GPIO expanders: | ||
| 832 | # | ||
| 833 | |||
| 834 | # | ||
| 835 | # I2C GPIO expanders: | ||
| 836 | # | ||
| 837 | # CONFIG_GPIO_MAX732X is not set | ||
| 838 | # CONFIG_GPIO_PCA953X is not set | ||
| 839 | # CONFIG_GPIO_PCF857X is not set | ||
| 840 | |||
| 841 | # | ||
| 842 | # PCI GPIO expanders: | ||
| 843 | # | ||
| 844 | |||
| 845 | # | ||
| 846 | # SPI GPIO expanders: | ||
| 847 | # | ||
| 848 | # CONFIG_GPIO_MAX7301 is not set | ||
| 849 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 827 | # CONFIG_W1 is not set | 850 | # CONFIG_W1 is not set |
| 828 | # CONFIG_POWER_SUPPLY is not set | 851 | # CONFIG_POWER_SUPPLY is not set |
| 829 | # CONFIG_HWMON is not set | 852 | # CONFIG_HWMON is not set |
| @@ -1123,16 +1146,6 @@ CONFIG_SYSFS=y | |||
| 1123 | # CONFIG_BEFS_FS is not set | 1146 | # CONFIG_BEFS_FS is not set |
| 1124 | # CONFIG_BFS_FS is not set | 1147 | # CONFIG_BFS_FS is not set |
| 1125 | # CONFIG_EFS_FS is not set | 1148 | # CONFIG_EFS_FS is not set |
| 1126 | CONFIG_YAFFS_FS=m | ||
| 1127 | CONFIG_YAFFS_YAFFS1=y | ||
| 1128 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1129 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1130 | CONFIG_YAFFS_YAFFS2=y | ||
| 1131 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1132 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1133 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1134 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1135 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1136 | CONFIG_JFFS2_FS=m | 1149 | CONFIG_JFFS2_FS=m |
| 1137 | CONFIG_JFFS2_FS_DEBUG=0 | 1150 | CONFIG_JFFS2_FS_DEBUG=0 |
| 1138 | CONFIG_JFFS2_FS_WRITEBUFFER=y | 1151 | CONFIG_JFFS2_FS_WRITEBUFFER=y |
| @@ -1144,6 +1157,16 @@ CONFIG_JFFS2_ZLIB=y | |||
| 1144 | # CONFIG_JFFS2_LZO is not set | 1157 | # CONFIG_JFFS2_LZO is not set |
| 1145 | CONFIG_JFFS2_RTIME=y | 1158 | CONFIG_JFFS2_RTIME=y |
| 1146 | # CONFIG_JFFS2_RUBIN is not set | 1159 | # CONFIG_JFFS2_RUBIN is not set |
| 1160 | CONFIG_YAFFS_FS=m | ||
| 1161 | CONFIG_YAFFS_YAFFS1=y | ||
| 1162 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1163 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1164 | CONFIG_YAFFS_YAFFS2=y | ||
| 1165 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1166 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1167 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1168 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1169 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1147 | # CONFIG_CRAMFS is not set | 1170 | # CONFIG_CRAMFS is not set |
| 1148 | # CONFIG_VXFS_FS is not set | 1171 | # CONFIG_VXFS_FS is not set |
| 1149 | # CONFIG_MINIX_FS is not set | 1172 | # CONFIG_MINIX_FS is not set |
| @@ -1232,7 +1255,7 @@ CONFIG_FRAME_WARN=1024 | |||
| 1232 | CONFIG_DEBUG_FS=y | 1255 | CONFIG_DEBUG_FS=y |
| 1233 | # CONFIG_HEADERS_CHECK is not set | 1256 | # CONFIG_HEADERS_CHECK is not set |
| 1234 | CONFIG_DEBUG_KERNEL=y | 1257 | CONFIG_DEBUG_KERNEL=y |
| 1235 | # CONFIG_DEBUG_SHIRQ is not set | 1258 | CONFIG_DEBUG_SHIRQ=y |
| 1236 | CONFIG_DETECT_SOFTLOCKUP=y | 1259 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1237 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | 1260 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set |
| 1238 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | 1261 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 |
| @@ -1241,8 +1264,6 @@ CONFIG_SCHED_DEBUG=y | |||
| 1241 | # CONFIG_TIMER_STATS is not set | 1264 | # CONFIG_TIMER_STATS is not set |
| 1242 | # CONFIG_DEBUG_OBJECTS is not set | 1265 | # CONFIG_DEBUG_OBJECTS is not set |
| 1243 | # CONFIG_DEBUG_SLAB is not set | 1266 | # CONFIG_DEBUG_SLAB is not set |
| 1244 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1245 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1246 | # CONFIG_DEBUG_SPINLOCK is not set | 1267 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1247 | # CONFIG_DEBUG_MUTEXES is not set | 1268 | # CONFIG_DEBUG_MUTEXES is not set |
| 1248 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1269 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| @@ -1262,7 +1283,6 @@ CONFIG_DEBUG_INFO=y | |||
| 1262 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1283 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1263 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 1284 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
| 1264 | # CONFIG_FAULT_INJECTION is not set | 1285 | # CONFIG_FAULT_INJECTION is not set |
| 1265 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1266 | 1286 | ||
| 1267 | # | 1287 | # |
| 1268 | # Tracers | 1288 | # Tracers |
| @@ -1278,16 +1298,20 @@ CONFIG_HAVE_ARCH_KGDB=y | |||
| 1278 | # CONFIG_DEBUG_STACK_USAGE is not set | 1298 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1279 | CONFIG_DEBUG_VERBOSE=y | 1299 | CONFIG_DEBUG_VERBOSE=y |
| 1280 | CONFIG_DEBUG_MMRS=y | 1300 | CONFIG_DEBUG_MMRS=y |
| 1281 | # CONFIG_DEBUG_HWERR is not set | 1301 | CONFIG_DEBUG_HWERR=y |
| 1282 | # CONFIG_DEBUG_DOUBLEFAULT is not set | 1302 | CONFIG_EXACT_HWERR=y |
| 1303 | CONFIG_DEBUG_DOUBLEFAULT=y | ||
| 1304 | CONFIG_DEBUG_DOUBLEFAULT_PRINT=y | ||
| 1305 | # CONFIG_DEBUG_DOUBLEFAULT_RESET is not set | ||
| 1306 | # CONFIG_DEBUG_ICACHE_CHECK is not set | ||
| 1283 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1307 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1284 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1308 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1285 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1309 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set |
| 1286 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set | 1310 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y |
| 1287 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set | 1311 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set |
| 1288 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 | 1312 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1 |
| 1289 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set | 1313 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set |
| 1290 | # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set | 1314 | CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y |
| 1291 | CONFIG_EARLY_PRINTK=y | 1315 | CONFIG_EARLY_PRINTK=y |
| 1292 | CONFIG_CPLB_INFO=y | 1316 | CONFIG_CPLB_INFO=y |
| 1293 | CONFIG_ACCESS_CHECK=y | 1317 | CONFIG_ACCESS_CHECK=y |
| @@ -1400,7 +1424,6 @@ CONFIG_CRC32=y | |||
| 1400 | # CONFIG_LIBCRC32C is not set | 1424 | # CONFIG_LIBCRC32C is not set |
| 1401 | CONFIG_ZLIB_INFLATE=y | 1425 | CONFIG_ZLIB_INFLATE=y |
| 1402 | CONFIG_ZLIB_DEFLATE=m | 1426 | CONFIG_ZLIB_DEFLATE=m |
| 1403 | CONFIG_PLIST=y | ||
| 1404 | CONFIG_HAS_IOMEM=y | 1427 | CONFIG_HAS_IOMEM=y |
| 1405 | CONFIG_HAS_IOPORT=y | 1428 | CONFIG_HAS_IOPORT=y |
| 1406 | CONFIG_HAS_DMA=y | 1429 | CONFIG_HAS_DMA=y |
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig index 1a8e8c3adf98..ee98e227b887 100644 --- a/arch/blackfin/configs/BF538-EZKIT_defconfig +++ b/arch/blackfin/configs/BF538-EZKIT_defconfig | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28.7 | 3 | # Linux kernel version: 2.6.28.10 |
| 4 | # Thu May 21 05:50:01 2009 | ||
| 4 | # | 5 | # |
| 5 | # CONFIG_MMU is not set | 6 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 7 | # CONFIG_FPU is not set |
| @@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 42 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 43 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 44 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 45 | # CONFIG_SYSCTL is not set | 46 | CONFIG_SYSCTL=y |
| 47 | CONFIG_ANON_INODES=y | ||
| 46 | CONFIG_EMBEDDED=y | 48 | CONFIG_EMBEDDED=y |
| 47 | CONFIG_UID16=y | 49 | CONFIG_UID16=y |
| 48 | CONFIG_SYSCTL_SYSCALL=y | 50 | # CONFIG_SYSCTL_SYSCALL is not set |
| 49 | CONFIG_KALLSYMS=y | 51 | CONFIG_KALLSYMS=y |
| 50 | # CONFIG_KALLSYMS_ALL is not set | 52 | # CONFIG_KALLSYMS_ALL is not set |
| 51 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 53 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| @@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y | |||
| 53 | CONFIG_PRINTK=y | 55 | CONFIG_PRINTK=y |
| 54 | CONFIG_BUG=y | 56 | CONFIG_BUG=y |
| 55 | # CONFIG_ELF_CORE is not set | 57 | # CONFIG_ELF_CORE is not set |
| 56 | CONFIG_COMPAT_BRK=y | ||
| 57 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 58 | # CONFIG_FUTEX is not set | 59 | # CONFIG_FUTEX is not set |
| 59 | CONFIG_ANON_INODES=y | ||
| 60 | CONFIG_EPOLL=y | 60 | CONFIG_EPOLL=y |
| 61 | CONFIG_SIGNALFD=y | 61 | # CONFIG_SIGNALFD is not set |
| 62 | CONFIG_TIMERFD=y | 62 | # CONFIG_TIMERFD is not set |
| 63 | CONFIG_EVENTFD=y | 63 | # CONFIG_EVENTFD is not set |
| 64 | # CONFIG_AIO is not set | 64 | # CONFIG_AIO is not set |
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 65 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_COMPAT_BRK=y | ||
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| @@ -71,7 +72,6 @@ CONFIG_SLAB=y | |||
| 71 | CONFIG_HAVE_OPROFILE=y | 72 | CONFIG_HAVE_OPROFILE=y |
| 72 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 73 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 74 | CONFIG_RT_MUTEXES=y | ||
| 75 | CONFIG_TINY_SHMEM=y | 75 | CONFIG_TINY_SHMEM=y |
| 76 | CONFIG_BASE_SMALL=0 | 76 | CONFIG_BASE_SMALL=0 |
| 77 | CONFIG_MODULES=y | 77 | CONFIG_MODULES=y |
| @@ -243,7 +243,10 @@ CONFIG_HZ=250 | |||
| 243 | CONFIG_SCHED_HRTICK=y | 243 | CONFIG_SCHED_HRTICK=y |
| 244 | CONFIG_GENERIC_TIME=y | 244 | CONFIG_GENERIC_TIME=y |
| 245 | CONFIG_GENERIC_CLOCKEVENTS=y | 245 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 246 | # CONFIG_TICKSOURCE_GPTMR0 is not set | ||
| 247 | CONFIG_TICKSOURCE_CORETMR=y | ||
| 246 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 248 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 249 | # CONFIG_GPTMR0_CLOCKSOURCE is not set | ||
| 247 | CONFIG_TICK_ONESHOT=y | 250 | CONFIG_TICK_ONESHOT=y |
| 248 | # CONFIG_NO_HZ is not set | 251 | # CONFIG_NO_HZ is not set |
| 249 | CONFIG_HIGH_RES_TIMERS=y | 252 | CONFIG_HIGH_RES_TIMERS=y |
| @@ -389,7 +392,7 @@ CONFIG_IP_PNP=y | |||
| 389 | # CONFIG_NET_IPIP is not set | 392 | # CONFIG_NET_IPIP is not set |
| 390 | # CONFIG_NET_IPGRE is not set | 393 | # CONFIG_NET_IPGRE is not set |
| 391 | # CONFIG_ARPD is not set | 394 | # CONFIG_ARPD is not set |
| 392 | CONFIG_SYN_COOKIES=y | 395 | # CONFIG_SYN_COOKIES is not set |
| 393 | # CONFIG_INET_AH is not set | 396 | # CONFIG_INET_AH is not set |
| 394 | # CONFIG_INET_ESP is not set | 397 | # CONFIG_INET_ESP is not set |
| 395 | # CONFIG_INET_IPCOMP is not set | 398 | # CONFIG_INET_IPCOMP is not set |
| @@ -546,9 +549,7 @@ CONFIG_MTD_ROM=m | |||
| 546 | # | 549 | # |
| 547 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 550 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 548 | CONFIG_MTD_PHYSMAP=m | 551 | CONFIG_MTD_PHYSMAP=m |
| 549 | CONFIG_MTD_PHYSMAP_START=0x20000000 | 552 | # CONFIG_MTD_PHYSMAP_COMPAT is not set |
| 550 | CONFIG_MTD_PHYSMAP_LEN=0x0 | ||
| 551 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 552 | # CONFIG_MTD_UCLINUX is not set | 553 | # CONFIG_MTD_UCLINUX is not set |
| 553 | # CONFIG_MTD_PLATRAM is not set | 554 | # CONFIG_MTD_PLATRAM is not set |
| 554 | 555 | ||
| @@ -691,11 +692,11 @@ CONFIG_INPUT_EVDEV=m | |||
| 691 | # CONFIG_INPUT_JOYSTICK is not set | 692 | # CONFIG_INPUT_JOYSTICK is not set |
| 692 | # CONFIG_INPUT_TABLET is not set | 693 | # CONFIG_INPUT_TABLET is not set |
| 693 | CONFIG_INPUT_TOUCHSCREEN=y | 694 | CONFIG_INPUT_TOUCHSCREEN=y |
| 694 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 695 | # CONFIG_TOUCHSCREEN_AD7877 is not set | 695 | # CONFIG_TOUCHSCREEN_AD7877 is not set |
| 696 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | 696 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set |
| 697 | CONFIG_TOUCHSCREEN_AD7879_SPI=y | 697 | CONFIG_TOUCHSCREEN_AD7879_SPI=y |
| 698 | CONFIG_TOUCHSCREEN_AD7879=y | 698 | CONFIG_TOUCHSCREEN_AD7879=y |
| 699 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 699 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 700 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 700 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 701 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 701 | # CONFIG_TOUCHSCREEN_ELO is not set | 702 | # CONFIG_TOUCHSCREEN_ELO is not set |
| @@ -720,14 +721,14 @@ CONFIG_INPUT_MISC=y | |||
| 720 | # Character devices | 721 | # Character devices |
| 721 | # | 722 | # |
| 722 | # CONFIG_AD9960 is not set | 723 | # CONFIG_AD9960 is not set |
| 723 | # CONFIG_SPI_ADC_BF533 is not set | 724 | CONFIG_BFIN_DMA_INTERFACE=m |
| 724 | # CONFIG_BF5xx_PPIFCD is not set | 725 | # CONFIG_BFIN_PPI is not set |
| 726 | # CONFIG_BFIN_PPIFCD is not set | ||
| 725 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 727 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 726 | CONFIG_BF5xx_PPI=m | 728 | # CONFIG_BFIN_SPI_ADC is not set |
| 727 | CONFIG_BFIN_SPORT=m | 729 | CONFIG_BFIN_SPORT=m |
| 728 | # CONFIG_BFIN_TIMER_LATENCY is not set | 730 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 729 | # CONFIG_TWI_LCD is not set | 731 | # CONFIG_BFIN_TWI_LCD is not set |
| 730 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 731 | CONFIG_SIMPLE_GPIO=m | 732 | CONFIG_SIMPLE_GPIO=m |
| 732 | # CONFIG_VT is not set | 733 | # CONFIG_VT is not set |
| 733 | # CONFIG_DEVKMEM is not set | 734 | # CONFIG_DEVKMEM is not set |
| @@ -833,7 +834,30 @@ CONFIG_SPI_BFIN=y | |||
| 833 | # CONFIG_SPI_SPIDEV is not set | 834 | # CONFIG_SPI_SPIDEV is not set |
| 834 | # CONFIG_SPI_TLE62X0 is not set | 835 | # CONFIG_SPI_TLE62X0 is not set |
| 835 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | 836 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 836 | # CONFIG_GPIOLIB is not set | 837 | CONFIG_GPIOLIB=y |
| 838 | # CONFIG_DEBUG_GPIO is not set | ||
| 839 | CONFIG_GPIO_SYSFS=y | ||
| 840 | |||
| 841 | # | ||
| 842 | # Memory mapped GPIO expanders: | ||
| 843 | # | ||
| 844 | |||
| 845 | # | ||
| 846 | # I2C GPIO expanders: | ||
| 847 | # | ||
| 848 | # CONFIG_GPIO_MAX732X is not set | ||
| 849 | # CONFIG_GPIO_PCA953X is not set | ||
| 850 | # CONFIG_GPIO_PCF857X is not set | ||
| 851 | |||
| 852 | # | ||
| 853 | # PCI GPIO expanders: | ||
| 854 | # | ||
| 855 | |||
| 856 | # | ||
| 857 | # SPI GPIO expanders: | ||
| 858 | # | ||
| 859 | # CONFIG_GPIO_MAX7301 is not set | ||
| 860 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 837 | # CONFIG_W1 is not set | 861 | # CONFIG_W1 is not set |
| 838 | # CONFIG_POWER_SUPPLY is not set | 862 | # CONFIG_POWER_SUPPLY is not set |
| 839 | # CONFIG_HWMON is not set | 863 | # CONFIG_HWMON is not set |
| @@ -1056,16 +1080,6 @@ CONFIG_SYSFS=y | |||
| 1056 | # CONFIG_BEFS_FS is not set | 1080 | # CONFIG_BEFS_FS is not set |
| 1057 | # CONFIG_BFS_FS is not set | 1081 | # CONFIG_BFS_FS is not set |
| 1058 | # CONFIG_EFS_FS is not set | 1082 | # CONFIG_EFS_FS is not set |
| 1059 | CONFIG_YAFFS_FS=m | ||
| 1060 | CONFIG_YAFFS_YAFFS1=y | ||
| 1061 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1062 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1063 | CONFIG_YAFFS_YAFFS2=y | ||
| 1064 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1065 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1066 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1067 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1068 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1069 | CONFIG_JFFS2_FS=m | 1083 | CONFIG_JFFS2_FS=m |
| 1070 | CONFIG_JFFS2_FS_DEBUG=0 | 1084 | CONFIG_JFFS2_FS_DEBUG=0 |
| 1071 | CONFIG_JFFS2_FS_WRITEBUFFER=y | 1085 | CONFIG_JFFS2_FS_WRITEBUFFER=y |
| @@ -1077,6 +1091,16 @@ CONFIG_JFFS2_ZLIB=y | |||
| 1077 | # CONFIG_JFFS2_LZO is not set | 1091 | # CONFIG_JFFS2_LZO is not set |
| 1078 | CONFIG_JFFS2_RTIME=y | 1092 | CONFIG_JFFS2_RTIME=y |
| 1079 | # CONFIG_JFFS2_RUBIN is not set | 1093 | # CONFIG_JFFS2_RUBIN is not set |
| 1094 | CONFIG_YAFFS_FS=m | ||
| 1095 | CONFIG_YAFFS_YAFFS1=y | ||
| 1096 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1097 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1098 | CONFIG_YAFFS_YAFFS2=y | ||
| 1099 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1100 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1101 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1102 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1103 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1080 | # CONFIG_CRAMFS is not set | 1104 | # CONFIG_CRAMFS is not set |
| 1081 | # CONFIG_VXFS_FS is not set | 1105 | # CONFIG_VXFS_FS is not set |
| 1082 | # CONFIG_MINIX_FS is not set | 1106 | # CONFIG_MINIX_FS is not set |
| @@ -1165,7 +1189,7 @@ CONFIG_FRAME_WARN=1024 | |||
| 1165 | CONFIG_DEBUG_FS=y | 1189 | CONFIG_DEBUG_FS=y |
| 1166 | # CONFIG_HEADERS_CHECK is not set | 1190 | # CONFIG_HEADERS_CHECK is not set |
| 1167 | CONFIG_DEBUG_KERNEL=y | 1191 | CONFIG_DEBUG_KERNEL=y |
| 1168 | # CONFIG_DEBUG_SHIRQ is not set | 1192 | CONFIG_DEBUG_SHIRQ=y |
| 1169 | CONFIG_DETECT_SOFTLOCKUP=y | 1193 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1170 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | 1194 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set |
| 1171 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | 1195 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 |
| @@ -1174,8 +1198,6 @@ CONFIG_SCHED_DEBUG=y | |||
| 1174 | # CONFIG_TIMER_STATS is not set | 1198 | # CONFIG_TIMER_STATS is not set |
| 1175 | # CONFIG_DEBUG_OBJECTS is not set | 1199 | # CONFIG_DEBUG_OBJECTS is not set |
| 1176 | # CONFIG_DEBUG_SLAB is not set | 1200 | # CONFIG_DEBUG_SLAB is not set |
| 1177 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1178 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1179 | # CONFIG_DEBUG_SPINLOCK is not set | 1201 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1180 | # CONFIG_DEBUG_MUTEXES is not set | 1202 | # CONFIG_DEBUG_MUTEXES is not set |
| 1181 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1203 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| @@ -1195,7 +1217,6 @@ CONFIG_DEBUG_INFO=y | |||
| 1195 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1217 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1196 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 1218 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
| 1197 | # CONFIG_FAULT_INJECTION is not set | 1219 | # CONFIG_FAULT_INJECTION is not set |
| 1198 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 1199 | 1220 | ||
| 1200 | # | 1221 | # |
| 1201 | # Tracers | 1222 | # Tracers |
| @@ -1211,16 +1232,20 @@ CONFIG_HAVE_ARCH_KGDB=y | |||
| 1211 | # CONFIG_DEBUG_STACK_USAGE is not set | 1232 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1212 | CONFIG_DEBUG_VERBOSE=y | 1233 | CONFIG_DEBUG_VERBOSE=y |
| 1213 | CONFIG_DEBUG_MMRS=y | 1234 | CONFIG_DEBUG_MMRS=y |
| 1214 | # CONFIG_DEBUG_HWERR is not set | 1235 | CONFIG_DEBUG_HWERR=y |
| 1215 | # CONFIG_DEBUG_DOUBLEFAULT is not set | 1236 | CONFIG_EXACT_HWERR=y |
| 1237 | CONFIG_DEBUG_DOUBLEFAULT=y | ||
| 1238 | CONFIG_DEBUG_DOUBLEFAULT_PRINT=y | ||
| 1239 | # CONFIG_DEBUG_DOUBLEFAULT_RESET is not set | ||
| 1240 | # CONFIG_DEBUG_ICACHE_CHECK is not set | ||
| 1216 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1241 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1217 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1242 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1218 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1243 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set |
| 1219 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set | 1244 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y |
| 1220 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set | 1245 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set |
| 1221 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 | 1246 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1 |
| 1222 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set | 1247 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set |
| 1223 | # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set | 1248 | CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y |
| 1224 | CONFIG_EARLY_PRINTK=y | 1249 | CONFIG_EARLY_PRINTK=y |
| 1225 | CONFIG_CPLB_INFO=y | 1250 | CONFIG_CPLB_INFO=y |
| 1226 | CONFIG_ACCESS_CHECK=y | 1251 | CONFIG_ACCESS_CHECK=y |
| @@ -1333,7 +1358,6 @@ CONFIG_CRC32=y | |||
| 1333 | # CONFIG_LIBCRC32C is not set | 1358 | # CONFIG_LIBCRC32C is not set |
| 1334 | CONFIG_ZLIB_INFLATE=y | 1359 | CONFIG_ZLIB_INFLATE=y |
| 1335 | CONFIG_ZLIB_DEFLATE=m | 1360 | CONFIG_ZLIB_DEFLATE=m |
| 1336 | CONFIG_PLIST=y | ||
| 1337 | CONFIG_HAS_IOMEM=y | 1361 | CONFIG_HAS_IOMEM=y |
| 1338 | CONFIG_HAS_IOPORT=y | 1362 | CONFIG_HAS_IOPORT=y |
| 1339 | CONFIG_HAS_DMA=y | 1363 | CONFIG_HAS_DMA=y |
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index 2cd1c2b218d7..deeabef8ab80 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28.7 | 3 | # Linux kernel version: 2.6.28.10 |
| 4 | # Thu May 21 05:50:01 2009 | ||
| 4 | # | 5 | # |
| 5 | # CONFIG_MMU is not set | 6 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 7 | # CONFIG_FPU is not set |
| @@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 42 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 43 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 44 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 45 | # CONFIG_SYSCTL is not set | 46 | CONFIG_SYSCTL=y |
| 47 | CONFIG_ANON_INODES=y | ||
| 46 | CONFIG_EMBEDDED=y | 48 | CONFIG_EMBEDDED=y |
| 47 | CONFIG_UID16=y | 49 | CONFIG_UID16=y |
| 48 | CONFIG_SYSCTL_SYSCALL=y | 50 | # CONFIG_SYSCTL_SYSCALL is not set |
| 49 | CONFIG_KALLSYMS=y | 51 | CONFIG_KALLSYMS=y |
| 50 | # CONFIG_KALLSYMS_ALL is not set | 52 | # CONFIG_KALLSYMS_ALL is not set |
| 51 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 53 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| @@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y | |||
| 53 | CONFIG_PRINTK=y | 55 | CONFIG_PRINTK=y |
| 54 | CONFIG_BUG=y | 56 | CONFIG_BUG=y |
| 55 | # CONFIG_ELF_CORE is not set | 57 | # CONFIG_ELF_CORE is not set |
| 56 | CONFIG_COMPAT_BRK=y | ||
| 57 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 58 | # CONFIG_FUTEX is not set | 59 | # CONFIG_FUTEX is not set |
| 59 | CONFIG_ANON_INODES=y | ||
| 60 | CONFIG_EPOLL=y | 60 | CONFIG_EPOLL=y |
| 61 | CONFIG_SIGNALFD=y | 61 | # CONFIG_SIGNALFD is not set |
| 62 | CONFIG_TIMERFD=y | 62 | # CONFIG_TIMERFD is not set |
| 63 | CONFIG_EVENTFD=y | 63 | # CONFIG_EVENTFD is not set |
| 64 | # CONFIG_AIO is not set | 64 | # CONFIG_AIO is not set |
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 65 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_COMPAT_BRK=y | ||
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| @@ -71,7 +72,6 @@ CONFIG_SLAB=y | |||
| 71 | CONFIG_HAVE_OPROFILE=y | 72 | CONFIG_HAVE_OPROFILE=y |
| 72 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 73 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 74 | CONFIG_RT_MUTEXES=y | ||
| 75 | CONFIG_TINY_SHMEM=y | 75 | CONFIG_TINY_SHMEM=y |
| 76 | CONFIG_BASE_SMALL=0 | 76 | CONFIG_BASE_SMALL=0 |
| 77 | CONFIG_MODULES=y | 77 | CONFIG_MODULES=y |
| @@ -196,6 +196,7 @@ CONFIG_BFIN548_EZKIT=y | |||
| 196 | # BF548 Specific Configuration | 196 | # BF548 Specific Configuration |
| 197 | # | 197 | # |
| 198 | # CONFIG_DEB_DMA_URGENT is not set | 198 | # CONFIG_DEB_DMA_URGENT is not set |
| 199 | # CONFIG_BF548_ATAPI_ALTERNATIVE_PORT is not set | ||
| 199 | 200 | ||
| 200 | # | 201 | # |
| 201 | # Interrupt Priority Assignment | 202 | # Interrupt Priority Assignment |
| @@ -298,7 +299,10 @@ CONFIG_HZ=250 | |||
| 298 | # CONFIG_SCHED_HRTICK is not set | 299 | # CONFIG_SCHED_HRTICK is not set |
| 299 | CONFIG_GENERIC_TIME=y | 300 | CONFIG_GENERIC_TIME=y |
| 300 | CONFIG_GENERIC_CLOCKEVENTS=y | 301 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 302 | # CONFIG_TICKSOURCE_GPTMR0 is not set | ||
| 303 | CONFIG_TICKSOURCE_CORETMR=y | ||
| 301 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 304 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 305 | # CONFIG_GPTMR0_CLOCKSOURCE is not set | ||
| 302 | # CONFIG_NO_HZ is not set | 306 | # CONFIG_NO_HZ is not set |
| 303 | # CONFIG_HIGH_RES_TIMERS is not set | 307 | # CONFIG_HIGH_RES_TIMERS is not set |
| 304 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 308 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| @@ -367,7 +371,9 @@ CONFIG_BFIN_DCACHE=y | |||
| 367 | # CONFIG_BFIN_ICACHE_LOCK is not set | 371 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 368 | CONFIG_BFIN_WB=y | 372 | CONFIG_BFIN_WB=y |
| 369 | # CONFIG_BFIN_WT is not set | 373 | # CONFIG_BFIN_WT is not set |
| 370 | # CONFIG_BFIN_L2_CACHEABLE is not set | 374 | # CONFIG_BFIN_L2_WB is not set |
| 375 | CONFIG_BFIN_L2_WT=y | ||
| 376 | # CONFIG_BFIN_L2_NOT_CACHED is not set | ||
| 371 | # CONFIG_MPU is not set | 377 | # CONFIG_MPU is not set |
| 372 | 378 | ||
| 373 | # | 379 | # |
| @@ -447,7 +453,7 @@ CONFIG_IP_PNP=y | |||
| 447 | # CONFIG_NET_IPIP is not set | 453 | # CONFIG_NET_IPIP is not set |
| 448 | # CONFIG_NET_IPGRE is not set | 454 | # CONFIG_NET_IPGRE is not set |
| 449 | # CONFIG_ARPD is not set | 455 | # CONFIG_ARPD is not set |
| 450 | CONFIG_SYN_COOKIES=y | 456 | # CONFIG_SYN_COOKIES is not set |
| 451 | # CONFIG_INET_AH is not set | 457 | # CONFIG_INET_AH is not set |
| 452 | # CONFIG_INET_ESP is not set | 458 | # CONFIG_INET_ESP is not set |
| 453 | # CONFIG_INET_IPCOMP is not set | 459 | # CONFIG_INET_IPCOMP is not set |
| @@ -616,9 +622,7 @@ CONFIG_MTD_RAM=y | |||
| 616 | # | 622 | # |
| 617 | CONFIG_MTD_COMPLEX_MAPPINGS=y | 623 | CONFIG_MTD_COMPLEX_MAPPINGS=y |
| 618 | CONFIG_MTD_PHYSMAP=y | 624 | CONFIG_MTD_PHYSMAP=y |
| 619 | CONFIG_MTD_PHYSMAP_START=0x20000000 | 625 | # CONFIG_MTD_PHYSMAP_COMPAT is not set |
| 620 | CONFIG_MTD_PHYSMAP_LEN=0 | ||
| 621 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 622 | # CONFIG_MTD_GPIO_ADDR is not set | 626 | # CONFIG_MTD_GPIO_ADDR is not set |
| 623 | # CONFIG_MTD_UCLINUX is not set | 627 | # CONFIG_MTD_UCLINUX is not set |
| 624 | # CONFIG_MTD_PLATRAM is not set | 628 | # CONFIG_MTD_PLATRAM is not set |
| @@ -696,7 +700,7 @@ CONFIG_SCSI_DMA=y | |||
| 696 | CONFIG_BLK_DEV_SD=y | 700 | CONFIG_BLK_DEV_SD=y |
| 697 | # CONFIG_CHR_DEV_ST is not set | 701 | # CONFIG_CHR_DEV_ST is not set |
| 698 | # CONFIG_CHR_DEV_OSST is not set | 702 | # CONFIG_CHR_DEV_OSST is not set |
| 699 | CONFIG_BLK_DEV_SR=y | 703 | CONFIG_BLK_DEV_SR=m |
| 700 | # CONFIG_BLK_DEV_SR_VENDOR is not set | 704 | # CONFIG_BLK_DEV_SR_VENDOR is not set |
| 701 | # CONFIG_CHR_DEV_SG is not set | 705 | # CONFIG_CHR_DEV_SG is not set |
| 702 | # CONFIG_CHR_DEV_SCH is not set | 706 | # CONFIG_CHR_DEV_SCH is not set |
| @@ -718,9 +722,7 @@ CONFIG_SCSI_WAIT_SCAN=m | |||
| 718 | # CONFIG_SCSI_ISCSI_ATTRS is not set | 722 | # CONFIG_SCSI_ISCSI_ATTRS is not set |
| 719 | # CONFIG_SCSI_SAS_LIBSAS is not set | 723 | # CONFIG_SCSI_SAS_LIBSAS is not set |
| 720 | # CONFIG_SCSI_SRP_ATTRS is not set | 724 | # CONFIG_SCSI_SRP_ATTRS is not set |
| 721 | CONFIG_SCSI_LOWLEVEL=y | 725 | # CONFIG_SCSI_LOWLEVEL is not set |
| 722 | # CONFIG_ISCSI_TCP is not set | ||
| 723 | # CONFIG_SCSI_DEBUG is not set | ||
| 724 | # CONFIG_SCSI_DH is not set | 726 | # CONFIG_SCSI_DH is not set |
| 725 | CONFIG_ATA=y | 727 | CONFIG_ATA=y |
| 726 | # CONFIG_ATA_NONSTANDARD is not set | 728 | # CONFIG_ATA_NONSTANDARD is not set |
| @@ -752,9 +754,8 @@ CONFIG_SMSC911X=y | |||
| 752 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | 754 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set |
| 753 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | 755 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set |
| 754 | # CONFIG_B44 is not set | 756 | # CONFIG_B44 is not set |
| 755 | CONFIG_NETDEV_1000=y | 757 | # CONFIG_NETDEV_1000 is not set |
| 756 | # CONFIG_AX88180 is not set | 758 | # CONFIG_NETDEV_10000 is not set |
| 757 | CONFIG_NETDEV_10000=y | ||
| 758 | 759 | ||
| 759 | # | 760 | # |
| 760 | # Wireless LAN | 761 | # Wireless LAN |
| @@ -821,11 +822,11 @@ CONFIG_KEYBOARD_BFIN=y | |||
| 821 | # CONFIG_INPUT_JOYSTICK is not set | 822 | # CONFIG_INPUT_JOYSTICK is not set |
| 822 | # CONFIG_INPUT_TABLET is not set | 823 | # CONFIG_INPUT_TABLET is not set |
| 823 | CONFIG_INPUT_TOUCHSCREEN=y | 824 | CONFIG_INPUT_TOUCHSCREEN=y |
| 824 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 825 | CONFIG_TOUCHSCREEN_AD7877=m | 825 | CONFIG_TOUCHSCREEN_AD7877=m |
| 826 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | 826 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set |
| 827 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | 827 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set |
| 828 | # CONFIG_TOUCHSCREEN_AD7879 is not set | 828 | # CONFIG_TOUCHSCREEN_AD7879 is not set |
| 829 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 829 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 830 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 830 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 831 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 831 | # CONFIG_TOUCHSCREEN_ELO is not set | 832 | # CONFIG_TOUCHSCREEN_ELO is not set |
| @@ -858,14 +859,14 @@ CONFIG_INPUT_MISC=y | |||
| 858 | # Character devices | 859 | # Character devices |
| 859 | # | 860 | # |
| 860 | # CONFIG_AD9960 is not set | 861 | # CONFIG_AD9960 is not set |
| 861 | # CONFIG_SPI_ADC_BF533 is not set | 862 | CONFIG_BFIN_DMA_INTERFACE=m |
| 862 | # CONFIG_BF5xx_PPIFCD is not set | 863 | # CONFIG_BFIN_PPI is not set |
| 864 | # CONFIG_BFIN_PPIFCD is not set | ||
| 863 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 865 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 864 | CONFIG_BF5xx_PPI=m | 866 | # CONFIG_BFIN_SPI_ADC is not set |
| 865 | CONFIG_BFIN_SPORT=m | 867 | CONFIG_BFIN_SPORT=m |
| 866 | # CONFIG_BFIN_TIMER_LATENCY is not set | 868 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 867 | # CONFIG_TWI_LCD is not set | 869 | # CONFIG_BFIN_TWI_LCD is not set |
| 868 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 869 | CONFIG_SIMPLE_GPIO=m | 870 | CONFIG_SIMPLE_GPIO=m |
| 870 | CONFIG_VT=y | 871 | CONFIG_VT=y |
| 871 | CONFIG_CONSOLE_TRANSLATIONS=y | 872 | CONFIG_CONSOLE_TRANSLATIONS=y |
| @@ -977,7 +978,30 @@ CONFIG_SPI_BFIN=y | |||
| 977 | # CONFIG_SPI_SPIDEV is not set | 978 | # CONFIG_SPI_SPIDEV is not set |
| 978 | # CONFIG_SPI_TLE62X0 is not set | 979 | # CONFIG_SPI_TLE62X0 is not set |
| 979 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | 980 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 980 | # CONFIG_GPIOLIB is not set | 981 | CONFIG_GPIOLIB=y |
| 982 | # CONFIG_DEBUG_GPIO is not set | ||
| 983 | CONFIG_GPIO_SYSFS=y | ||
| 984 | |||
| 985 | # | ||
| 986 | # Memory mapped GPIO expanders: | ||
| 987 | # | ||
| 988 | |||
| 989 | # | ||
| 990 | # I2C GPIO expanders: | ||
| 991 | # | ||
| 992 | # CONFIG_GPIO_MAX732X is not set | ||
| 993 | # CONFIG_GPIO_PCA953X is not set | ||
| 994 | # CONFIG_GPIO_PCF857X is not set | ||
| 995 | |||
| 996 | # | ||
| 997 | # PCI GPIO expanders: | ||
| 998 | # | ||
| 999 | |||
| 1000 | # | ||
| 1001 | # SPI GPIO expanders: | ||
| 1002 | # | ||
| 1003 | # CONFIG_GPIO_MAX7301 is not set | ||
| 1004 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 981 | # CONFIG_W1 is not set | 1005 | # CONFIG_W1 is not set |
| 982 | # CONFIG_POWER_SUPPLY is not set | 1006 | # CONFIG_POWER_SUPPLY is not set |
| 983 | # CONFIG_HWMON is not set | 1007 | # CONFIG_HWMON is not set |
| @@ -1011,6 +1035,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 1011 | # CONFIG_HTC_PASIC3 is not set | 1035 | # CONFIG_HTC_PASIC3 is not set |
| 1012 | # CONFIG_MFD_TMIO is not set | 1036 | # CONFIG_MFD_TMIO is not set |
| 1013 | # CONFIG_PMIC_DA903X is not set | 1037 | # CONFIG_PMIC_DA903X is not set |
| 1038 | # CONFIG_PMIC_ADP5520 is not set | ||
| 1014 | # CONFIG_MFD_WM8400 is not set | 1039 | # CONFIG_MFD_WM8400 is not set |
| 1015 | # CONFIG_MFD_WM8350_I2C is not set | 1040 | # CONFIG_MFD_WM8350_I2C is not set |
| 1016 | # CONFIG_REGULATOR is not set | 1041 | # CONFIG_REGULATOR is not set |
| @@ -1193,8 +1218,8 @@ CONFIG_USB=y | |||
| 1193 | # | 1218 | # |
| 1194 | # Miscellaneous USB options | 1219 | # Miscellaneous USB options |
| 1195 | # | 1220 | # |
| 1196 | # CONFIG_USB_DEVICEFS is not set | 1221 | CONFIG_USB_DEVICEFS=y |
| 1197 | CONFIG_USB_DEVICE_CLASS=y | 1222 | # CONFIG_USB_DEVICE_CLASS is not set |
| 1198 | # CONFIG_USB_DYNAMIC_MINORS is not set | 1223 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 1199 | # CONFIG_USB_OTG is not set | 1224 | # CONFIG_USB_OTG is not set |
| 1200 | # CONFIG_USB_OTG_WHITELIST is not set | 1225 | # CONFIG_USB_OTG_WHITELIST is not set |
| @@ -1222,10 +1247,10 @@ CONFIG_USB_MUSB_SOC=y | |||
| 1222 | CONFIG_USB_MUSB_HOST=y | 1247 | CONFIG_USB_MUSB_HOST=y |
| 1223 | # CONFIG_USB_MUSB_PERIPHERAL is not set | 1248 | # CONFIG_USB_MUSB_PERIPHERAL is not set |
| 1224 | # CONFIG_USB_MUSB_OTG is not set | 1249 | # CONFIG_USB_MUSB_OTG is not set |
| 1225 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 1226 | CONFIG_USB_MUSB_HDRC_HCD=y | 1250 | CONFIG_USB_MUSB_HDRC_HCD=y |
| 1227 | CONFIG_MUSB_PIO_ONLY=y | 1251 | # CONFIG_MUSB_PIO_ONLY is not set |
| 1228 | CONFIG_MUSB_DMA_POLL=y | 1252 | CONFIG_USB_INVENTRA_DMA=y |
| 1253 | # CONFIG_USB_TI_CPPI_DMA is not set | ||
| 1229 | # CONFIG_USB_MUSB_DEBUG is not set | 1254 | # CONFIG_USB_MUSB_DEBUG is not set |
| 1230 | 1255 | ||
| 1231 | # | 1256 | # |
| @@ -1243,7 +1268,7 @@ CONFIG_MUSB_DMA_POLL=y | |||
| 1243 | # | 1268 | # |
| 1244 | # see USB_STORAGE Help for more information | 1269 | # see USB_STORAGE Help for more information |
| 1245 | # | 1270 | # |
| 1246 | CONFIG_USB_STORAGE=m | 1271 | CONFIG_USB_STORAGE=y |
| 1247 | # CONFIG_USB_STORAGE_DEBUG is not set | 1272 | # CONFIG_USB_STORAGE_DEBUG is not set |
| 1248 | # CONFIG_USB_STORAGE_DATAFAB is not set | 1273 | # CONFIG_USB_STORAGE_DATAFAB is not set |
| 1249 | # CONFIG_USB_STORAGE_FREECOM is not set | 1274 | # CONFIG_USB_STORAGE_FREECOM is not set |
| @@ -1292,33 +1317,10 @@ CONFIG_USB_STORAGE=m | |||
| 1292 | # CONFIG_USB_LD is not set | 1317 | # CONFIG_USB_LD is not set |
| 1293 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1318 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 1294 | # CONFIG_USB_IOWARRIOR is not set | 1319 | # CONFIG_USB_IOWARRIOR is not set |
| 1320 | # CONFIG_USB_TEST is not set | ||
| 1295 | # CONFIG_USB_ISIGHTFW is not set | 1321 | # CONFIG_USB_ISIGHTFW is not set |
| 1296 | # CONFIG_USB_VST is not set | 1322 | # CONFIG_USB_VST is not set |
| 1297 | # CONFIG_USB_GADGET is not set | 1323 | # CONFIG_USB_GADGET is not set |
| 1298 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 1299 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 1300 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 1301 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 1302 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 1303 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1304 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 1305 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 1306 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1307 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1308 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1309 | # CONFIG_USB_GADGET_NET2272 is not set | ||
| 1310 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1311 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1312 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 1313 | # CONFIG_USB_ZERO is not set | ||
| 1314 | # CONFIG_USB_AUDIO is not set | ||
| 1315 | # CONFIG_USB_ETH is not set | ||
| 1316 | # CONFIG_USB_GADGETFS is not set | ||
| 1317 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 1318 | # CONFIG_USB_G_SERIAL is not set | ||
| 1319 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 1320 | # CONFIG_USB_G_PRINTER is not set | ||
| 1321 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 1322 | CONFIG_MMC=y | 1324 | CONFIG_MMC=y |
| 1323 | # CONFIG_MMC_DEBUG is not set | 1325 | # CONFIG_MMC_DEBUG is not set |
| 1324 | # CONFIG_MMC_UNSAFE_RESUME is not set | 1326 | # CONFIG_MMC_UNSAFE_RESUME is not set |
| @@ -1414,13 +1416,8 @@ CONFIG_EXT2_FS=y | |||
| 1414 | CONFIG_EXT2_FS_XATTR=y | 1416 | CONFIG_EXT2_FS_XATTR=y |
| 1415 | # CONFIG_EXT2_FS_POSIX_ACL is not set | 1417 | # CONFIG_EXT2_FS_POSIX_ACL is not set |
| 1416 | # CONFIG_EXT2_FS_SECURITY is not set | 1418 | # CONFIG_EXT2_FS_SECURITY is not set |
| 1417 | CONFIG_EXT3_FS=y | 1419 | # CONFIG_EXT3_FS is not set |
| 1418 | CONFIG_EXT3_FS_XATTR=y | ||
| 1419 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
| 1420 | # CONFIG_EXT3_FS_SECURITY is not set | ||
| 1421 | # CONFIG_EXT4_FS is not set | 1420 | # CONFIG_EXT4_FS is not set |
| 1422 | CONFIG_JBD=y | ||
| 1423 | # CONFIG_JBD_DEBUG is not set | ||
| 1424 | CONFIG_FS_MBCACHE=y | 1421 | CONFIG_FS_MBCACHE=y |
| 1425 | # CONFIG_REISERFS_FS is not set | 1422 | # CONFIG_REISERFS_FS is not set |
| 1426 | # CONFIG_JFS_FS is not set | 1423 | # CONFIG_JFS_FS is not set |
| @@ -1476,16 +1473,6 @@ CONFIG_SYSFS=y | |||
| 1476 | # CONFIG_BEFS_FS is not set | 1473 | # CONFIG_BEFS_FS is not set |
| 1477 | # CONFIG_BFS_FS is not set | 1474 | # CONFIG_BFS_FS is not set |
| 1478 | # CONFIG_EFS_FS is not set | 1475 | # CONFIG_EFS_FS is not set |
| 1479 | CONFIG_YAFFS_FS=m | ||
| 1480 | CONFIG_YAFFS_YAFFS1=y | ||
| 1481 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1482 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1483 | CONFIG_YAFFS_YAFFS2=y | ||
| 1484 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1485 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1486 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1487 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1488 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1489 | CONFIG_JFFS2_FS=m | 1476 | CONFIG_JFFS2_FS=m |
| 1490 | CONFIG_JFFS2_FS_DEBUG=0 | 1477 | CONFIG_JFFS2_FS_DEBUG=0 |
| 1491 | CONFIG_JFFS2_FS_WRITEBUFFER=y | 1478 | CONFIG_JFFS2_FS_WRITEBUFFER=y |
| @@ -1497,6 +1484,16 @@ CONFIG_JFFS2_ZLIB=y | |||
| 1497 | # CONFIG_JFFS2_LZO is not set | 1484 | # CONFIG_JFFS2_LZO is not set |
| 1498 | CONFIG_JFFS2_RTIME=y | 1485 | CONFIG_JFFS2_RTIME=y |
| 1499 | # CONFIG_JFFS2_RUBIN is not set | 1486 | # CONFIG_JFFS2_RUBIN is not set |
| 1487 | CONFIG_YAFFS_FS=m | ||
| 1488 | CONFIG_YAFFS_YAFFS1=y | ||
| 1489 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1490 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1491 | CONFIG_YAFFS_YAFFS2=y | ||
| 1492 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1493 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1494 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1495 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1496 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1500 | # CONFIG_CRAMFS is not set | 1497 | # CONFIG_CRAMFS is not set |
| 1501 | # CONFIG_VXFS_FS is not set | 1498 | # CONFIG_VXFS_FS is not set |
| 1502 | # CONFIG_MINIX_FS is not set | 1499 | # CONFIG_MINIX_FS is not set |
| @@ -1539,63 +1536,47 @@ CONFIG_CIFS=y | |||
| 1539 | # | 1536 | # |
| 1540 | # Partition Types | 1537 | # Partition Types |
| 1541 | # | 1538 | # |
| 1542 | CONFIG_PARTITION_ADVANCED=y | 1539 | # CONFIG_PARTITION_ADVANCED is not set |
| 1543 | # CONFIG_ACORN_PARTITION is not set | ||
| 1544 | # CONFIG_OSF_PARTITION is not set | ||
| 1545 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1546 | # CONFIG_ATARI_PARTITION is not set | ||
| 1547 | # CONFIG_MAC_PARTITION is not set | ||
| 1548 | CONFIG_MSDOS_PARTITION=y | 1540 | CONFIG_MSDOS_PARTITION=y |
| 1549 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1550 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1551 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1552 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1553 | # CONFIG_LDM_PARTITION is not set | ||
| 1554 | # CONFIG_SGI_PARTITION is not set | ||
| 1555 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1556 | # CONFIG_SUN_PARTITION is not set | ||
| 1557 | # CONFIG_KARMA_PARTITION is not set | ||
| 1558 | # CONFIG_EFI_PARTITION is not set | ||
| 1559 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1560 | CONFIG_NLS=y | 1541 | CONFIG_NLS=y |
| 1561 | CONFIG_NLS_DEFAULT="iso8859-1" | 1542 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 1562 | CONFIG_NLS_CODEPAGE_437=m | 1543 | CONFIG_NLS_CODEPAGE_437=m |
| 1563 | CONFIG_NLS_CODEPAGE_737=m | 1544 | # CONFIG_NLS_CODEPAGE_737 is not set |
| 1564 | CONFIG_NLS_CODEPAGE_775=m | 1545 | # CONFIG_NLS_CODEPAGE_775 is not set |
| 1565 | CONFIG_NLS_CODEPAGE_850=m | 1546 | # CONFIG_NLS_CODEPAGE_850 is not set |
| 1566 | CONFIG_NLS_CODEPAGE_852=m | 1547 | # CONFIG_NLS_CODEPAGE_852 is not set |
| 1567 | CONFIG_NLS_CODEPAGE_855=m | 1548 | # CONFIG_NLS_CODEPAGE_855 is not set |
| 1568 | CONFIG_NLS_CODEPAGE_857=m | 1549 | # CONFIG_NLS_CODEPAGE_857 is not set |
| 1569 | CONFIG_NLS_CODEPAGE_860=m | 1550 | # CONFIG_NLS_CODEPAGE_860 is not set |
| 1570 | CONFIG_NLS_CODEPAGE_861=m | 1551 | # CONFIG_NLS_CODEPAGE_861 is not set |
| 1571 | CONFIG_NLS_CODEPAGE_862=m | 1552 | # CONFIG_NLS_CODEPAGE_862 is not set |
| 1572 | CONFIG_NLS_CODEPAGE_863=m | 1553 | # CONFIG_NLS_CODEPAGE_863 is not set |
| 1573 | CONFIG_NLS_CODEPAGE_864=m | 1554 | # CONFIG_NLS_CODEPAGE_864 is not set |
| 1574 | CONFIG_NLS_CODEPAGE_865=m | 1555 | # CONFIG_NLS_CODEPAGE_865 is not set |
| 1575 | CONFIG_NLS_CODEPAGE_866=m | 1556 | # CONFIG_NLS_CODEPAGE_866 is not set |
| 1576 | CONFIG_NLS_CODEPAGE_869=m | 1557 | # CONFIG_NLS_CODEPAGE_869 is not set |
| 1577 | CONFIG_NLS_CODEPAGE_936=m | 1558 | CONFIG_NLS_CODEPAGE_936=m |
| 1578 | CONFIG_NLS_CODEPAGE_950=m | 1559 | # CONFIG_NLS_CODEPAGE_950 is not set |
| 1579 | CONFIG_NLS_CODEPAGE_932=m | 1560 | # CONFIG_NLS_CODEPAGE_932 is not set |
| 1580 | CONFIG_NLS_CODEPAGE_949=m | 1561 | # CONFIG_NLS_CODEPAGE_949 is not set |
| 1581 | CONFIG_NLS_CODEPAGE_874=m | 1562 | # CONFIG_NLS_CODEPAGE_874 is not set |
| 1582 | CONFIG_NLS_ISO8859_8=m | 1563 | # CONFIG_NLS_ISO8859_8 is not set |
| 1583 | CONFIG_NLS_CODEPAGE_1250=m | 1564 | # CONFIG_NLS_CODEPAGE_1250 is not set |
| 1584 | CONFIG_NLS_CODEPAGE_1251=m | 1565 | # CONFIG_NLS_CODEPAGE_1251 is not set |
| 1585 | CONFIG_NLS_ASCII=m | 1566 | # CONFIG_NLS_ASCII is not set |
| 1586 | CONFIG_NLS_ISO8859_1=m | 1567 | CONFIG_NLS_ISO8859_1=m |
| 1587 | CONFIG_NLS_ISO8859_2=m | 1568 | # CONFIG_NLS_ISO8859_2 is not set |
| 1588 | CONFIG_NLS_ISO8859_3=m | 1569 | # CONFIG_NLS_ISO8859_3 is not set |
| 1589 | CONFIG_NLS_ISO8859_4=m | 1570 | # CONFIG_NLS_ISO8859_4 is not set |
| 1590 | CONFIG_NLS_ISO8859_5=m | 1571 | # CONFIG_NLS_ISO8859_5 is not set |
| 1591 | CONFIG_NLS_ISO8859_6=m | 1572 | # CONFIG_NLS_ISO8859_6 is not set |
| 1592 | CONFIG_NLS_ISO8859_7=m | 1573 | # CONFIG_NLS_ISO8859_7 is not set |
| 1593 | CONFIG_NLS_ISO8859_9=m | 1574 | # CONFIG_NLS_ISO8859_9 is not set |
| 1594 | CONFIG_NLS_ISO8859_13=m | 1575 | # CONFIG_NLS_ISO8859_13 is not set |
| 1595 | CONFIG_NLS_ISO8859_14=m | 1576 | # CONFIG_NLS_ISO8859_14 is not set |
| 1596 | CONFIG_NLS_ISO8859_15=m | 1577 | # CONFIG_NLS_ISO8859_15 is not set |
| 1597 | CONFIG_NLS_KOI8_R=m | 1578 | # CONFIG_NLS_KOI8_R is not set |
| 1598 | CONFIG_NLS_KOI8_U=m | 1579 | # CONFIG_NLS_KOI8_U is not set |
| 1599 | CONFIG_NLS_UTF8=m | 1580 | CONFIG_NLS_UTF8=m |
| 1600 | # CONFIG_DLM is not set | 1581 | # CONFIG_DLM is not set |
| 1601 | 1582 | ||
| @@ -1611,7 +1592,7 @@ CONFIG_FRAME_WARN=1024 | |||
| 1611 | CONFIG_DEBUG_FS=y | 1592 | CONFIG_DEBUG_FS=y |
| 1612 | # CONFIG_HEADERS_CHECK is not set | 1593 | # CONFIG_HEADERS_CHECK is not set |
| 1613 | CONFIG_DEBUG_KERNEL=y | 1594 | CONFIG_DEBUG_KERNEL=y |
| 1614 | # CONFIG_DEBUG_SHIRQ is not set | 1595 | CONFIG_DEBUG_SHIRQ=y |
| 1615 | CONFIG_DETECT_SOFTLOCKUP=y | 1596 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1616 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | 1597 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set |
| 1617 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | 1598 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 |
| @@ -1620,8 +1601,6 @@ CONFIG_SCHED_DEBUG=y | |||
| 1620 | # CONFIG_TIMER_STATS is not set | 1601 | # CONFIG_TIMER_STATS is not set |
| 1621 | # CONFIG_DEBUG_OBJECTS is not set | 1602 | # CONFIG_DEBUG_OBJECTS is not set |
| 1622 | # CONFIG_DEBUG_SLAB is not set | 1603 | # CONFIG_DEBUG_SLAB is not set |
| 1623 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1624 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1625 | # CONFIG_DEBUG_SPINLOCK is not set | 1604 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1626 | # CONFIG_DEBUG_MUTEXES is not set | 1605 | # CONFIG_DEBUG_MUTEXES is not set |
| 1627 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1606 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| @@ -1641,7 +1620,6 @@ CONFIG_DEBUG_INFO=y | |||
| 1641 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1620 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1642 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 1621 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
| 1643 | # CONFIG_FAULT_INJECTION is not set | 1622 | # CONFIG_FAULT_INJECTION is not set |
| 1644 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1645 | 1623 | ||
| 1646 | # | 1624 | # |
| 1647 | # Tracers | 1625 | # Tracers |
| @@ -1657,16 +1635,20 @@ CONFIG_HAVE_ARCH_KGDB=y | |||
| 1657 | # CONFIG_DEBUG_STACK_USAGE is not set | 1635 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1658 | CONFIG_DEBUG_VERBOSE=y | 1636 | CONFIG_DEBUG_VERBOSE=y |
| 1659 | CONFIG_DEBUG_MMRS=y | 1637 | CONFIG_DEBUG_MMRS=y |
| 1660 | # CONFIG_DEBUG_HWERR is not set | 1638 | CONFIG_DEBUG_HWERR=y |
| 1661 | # CONFIG_DEBUG_DOUBLEFAULT is not set | 1639 | CONFIG_EXACT_HWERR=y |
| 1640 | CONFIG_DEBUG_DOUBLEFAULT=y | ||
| 1641 | CONFIG_DEBUG_DOUBLEFAULT_PRINT=y | ||
| 1642 | # CONFIG_DEBUG_DOUBLEFAULT_RESET is not set | ||
| 1643 | # CONFIG_DEBUG_ICACHE_CHECK is not set | ||
| 1662 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1644 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1663 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1645 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1664 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1646 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set |
| 1665 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set | 1647 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y |
| 1666 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set | 1648 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set |
| 1667 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 | 1649 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1 |
| 1668 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set | 1650 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set |
| 1669 | # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set | 1651 | CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y |
| 1670 | CONFIG_EARLY_PRINTK=y | 1652 | CONFIG_EARLY_PRINTK=y |
| 1671 | CONFIG_CPLB_INFO=y | 1653 | CONFIG_CPLB_INFO=y |
| 1672 | CONFIG_ACCESS_CHECK=y | 1654 | CONFIG_ACCESS_CHECK=y |
| @@ -1780,7 +1762,6 @@ CONFIG_CRC32=y | |||
| 1780 | # CONFIG_LIBCRC32C is not set | 1762 | # CONFIG_LIBCRC32C is not set |
| 1781 | CONFIG_ZLIB_INFLATE=y | 1763 | CONFIG_ZLIB_INFLATE=y |
| 1782 | CONFIG_ZLIB_DEFLATE=m | 1764 | CONFIG_ZLIB_DEFLATE=m |
| 1783 | CONFIG_PLIST=y | ||
| 1784 | CONFIG_HAS_IOMEM=y | 1765 | CONFIG_HAS_IOMEM=y |
| 1785 | CONFIG_HAS_IOPORT=y | 1766 | CONFIG_HAS_IOPORT=y |
| 1786 | CONFIG_HAS_DMA=y | 1767 | CONFIG_HAS_DMA=y |
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig index 4a6ea8e31df7..dcfbe2e2931e 100644 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT_defconfig | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28.7 | 3 | # Linux kernel version: 2.6.28.10 |
| 4 | # Thu May 21 05:50:01 2009 | ||
| 4 | # | 5 | # |
| 5 | # CONFIG_MMU is not set | 6 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 7 | # CONFIG_FPU is not set |
| @@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 42 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 43 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 44 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 45 | # CONFIG_SYSCTL is not set | 46 | CONFIG_SYSCTL=y |
| 47 | CONFIG_ANON_INODES=y | ||
| 46 | CONFIG_EMBEDDED=y | 48 | CONFIG_EMBEDDED=y |
| 47 | CONFIG_UID16=y | 49 | CONFIG_UID16=y |
| 48 | CONFIG_SYSCTL_SYSCALL=y | 50 | # CONFIG_SYSCTL_SYSCALL is not set |
| 49 | CONFIG_KALLSYMS=y | 51 | CONFIG_KALLSYMS=y |
| 50 | # CONFIG_KALLSYMS_ALL is not set | 52 | # CONFIG_KALLSYMS_ALL is not set |
| 51 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 53 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| @@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y | |||
| 53 | CONFIG_PRINTK=y | 55 | CONFIG_PRINTK=y |
| 54 | CONFIG_BUG=y | 56 | CONFIG_BUG=y |
| 55 | # CONFIG_ELF_CORE is not set | 57 | # CONFIG_ELF_CORE is not set |
| 56 | CONFIG_COMPAT_BRK=y | ||
| 57 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 58 | # CONFIG_FUTEX is not set | 59 | # CONFIG_FUTEX is not set |
| 59 | CONFIG_ANON_INODES=y | ||
| 60 | CONFIG_EPOLL=y | 60 | CONFIG_EPOLL=y |
| 61 | CONFIG_SIGNALFD=y | 61 | # CONFIG_SIGNALFD is not set |
| 62 | CONFIG_TIMERFD=y | 62 | # CONFIG_TIMERFD is not set |
| 63 | CONFIG_EVENTFD=y | 63 | # CONFIG_EVENTFD is not set |
| 64 | # CONFIG_AIO is not set | 64 | # CONFIG_AIO is not set |
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 65 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_COMPAT_BRK=y | ||
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| @@ -71,7 +72,6 @@ CONFIG_SLAB=y | |||
| 71 | CONFIG_HAVE_OPROFILE=y | 72 | CONFIG_HAVE_OPROFILE=y |
| 72 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 73 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 74 | CONFIG_RT_MUTEXES=y | ||
| 75 | CONFIG_TINY_SHMEM=y | 75 | CONFIG_TINY_SHMEM=y |
| 76 | CONFIG_BASE_SMALL=0 | 76 | CONFIG_BASE_SMALL=0 |
| 77 | CONFIG_MODULES=y | 77 | CONFIG_MODULES=y |
| @@ -148,9 +148,9 @@ CONFIG_BF_REV_MAX=5 | |||
| 148 | # CONFIG_BF_REV_0_0 is not set | 148 | # CONFIG_BF_REV_0_0 is not set |
| 149 | # CONFIG_BF_REV_0_1 is not set | 149 | # CONFIG_BF_REV_0_1 is not set |
| 150 | # CONFIG_BF_REV_0_2 is not set | 150 | # CONFIG_BF_REV_0_2 is not set |
| 151 | CONFIG_BF_REV_0_3=y | 151 | # CONFIG_BF_REV_0_3 is not set |
| 152 | # CONFIG_BF_REV_0_4 is not set | 152 | # CONFIG_BF_REV_0_4 is not set |
| 153 | # CONFIG_BF_REV_0_5 is not set | 153 | CONFIG_BF_REV_0_5=y |
| 154 | # CONFIG_BF_REV_0_6 is not set | 154 | # CONFIG_BF_REV_0_6 is not set |
| 155 | # CONFIG_BF_REV_ANY is not set | 155 | # CONFIG_BF_REV_ANY is not set |
| 156 | # CONFIG_BF_REV_NONE is not set | 156 | # CONFIG_BF_REV_NONE is not set |
| @@ -179,7 +179,6 @@ CONFIG_BFIN561_EZKIT=y | |||
| 179 | # Core B Support | 179 | # Core B Support |
| 180 | # | 180 | # |
| 181 | CONFIG_BF561_COREB=y | 181 | CONFIG_BF561_COREB=y |
| 182 | CONFIG_BF561_COREB_RESET=y | ||
| 183 | 182 | ||
| 184 | # | 183 | # |
| 185 | # Interrupt Priority Assignment | 184 | # Interrupt Priority Assignment |
| @@ -264,7 +263,10 @@ CONFIG_HZ=250 | |||
| 264 | CONFIG_SCHED_HRTICK=y | 263 | CONFIG_SCHED_HRTICK=y |
| 265 | CONFIG_GENERIC_TIME=y | 264 | CONFIG_GENERIC_TIME=y |
| 266 | CONFIG_GENERIC_CLOCKEVENTS=y | 265 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 266 | # CONFIG_TICKSOURCE_GPTMR0 is not set | ||
| 267 | CONFIG_TICKSOURCE_CORETMR=y | ||
| 267 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 268 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 269 | # CONFIG_GPTMR0_CLOCKSOURCE is not set | ||
| 268 | CONFIG_TICK_ONESHOT=y | 270 | CONFIG_TICK_ONESHOT=y |
| 269 | # CONFIG_NO_HZ is not set | 271 | # CONFIG_NO_HZ is not set |
| 270 | CONFIG_HIGH_RES_TIMERS=y | 272 | CONFIG_HIGH_RES_TIMERS=y |
| @@ -334,7 +336,9 @@ CONFIG_BFIN_DCACHE=y | |||
| 334 | # CONFIG_BFIN_ICACHE_LOCK is not set | 336 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 335 | CONFIG_BFIN_WB=y | 337 | CONFIG_BFIN_WB=y |
| 336 | # CONFIG_BFIN_WT is not set | 338 | # CONFIG_BFIN_WT is not set |
| 337 | # CONFIG_BFIN_L2_CACHEABLE is not set | 339 | # CONFIG_BFIN_L2_WB is not set |
| 340 | CONFIG_BFIN_L2_WT=y | ||
| 341 | # CONFIG_BFIN_L2_NOT_CACHED is not set | ||
| 338 | # CONFIG_MPU is not set | 342 | # CONFIG_MPU is not set |
| 339 | 343 | ||
| 340 | # | 344 | # |
| @@ -415,7 +419,7 @@ CONFIG_IP_PNP=y | |||
| 415 | # CONFIG_NET_IPIP is not set | 419 | # CONFIG_NET_IPIP is not set |
| 416 | # CONFIG_NET_IPGRE is not set | 420 | # CONFIG_NET_IPGRE is not set |
| 417 | # CONFIG_ARPD is not set | 421 | # CONFIG_ARPD is not set |
| 418 | CONFIG_SYN_COOKIES=y | 422 | # CONFIG_SYN_COOKIES is not set |
| 419 | # CONFIG_INET_AH is not set | 423 | # CONFIG_INET_AH is not set |
| 420 | # CONFIG_INET_ESP is not set | 424 | # CONFIG_INET_ESP is not set |
| 421 | # CONFIG_INET_IPCOMP is not set | 425 | # CONFIG_INET_IPCOMP is not set |
| @@ -570,9 +574,7 @@ CONFIG_MTD_ROM=m | |||
| 570 | # | 574 | # |
| 571 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 575 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 572 | CONFIG_MTD_PHYSMAP=m | 576 | CONFIG_MTD_PHYSMAP=m |
| 573 | CONFIG_MTD_PHYSMAP_START=0x20000000 | 577 | # CONFIG_MTD_PHYSMAP_COMPAT is not set |
| 574 | CONFIG_MTD_PHYSMAP_LEN=0x0 | ||
| 575 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 576 | # CONFIG_MTD_UCLINUX is not set | 578 | # CONFIG_MTD_UCLINUX is not set |
| 577 | # CONFIG_MTD_PLATRAM is not set | 579 | # CONFIG_MTD_PLATRAM is not set |
| 578 | 580 | ||
| @@ -649,9 +651,8 @@ CONFIG_SMC91X=y | |||
| 649 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | 651 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set |
| 650 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | 652 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set |
| 651 | # CONFIG_B44 is not set | 653 | # CONFIG_B44 is not set |
| 652 | CONFIG_NETDEV_1000=y | 654 | # CONFIG_NETDEV_1000 is not set |
| 653 | # CONFIG_AX88180 is not set | 655 | # CONFIG_NETDEV_10000 is not set |
| 654 | CONFIG_NETDEV_10000=y | ||
| 655 | 656 | ||
| 656 | # | 657 | # |
| 657 | # Wireless LAN | 658 | # Wireless LAN |
| @@ -703,13 +704,13 @@ CONFIG_INPUT_EVDEV=m | |||
| 703 | # Character devices | 704 | # Character devices |
| 704 | # | 705 | # |
| 705 | # CONFIG_AD9960 is not set | 706 | # CONFIG_AD9960 is not set |
| 706 | # CONFIG_SPI_ADC_BF533 is not set | 707 | CONFIG_BFIN_DMA_INTERFACE=m |
| 707 | # CONFIG_BF5xx_PPIFCD is not set | 708 | # CONFIG_BFIN_PPI is not set |
| 709 | # CONFIG_BFIN_PPIFCD is not set | ||
| 708 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 710 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 709 | # CONFIG_BF5xx_PPI is not set | 711 | # CONFIG_BFIN_SPI_ADC is not set |
| 710 | # CONFIG_BFIN_SPORT is not set | 712 | # CONFIG_BFIN_SPORT is not set |
| 711 | # CONFIG_BFIN_TIMER_LATENCY is not set | 713 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 712 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 713 | CONFIG_SIMPLE_GPIO=m | 714 | CONFIG_SIMPLE_GPIO=m |
| 714 | # CONFIG_VT is not set | 715 | # CONFIG_VT is not set |
| 715 | # CONFIG_DEVKMEM is not set | 716 | # CONFIG_DEVKMEM is not set |
| @@ -765,7 +766,30 @@ CONFIG_SPI_BFIN=y | |||
| 765 | # CONFIG_SPI_SPIDEV is not set | 766 | # CONFIG_SPI_SPIDEV is not set |
| 766 | # CONFIG_SPI_TLE62X0 is not set | 767 | # CONFIG_SPI_TLE62X0 is not set |
| 767 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | 768 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 768 | # CONFIG_GPIOLIB is not set | 769 | CONFIG_GPIOLIB=y |
| 770 | # CONFIG_DEBUG_GPIO is not set | ||
| 771 | CONFIG_GPIO_SYSFS=y | ||
| 772 | |||
| 773 | # | ||
| 774 | # Memory mapped GPIO expanders: | ||
| 775 | # | ||
| 776 | |||
| 777 | # | ||
| 778 | # I2C GPIO expanders: | ||
| 779 | # | ||
| 780 | # CONFIG_GPIO_MAX732X is not set | ||
| 781 | # CONFIG_GPIO_PCA953X is not set | ||
| 782 | # CONFIG_GPIO_PCF857X is not set | ||
| 783 | |||
| 784 | # | ||
| 785 | # PCI GPIO expanders: | ||
| 786 | # | ||
| 787 | |||
| 788 | # | ||
| 789 | # SPI GPIO expanders: | ||
| 790 | # | ||
| 791 | # CONFIG_GPIO_MAX7301 is not set | ||
| 792 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 769 | # CONFIG_W1 is not set | 793 | # CONFIG_W1 is not set |
| 770 | # CONFIG_POWER_SUPPLY is not set | 794 | # CONFIG_POWER_SUPPLY is not set |
| 771 | # CONFIG_HWMON is not set | 795 | # CONFIG_HWMON is not set |
| @@ -897,16 +921,6 @@ CONFIG_SYSFS=y | |||
| 897 | # CONFIG_BEFS_FS is not set | 921 | # CONFIG_BEFS_FS is not set |
| 898 | # CONFIG_BFS_FS is not set | 922 | # CONFIG_BFS_FS is not set |
| 899 | # CONFIG_EFS_FS is not set | 923 | # CONFIG_EFS_FS is not set |
| 900 | CONFIG_YAFFS_FS=m | ||
| 901 | CONFIG_YAFFS_YAFFS1=y | ||
| 902 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 903 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 904 | CONFIG_YAFFS_YAFFS2=y | ||
| 905 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 906 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 907 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 908 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 909 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 910 | CONFIG_JFFS2_FS=m | 924 | CONFIG_JFFS2_FS=m |
| 911 | CONFIG_JFFS2_FS_DEBUG=0 | 925 | CONFIG_JFFS2_FS_DEBUG=0 |
| 912 | CONFIG_JFFS2_FS_WRITEBUFFER=y | 926 | CONFIG_JFFS2_FS_WRITEBUFFER=y |
| @@ -918,6 +932,16 @@ CONFIG_JFFS2_ZLIB=y | |||
| 918 | # CONFIG_JFFS2_LZO is not set | 932 | # CONFIG_JFFS2_LZO is not set |
| 919 | CONFIG_JFFS2_RTIME=y | 933 | CONFIG_JFFS2_RTIME=y |
| 920 | # CONFIG_JFFS2_RUBIN is not set | 934 | # CONFIG_JFFS2_RUBIN is not set |
| 935 | CONFIG_YAFFS_FS=m | ||
| 936 | CONFIG_YAFFS_YAFFS1=y | ||
| 937 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 938 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 939 | CONFIG_YAFFS_YAFFS2=y | ||
| 940 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 941 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 942 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 943 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 944 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 921 | # CONFIG_CRAMFS is not set | 945 | # CONFIG_CRAMFS is not set |
| 922 | # CONFIG_VXFS_FS is not set | 946 | # CONFIG_VXFS_FS is not set |
| 923 | # CONFIG_MINIX_FS is not set | 947 | # CONFIG_MINIX_FS is not set |
| @@ -1006,7 +1030,7 @@ CONFIG_FRAME_WARN=1024 | |||
| 1006 | CONFIG_DEBUG_FS=y | 1030 | CONFIG_DEBUG_FS=y |
| 1007 | # CONFIG_HEADERS_CHECK is not set | 1031 | # CONFIG_HEADERS_CHECK is not set |
| 1008 | CONFIG_DEBUG_KERNEL=y | 1032 | CONFIG_DEBUG_KERNEL=y |
| 1009 | # CONFIG_DEBUG_SHIRQ is not set | 1033 | CONFIG_DEBUG_SHIRQ=y |
| 1010 | CONFIG_DETECT_SOFTLOCKUP=y | 1034 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1011 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | 1035 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set |
| 1012 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | 1036 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 |
| @@ -1015,8 +1039,6 @@ CONFIG_SCHED_DEBUG=y | |||
| 1015 | # CONFIG_TIMER_STATS is not set | 1039 | # CONFIG_TIMER_STATS is not set |
| 1016 | # CONFIG_DEBUG_OBJECTS is not set | 1040 | # CONFIG_DEBUG_OBJECTS is not set |
| 1017 | # CONFIG_DEBUG_SLAB is not set | 1041 | # CONFIG_DEBUG_SLAB is not set |
| 1018 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1019 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1020 | # CONFIG_DEBUG_SPINLOCK is not set | 1042 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1021 | # CONFIG_DEBUG_MUTEXES is not set | 1043 | # CONFIG_DEBUG_MUTEXES is not set |
| 1022 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1044 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| @@ -1036,7 +1058,6 @@ CONFIG_DEBUG_INFO=y | |||
| 1036 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1058 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1037 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 1059 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
| 1038 | # CONFIG_FAULT_INJECTION is not set | 1060 | # CONFIG_FAULT_INJECTION is not set |
| 1039 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1040 | 1061 | ||
| 1041 | # | 1062 | # |
| 1042 | # Tracers | 1063 | # Tracers |
| @@ -1052,16 +1073,20 @@ CONFIG_HAVE_ARCH_KGDB=y | |||
| 1052 | # CONFIG_DEBUG_STACK_USAGE is not set | 1073 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1053 | CONFIG_DEBUG_VERBOSE=y | 1074 | CONFIG_DEBUG_VERBOSE=y |
| 1054 | CONFIG_DEBUG_MMRS=y | 1075 | CONFIG_DEBUG_MMRS=y |
| 1055 | # CONFIG_DEBUG_HWERR is not set | 1076 | CONFIG_DEBUG_HWERR=y |
| 1056 | # CONFIG_DEBUG_DOUBLEFAULT is not set | 1077 | CONFIG_EXACT_HWERR=y |
| 1078 | CONFIG_DEBUG_DOUBLEFAULT=y | ||
| 1079 | CONFIG_DEBUG_DOUBLEFAULT_PRINT=y | ||
| 1080 | # CONFIG_DEBUG_DOUBLEFAULT_RESET is not set | ||
| 1081 | # CONFIG_DEBUG_ICACHE_CHECK is not set | ||
| 1057 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1082 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1058 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1083 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1059 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1084 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set |
| 1060 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set | 1085 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y |
| 1061 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set | 1086 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set |
| 1062 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 | 1087 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1 |
| 1063 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set | 1088 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set |
| 1064 | # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set | 1089 | CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y |
| 1065 | CONFIG_EARLY_PRINTK=y | 1090 | CONFIG_EARLY_PRINTK=y |
| 1066 | CONFIG_CPLB_INFO=y | 1091 | CONFIG_CPLB_INFO=y |
| 1067 | CONFIG_ACCESS_CHECK=y | 1092 | CONFIG_ACCESS_CHECK=y |
| @@ -1174,7 +1199,6 @@ CONFIG_CRC32=y | |||
| 1174 | # CONFIG_LIBCRC32C is not set | 1199 | # CONFIG_LIBCRC32C is not set |
| 1175 | CONFIG_ZLIB_INFLATE=y | 1200 | CONFIG_ZLIB_INFLATE=y |
| 1176 | CONFIG_ZLIB_DEFLATE=m | 1201 | CONFIG_ZLIB_DEFLATE=m |
| 1177 | CONFIG_PLIST=y | ||
| 1178 | CONFIG_HAS_IOMEM=y | 1202 | CONFIG_HAS_IOMEM=y |
| 1179 | CONFIG_HAS_IOPORT=y | 1203 | CONFIG_HAS_IOPORT=y |
| 1180 | CONFIG_HAS_DMA=y | 1204 | CONFIG_HAS_DMA=y |
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig index ef1a2c84ace1..174c578b8ec4 100644 --- a/arch/blackfin/configs/BlackStamp_defconfig +++ b/arch/blackfin/configs/BlackStamp_defconfig | |||
| @@ -46,7 +46,7 @@ CONFIG_INITRAMFS_SOURCE="" | |||
| 46 | # CONFIG_SYSCTL is not set | 46 | # CONFIG_SYSCTL is not set |
| 47 | CONFIG_EMBEDDED=y | 47 | CONFIG_EMBEDDED=y |
| 48 | CONFIG_UID16=y | 48 | CONFIG_UID16=y |
| 49 | CONFIG_SYSCTL_SYSCALL=y | 49 | # CONFIG_SYSCTL_SYSCALL is not set |
| 50 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 50 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 51 | CONFIG_KALLSYMS=y | 51 | CONFIG_KALLSYMS=y |
| 52 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 52 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| @@ -381,7 +381,7 @@ CONFIG_IP_PNP=y | |||
| 381 | # CONFIG_NET_IPIP is not set | 381 | # CONFIG_NET_IPIP is not set |
| 382 | # CONFIG_NET_IPGRE is not set | 382 | # CONFIG_NET_IPGRE is not set |
| 383 | # CONFIG_ARPD is not set | 383 | # CONFIG_ARPD is not set |
| 384 | CONFIG_SYN_COOKIES=y | 384 | # CONFIG_SYN_COOKIES is not set |
| 385 | # CONFIG_INET_AH is not set | 385 | # CONFIG_INET_AH is not set |
| 386 | # CONFIG_INET_ESP is not set | 386 | # CONFIG_INET_ESP is not set |
| 387 | # CONFIG_INET_IPCOMP is not set | 387 | # CONFIG_INET_IPCOMP is not set |
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig index e2fc588e4336..e17875e8abe8 100644 --- a/arch/blackfin/configs/CM-BF527_defconfig +++ b/arch/blackfin/configs/CM-BF527_defconfig | |||
| @@ -46,7 +46,7 @@ CONFIG_INITRAMFS_SOURCE="" | |||
| 46 | # CONFIG_SYSCTL is not set | 46 | # CONFIG_SYSCTL is not set |
| 47 | CONFIG_EMBEDDED=y | 47 | CONFIG_EMBEDDED=y |
| 48 | CONFIG_UID16=y | 48 | CONFIG_UID16=y |
| 49 | CONFIG_SYSCTL_SYSCALL=y | 49 | # CONFIG_SYSCTL_SYSCALL is not set |
| 50 | CONFIG_KALLSYMS=y | 50 | CONFIG_KALLSYMS=y |
| 51 | # CONFIG_KALLSYMS_ALL is not set | 51 | # CONFIG_KALLSYMS_ALL is not set |
| 52 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 52 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| @@ -411,7 +411,7 @@ CONFIG_IP_PNP=y | |||
| 411 | # CONFIG_NET_IPIP is not set | 411 | # CONFIG_NET_IPIP is not set |
| 412 | # CONFIG_NET_IPGRE is not set | 412 | # CONFIG_NET_IPGRE is not set |
| 413 | # CONFIG_ARPD is not set | 413 | # CONFIG_ARPD is not set |
| 414 | CONFIG_SYN_COOKIES=y | 414 | # CONFIG_SYN_COOKIES is not set |
| 415 | # CONFIG_INET_AH is not set | 415 | # CONFIG_INET_AH is not set |
| 416 | # CONFIG_INET_ESP is not set | 416 | # CONFIG_INET_ESP is not set |
| 417 | # CONFIG_INET_IPCOMP is not set | 417 | # CONFIG_INET_IPCOMP is not set |
| @@ -783,7 +783,30 @@ CONFIG_SPI_BFIN=y | |||
| 783 | # CONFIG_SPI_SPIDEV is not set | 783 | # CONFIG_SPI_SPIDEV is not set |
| 784 | # CONFIG_SPI_TLE62X0 is not set | 784 | # CONFIG_SPI_TLE62X0 is not set |
| 785 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | 785 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 786 | # CONFIG_GPIOLIB is not set | 786 | CONFIG_GPIOLIB=y |
| 787 | # CONFIG_DEBUG_GPIO is not set | ||
| 788 | CONFIG_GPIO_SYSFS=y | ||
| 789 | |||
| 790 | # | ||
| 791 | # Memory mapped GPIO expanders: | ||
| 792 | # | ||
| 793 | |||
| 794 | # | ||
| 795 | # I2C GPIO expanders: | ||
| 796 | # | ||
| 797 | # CONFIG_GPIO_MAX732X is not set | ||
| 798 | # CONFIG_GPIO_PCA953X is not set | ||
| 799 | # CONFIG_GPIO_PCF857X is not set | ||
| 800 | |||
| 801 | # | ||
| 802 | # PCI GPIO expanders: | ||
| 803 | # | ||
| 804 | |||
| 805 | # | ||
| 806 | # SPI GPIO expanders: | ||
| 807 | # | ||
| 808 | # CONFIG_GPIO_MAX7301 is not set | ||
| 809 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 787 | # CONFIG_W1 is not set | 810 | # CONFIG_W1 is not set |
| 788 | # CONFIG_POWER_SUPPLY is not set | 811 | # CONFIG_POWER_SUPPLY is not set |
| 789 | CONFIG_HWMON=y | 812 | CONFIG_HWMON=y |
diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig index 65a8bbb8d647..fafd95e84b28 100644 --- a/arch/blackfin/configs/CM-BF533_defconfig +++ b/arch/blackfin/configs/CM-BF533_defconfig | |||
| @@ -49,7 +49,7 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 49 | # CONFIG_SYSCTL is not set | 49 | # CONFIG_SYSCTL is not set |
| 50 | CONFIG_EMBEDDED=y | 50 | CONFIG_EMBEDDED=y |
| 51 | # CONFIG_UID16 is not set | 51 | # CONFIG_UID16 is not set |
| 52 | CONFIG_SYSCTL_SYSCALL=y | 52 | # CONFIG_SYSCTL_SYSCALL is not set |
| 53 | CONFIG_KALLSYMS=y | 53 | CONFIG_KALLSYMS=y |
| 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 55 | # CONFIG_HOTPLUG is not set | 55 | # CONFIG_HOTPLUG is not set |
| @@ -347,7 +347,7 @@ CONFIG_IP_FIB_HASH=y | |||
| 347 | # CONFIG_NET_IPIP is not set | 347 | # CONFIG_NET_IPIP is not set |
| 348 | # CONFIG_NET_IPGRE is not set | 348 | # CONFIG_NET_IPGRE is not set |
| 349 | # CONFIG_ARPD is not set | 349 | # CONFIG_ARPD is not set |
| 350 | CONFIG_SYN_COOKIES=y | 350 | # CONFIG_SYN_COOKIES is not set |
| 351 | # CONFIG_INET_AH is not set | 351 | # CONFIG_INET_AH is not set |
| 352 | # CONFIG_INET_ESP is not set | 352 | # CONFIG_INET_ESP is not set |
| 353 | # CONFIG_INET_IPCOMP is not set | 353 | # CONFIG_INET_IPCOMP is not set |
| @@ -547,9 +547,9 @@ CONFIG_MII=y | |||
| 547 | CONFIG_SMC91X=y | 547 | CONFIG_SMC91X=y |
| 548 | # CONFIG_SMSC911X is not set | 548 | # CONFIG_SMSC911X is not set |
| 549 | # CONFIG_DM9000 is not set | 549 | # CONFIG_DM9000 is not set |
| 550 | CONFIG_NETDEV_1000=y | 550 | # CONFIG_NETDEV_1000 is not set |
| 551 | # CONFIG_AX88180 is not set | 551 | # CONFIG_AX88180 is not set |
| 552 | CONFIG_NETDEV_10000=y | 552 | # CONFIG_NETDEV_10000 is not set |
| 553 | 553 | ||
| 554 | # | 554 | # |
| 555 | # Wireless LAN | 555 | # Wireless LAN |
| @@ -641,6 +641,10 @@ CONFIG_UNIX98_PTYS=y | |||
| 641 | # CONFIG_TCG_TPM is not set | 641 | # CONFIG_TCG_TPM is not set |
| 642 | # CONFIG_I2C is not set | 642 | # CONFIG_I2C is not set |
| 643 | 643 | ||
| 644 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 645 | CONFIG_GPIOLIB=y | ||
| 646 | CONFIG_GPIO_SYSFS=y | ||
| 647 | |||
| 644 | # | 648 | # |
| 645 | # SPI support | 649 | # SPI support |
| 646 | # | 650 | # |
diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig index 9b7e9d781145..e73aa5af58b9 100644 --- a/arch/blackfin/configs/CM-BF537E_defconfig +++ b/arch/blackfin/configs/CM-BF537E_defconfig | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.22.16 | 3 | # Linux kernel version: 2.6.28.10 |
| 4 | # Wed Jun 3 06:27:41 2009 | ||
| 4 | # | 5 | # |
| 5 | # CONFIG_MMU is not set | 6 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 7 | # CONFIG_FPU is not set |
| @@ -8,48 +9,44 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set | 9 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set |
| 9 | CONFIG_BLACKFIN=y | 10 | CONFIG_BLACKFIN=y |
| 10 | CONFIG_ZONE_DMA=y | 11 | CONFIG_ZONE_DMA=y |
| 11 | CONFIG_SEMAPHORE_SLEEPERS=y | ||
| 12 | CONFIG_GENERIC_FIND_NEXT_BIT=y | 12 | CONFIG_GENERIC_FIND_NEXT_BIT=y |
| 13 | CONFIG_GENERIC_HWEIGHT=y | 13 | CONFIG_GENERIC_HWEIGHT=y |
| 14 | CONFIG_GENERIC_HARDIRQS=y | 14 | CONFIG_GENERIC_HARDIRQS=y |
| 15 | CONFIG_GENERIC_IRQ_PROBE=y | 15 | CONFIG_GENERIC_IRQ_PROBE=y |
| 16 | CONFIG_GENERIC_TIME=y | ||
| 17 | CONFIG_GENERIC_GPIO=y | 16 | CONFIG_GENERIC_GPIO=y |
| 18 | CONFIG_FORCE_MAX_ZONEORDER=14 | 17 | CONFIG_FORCE_MAX_ZONEORDER=14 |
| 19 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 18 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 20 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 19 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 21 | 20 | ||
| 22 | # | 21 | # |
| 23 | # Code maturity level options | 22 | # General setup |
| 24 | # | 23 | # |
| 25 | CONFIG_EXPERIMENTAL=y | 24 | CONFIG_EXPERIMENTAL=y |
| 26 | CONFIG_BROKEN_ON_SMP=y | 25 | CONFIG_BROKEN_ON_SMP=y |
| 27 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 26 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 28 | |||
| 29 | # | ||
| 30 | # General setup | ||
| 31 | # | ||
| 32 | CONFIG_LOCALVERSION="" | 27 | CONFIG_LOCALVERSION="" |
| 33 | CONFIG_LOCALVERSION_AUTO=y | 28 | CONFIG_LOCALVERSION_AUTO=y |
| 34 | CONFIG_SYSVIPC=y | 29 | CONFIG_SYSVIPC=y |
| 35 | # CONFIG_IPC_NS is not set | ||
| 36 | CONFIG_SYSVIPC_SYSCTL=y | 30 | CONFIG_SYSVIPC_SYSCTL=y |
| 37 | # CONFIG_POSIX_MQUEUE is not set | 31 | # CONFIG_POSIX_MQUEUE is not set |
| 38 | # CONFIG_BSD_PROCESS_ACCT is not set | 32 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 39 | # CONFIG_TASKSTATS is not set | 33 | # CONFIG_TASKSTATS is not set |
| 40 | # CONFIG_UTS_NS is not set | ||
| 41 | # CONFIG_AUDIT is not set | 34 | # CONFIG_AUDIT is not set |
| 42 | CONFIG_IKCONFIG=y | 35 | CONFIG_IKCONFIG=y |
| 43 | CONFIG_IKCONFIG_PROC=y | 36 | CONFIG_IKCONFIG_PROC=y |
| 44 | CONFIG_LOG_BUF_SHIFT=14 | 37 | CONFIG_LOG_BUF_SHIFT=14 |
| 45 | # CONFIG_SYSFS_DEPRECATED is not set | 38 | # CONFIG_CGROUPS is not set |
| 39 | # CONFIG_GROUP_SCHED is not set | ||
| 40 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
| 46 | # CONFIG_RELAY is not set | 41 | # CONFIG_RELAY is not set |
| 42 | # CONFIG_NAMESPACES is not set | ||
| 47 | # CONFIG_BLK_DEV_INITRD is not set | 43 | # CONFIG_BLK_DEV_INITRD is not set |
| 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 44 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 49 | # CONFIG_SYSCTL is not set | 45 | CONFIG_SYSCTL=y |
| 46 | CONFIG_ANON_INODES=y | ||
| 50 | CONFIG_EMBEDDED=y | 47 | CONFIG_EMBEDDED=y |
| 51 | # CONFIG_UID16 is not set | 48 | # CONFIG_UID16 is not set |
| 52 | CONFIG_SYSCTL_SYSCALL=y | 49 | # CONFIG_SYSCTL_SYSCALL is not set |
| 53 | CONFIG_KALLSYMS=y | 50 | CONFIG_KALLSYMS=y |
| 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 51 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 55 | # CONFIG_HOTPLUG is not set | 52 | # CONFIG_HOTPLUG is not set |
| @@ -58,37 +55,36 @@ CONFIG_BUG=y | |||
| 58 | # CONFIG_ELF_CORE is not set | 55 | # CONFIG_ELF_CORE is not set |
| 59 | CONFIG_BASE_FULL=y | 56 | CONFIG_BASE_FULL=y |
| 60 | # CONFIG_FUTEX is not set | 57 | # CONFIG_FUTEX is not set |
| 61 | CONFIG_ANON_INODES=y | ||
| 62 | CONFIG_EPOLL=y | 58 | CONFIG_EPOLL=y |
| 63 | CONFIG_SIGNALFD=y | 59 | # CONFIG_SIGNALFD is not set |
| 64 | CONFIG_EVENTFD=y | 60 | # CONFIG_TIMERFD is not set |
| 61 | # CONFIG_EVENTFD is not set | ||
| 62 | # CONFIG_AIO is not set | ||
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 63 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 | 64 | CONFIG_COMPAT_BRK=y |
| 67 | # CONFIG_NP2 is not set | ||
| 68 | CONFIG_SLAB=y | 65 | CONFIG_SLAB=y |
| 69 | # CONFIG_SLUB is not set | 66 | # CONFIG_SLUB is not set |
| 70 | # CONFIG_SLOB is not set | 67 | # CONFIG_SLOB is not set |
| 71 | CONFIG_RT_MUTEXES=y | 68 | # CONFIG_PROFILING is not set |
| 69 | # CONFIG_MARKERS is not set | ||
| 70 | CONFIG_HAVE_OPROFILE=y | ||
| 71 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 72 | CONFIG_SLABINFO=y | ||
| 72 | CONFIG_TINY_SHMEM=y | 73 | CONFIG_TINY_SHMEM=y |
| 73 | CONFIG_BASE_SMALL=0 | 74 | CONFIG_BASE_SMALL=0 |
| 74 | |||
| 75 | # | ||
| 76 | # Loadable module support | ||
| 77 | # | ||
| 78 | CONFIG_MODULES=y | 75 | CONFIG_MODULES=y |
| 76 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 79 | CONFIG_MODULE_UNLOAD=y | 77 | CONFIG_MODULE_UNLOAD=y |
| 80 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 78 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 81 | # CONFIG_MODVERSIONS is not set | 79 | # CONFIG_MODVERSIONS is not set |
| 82 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 80 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 83 | CONFIG_KMOD=y | 81 | CONFIG_KMOD=y |
| 84 | |||
| 85 | # | ||
| 86 | # Block layer | ||
| 87 | # | ||
| 88 | CONFIG_BLOCK=y | 82 | CONFIG_BLOCK=y |
| 89 | # CONFIG_LBD is not set | 83 | # CONFIG_LBD is not set |
| 90 | # CONFIG_BLK_DEV_IO_TRACE is not set | 84 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 91 | # CONFIG_LSF is not set | 85 | # CONFIG_LSF is not set |
| 86 | # CONFIG_BLK_DEV_BSG is not set | ||
| 87 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 92 | 88 | ||
| 93 | # | 89 | # |
| 94 | # IO Schedulers | 90 | # IO Schedulers |
| @@ -102,9 +98,11 @@ CONFIG_IOSCHED_CFQ=y | |||
| 102 | # CONFIG_DEFAULT_CFQ is not set | 98 | # CONFIG_DEFAULT_CFQ is not set |
| 103 | CONFIG_DEFAULT_NOOP=y | 99 | CONFIG_DEFAULT_NOOP=y |
| 104 | CONFIG_DEFAULT_IOSCHED="noop" | 100 | CONFIG_DEFAULT_IOSCHED="noop" |
| 101 | CONFIG_CLASSIC_RCU=y | ||
| 105 | CONFIG_PREEMPT_NONE=y | 102 | CONFIG_PREEMPT_NONE=y |
| 106 | # CONFIG_PREEMPT_VOLUNTARY is not set | 103 | # CONFIG_PREEMPT_VOLUNTARY is not set |
| 107 | # CONFIG_PREEMPT is not set | 104 | # CONFIG_PREEMPT is not set |
| 105 | # CONFIG_FREEZER is not set | ||
| 108 | 106 | ||
| 109 | # | 107 | # |
| 110 | # Blackfin Processor Options | 108 | # Blackfin Processor Options |
| @@ -113,6 +111,10 @@ CONFIG_PREEMPT_NONE=y | |||
| 113 | # | 111 | # |
| 114 | # Processor and Board Settings | 112 | # Processor and Board Settings |
| 115 | # | 113 | # |
| 114 | # CONFIG_BF512 is not set | ||
| 115 | # CONFIG_BF514 is not set | ||
| 116 | # CONFIG_BF516 is not set | ||
| 117 | # CONFIG_BF518 is not set | ||
| 116 | # CONFIG_BF522 is not set | 118 | # CONFIG_BF522 is not set |
| 117 | # CONFIG_BF523 is not set | 119 | # CONFIG_BF523 is not set |
| 118 | # CONFIG_BF524 is not set | 120 | # CONFIG_BF524 is not set |
| @@ -125,22 +127,31 @@ CONFIG_PREEMPT_NONE=y | |||
| 125 | # CONFIG_BF534 is not set | 127 | # CONFIG_BF534 is not set |
| 126 | # CONFIG_BF536 is not set | 128 | # CONFIG_BF536 is not set |
| 127 | CONFIG_BF537=y | 129 | CONFIG_BF537=y |
| 130 | # CONFIG_BF538 is not set | ||
| 131 | # CONFIG_BF539 is not set | ||
| 128 | # CONFIG_BF542 is not set | 132 | # CONFIG_BF542 is not set |
| 133 | # CONFIG_BF542M is not set | ||
| 129 | # CONFIG_BF544 is not set | 134 | # CONFIG_BF544 is not set |
| 135 | # CONFIG_BF544M is not set | ||
| 130 | # CONFIG_BF547 is not set | 136 | # CONFIG_BF547 is not set |
| 137 | # CONFIG_BF547M is not set | ||
| 131 | # CONFIG_BF548 is not set | 138 | # CONFIG_BF548 is not set |
| 139 | # CONFIG_BF548M is not set | ||
| 132 | # CONFIG_BF549 is not set | 140 | # CONFIG_BF549 is not set |
| 141 | # CONFIG_BF549M is not set | ||
| 133 | # CONFIG_BF561 is not set | 142 | # CONFIG_BF561 is not set |
| 143 | CONFIG_BF_REV_MIN=2 | ||
| 144 | CONFIG_BF_REV_MAX=3 | ||
| 134 | # CONFIG_BF_REV_0_0 is not set | 145 | # CONFIG_BF_REV_0_0 is not set |
| 135 | # CONFIG_BF_REV_0_1 is not set | 146 | # CONFIG_BF_REV_0_1 is not set |
| 136 | CONFIG_BF_REV_0_2=y | 147 | CONFIG_BF_REV_0_2=y |
| 137 | # CONFIG_BF_REV_0_3 is not set | 148 | # CONFIG_BF_REV_0_3 is not set |
| 138 | # CONFIG_BF_REV_0_4 is not set | 149 | # CONFIG_BF_REV_0_4 is not set |
| 139 | # CONFIG_BF_REV_0_5 is not set | 150 | # CONFIG_BF_REV_0_5 is not set |
| 151 | # CONFIG_BF_REV_0_6 is not set | ||
| 140 | # CONFIG_BF_REV_ANY is not set | 152 | # CONFIG_BF_REV_ANY is not set |
| 141 | # CONFIG_BF_REV_NONE is not set | 153 | # CONFIG_BF_REV_NONE is not set |
| 142 | CONFIG_BF53x=y | 154 | CONFIG_BF53x=y |
| 143 | CONFIG_BFIN_SINGLE_CORE=y | ||
| 144 | CONFIG_MEM_MT48LC16M16A2TG_75=y | 155 | CONFIG_MEM_MT48LC16M16A2TG_75=y |
| 145 | CONFIG_IRQ_PLL_WAKEUP=7 | 156 | CONFIG_IRQ_PLL_WAKEUP=7 |
| 146 | CONFIG_IRQ_RTC=8 | 157 | CONFIG_IRQ_RTC=8 |
| @@ -150,7 +161,6 @@ CONFIG_IRQ_SPORT0_TX=9 | |||
| 150 | CONFIG_IRQ_SPORT1_RX=9 | 161 | CONFIG_IRQ_SPORT1_RX=9 |
| 151 | CONFIG_IRQ_SPORT1_TX=9 | 162 | CONFIG_IRQ_SPORT1_TX=9 |
| 152 | CONFIG_IRQ_TWI=10 | 163 | CONFIG_IRQ_TWI=10 |
| 153 | CONFIG_IRQ_SPI=10 | ||
| 154 | CONFIG_IRQ_UART0_RX=10 | 164 | CONFIG_IRQ_UART0_RX=10 |
| 155 | CONFIG_IRQ_UART0_TX=10 | 165 | CONFIG_IRQ_UART0_TX=10 |
| 156 | CONFIG_IRQ_UART1_RX=10 | 166 | CONFIG_IRQ_UART1_RX=10 |
| @@ -169,11 +179,12 @@ CONFIG_IRQ_PORTG_INTB=12 | |||
| 169 | CONFIG_IRQ_MEM_DMA0=13 | 179 | CONFIG_IRQ_MEM_DMA0=13 |
| 170 | CONFIG_IRQ_MEM_DMA1=13 | 180 | CONFIG_IRQ_MEM_DMA1=13 |
| 171 | CONFIG_IRQ_WATCH=13 | 181 | CONFIG_IRQ_WATCH=13 |
| 182 | CONFIG_IRQ_SPI=10 | ||
| 172 | # CONFIG_BFIN537_STAMP is not set | 183 | # CONFIG_BFIN537_STAMP is not set |
| 173 | CONFIG_BFIN537_BLUETECHNIX_CM=y | 184 | CONFIG_BFIN537_BLUETECHNIX_CM=y |
| 185 | # CONFIG_BFIN537_BLUETECHNIX_TCM is not set | ||
| 174 | # CONFIG_PNAV10 is not set | 186 | # CONFIG_PNAV10 is not set |
| 175 | # CONFIG_CAMSIG_MINOTAUR is not set | 187 | # CONFIG_CAMSIG_MINOTAUR is not set |
| 176 | # CONFIG_GENERIC_BF537_BOARD is not set | ||
| 177 | 188 | ||
| 178 | # | 189 | # |
| 179 | # BF537 Specific Configuration | 190 | # BF537 Specific Configuration |
| @@ -196,6 +207,7 @@ CONFIG_IRQ_PROG_INTA=12 | |||
| 196 | # Board customizations | 207 | # Board customizations |
| 197 | # | 208 | # |
| 198 | # CONFIG_CMDLINE_BOOL is not set | 209 | # CONFIG_CMDLINE_BOOL is not set |
| 210 | CONFIG_BOOT_LOAD=0x1000 | ||
| 199 | 211 | ||
| 200 | # | 212 | # |
| 201 | # Clock/PLL Setup | 213 | # Clock/PLL Setup |
| @@ -215,13 +227,20 @@ CONFIG_HZ_250=y | |||
| 215 | # CONFIG_HZ_300 is not set | 227 | # CONFIG_HZ_300 is not set |
| 216 | # CONFIG_HZ_1000 is not set | 228 | # CONFIG_HZ_1000 is not set |
| 217 | CONFIG_HZ=250 | 229 | CONFIG_HZ=250 |
| 230 | # CONFIG_SCHED_HRTICK is not set | ||
| 231 | CONFIG_GENERIC_TIME=y | ||
| 232 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 233 | # CONFIG_TICKSOURCE_GPTMR0 is not set | ||
| 234 | CONFIG_TICKSOURCE_CORETMR=y | ||
| 235 | # CONFIG_CYCLES_CLOCKSOURCE is not set | ||
| 236 | # CONFIG_GPTMR0_CLOCKSOURCE is not set | ||
| 237 | # CONFIG_NO_HZ is not set | ||
| 238 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 239 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 218 | 240 | ||
| 219 | # | 241 | # |
| 220 | # Memory Setup | 242 | # Misc |
| 221 | # | 243 | # |
| 222 | CONFIG_MAX_MEM_SIZE=32 | ||
| 223 | CONFIG_MEM_ADD_WIDTH=9 | ||
| 224 | CONFIG_BOOT_LOAD=0x1000 | ||
| 225 | CONFIG_BFIN_SCRATCH_REG_RETN=y | 244 | CONFIG_BFIN_SCRATCH_REG_RETN=y |
| 226 | # CONFIG_BFIN_SCRATCH_REG_RETE is not set | 245 | # CONFIG_BFIN_SCRATCH_REG_RETE is not set |
| 227 | # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set | 246 | # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set |
| @@ -248,6 +267,12 @@ CONFIG_IP_CHECKSUM_L1=y | |||
| 248 | CONFIG_CACHELINE_ALIGNED_L1=y | 267 | CONFIG_CACHELINE_ALIGNED_L1=y |
| 249 | CONFIG_SYSCALL_TAB_L1=y | 268 | CONFIG_SYSCALL_TAB_L1=y |
| 250 | CONFIG_CPLB_SWITCH_TAB_L1=y | 269 | CONFIG_CPLB_SWITCH_TAB_L1=y |
| 270 | CONFIG_APP_STACK_L1=y | ||
| 271 | |||
| 272 | # | ||
| 273 | # Speed Optimizations | ||
| 274 | # | ||
| 275 | CONFIG_BFIN_INS_LOWOVERHEAD=y | ||
| 251 | CONFIG_RAMKERNEL=y | 276 | CONFIG_RAMKERNEL=y |
| 252 | # CONFIG_ROMKERNEL is not set | 277 | # CONFIG_ROMKERNEL is not set |
| 253 | CONFIG_SELECT_MEMORY_MODEL=y | 278 | CONFIG_SELECT_MEMORY_MODEL=y |
| @@ -256,12 +281,14 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 256 | # CONFIG_SPARSEMEM_MANUAL is not set | 281 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 257 | CONFIG_FLATMEM=y | 282 | CONFIG_FLATMEM=y |
| 258 | CONFIG_FLAT_NODE_MEM_MAP=y | 283 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 259 | # CONFIG_SPARSEMEM_STATIC is not set | 284 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 260 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 285 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 261 | # CONFIG_RESOURCES_64BIT is not set | 286 | # CONFIG_RESOURCES_64BIT is not set |
| 287 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 262 | CONFIG_ZONE_DMA_FLAG=1 | 288 | CONFIG_ZONE_DMA_FLAG=1 |
| 263 | CONFIG_LARGE_ALLOCS=y | 289 | CONFIG_VIRT_TO_BUS=y |
| 264 | # CONFIG_BFIN_GPTIMERS is not set | 290 | # CONFIG_BFIN_GPTIMERS is not set |
| 291 | # CONFIG_DMA_UNCACHED_4M is not set | ||
| 265 | # CONFIG_DMA_UNCACHED_2M is not set | 292 | # CONFIG_DMA_UNCACHED_2M is not set |
| 266 | CONFIG_DMA_UNCACHED_1M=y | 293 | CONFIG_DMA_UNCACHED_1M=y |
| 267 | # CONFIG_DMA_UNCACHED_NONE is not set | 294 | # CONFIG_DMA_UNCACHED_NONE is not set |
| @@ -275,7 +302,6 @@ CONFIG_BFIN_DCACHE=y | |||
| 275 | # CONFIG_BFIN_ICACHE_LOCK is not set | 302 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 276 | CONFIG_BFIN_WB=y | 303 | CONFIG_BFIN_WB=y |
| 277 | # CONFIG_BFIN_WT is not set | 304 | # CONFIG_BFIN_WT is not set |
| 278 | CONFIG_L1_MAX_PIECE=16 | ||
| 279 | # CONFIG_MPU is not set | 305 | # CONFIG_MPU is not set |
| 280 | 306 | ||
| 281 | # | 307 | # |
| @@ -304,36 +330,28 @@ CONFIG_BANK_3=0xFFC2 | |||
| 304 | # | 330 | # |
| 305 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | 331 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) |
| 306 | # | 332 | # |
| 307 | # CONFIG_PCI is not set | ||
| 308 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 333 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 309 | 334 | ||
| 310 | # | 335 | # |
| 311 | # PCCARD (PCMCIA/CardBus) support | ||
| 312 | # | ||
| 313 | |||
| 314 | # | ||
| 315 | # Executable file formats | 336 | # Executable file formats |
| 316 | # | 337 | # |
| 317 | CONFIG_BINFMT_ELF_FDPIC=y | 338 | CONFIG_BINFMT_ELF_FDPIC=y |
| 318 | CONFIG_BINFMT_FLAT=y | 339 | CONFIG_BINFMT_FLAT=y |
| 319 | CONFIG_BINFMT_ZFLAT=y | 340 | CONFIG_BINFMT_ZFLAT=y |
| 320 | CONFIG_BINFMT_SHARED_FLAT=y | 341 | CONFIG_BINFMT_SHARED_FLAT=y |
| 342 | # CONFIG_HAVE_AOUT is not set | ||
| 321 | # CONFIG_BINFMT_MISC is not set | 343 | # CONFIG_BINFMT_MISC is not set |
| 322 | 344 | ||
| 323 | # | 345 | # |
| 324 | # Power management options | 346 | # Power management options |
| 325 | # | 347 | # |
| 326 | # CONFIG_PM is not set | 348 | # CONFIG_PM is not set |
| 327 | # CONFIG_PM_WAKEUP_BY_GPIO is not set | 349 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 328 | 350 | ||
| 329 | # | 351 | # |
| 330 | # CPU Frequency scaling | 352 | # CPU Frequency scaling |
| 331 | # | 353 | # |
| 332 | # CONFIG_CPU_FREQ is not set | 354 | # CONFIG_CPU_FREQ is not set |
| 333 | |||
| 334 | # | ||
| 335 | # Networking | ||
| 336 | # | ||
| 337 | CONFIG_NET=y | 355 | CONFIG_NET=y |
| 338 | 356 | ||
| 339 | # | 357 | # |
| @@ -346,6 +364,7 @@ CONFIG_XFRM=y | |||
| 346 | # CONFIG_XFRM_USER is not set | 364 | # CONFIG_XFRM_USER is not set |
| 347 | # CONFIG_XFRM_SUB_POLICY is not set | 365 | # CONFIG_XFRM_SUB_POLICY is not set |
| 348 | # CONFIG_XFRM_MIGRATE is not set | 366 | # CONFIG_XFRM_MIGRATE is not set |
| 367 | # CONFIG_XFRM_STATISTICS is not set | ||
| 349 | # CONFIG_NET_KEY is not set | 368 | # CONFIG_NET_KEY is not set |
| 350 | CONFIG_INET=y | 369 | CONFIG_INET=y |
| 351 | # CONFIG_IP_MULTICAST is not set | 370 | # CONFIG_IP_MULTICAST is not set |
| @@ -358,7 +377,7 @@ CONFIG_IP_PNP=y | |||
| 358 | # CONFIG_NET_IPIP is not set | 377 | # CONFIG_NET_IPIP is not set |
| 359 | # CONFIG_NET_IPGRE is not set | 378 | # CONFIG_NET_IPGRE is not set |
| 360 | # CONFIG_ARPD is not set | 379 | # CONFIG_ARPD is not set |
| 361 | CONFIG_SYN_COOKIES=y | 380 | # CONFIG_SYN_COOKIES is not set |
| 362 | # CONFIG_INET_AH is not set | 381 | # CONFIG_INET_AH is not set |
| 363 | # CONFIG_INET_ESP is not set | 382 | # CONFIG_INET_ESP is not set |
| 364 | # CONFIG_INET_IPCOMP is not set | 383 | # CONFIG_INET_IPCOMP is not set |
| @@ -367,6 +386,7 @@ CONFIG_SYN_COOKIES=y | |||
| 367 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 386 | CONFIG_INET_XFRM_MODE_TRANSPORT=y |
| 368 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 387 | CONFIG_INET_XFRM_MODE_TUNNEL=y |
| 369 | CONFIG_INET_XFRM_MODE_BEET=y | 388 | CONFIG_INET_XFRM_MODE_BEET=y |
| 389 | # CONFIG_INET_LRO is not set | ||
| 370 | CONFIG_INET_DIAG=y | 390 | CONFIG_INET_DIAG=y |
| 371 | CONFIG_INET_TCP_DIAG=y | 391 | CONFIG_INET_TCP_DIAG=y |
| 372 | # CONFIG_TCP_CONG_ADVANCED is not set | 392 | # CONFIG_TCP_CONG_ADVANCED is not set |
| @@ -374,8 +394,6 @@ CONFIG_TCP_CONG_CUBIC=y | |||
| 374 | CONFIG_DEFAULT_TCP_CONG="cubic" | 394 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 375 | # CONFIG_TCP_MD5SIG is not set | 395 | # CONFIG_TCP_MD5SIG is not set |
| 376 | # CONFIG_IPV6 is not set | 396 | # CONFIG_IPV6 is not set |
| 377 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 378 | # CONFIG_INET6_TUNNEL is not set | ||
| 379 | # CONFIG_NETLABEL is not set | 397 | # CONFIG_NETLABEL is not set |
| 380 | # CONFIG_NETWORK_SECMARK is not set | 398 | # CONFIG_NETWORK_SECMARK is not set |
| 381 | # CONFIG_NETFILTER is not set | 399 | # CONFIG_NETFILTER is not set |
| @@ -384,6 +402,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 384 | # CONFIG_TIPC is not set | 402 | # CONFIG_TIPC is not set |
| 385 | # CONFIG_ATM is not set | 403 | # CONFIG_ATM is not set |
| 386 | # CONFIG_BRIDGE is not set | 404 | # CONFIG_BRIDGE is not set |
| 405 | # CONFIG_NET_DSA is not set | ||
| 387 | # CONFIG_VLAN_8021Q is not set | 406 | # CONFIG_VLAN_8021Q is not set |
| 388 | # CONFIG_DECNET is not set | 407 | # CONFIG_DECNET is not set |
| 389 | # CONFIG_LLC2 is not set | 408 | # CONFIG_LLC2 is not set |
| @@ -393,10 +412,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 393 | # CONFIG_LAPB is not set | 412 | # CONFIG_LAPB is not set |
| 394 | # CONFIG_ECONET is not set | 413 | # CONFIG_ECONET is not set |
| 395 | # CONFIG_WAN_ROUTER is not set | 414 | # CONFIG_WAN_ROUTER is not set |
| 396 | |||
| 397 | # | ||
| 398 | # QoS and/or fair queueing | ||
| 399 | # | ||
| 400 | # CONFIG_NET_SCHED is not set | 415 | # CONFIG_NET_SCHED is not set |
| 401 | 416 | ||
| 402 | # | 417 | # |
| @@ -404,18 +419,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 404 | # | 419 | # |
| 405 | # CONFIG_NET_PKTGEN is not set | 420 | # CONFIG_NET_PKTGEN is not set |
| 406 | # CONFIG_HAMRADIO is not set | 421 | # CONFIG_HAMRADIO is not set |
| 422 | # CONFIG_CAN is not set | ||
| 407 | # CONFIG_IRDA is not set | 423 | # CONFIG_IRDA is not set |
| 408 | # CONFIG_BT is not set | 424 | # CONFIG_BT is not set |
| 409 | # CONFIG_AF_RXRPC is not set | 425 | # CONFIG_AF_RXRPC is not set |
| 410 | 426 | # CONFIG_PHONET is not set | |
| 411 | # | 427 | # CONFIG_WIRELESS is not set |
| 412 | # Wireless | ||
| 413 | # | ||
| 414 | # CONFIG_CFG80211 is not set | ||
| 415 | # CONFIG_WIRELESS_EXT is not set | ||
| 416 | # CONFIG_MAC80211 is not set | ||
| 417 | # CONFIG_IEEE80211 is not set | ||
| 418 | # CONFIG_RFKILL is not set | 428 | # CONFIG_RFKILL is not set |
| 429 | # CONFIG_NET_9P is not set | ||
| 419 | 430 | ||
| 420 | # | 431 | # |
| 421 | # Device Drivers | 432 | # Device Drivers |
| @@ -427,10 +438,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 427 | CONFIG_STANDALONE=y | 438 | CONFIG_STANDALONE=y |
| 428 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 439 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 429 | # CONFIG_SYS_HYPERVISOR is not set | 440 | # CONFIG_SYS_HYPERVISOR is not set |
| 430 | |||
| 431 | # | ||
| 432 | # Connector - unified userspace <-> kernelspace linker | ||
| 433 | # | ||
| 434 | # CONFIG_CONNECTOR is not set | 441 | # CONFIG_CONNECTOR is not set |
| 435 | CONFIG_MTD=y | 442 | CONFIG_MTD=y |
| 436 | # CONFIG_MTD_DEBUG is not set | 443 | # CONFIG_MTD_DEBUG is not set |
| @@ -438,6 +445,7 @@ CONFIG_MTD=y | |||
| 438 | CONFIG_MTD_PARTITIONS=y | 445 | CONFIG_MTD_PARTITIONS=y |
| 439 | # CONFIG_MTD_REDBOOT_PARTS is not set | 446 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 440 | # CONFIG_MTD_CMDLINE_PARTS is not set | 447 | # CONFIG_MTD_CMDLINE_PARTS is not set |
| 448 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 441 | 449 | ||
| 442 | # | 450 | # |
| 443 | # User Modules And Translation Layers | 451 | # User Modules And Translation Layers |
| @@ -450,12 +458,15 @@ CONFIG_MTD_BLOCK=y | |||
| 450 | # CONFIG_INFTL is not set | 458 | # CONFIG_INFTL is not set |
| 451 | # CONFIG_RFD_FTL is not set | 459 | # CONFIG_RFD_FTL is not set |
| 452 | # CONFIG_SSFDC is not set | 460 | # CONFIG_SSFDC is not set |
| 461 | # CONFIG_MTD_OOPS is not set | ||
| 453 | 462 | ||
| 454 | # | 463 | # |
| 455 | # RAM/ROM/Flash chip drivers | 464 | # RAM/ROM/Flash chip drivers |
| 456 | # | 465 | # |
| 457 | # CONFIG_MTD_CFI is not set | 466 | CONFIG_MTD_CFI=y |
| 458 | # CONFIG_MTD_JEDECPROBE is not set | 467 | # CONFIG_MTD_JEDECPROBE is not set |
| 468 | CONFIG_MTD_GEN_PROBE=y | ||
| 469 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 459 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | 470 | CONFIG_MTD_MAP_BANK_WIDTH_1=y |
| 460 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | 471 | CONFIG_MTD_MAP_BANK_WIDTH_2=y |
| 461 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | 472 | CONFIG_MTD_MAP_BANK_WIDTH_4=y |
| @@ -466,6 +477,10 @@ CONFIG_MTD_CFI_I1=y | |||
| 466 | CONFIG_MTD_CFI_I2=y | 477 | CONFIG_MTD_CFI_I2=y |
| 467 | # CONFIG_MTD_CFI_I4 is not set | 478 | # CONFIG_MTD_CFI_I4 is not set |
| 468 | # CONFIG_MTD_CFI_I8 is not set | 479 | # CONFIG_MTD_CFI_I8 is not set |
| 480 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 481 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 482 | # CONFIG_MTD_CFI_STAA is not set | ||
| 483 | CONFIG_MTD_CFI_UTIL=y | ||
| 469 | CONFIG_MTD_RAM=y | 484 | CONFIG_MTD_RAM=y |
| 470 | # CONFIG_MTD_ROM is not set | 485 | # CONFIG_MTD_ROM is not set |
| 471 | # CONFIG_MTD_ABSENT is not set | 486 | # CONFIG_MTD_ABSENT is not set |
| @@ -473,7 +488,8 @@ CONFIG_MTD_RAM=y | |||
| 473 | # | 488 | # |
| 474 | # Mapping drivers for chip access | 489 | # Mapping drivers for chip access |
| 475 | # | 490 | # |
| 476 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 491 | CONFIG_MTD_COMPLEX_MAPPINGS=y |
| 492 | CONFIG_MTD_GPIO_ADDR=y | ||
| 477 | CONFIG_MTD_UCLINUX=y | 493 | CONFIG_MTD_UCLINUX=y |
| 478 | # CONFIG_MTD_PLATRAM is not set | 494 | # CONFIG_MTD_PLATRAM is not set |
| 479 | 495 | ||
| @@ -498,33 +514,23 @@ CONFIG_MTD_UCLINUX=y | |||
| 498 | # UBI - Unsorted block images | 514 | # UBI - Unsorted block images |
| 499 | # | 515 | # |
| 500 | # CONFIG_MTD_UBI is not set | 516 | # CONFIG_MTD_UBI is not set |
| 501 | |||
| 502 | # | ||
| 503 | # Parallel port support | ||
| 504 | # | ||
| 505 | # CONFIG_PARPORT is not set | 517 | # CONFIG_PARPORT is not set |
| 506 | 518 | CONFIG_BLK_DEV=y | |
| 507 | # | ||
| 508 | # Plug and Play support | ||
| 509 | # | ||
| 510 | # CONFIG_PNPACPI is not set | ||
| 511 | |||
| 512 | # | ||
| 513 | # Block devices | ||
| 514 | # | ||
| 515 | # CONFIG_BLK_DEV_COW_COMMON is not set | 519 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 516 | # CONFIG_BLK_DEV_LOOP is not set | 520 | # CONFIG_BLK_DEV_LOOP is not set |
| 517 | # CONFIG_BLK_DEV_NBD is not set | 521 | # CONFIG_BLK_DEV_NBD is not set |
| 518 | CONFIG_BLK_DEV_RAM=y | 522 | CONFIG_BLK_DEV_RAM=y |
| 519 | CONFIG_BLK_DEV_RAM_COUNT=16 | 523 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 520 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 524 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 521 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 525 | # CONFIG_BLK_DEV_XIP is not set |
| 522 | # CONFIG_CDROM_PKTCDVD is not set | 526 | # CONFIG_CDROM_PKTCDVD is not set |
| 523 | # CONFIG_ATA_OVER_ETH is not set | 527 | # CONFIG_ATA_OVER_ETH is not set |
| 524 | 528 | # CONFIG_BLK_DEV_HD is not set | |
| 525 | # | 529 | CONFIG_MISC_DEVICES=y |
| 526 | # Misc devices | 530 | # CONFIG_EEPROM_93CX6 is not set |
| 527 | # | 531 | # CONFIG_ENCLOSURE_SERVICES is not set |
| 532 | # CONFIG_C2PORT is not set | ||
| 533 | CONFIG_HAVE_IDE=y | ||
| 528 | # CONFIG_IDE is not set | 534 | # CONFIG_IDE is not set |
| 529 | 535 | ||
| 530 | # | 536 | # |
| @@ -532,22 +538,17 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | |||
| 532 | # | 538 | # |
| 533 | # CONFIG_RAID_ATTRS is not set | 539 | # CONFIG_RAID_ATTRS is not set |
| 534 | # CONFIG_SCSI is not set | 540 | # CONFIG_SCSI is not set |
| 541 | # CONFIG_SCSI_DMA is not set | ||
| 535 | # CONFIG_SCSI_NETLINK is not set | 542 | # CONFIG_SCSI_NETLINK is not set |
| 536 | # CONFIG_ATA is not set | 543 | # CONFIG_ATA is not set |
| 537 | |||
| 538 | # | ||
| 539 | # Multi-device support (RAID and LVM) | ||
| 540 | # | ||
| 541 | # CONFIG_MD is not set | 544 | # CONFIG_MD is not set |
| 542 | |||
| 543 | # | ||
| 544 | # Network device support | ||
| 545 | # | ||
| 546 | CONFIG_NETDEVICES=y | 545 | CONFIG_NETDEVICES=y |
| 547 | # CONFIG_DUMMY is not set | 546 | # CONFIG_DUMMY is not set |
| 548 | # CONFIG_BONDING is not set | 547 | # CONFIG_BONDING is not set |
| 548 | # CONFIG_MACVLAN is not set | ||
| 549 | # CONFIG_EQUALIZER is not set | 549 | # CONFIG_EQUALIZER is not set |
| 550 | # CONFIG_TUN is not set | 550 | # CONFIG_TUN is not set |
| 551 | # CONFIG_VETH is not set | ||
| 551 | CONFIG_PHYLIB=y | 552 | CONFIG_PHYLIB=y |
| 552 | 553 | ||
| 553 | # | 554 | # |
| @@ -561,46 +562,44 @@ CONFIG_PHYLIB=y | |||
| 561 | # CONFIG_VITESSE_PHY is not set | 562 | # CONFIG_VITESSE_PHY is not set |
| 562 | # CONFIG_SMSC_PHY is not set | 563 | # CONFIG_SMSC_PHY is not set |
| 563 | # CONFIG_BROADCOM_PHY is not set | 564 | # CONFIG_BROADCOM_PHY is not set |
| 565 | # CONFIG_ICPLUS_PHY is not set | ||
| 566 | # CONFIG_REALTEK_PHY is not set | ||
| 564 | # CONFIG_FIXED_PHY is not set | 567 | # CONFIG_FIXED_PHY is not set |
| 565 | 568 | # CONFIG_MDIO_BITBANG is not set | |
| 566 | # | ||
| 567 | # Ethernet (10 or 100Mbit) | ||
| 568 | # | ||
| 569 | CONFIG_NET_ETHERNET=y | 569 | CONFIG_NET_ETHERNET=y |
| 570 | CONFIG_MII=y | 570 | CONFIG_MII=y |
| 571 | # CONFIG_SMC91X is not set | ||
| 572 | CONFIG_BFIN_MAC=y | 571 | CONFIG_BFIN_MAC=y |
| 573 | CONFIG_BFIN_MAC_USE_L1=y | 572 | CONFIG_BFIN_MAC_USE_L1=y |
| 574 | CONFIG_BFIN_TX_DESC_NUM=10 | 573 | CONFIG_BFIN_TX_DESC_NUM=10 |
| 575 | CONFIG_BFIN_RX_DESC_NUM=20 | 574 | CONFIG_BFIN_RX_DESC_NUM=20 |
| 576 | # CONFIG_BFIN_MAC_RMII is not set | 575 | # CONFIG_BFIN_MAC_RMII is not set |
| 576 | # CONFIG_SMC91X is not set | ||
| 577 | # CONFIG_SMSC911X is not set | 577 | # CONFIG_SMSC911X is not set |
| 578 | # CONFIG_DM9000 is not set | 578 | # CONFIG_DM9000 is not set |
| 579 | CONFIG_NETDEV_1000=y | 579 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| 580 | # CONFIG_AX88180 is not set | 580 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 581 | CONFIG_NETDEV_10000=y | 581 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 582 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 583 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 584 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 585 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 586 | # CONFIG_B44 is not set | ||
| 587 | # CONFIG_NETDEV_1000 is not set | ||
| 588 | # CONFIG_NETDEV_10000 is not set | ||
| 582 | 589 | ||
| 583 | # | 590 | # |
| 584 | # Wireless LAN | 591 | # Wireless LAN |
| 585 | # | 592 | # |
| 586 | # CONFIG_WLAN_PRE80211 is not set | 593 | # CONFIG_WLAN_PRE80211 is not set |
| 587 | # CONFIG_WLAN_80211 is not set | 594 | # CONFIG_WLAN_80211 is not set |
| 595 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 588 | # CONFIG_WAN is not set | 596 | # CONFIG_WAN is not set |
| 589 | # CONFIG_PPP is not set | 597 | # CONFIG_PPP is not set |
| 590 | # CONFIG_SLIP is not set | 598 | # CONFIG_SLIP is not set |
| 591 | # CONFIG_SHAPER is not set | ||
| 592 | # CONFIG_NETCONSOLE is not set | 599 | # CONFIG_NETCONSOLE is not set |
| 593 | # CONFIG_NETPOLL is not set | 600 | # CONFIG_NETPOLL is not set |
| 594 | # CONFIG_NET_POLL_CONTROLLER is not set | 601 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 595 | |||
| 596 | # | ||
| 597 | # ISDN subsystem | ||
| 598 | # | ||
| 599 | # CONFIG_ISDN is not set | 602 | # CONFIG_ISDN is not set |
| 600 | |||
| 601 | # | ||
| 602 | # Telephony Support | ||
| 603 | # | ||
| 604 | # CONFIG_PHONE is not set | 603 | # CONFIG_PHONE is not set |
| 605 | 604 | ||
| 606 | # | 605 | # |
| @@ -618,15 +617,17 @@ CONFIG_NETDEV_10000=y | |||
| 618 | # Character devices | 617 | # Character devices |
| 619 | # | 618 | # |
| 620 | # CONFIG_AD9960 is not set | 619 | # CONFIG_AD9960 is not set |
| 621 | # CONFIG_SPI_ADC_BF533 is not set | 620 | CONFIG_BFIN_DMA_INTERFACE=m |
| 622 | # CONFIG_BF5xx_PFLAGS is not set | 621 | # CONFIG_BFIN_PPI is not set |
| 623 | # CONFIG_BF5xx_PPIFCD is not set | 622 | # CONFIG_BFIN_PPIFCD is not set |
| 624 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 623 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 625 | # CONFIG_BF5xx_PPI is not set | 624 | # CONFIG_BFIN_SPI_ADC is not set |
| 626 | CONFIG_BFIN_SPORT=y | 625 | CONFIG_BFIN_SPORT=y |
| 627 | # CONFIG_BFIN_TIMER_LATENCY is not set | 626 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 627 | # CONFIG_SIMPLE_GPIO is not set | ||
| 628 | # CONFIG_VT is not set | 628 | # CONFIG_VT is not set |
| 629 | # CONFIG_DEVKMEM is not set | 629 | # CONFIG_DEVKMEM is not set |
| 630 | # CONFIG_BFIN_JTAG_COMM is not set | ||
| 630 | # CONFIG_SERIAL_NONSTANDARD is not set | 631 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 631 | 632 | ||
| 632 | # | 633 | # |
| @@ -655,138 +656,119 @@ CONFIG_UNIX98_PTYS=y | |||
| 655 | # CAN, the car bus and industrial fieldbus | 656 | # CAN, the car bus and industrial fieldbus |
| 656 | # | 657 | # |
| 657 | # CONFIG_CAN4LINUX is not set | 658 | # CONFIG_CAN4LINUX is not set |
| 658 | |||
| 659 | # | ||
| 660 | # IPMI | ||
| 661 | # | ||
| 662 | # CONFIG_IPMI_HANDLER is not set | 659 | # CONFIG_IPMI_HANDLER is not set |
| 663 | # CONFIG_WATCHDOG is not set | ||
| 664 | # CONFIG_HW_RANDOM is not set | 660 | # CONFIG_HW_RANDOM is not set |
| 665 | # CONFIG_GEN_RTC is not set | ||
| 666 | # CONFIG_R3964 is not set | 661 | # CONFIG_R3964 is not set |
| 667 | # CONFIG_RAW_DRIVER is not set | 662 | # CONFIG_RAW_DRIVER is not set |
| 663 | # CONFIG_TCG_TPM is not set | ||
| 664 | # CONFIG_I2C is not set | ||
| 665 | # CONFIG_SPI is not set | ||
| 666 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 667 | CONFIG_GPIOLIB=y | ||
| 668 | CONFIG_GPIO_SYSFS=y | ||
| 668 | 669 | ||
| 669 | # | 670 | # |
| 670 | # TPM devices | 671 | # Memory mapped GPIO expanders: |
| 671 | # | 672 | # |
| 672 | # CONFIG_TCG_TPM is not set | ||
| 673 | # CONFIG_I2C is not set | ||
| 674 | 673 | ||
| 675 | # | 674 | # |
| 676 | # SPI support | 675 | # I2C GPIO expanders: |
| 676 | # | ||
| 677 | |||
| 678 | # | ||
| 679 | # PCI GPIO expanders: | ||
| 677 | # | 680 | # |
| 678 | # CONFIG_SPI is not set | ||
| 679 | # CONFIG_SPI_MASTER is not set | ||
| 680 | 681 | ||
| 681 | # | 682 | # |
| 682 | # Dallas's 1-wire bus | 683 | # SPI GPIO expanders: |
| 683 | # | 684 | # |
| 684 | # CONFIG_W1 is not set | 685 | # CONFIG_W1 is not set |
| 686 | # CONFIG_POWER_SUPPLY is not set | ||
| 685 | CONFIG_HWMON=y | 687 | CONFIG_HWMON=y |
| 686 | # CONFIG_HWMON_VID is not set | 688 | # CONFIG_HWMON_VID is not set |
| 687 | # CONFIG_SENSORS_ABITUGURU is not set | ||
| 688 | # CONFIG_SENSORS_F71805F is not set | 689 | # CONFIG_SENSORS_F71805F is not set |
| 690 | # CONFIG_SENSORS_F71882FG is not set | ||
| 691 | # CONFIG_SENSORS_IT87 is not set | ||
| 692 | # CONFIG_SENSORS_PC87360 is not set | ||
| 689 | # CONFIG_SENSORS_PC87427 is not set | 693 | # CONFIG_SENSORS_PC87427 is not set |
| 690 | # CONFIG_SENSORS_SMSC47M1 is not set | 694 | # CONFIG_SENSORS_SMSC47M1 is not set |
| 691 | # CONFIG_SENSORS_SMSC47B397 is not set | 695 | # CONFIG_SENSORS_SMSC47B397 is not set |
| 692 | # CONFIG_SENSORS_VT1211 is not set | 696 | # CONFIG_SENSORS_VT1211 is not set |
| 693 | # CONFIG_SENSORS_W83627HF is not set | 697 | # CONFIG_SENSORS_W83627HF is not set |
| 698 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 694 | # CONFIG_HWMON_DEBUG_CHIP is not set | 699 | # CONFIG_HWMON_DEBUG_CHIP is not set |
| 700 | # CONFIG_THERMAL is not set | ||
| 701 | # CONFIG_THERMAL_HWMON is not set | ||
| 702 | # CONFIG_WATCHDOG is not set | ||
| 703 | CONFIG_SSB_POSSIBLE=y | ||
| 704 | |||
| 705 | # | ||
| 706 | # Sonics Silicon Backplane | ||
| 707 | # | ||
| 708 | # CONFIG_SSB is not set | ||
| 695 | 709 | ||
| 696 | # | 710 | # |
| 697 | # Multifunction device drivers | 711 | # Multifunction device drivers |
| 698 | # | 712 | # |
| 713 | # CONFIG_MFD_CORE is not set | ||
| 699 | # CONFIG_MFD_SM501 is not set | 714 | # CONFIG_MFD_SM501 is not set |
| 715 | # CONFIG_HTC_PASIC3 is not set | ||
| 716 | # CONFIG_MFD_TMIO is not set | ||
| 717 | # CONFIG_REGULATOR is not set | ||
| 700 | 718 | ||
| 701 | # | 719 | # |
| 702 | # Multimedia devices | 720 | # Multimedia devices |
| 703 | # | 721 | # |
| 722 | |||
| 723 | # | ||
| 724 | # Multimedia core support | ||
| 725 | # | ||
| 704 | # CONFIG_VIDEO_DEV is not set | 726 | # CONFIG_VIDEO_DEV is not set |
| 705 | # CONFIG_DVB_CORE is not set | 727 | # CONFIG_DVB_CORE is not set |
| 706 | # CONFIG_DAB is not set | 728 | # CONFIG_VIDEO_MEDIA is not set |
| 707 | 729 | ||
| 708 | # | 730 | # |
| 709 | # Graphics support | 731 | # Multimedia drivers |
| 710 | # | 732 | # |
| 711 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 733 | # CONFIG_DAB is not set |
| 712 | 734 | ||
| 713 | # | 735 | # |
| 714 | # Display device support | 736 | # Graphics support |
| 715 | # | 737 | # |
| 716 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 717 | # CONFIG_VGASTATE is not set | 738 | # CONFIG_VGASTATE is not set |
| 739 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 718 | # CONFIG_FB is not set | 740 | # CONFIG_FB is not set |
| 741 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 719 | 742 | ||
| 720 | # | 743 | # |
| 721 | # Sound | 744 | # Display device support |
| 722 | # | 745 | # |
| 746 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 723 | # CONFIG_SOUND is not set | 747 | # CONFIG_SOUND is not set |
| 724 | 748 | CONFIG_USB_SUPPORT=y | |
| 725 | # | ||
| 726 | # USB support | ||
| 727 | # | ||
| 728 | CONFIG_USB_ARCH_HAS_HCD=y | 749 | CONFIG_USB_ARCH_HAS_HCD=y |
| 729 | # CONFIG_USB_ARCH_HAS_OHCI is not set | 750 | # CONFIG_USB_ARCH_HAS_OHCI is not set |
| 730 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 751 | # CONFIG_USB_ARCH_HAS_EHCI is not set |
| 731 | # CONFIG_USB is not set | 752 | # CONFIG_USB is not set |
| 753 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 754 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 732 | 755 | ||
| 733 | # | 756 | # |
| 734 | # Enable Host or Gadget support to see Inventra options | 757 | # Enable Host or Gadget support to see Inventra options |
| 735 | # | 758 | # |
| 736 | 759 | ||
| 737 | # | 760 | # |
| 738 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 761 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; |
| 739 | # | ||
| 740 | |||
| 741 | # | ||
| 742 | # USB Gadget Support | ||
| 743 | # | 762 | # |
| 744 | # CONFIG_USB_GADGET is not set | 763 | # CONFIG_USB_GADGET is not set |
| 745 | # CONFIG_MMC is not set | 764 | # CONFIG_MMC is not set |
| 746 | 765 | # CONFIG_MEMSTICK is not set | |
| 747 | # | ||
| 748 | # LED devices | ||
| 749 | # | ||
| 750 | # CONFIG_NEW_LEDS is not set | 766 | # CONFIG_NEW_LEDS is not set |
| 751 | 767 | # CONFIG_ACCESSIBILITY is not set | |
| 752 | # | ||
| 753 | # LED drivers | ||
| 754 | # | ||
| 755 | |||
| 756 | # | ||
| 757 | # LED Triggers | ||
| 758 | # | ||
| 759 | |||
| 760 | # | ||
| 761 | # InfiniBand support | ||
| 762 | # | ||
| 763 | |||
| 764 | # | ||
| 765 | # EDAC - error detection and reporting (RAS) (EXPERIMENTAL) | ||
| 766 | # | ||
| 767 | |||
| 768 | # | ||
| 769 | # Real Time Clock | ||
| 770 | # | ||
| 771 | # CONFIG_RTC_CLASS is not set | 768 | # CONFIG_RTC_CLASS is not set |
| 772 | 769 | # CONFIG_DMADEVICES is not set | |
| 773 | # | 770 | # CONFIG_UIO is not set |
| 774 | # DMA Engine support | 771 | # CONFIG_STAGING is not set |
| 775 | # | ||
| 776 | # CONFIG_DMA_ENGINE is not set | ||
| 777 | |||
| 778 | # | ||
| 779 | # DMA Clients | ||
| 780 | # | ||
| 781 | |||
| 782 | # | ||
| 783 | # DMA Devices | ||
| 784 | # | ||
| 785 | |||
| 786 | # | ||
| 787 | # PBX support | ||
| 788 | # | ||
| 789 | # CONFIG_PBX is not set | ||
| 790 | 772 | ||
| 791 | # | 773 | # |
| 792 | # File systems | 774 | # File systems |
| @@ -796,20 +778,18 @@ CONFIG_EXT2_FS_XATTR=y | |||
| 796 | # CONFIG_EXT2_FS_POSIX_ACL is not set | 778 | # CONFIG_EXT2_FS_POSIX_ACL is not set |
| 797 | # CONFIG_EXT2_FS_SECURITY is not set | 779 | # CONFIG_EXT2_FS_SECURITY is not set |
| 798 | # CONFIG_EXT3_FS is not set | 780 | # CONFIG_EXT3_FS is not set |
| 799 | # CONFIG_EXT4DEV_FS is not set | 781 | # CONFIG_EXT4_FS is not set |
| 800 | CONFIG_FS_MBCACHE=y | 782 | CONFIG_FS_MBCACHE=y |
| 801 | # CONFIG_REISERFS_FS is not set | 783 | # CONFIG_REISERFS_FS is not set |
| 802 | # CONFIG_JFS_FS is not set | 784 | # CONFIG_JFS_FS is not set |
| 803 | # CONFIG_FS_POSIX_ACL is not set | 785 | # CONFIG_FS_POSIX_ACL is not set |
| 786 | CONFIG_FILE_LOCKING=y | ||
| 804 | # CONFIG_XFS_FS is not set | 787 | # CONFIG_XFS_FS is not set |
| 805 | # CONFIG_GFS2_FS is not set | ||
| 806 | # CONFIG_OCFS2_FS is not set | 788 | # CONFIG_OCFS2_FS is not set |
| 807 | # CONFIG_MINIX_FS is not set | 789 | # CONFIG_DNOTIFY is not set |
| 808 | # CONFIG_ROMFS_FS is not set | ||
| 809 | CONFIG_INOTIFY=y | 790 | CONFIG_INOTIFY=y |
| 810 | CONFIG_INOTIFY_USER=y | 791 | CONFIG_INOTIFY_USER=y |
| 811 | # CONFIG_QUOTA is not set | 792 | # CONFIG_QUOTA is not set |
| 812 | # CONFIG_DNOTIFY is not set | ||
| 813 | # CONFIG_AUTOFS_FS is not set | 793 | # CONFIG_AUTOFS_FS is not set |
| 814 | # CONFIG_AUTOFS4_FS is not set | 794 | # CONFIG_AUTOFS4_FS is not set |
| 815 | # CONFIG_FUSE_FS is not set | 795 | # CONFIG_FUSE_FS is not set |
| @@ -835,7 +815,6 @@ CONFIG_PROC_SYSCTL=y | |||
| 835 | CONFIG_SYSFS=y | 815 | CONFIG_SYSFS=y |
| 836 | # CONFIG_TMPFS is not set | 816 | # CONFIG_TMPFS is not set |
| 837 | # CONFIG_HUGETLB_PAGE is not set | 817 | # CONFIG_HUGETLB_PAGE is not set |
| 838 | CONFIG_RAMFS=y | ||
| 839 | # CONFIG_CONFIGFS_FS is not set | 818 | # CONFIG_CONFIGFS_FS is not set |
| 840 | 819 | ||
| 841 | # | 820 | # |
| @@ -848,60 +827,53 @@ CONFIG_RAMFS=y | |||
| 848 | # CONFIG_BEFS_FS is not set | 827 | # CONFIG_BEFS_FS is not set |
| 849 | # CONFIG_BFS_FS is not set | 828 | # CONFIG_BFS_FS is not set |
| 850 | # CONFIG_EFS_FS is not set | 829 | # CONFIG_EFS_FS is not set |
| 851 | # CONFIG_YAFFS_FS is not set | ||
| 852 | # CONFIG_JFFS2_FS is not set | 830 | # CONFIG_JFFS2_FS is not set |
| 831 | # CONFIG_YAFFS_FS is not set | ||
| 853 | # CONFIG_CRAMFS is not set | 832 | # CONFIG_CRAMFS is not set |
| 854 | # CONFIG_VXFS_FS is not set | 833 | # CONFIG_VXFS_FS is not set |
| 834 | # CONFIG_MINIX_FS is not set | ||
| 835 | # CONFIG_OMFS_FS is not set | ||
| 855 | # CONFIG_HPFS_FS is not set | 836 | # CONFIG_HPFS_FS is not set |
| 856 | # CONFIG_QNX4FS_FS is not set | 837 | # CONFIG_QNX4FS_FS is not set |
| 838 | # CONFIG_ROMFS_FS is not set | ||
| 857 | # CONFIG_SYSV_FS is not set | 839 | # CONFIG_SYSV_FS is not set |
| 858 | # CONFIG_UFS_FS is not set | 840 | # CONFIG_UFS_FS is not set |
| 859 | 841 | # CONFIG_NETWORK_FILESYSTEMS is not set | |
| 860 | # | ||
| 861 | # Network File Systems | ||
| 862 | # | ||
| 863 | # CONFIG_NFS_FS is not set | ||
| 864 | # CONFIG_NFSD is not set | ||
| 865 | # CONFIG_SMB_FS is not set | ||
| 866 | # CONFIG_CIFS is not set | ||
| 867 | # CONFIG_NCP_FS is not set | ||
| 868 | # CONFIG_CODA_FS is not set | ||
| 869 | # CONFIG_AFS_FS is not set | ||
| 870 | # CONFIG_9P_FS is not set | ||
| 871 | 842 | ||
| 872 | # | 843 | # |
| 873 | # Partition Types | 844 | # Partition Types |
| 874 | # | 845 | # |
| 875 | # CONFIG_PARTITION_ADVANCED is not set | 846 | # CONFIG_PARTITION_ADVANCED is not set |
| 876 | CONFIG_MSDOS_PARTITION=y | 847 | CONFIG_MSDOS_PARTITION=y |
| 877 | |||
| 878 | # | ||
| 879 | # Native Language Support | ||
| 880 | # | ||
| 881 | # CONFIG_NLS is not set | 848 | # CONFIG_NLS is not set |
| 882 | |||
| 883 | # | ||
| 884 | # Distributed Lock Manager | ||
| 885 | # | ||
| 886 | # CONFIG_DLM is not set | 849 | # CONFIG_DLM is not set |
| 887 | 850 | ||
| 888 | # | 851 | # |
| 889 | # Profiling support | ||
| 890 | # | ||
| 891 | # CONFIG_PROFILING is not set | ||
| 892 | |||
| 893 | # | ||
| 894 | # Kernel hacking | 852 | # Kernel hacking |
| 895 | # | 853 | # |
| 896 | # CONFIG_PRINTK_TIME is not set | 854 | # CONFIG_PRINTK_TIME is not set |
| 855 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 897 | CONFIG_ENABLE_MUST_CHECK=y | 856 | CONFIG_ENABLE_MUST_CHECK=y |
| 857 | CONFIG_FRAME_WARN=1024 | ||
| 898 | # CONFIG_MAGIC_SYSRQ is not set | 858 | # CONFIG_MAGIC_SYSRQ is not set |
| 899 | # CONFIG_UNUSED_SYMBOLS is not set | 859 | # CONFIG_UNUSED_SYMBOLS is not set |
| 900 | CONFIG_DEBUG_FS=y | 860 | CONFIG_DEBUG_FS=y |
| 901 | # CONFIG_HEADERS_CHECK is not set | 861 | # CONFIG_HEADERS_CHECK is not set |
| 862 | CONFIG_DEBUG_SECTION_MISMATCH=y | ||
| 902 | # CONFIG_DEBUG_KERNEL is not set | 863 | # CONFIG_DEBUG_KERNEL is not set |
| 903 | # CONFIG_DEBUG_BUGVERBOSE is not set | 864 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 865 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 866 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 867 | |||
| 868 | # | ||
| 869 | # Tracers | ||
| 870 | # | ||
| 871 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 872 | # CONFIG_SAMPLES is not set | ||
| 873 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 874 | CONFIG_DEBUG_VERBOSE=y | ||
| 904 | CONFIG_DEBUG_MMRS=y | 875 | CONFIG_DEBUG_MMRS=y |
| 876 | # CONFIG_DEBUG_DOUBLEFAULT is not set | ||
| 905 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 877 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 906 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 878 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 907 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 879 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y |
| @@ -919,13 +891,95 @@ CONFIG_ACCESS_CHECK=y | |||
| 919 | # | 891 | # |
| 920 | # CONFIG_KEYS is not set | 892 | # CONFIG_KEYS is not set |
| 921 | CONFIG_SECURITY=y | 893 | CONFIG_SECURITY=y |
| 894 | # CONFIG_SECURITYFS is not set | ||
| 922 | # CONFIG_SECURITY_NETWORK is not set | 895 | # CONFIG_SECURITY_NETWORK is not set |
| 923 | CONFIG_SECURITY_CAPABILITIES=y | 896 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 897 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 | ||
| 898 | CONFIG_CRYPTO=y | ||
| 899 | |||
| 900 | # | ||
| 901 | # Crypto core or helper | ||
| 902 | # | ||
| 903 | # CONFIG_CRYPTO_FIPS is not set | ||
| 904 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 905 | # CONFIG_CRYPTO_MANAGER2 is not set | ||
| 906 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 907 | # CONFIG_CRYPTO_NULL is not set | ||
| 908 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 909 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 910 | # CONFIG_CRYPTO_TEST is not set | ||
| 911 | |||
| 912 | # | ||
| 913 | # Authenticated Encryption with Associated Data | ||
| 914 | # | ||
| 915 | # CONFIG_CRYPTO_CCM is not set | ||
| 916 | # CONFIG_CRYPTO_GCM is not set | ||
| 917 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 918 | |||
| 919 | # | ||
| 920 | # Block modes | ||
| 921 | # | ||
| 922 | # CONFIG_CRYPTO_CBC is not set | ||
| 923 | # CONFIG_CRYPTO_CTR is not set | ||
| 924 | # CONFIG_CRYPTO_CTS is not set | ||
| 925 | # CONFIG_CRYPTO_ECB is not set | ||
| 926 | # CONFIG_CRYPTO_LRW is not set | ||
| 927 | # CONFIG_CRYPTO_PCBC is not set | ||
| 928 | # CONFIG_CRYPTO_XTS is not set | ||
| 929 | |||
| 930 | # | ||
| 931 | # Hash modes | ||
| 932 | # | ||
| 933 | # CONFIG_CRYPTO_HMAC is not set | ||
| 934 | # CONFIG_CRYPTO_XCBC is not set | ||
| 935 | |||
| 936 | # | ||
| 937 | # Digest | ||
| 938 | # | ||
| 939 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 940 | # CONFIG_CRYPTO_MD4 is not set | ||
| 941 | # CONFIG_CRYPTO_MD5 is not set | ||
| 942 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 943 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 944 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 945 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 946 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 947 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 948 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 949 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 950 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 951 | # CONFIG_CRYPTO_WP512 is not set | ||
| 952 | |||
| 953 | # | ||
| 954 | # Ciphers | ||
| 955 | # | ||
| 956 | # CONFIG_CRYPTO_AES is not set | ||
| 957 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 958 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 959 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 960 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 961 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 962 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 963 | # CONFIG_CRYPTO_DES is not set | ||
| 964 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 965 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 966 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 967 | # CONFIG_CRYPTO_SEED is not set | ||
| 968 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 969 | # CONFIG_CRYPTO_TEA is not set | ||
| 970 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 971 | |||
| 972 | # | ||
| 973 | # Compression | ||
| 974 | # | ||
| 975 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 976 | # CONFIG_CRYPTO_LZO is not set | ||
| 924 | 977 | ||
| 925 | # | 978 | # |
| 926 | # Cryptographic options | 979 | # Random Number Generation |
| 927 | # | 980 | # |
| 928 | # CONFIG_CRYPTO is not set | 981 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 982 | CONFIG_CRYPTO_HW=y | ||
| 929 | 983 | ||
| 930 | # | 984 | # |
| 931 | # Library routines | 985 | # Library routines |
| @@ -933,11 +987,12 @@ CONFIG_SECURITY_CAPABILITIES=y | |||
| 933 | CONFIG_BITREVERSE=y | 987 | CONFIG_BITREVERSE=y |
| 934 | CONFIG_CRC_CCITT=m | 988 | CONFIG_CRC_CCITT=m |
| 935 | # CONFIG_CRC16 is not set | 989 | # CONFIG_CRC16 is not set |
| 990 | # CONFIG_CRC_T10DIF is not set | ||
| 936 | # CONFIG_CRC_ITU_T is not set | 991 | # CONFIG_CRC_ITU_T is not set |
| 937 | CONFIG_CRC32=y | 992 | CONFIG_CRC32=y |
| 993 | # CONFIG_CRC7 is not set | ||
| 938 | # CONFIG_LIBCRC32C is not set | 994 | # CONFIG_LIBCRC32C is not set |
| 939 | CONFIG_ZLIB_INFLATE=y | 995 | CONFIG_ZLIB_INFLATE=y |
| 940 | CONFIG_PLIST=y | ||
| 941 | CONFIG_HAS_IOMEM=y | 996 | CONFIG_HAS_IOMEM=y |
| 942 | CONFIG_HAS_IOPORT=y | 997 | CONFIG_HAS_IOPORT=y |
| 943 | CONFIG_HAS_DMA=y | 998 | CONFIG_HAS_DMA=y |
diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig index 569523c1c034..80211303f6b9 100644 --- a/arch/blackfin/configs/CM-BF537U_defconfig +++ b/arch/blackfin/configs/CM-BF537U_defconfig | |||
| @@ -49,7 +49,7 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 49 | # CONFIG_SYSCTL is not set | 49 | # CONFIG_SYSCTL is not set |
| 50 | CONFIG_EMBEDDED=y | 50 | CONFIG_EMBEDDED=y |
| 51 | # CONFIG_UID16 is not set | 51 | # CONFIG_UID16 is not set |
| 52 | CONFIG_SYSCTL_SYSCALL=y | 52 | # CONFIG_SYSCTL_SYSCALL is not set |
| 53 | CONFIG_KALLSYMS=y | 53 | CONFIG_KALLSYMS=y |
| 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 55 | # CONFIG_HOTPLUG is not set | 55 | # CONFIG_HOTPLUG is not set |
| @@ -355,7 +355,7 @@ CONFIG_IP_FIB_HASH=y | |||
| 355 | # CONFIG_NET_IPIP is not set | 355 | # CONFIG_NET_IPIP is not set |
| 356 | # CONFIG_NET_IPGRE is not set | 356 | # CONFIG_NET_IPGRE is not set |
| 357 | # CONFIG_ARPD is not set | 357 | # CONFIG_ARPD is not set |
| 358 | CONFIG_SYN_COOKIES=y | 358 | # CONFIG_SYN_COOKIES is not set |
| 359 | # CONFIG_INET_AH is not set | 359 | # CONFIG_INET_AH is not set |
| 360 | # CONFIG_INET_ESP is not set | 360 | # CONFIG_INET_ESP is not set |
| 361 | # CONFIG_INET_IPCOMP is not set | 361 | # CONFIG_INET_IPCOMP is not set |
| @@ -556,9 +556,9 @@ CONFIG_SMC91X=y | |||
| 556 | # CONFIG_BFIN_MAC is not set | 556 | # CONFIG_BFIN_MAC is not set |
| 557 | # CONFIG_SMSC911X is not set | 557 | # CONFIG_SMSC911X is not set |
| 558 | # CONFIG_DM9000 is not set | 558 | # CONFIG_DM9000 is not set |
| 559 | CONFIG_NETDEV_1000=y | 559 | # CONFIG_NETDEV_1000 is not set |
| 560 | # CONFIG_AX88180 is not set | 560 | # CONFIG_AX88180 is not set |
| 561 | CONFIG_NETDEV_10000=y | 561 | # CONFIG_NETDEV_10000 is not set |
| 562 | 562 | ||
| 563 | # | 563 | # |
| 564 | # Wireless LAN | 564 | # Wireless LAN |
| @@ -652,6 +652,10 @@ CONFIG_UNIX98_PTYS=y | |||
| 652 | # CONFIG_TCG_TPM is not set | 652 | # CONFIG_TCG_TPM is not set |
| 653 | # CONFIG_I2C is not set | 653 | # CONFIG_I2C is not set |
| 654 | 654 | ||
| 655 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 656 | CONFIG_GPIOLIB=y | ||
| 657 | CONFIG_GPIO_SYSFS=y | ||
| 658 | |||
| 655 | # | 659 | # |
| 656 | # SPI support | 660 | # SPI support |
| 657 | # | 661 | # |
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig index 035b635e599c..dd815f0d1517 100644 --- a/arch/blackfin/configs/CM-BF548_defconfig +++ b/arch/blackfin/configs/CM-BF548_defconfig | |||
| @@ -49,7 +49,7 @@ CONFIG_INITRAMFS_SOURCE="" | |||
| 49 | # CONFIG_SYSCTL is not set | 49 | # CONFIG_SYSCTL is not set |
| 50 | CONFIG_EMBEDDED=y | 50 | CONFIG_EMBEDDED=y |
| 51 | CONFIG_UID16=y | 51 | CONFIG_UID16=y |
| 52 | CONFIG_SYSCTL_SYSCALL=y | 52 | # CONFIG_SYSCTL_SYSCALL is not set |
| 53 | CONFIG_KALLSYMS=y | 53 | CONFIG_KALLSYMS=y |
| 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 55 | CONFIG_HOTPLUG=y | 55 | CONFIG_HOTPLUG=y |
| @@ -125,9 +125,9 @@ CONFIG_PREEMPT_VOLUNTARY=y | |||
| 125 | CONFIG_BF548=y | 125 | CONFIG_BF548=y |
| 126 | # CONFIG_BF549 is not set | 126 | # CONFIG_BF549 is not set |
| 127 | # CONFIG_BF561 is not set | 127 | # CONFIG_BF561 is not set |
| 128 | CONFIG_BF_REV_0_0=y | 128 | # CONFIG_BF_REV_0_0 is not set |
| 129 | # CONFIG_BF_REV_0_1 is not set | 129 | # CONFIG_BF_REV_0_1 is not set |
| 130 | # CONFIG_BF_REV_0_2 is not set | 130 | CONFIG_BF_REV_0_2=y |
| 131 | # CONFIG_BF_REV_0_3 is not set | 131 | # CONFIG_BF_REV_0_3 is not set |
| 132 | # CONFIG_BF_REV_0_4 is not set | 132 | # CONFIG_BF_REV_0_4 is not set |
| 133 | # CONFIG_BF_REV_0_5 is not set | 133 | # CONFIG_BF_REV_0_5 is not set |
| @@ -422,7 +422,7 @@ CONFIG_IP_PNP=y | |||
| 422 | # CONFIG_NET_IPIP is not set | 422 | # CONFIG_NET_IPIP is not set |
| 423 | # CONFIG_NET_IPGRE is not set | 423 | # CONFIG_NET_IPGRE is not set |
| 424 | # CONFIG_ARPD is not set | 424 | # CONFIG_ARPD is not set |
| 425 | CONFIG_SYN_COOKIES=y | 425 | # CONFIG_SYN_COOKIES is not set |
| 426 | # CONFIG_INET_AH is not set | 426 | # CONFIG_INET_AH is not set |
| 427 | # CONFIG_INET_ESP is not set | 427 | # CONFIG_INET_ESP is not set |
| 428 | # CONFIG_INET_IPCOMP is not set | 428 | # CONFIG_INET_IPCOMP is not set |
| @@ -811,6 +811,10 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 | |||
| 811 | # CONFIG_I2C_DEBUG_BUS is not set | 811 | # CONFIG_I2C_DEBUG_BUS is not set |
| 812 | # CONFIG_I2C_DEBUG_CHIP is not set | 812 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 813 | 813 | ||
| 814 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 815 | CONFIG_GPIOLIB=y | ||
| 816 | CONFIG_GPIO_SYSFS=y | ||
| 817 | |||
| 814 | # | 818 | # |
| 815 | # SPI support | 819 | # SPI support |
| 816 | # | 820 | # |
diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig index 7015e42ccce5..16c198bd40c5 100644 --- a/arch/blackfin/configs/CM-BF561_defconfig +++ b/arch/blackfin/configs/CM-BF561_defconfig | |||
| @@ -49,7 +49,7 @@ CONFIG_FAIR_USER_SCHED=y | |||
| 49 | # CONFIG_SYSCTL is not set | 49 | # CONFIG_SYSCTL is not set |
| 50 | CONFIG_EMBEDDED=y | 50 | CONFIG_EMBEDDED=y |
| 51 | # CONFIG_UID16 is not set | 51 | # CONFIG_UID16 is not set |
| 52 | CONFIG_SYSCTL_SYSCALL=y | 52 | # CONFIG_SYSCTL_SYSCALL is not set |
| 53 | CONFIG_KALLSYMS=y | 53 | CONFIG_KALLSYMS=y |
| 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 55 | # CONFIG_HOTPLUG is not set | 55 | # CONFIG_HOTPLUG is not set |
| @@ -389,7 +389,7 @@ CONFIG_IP_FIB_HASH=y | |||
| 389 | # CONFIG_NET_IPIP is not set | 389 | # CONFIG_NET_IPIP is not set |
| 390 | # CONFIG_NET_IPGRE is not set | 390 | # CONFIG_NET_IPGRE is not set |
| 391 | # CONFIG_ARPD is not set | 391 | # CONFIG_ARPD is not set |
| 392 | CONFIG_SYN_COOKIES=y | 392 | # CONFIG_SYN_COOKIES is not set |
| 393 | # CONFIG_INET_AH is not set | 393 | # CONFIG_INET_AH is not set |
| 394 | # CONFIG_INET_ESP is not set | 394 | # CONFIG_INET_ESP is not set |
| 395 | # CONFIG_INET_IPCOMP is not set | 395 | # CONFIG_INET_IPCOMP is not set |
| @@ -569,9 +569,9 @@ CONFIG_SMC91X=y | |||
| 569 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 569 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 570 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 570 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 571 | # CONFIG_B44 is not set | 571 | # CONFIG_B44 is not set |
| 572 | CONFIG_NETDEV_1000=y | 572 | # CONFIG_NETDEV_1000 is not set |
| 573 | # CONFIG_AX88180 is not set | 573 | # CONFIG_AX88180 is not set |
| 574 | CONFIG_NETDEV_10000=y | 574 | # CONFIG_NETDEV_10000 is not set |
| 575 | 575 | ||
| 576 | # | 576 | # |
| 577 | # Wireless LAN | 577 | # Wireless LAN |
| @@ -646,6 +646,10 @@ CONFIG_UNIX98_PTYS=y | |||
| 646 | # CONFIG_TCG_TPM is not set | 646 | # CONFIG_TCG_TPM is not set |
| 647 | # CONFIG_I2C is not set | 647 | # CONFIG_I2C is not set |
| 648 | 648 | ||
| 649 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 650 | CONFIG_GPIOLIB=y | ||
| 651 | CONFIG_GPIO_SYSFS=y | ||
| 652 | |||
| 649 | # | 653 | # |
| 650 | # SPI support | 654 | # SPI support |
| 651 | # | 655 | # |
diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig index dfc8e1ddd77a..6b4c1a982383 100644 --- a/arch/blackfin/configs/H8606_defconfig +++ b/arch/blackfin/configs/H8606_defconfig | |||
| @@ -48,7 +48,7 @@ CONFIG_SYSFS_DEPRECATED=y | |||
| 48 | # CONFIG_SYSCTL is not set | 48 | # CONFIG_SYSCTL is not set |
| 49 | CONFIG_EMBEDDED=y | 49 | CONFIG_EMBEDDED=y |
| 50 | CONFIG_UID16=y | 50 | CONFIG_UID16=y |
| 51 | CONFIG_SYSCTL_SYSCALL=y | 51 | # CONFIG_SYSCTL_SYSCALL is not set |
| 52 | CONFIG_KALLSYMS=y | 52 | CONFIG_KALLSYMS=y |
| 53 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 53 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 54 | CONFIG_HOTPLUG=y | 54 | CONFIG_HOTPLUG=y |
| @@ -347,7 +347,7 @@ CONFIG_IP_PNP=y | |||
| 347 | # CONFIG_NET_IPIP is not set | 347 | # CONFIG_NET_IPIP is not set |
| 348 | # CONFIG_NET_IPGRE is not set | 348 | # CONFIG_NET_IPGRE is not set |
| 349 | # CONFIG_ARPD is not set | 349 | # CONFIG_ARPD is not set |
| 350 | CONFIG_SYN_COOKIES=y | 350 | # CONFIG_SYN_COOKIES is not set |
| 351 | # CONFIG_INET_AH is not set | 351 | # CONFIG_INET_AH is not set |
| 352 | # CONFIG_INET_ESP is not set | 352 | # CONFIG_INET_ESP is not set |
| 353 | # CONFIG_INET_IPCOMP is not set | 353 | # CONFIG_INET_IPCOMP is not set |
| @@ -594,8 +594,8 @@ CONFIG_MII=y | |||
| 594 | # CONFIG_SMC91X is not set | 594 | # CONFIG_SMC91X is not set |
| 595 | # CONFIG_SMSC911X is not set | 595 | # CONFIG_SMSC911X is not set |
| 596 | CONFIG_DM9000=y | 596 | CONFIG_DM9000=y |
| 597 | CONFIG_NETDEV_1000=y | 597 | # CONFIG_NETDEV_1000 is not set |
| 598 | CONFIG_NETDEV_10000=y | 598 | # CONFIG_NETDEV_10000 is not set |
| 599 | # CONFIG_AX88180 is not set | 599 | # CONFIG_AX88180 is not set |
| 600 | 600 | ||
| 601 | # | 601 | # |
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig index 95a5f91aebaa..1ec9ae2e964b 100644 --- a/arch/blackfin/configs/IP0X_defconfig +++ b/arch/blackfin/configs/IP0X_defconfig | |||
| @@ -49,7 +49,7 @@ CONFIG_INITRAMFS_SOURCE="" | |||
| 49 | # CONFIG_SYSCTL is not set | 49 | # CONFIG_SYSCTL is not set |
| 50 | CONFIG_EMBEDDED=y | 50 | CONFIG_EMBEDDED=y |
| 51 | CONFIG_UID16=y | 51 | CONFIG_UID16=y |
| 52 | CONFIG_SYSCTL_SYSCALL=y | 52 | # CONFIG_SYSCTL_SYSCALL is not set |
| 53 | CONFIG_KALLSYMS=y | 53 | CONFIG_KALLSYMS=y |
| 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 55 | # CONFIG_HOTPLUG is not set | 55 | # CONFIG_HOTPLUG is not set |
| @@ -355,7 +355,7 @@ CONFIG_IP_PNP=y | |||
| 355 | # CONFIG_NET_IPIP is not set | 355 | # CONFIG_NET_IPIP is not set |
| 356 | # CONFIG_NET_IPGRE is not set | 356 | # CONFIG_NET_IPGRE is not set |
| 357 | # CONFIG_ARPD is not set | 357 | # CONFIG_ARPD is not set |
| 358 | CONFIG_SYN_COOKIES=y | 358 | # CONFIG_SYN_COOKIES is not set |
| 359 | # CONFIG_INET_AH is not set | 359 | # CONFIG_INET_AH is not set |
| 360 | # CONFIG_INET_ESP is not set | 360 | # CONFIG_INET_ESP is not set |
| 361 | # CONFIG_INET_IPCOMP is not set | 361 | # CONFIG_INET_IPCOMP is not set |
| @@ -672,9 +672,9 @@ CONFIG_MII=y | |||
| 672 | # CONFIG_SMC91X is not set | 672 | # CONFIG_SMC91X is not set |
| 673 | # CONFIG_SMSC911X is not set | 673 | # CONFIG_SMSC911X is not set |
| 674 | CONFIG_DM9000=y | 674 | CONFIG_DM9000=y |
| 675 | CONFIG_NETDEV_1000=y | 675 | # CONFIG_NETDEV_1000 is not set |
| 676 | # CONFIG_AX88180 is not set | 676 | # CONFIG_AX88180 is not set |
| 677 | CONFIG_NETDEV_10000=y | 677 | # CONFIG_NETDEV_10000 is not set |
| 678 | 678 | ||
| 679 | # | 679 | # |
| 680 | # Wireless LAN | 680 | # Wireless LAN |
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig index 78e24080e7f1..09701f907e9b 100644 --- a/arch/blackfin/configs/PNAV-10_defconfig +++ b/arch/blackfin/configs/PNAV-10_defconfig | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28.7 | 3 | # Linux kernel version: 2.6.28.10 |
| 4 | # | 4 | # |
| 5 | # CONFIG_MMU is not set | 5 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 6 | # CONFIG_FPU is not set |
| @@ -40,26 +40,26 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 40 | # CONFIG_NAMESPACES is not set | 40 | # CONFIG_NAMESPACES is not set |
| 41 | # CONFIG_BLK_DEV_INITRD is not set | 41 | # CONFIG_BLK_DEV_INITRD is not set |
| 42 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 42 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 43 | # CONFIG_SYSCTL is not set | 43 | CONFIG_SYSCTL=y |
| 44 | CONFIG_ANON_INODES=y | ||
| 44 | CONFIG_EMBEDDED=y | 45 | CONFIG_EMBEDDED=y |
| 45 | CONFIG_UID16=y | 46 | CONFIG_UID16=y |
| 46 | CONFIG_SYSCTL_SYSCALL=y | 47 | # CONFIG_SYSCTL_SYSCALL is not set |
| 47 | CONFIG_KALLSYMS=y | 48 | CONFIG_KALLSYMS=y |
| 48 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 49 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 49 | CONFIG_HOTPLUG=y | 50 | CONFIG_HOTPLUG=y |
| 50 | CONFIG_PRINTK=y | 51 | CONFIG_PRINTK=y |
| 51 | CONFIG_BUG=y | 52 | CONFIG_BUG=y |
| 52 | # CONFIG_ELF_CORE is not set | 53 | # CONFIG_ELF_CORE is not set |
| 53 | CONFIG_COMPAT_BRK=y | ||
| 54 | CONFIG_BASE_FULL=y | 54 | CONFIG_BASE_FULL=y |
| 55 | # CONFIG_FUTEX is not set | 55 | # CONFIG_FUTEX is not set |
| 56 | CONFIG_ANON_INODES=y | ||
| 57 | CONFIG_EPOLL=y | 56 | CONFIG_EPOLL=y |
| 58 | CONFIG_SIGNALFD=y | 57 | CONFIG_SIGNALFD=y |
| 59 | CONFIG_TIMERFD=y | 58 | CONFIG_TIMERFD=y |
| 60 | CONFIG_EVENTFD=y | 59 | CONFIG_EVENTFD=y |
| 61 | # CONFIG_AIO is not set | 60 | # CONFIG_AIO is not set |
| 62 | CONFIG_VM_EVENT_COUNTERS=y | 61 | CONFIG_VM_EVENT_COUNTERS=y |
| 62 | CONFIG_COMPAT_BRK=y | ||
| 63 | CONFIG_SLAB=y | 63 | CONFIG_SLAB=y |
| 64 | # CONFIG_SLUB is not set | 64 | # CONFIG_SLUB is not set |
| 65 | # CONFIG_SLOB is not set | 65 | # CONFIG_SLOB is not set |
| @@ -68,7 +68,6 @@ CONFIG_SLAB=y | |||
| 68 | CONFIG_HAVE_OPROFILE=y | 68 | CONFIG_HAVE_OPROFILE=y |
| 69 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 69 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 70 | CONFIG_SLABINFO=y | 70 | CONFIG_SLABINFO=y |
| 71 | CONFIG_RT_MUTEXES=y | ||
| 72 | CONFIG_TINY_SHMEM=y | 71 | CONFIG_TINY_SHMEM=y |
| 73 | CONFIG_BASE_SMALL=0 | 72 | CONFIG_BASE_SMALL=0 |
| 74 | CONFIG_MODULES=y | 73 | CONFIG_MODULES=y |
| @@ -229,7 +228,10 @@ CONFIG_HZ=250 | |||
| 229 | # CONFIG_SCHED_HRTICK is not set | 228 | # CONFIG_SCHED_HRTICK is not set |
| 230 | CONFIG_GENERIC_TIME=y | 229 | CONFIG_GENERIC_TIME=y |
| 231 | CONFIG_GENERIC_CLOCKEVENTS=y | 230 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 231 | # CONFIG_TICKSOURCE_GPTMR0 is not set | ||
| 232 | CONFIG_TICKSOURCE_CORETMR=y | ||
| 232 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 233 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 234 | # CONFIG_GPTMR0_CLOCKSOURCE is not set | ||
| 233 | # CONFIG_NO_HZ is not set | 235 | # CONFIG_NO_HZ is not set |
| 234 | # CONFIG_HIGH_RES_TIMERS is not set | 236 | # CONFIG_HIGH_RES_TIMERS is not set |
| 235 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 237 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| @@ -374,7 +376,7 @@ CONFIG_IP_PNP=y | |||
| 374 | # CONFIG_NET_IPIP is not set | 376 | # CONFIG_NET_IPIP is not set |
| 375 | # CONFIG_NET_IPGRE is not set | 377 | # CONFIG_NET_IPGRE is not set |
| 376 | # CONFIG_ARPD is not set | 378 | # CONFIG_ARPD is not set |
| 377 | CONFIG_SYN_COOKIES=y | 379 | # CONFIG_SYN_COOKIES is not set |
| 378 | # CONFIG_INET_AH is not set | 380 | # CONFIG_INET_AH is not set |
| 379 | # CONFIG_INET_ESP is not set | 381 | # CONFIG_INET_ESP is not set |
| 380 | # CONFIG_INET_IPCOMP is not set | 382 | # CONFIG_INET_IPCOMP is not set |
| @@ -598,9 +600,8 @@ CONFIG_BFIN_MAC_RMII=y | |||
| 598 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | 600 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set |
| 599 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | 601 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set |
| 600 | # CONFIG_B44 is not set | 602 | # CONFIG_B44 is not set |
| 601 | CONFIG_NETDEV_1000=y | 603 | # CONFIG_NETDEV_1000 is not set |
| 602 | # CONFIG_AX88180 is not set | 604 | # CONFIG_NETDEV_10000 is not set |
| 603 | CONFIG_NETDEV_10000=y | ||
| 604 | 605 | ||
| 605 | # | 606 | # |
| 606 | # Wireless LAN | 607 | # Wireless LAN |
| @@ -640,11 +641,11 @@ CONFIG_INPUT_EVDEV=y | |||
| 640 | # CONFIG_INPUT_JOYSTICK is not set | 641 | # CONFIG_INPUT_JOYSTICK is not set |
| 641 | # CONFIG_INPUT_TABLET is not set | 642 | # CONFIG_INPUT_TABLET is not set |
| 642 | CONFIG_INPUT_TOUCHSCREEN=y | 643 | CONFIG_INPUT_TOUCHSCREEN=y |
| 643 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 644 | CONFIG_TOUCHSCREEN_AD7877=y | 644 | CONFIG_TOUCHSCREEN_AD7877=y |
| 645 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | 645 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set |
| 646 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | 646 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set |
| 647 | # CONFIG_TOUCHSCREEN_AD7879 is not set | 647 | # CONFIG_TOUCHSCREEN_AD7879 is not set |
| 648 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 648 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 649 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 649 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 650 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 650 | # CONFIG_TOUCHSCREEN_ELO is not set | 651 | # CONFIG_TOUCHSCREEN_ELO is not set |
| @@ -676,14 +677,14 @@ CONFIG_INPUT_UINPUT=y | |||
| 676 | # Character devices | 677 | # Character devices |
| 677 | # | 678 | # |
| 678 | # CONFIG_AD9960 is not set | 679 | # CONFIG_AD9960 is not set |
| 679 | # CONFIG_SPI_ADC_BF533 is not set | 680 | CONFIG_BFIN_DMA_INTERFACE=m |
| 680 | # CONFIG_BF5xx_PPIFCD is not set | 681 | # CONFIG_BFIN_PPI is not set |
| 682 | # CONFIG_BFIN_PPIFCD is not set | ||
| 681 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 683 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 682 | # CONFIG_BF5xx_PPI is not set | 684 | # CONFIG_BFIN_SPI_ADC is not set |
| 683 | CONFIG_BFIN_SPORT=y | 685 | CONFIG_BFIN_SPORT=y |
| 684 | # CONFIG_BFIN_TIMER_LATENCY is not set | 686 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 685 | CONFIG_TWI_LCD=m | 687 | # CONFIG_BFIN_TWI_LCD is not set |
| 686 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 687 | # CONFIG_SIMPLE_GPIO is not set | 688 | # CONFIG_SIMPLE_GPIO is not set |
| 688 | # CONFIG_VT is not set | 689 | # CONFIG_VT is not set |
| 689 | CONFIG_DEVKMEM=y | 690 | CONFIG_DEVKMEM=y |
| @@ -796,6 +797,7 @@ CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | |||
| 796 | # CONFIG_POWER_SUPPLY is not set | 797 | # CONFIG_POWER_SUPPLY is not set |
| 797 | CONFIG_HWMON=y | 798 | CONFIG_HWMON=y |
| 798 | # CONFIG_HWMON_VID is not set | 799 | # CONFIG_HWMON_VID is not set |
| 800 | # CONFIG_SENSORS_AD5252 is not set | ||
| 799 | # CONFIG_SENSORS_AD7414 is not set | 801 | # CONFIG_SENSORS_AD7414 is not set |
| 800 | # CONFIG_SENSORS_AD7418 is not set | 802 | # CONFIG_SENSORS_AD7418 is not set |
| 801 | # CONFIG_SENSORS_ADCXX is not set | 803 | # CONFIG_SENSORS_ADCXX is not set |
| @@ -867,6 +869,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 867 | # CONFIG_HTC_PASIC3 is not set | 869 | # CONFIG_HTC_PASIC3 is not set |
| 868 | # CONFIG_MFD_TMIO is not set | 870 | # CONFIG_MFD_TMIO is not set |
| 869 | # CONFIG_PMIC_DA903X is not set | 871 | # CONFIG_PMIC_DA903X is not set |
| 872 | # CONFIG_PMIC_ADP5520 is not set | ||
| 870 | # CONFIG_MFD_WM8400 is not set | 873 | # CONFIG_MFD_WM8400 is not set |
| 871 | # CONFIG_MFD_WM8350_I2C is not set | 874 | # CONFIG_MFD_WM8350_I2C is not set |
| 872 | # CONFIG_REGULATOR is not set | 875 | # CONFIG_REGULATOR is not set |
| @@ -1111,6 +1114,7 @@ CONFIG_SYSFS=y | |||
| 1111 | # CONFIG_BEFS_FS is not set | 1114 | # CONFIG_BEFS_FS is not set |
| 1112 | # CONFIG_BFS_FS is not set | 1115 | # CONFIG_BFS_FS is not set |
| 1113 | # CONFIG_EFS_FS is not set | 1116 | # CONFIG_EFS_FS is not set |
| 1117 | # CONFIG_JFFS2_FS is not set | ||
| 1114 | CONFIG_YAFFS_FS=y | 1118 | CONFIG_YAFFS_FS=y |
| 1115 | CONFIG_YAFFS_YAFFS1=y | 1119 | CONFIG_YAFFS_YAFFS1=y |
| 1116 | # CONFIG_YAFFS_9BYTE_TAGS is not set | 1120 | # CONFIG_YAFFS_9BYTE_TAGS is not set |
| @@ -1121,7 +1125,6 @@ CONFIG_YAFFS_AUTO_YAFFS2=y | |||
| 1121 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | 1125 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set |
| 1122 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | 1126 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set |
| 1123 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | 1127 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y |
| 1124 | # CONFIG_JFFS2_FS is not set | ||
| 1125 | # CONFIG_CRAMFS is not set | 1128 | # CONFIG_CRAMFS is not set |
| 1126 | # CONFIG_VXFS_FS is not set | 1129 | # CONFIG_VXFS_FS is not set |
| 1127 | # CONFIG_MINIX_FS is not set | 1130 | # CONFIG_MINIX_FS is not set |
| @@ -1213,7 +1216,6 @@ CONFIG_FRAME_WARN=1024 | |||
| 1213 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1216 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 1214 | # CONFIG_DEBUG_MEMORY_INIT is not set | 1217 | # CONFIG_DEBUG_MEMORY_INIT is not set |
| 1215 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 1218 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| 1216 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1217 | 1219 | ||
| 1218 | # | 1220 | # |
| 1219 | # Tracers | 1221 | # Tracers |
| @@ -1343,7 +1345,6 @@ CONFIG_CRC32=y | |||
| 1343 | # CONFIG_CRC7 is not set | 1345 | # CONFIG_CRC7 is not set |
| 1344 | # CONFIG_LIBCRC32C is not set | 1346 | # CONFIG_LIBCRC32C is not set |
| 1345 | CONFIG_ZLIB_INFLATE=y | 1347 | CONFIG_ZLIB_INFLATE=y |
| 1346 | CONFIG_PLIST=y | ||
| 1347 | CONFIG_HAS_IOMEM=y | 1348 | CONFIG_HAS_IOMEM=y |
| 1348 | CONFIG_HAS_IOPORT=y | 1349 | CONFIG_HAS_IOPORT=y |
| 1349 | CONFIG_HAS_DMA=y | 1350 | CONFIG_HAS_DMA=y |
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig index 2bc0779d22ea..ec84a53daae9 100644 --- a/arch/blackfin/configs/SRV1_defconfig +++ b/arch/blackfin/configs/SRV1_defconfig | |||
| @@ -52,7 +52,7 @@ CONFIG_INITRAMFS_SOURCE="" | |||
| 52 | # CONFIG_SYSCTL is not set | 52 | # CONFIG_SYSCTL is not set |
| 53 | CONFIG_EMBEDDED=y | 53 | CONFIG_EMBEDDED=y |
| 54 | CONFIG_UID16=y | 54 | CONFIG_UID16=y |
| 55 | CONFIG_SYSCTL_SYSCALL=y | 55 | # CONFIG_SYSCTL_SYSCALL is not set |
| 56 | CONFIG_KALLSYMS=y | 56 | CONFIG_KALLSYMS=y |
| 57 | CONFIG_KALLSYMS_ALL=y | 57 | CONFIG_KALLSYMS_ALL=y |
| 58 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 58 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| @@ -373,7 +373,7 @@ CONFIG_IP_PNP=y | |||
| 373 | # CONFIG_NET_IPIP is not set | 373 | # CONFIG_NET_IPIP is not set |
| 374 | # CONFIG_NET_IPGRE is not set | 374 | # CONFIG_NET_IPGRE is not set |
| 375 | # CONFIG_ARPD is not set | 375 | # CONFIG_ARPD is not set |
| 376 | CONFIG_SYN_COOKIES=y | 376 | # CONFIG_SYN_COOKIES is not set |
| 377 | # CONFIG_INET_AH is not set | 377 | # CONFIG_INET_AH is not set |
| 378 | # CONFIG_INET_ESP is not set | 378 | # CONFIG_INET_ESP is not set |
| 379 | # CONFIG_INET_IPCOMP is not set | 379 | # CONFIG_INET_IPCOMP is not set |
diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig index e65b3a49214f..6e2796240fdc 100644 --- a/arch/blackfin/configs/TCM-BF537_defconfig +++ b/arch/blackfin/configs/TCM-BF537_defconfig | |||
| @@ -42,7 +42,7 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 42 | # CONFIG_SYSCTL is not set | 42 | # CONFIG_SYSCTL is not set |
| 43 | CONFIG_EMBEDDED=y | 43 | CONFIG_EMBEDDED=y |
| 44 | # CONFIG_UID16 is not set | 44 | # CONFIG_UID16 is not set |
| 45 | CONFIG_SYSCTL_SYSCALL=y | 45 | # CONFIG_SYSCTL_SYSCALL is not set |
| 46 | CONFIG_KALLSYMS=y | 46 | CONFIG_KALLSYMS=y |
| 47 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 47 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 48 | # CONFIG_HOTPLUG is not set | 48 | # CONFIG_HOTPLUG is not set |
| @@ -537,7 +537,30 @@ CONFIG_SPI_BFIN=y | |||
| 537 | # CONFIG_SPI_SPIDEV is not set | 537 | # CONFIG_SPI_SPIDEV is not set |
| 538 | # CONFIG_SPI_TLE62X0 is not set | 538 | # CONFIG_SPI_TLE62X0 is not set |
| 539 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | 539 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 540 | # CONFIG_GPIOLIB is not set | 540 | CONFIG_GPIOLIB=y |
| 541 | # CONFIG_DEBUG_GPIO is not set | ||
| 542 | CONFIG_GPIO_SYSFS=y | ||
| 543 | |||
| 544 | # | ||
| 545 | # Memory mapped GPIO expanders: | ||
| 546 | # | ||
| 547 | |||
| 548 | # | ||
| 549 | # I2C GPIO expanders: | ||
| 550 | # | ||
| 551 | # CONFIG_GPIO_MAX732X is not set | ||
| 552 | # CONFIG_GPIO_PCA953X is not set | ||
| 553 | # CONFIG_GPIO_PCF857X is not set | ||
| 554 | |||
| 555 | # | ||
| 556 | # PCI GPIO expanders: | ||
| 557 | # | ||
| 558 | |||
| 559 | # | ||
| 560 | # SPI GPIO expanders: | ||
| 561 | # | ||
| 562 | # CONFIG_GPIO_MAX7301 is not set | ||
| 563 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 541 | # CONFIG_W1 is not set | 564 | # CONFIG_W1 is not set |
| 542 | # CONFIG_POWER_SUPPLY is not set | 565 | # CONFIG_POWER_SUPPLY is not set |
| 543 | # CONFIG_HWMON is not set | 566 | # CONFIG_HWMON is not set |
diff --git a/arch/blackfin/include/asm/.gitignore b/arch/blackfin/include/asm/.gitignore deleted file mode 100644 index 7858564a4466..000000000000 --- a/arch/blackfin/include/asm/.gitignore +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | +mach | ||
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h index 94b2a9b19451..88f36d599fe8 100644 --- a/arch/blackfin/include/asm/atomic.h +++ b/arch/blackfin/include/asm/atomic.h | |||
| @@ -1,24 +1,21 @@ | |||
| 1 | #ifndef __ARCH_BLACKFIN_ATOMIC__ | 1 | #ifndef __ARCH_BLACKFIN_ATOMIC__ |
| 2 | #define __ARCH_BLACKFIN_ATOMIC__ | 2 | #define __ARCH_BLACKFIN_ATOMIC__ |
| 3 | 3 | ||
| 4 | #ifndef CONFIG_SMP | ||
| 5 | # include <asm-generic/atomic.h> | ||
| 6 | #else | ||
| 7 | |||
| 4 | #include <linux/types.h> | 8 | #include <linux/types.h> |
| 5 | #include <asm/system.h> /* local_irq_XXX() */ | 9 | #include <asm/system.h> /* local_irq_XXX() */ |
| 6 | 10 | ||
| 7 | /* | 11 | /* |
| 8 | * Atomic operations that C can't guarantee us. Useful for | 12 | * Atomic operations that C can't guarantee us. Useful for |
| 9 | * resource counting etc.. | 13 | * resource counting etc.. |
| 10 | * | ||
| 11 | * Generally we do not concern about SMP BFIN systems, so we don't have | ||
| 12 | * to deal with that. | ||
| 13 | * | ||
| 14 | * Tony Kou (tonyko@lineo.ca) Lineo Inc. 2001 | ||
| 15 | */ | 14 | */ |
| 16 | 15 | ||
| 17 | #define ATOMIC_INIT(i) { (i) } | 16 | #define ATOMIC_INIT(i) { (i) } |
| 18 | #define atomic_set(v, i) (((v)->counter) = i) | 17 | #define atomic_set(v, i) (((v)->counter) = i) |
| 19 | 18 | ||
| 20 | #ifdef CONFIG_SMP | ||
| 21 | |||
| 22 | #define atomic_read(v) __raw_uncached_fetch_asm(&(v)->counter) | 19 | #define atomic_read(v) __raw_uncached_fetch_asm(&(v)->counter) |
| 23 | 20 | ||
| 24 | asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr); | 21 | asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr); |
| @@ -84,100 +81,6 @@ static inline int atomic_test_mask(int mask, atomic_t *v) | |||
| 84 | #define smp_mb__before_atomic_inc() barrier() | 81 | #define smp_mb__before_atomic_inc() barrier() |
| 85 | #define smp_mb__after_atomic_inc() barrier() | 82 | #define smp_mb__after_atomic_inc() barrier() |
| 86 | 83 | ||
| 87 | #else /* !CONFIG_SMP */ | ||
| 88 | |||
| 89 | #define atomic_read(v) ((v)->counter) | ||
| 90 | |||
| 91 | static inline void atomic_add(int i, atomic_t *v) | ||
| 92 | { | ||
| 93 | long flags; | ||
| 94 | |||
| 95 | local_irq_save_hw(flags); | ||
| 96 | v->counter += i; | ||
| 97 | local_irq_restore_hw(flags); | ||
| 98 | } | ||
| 99 | |||
| 100 | static inline void atomic_sub(int i, atomic_t *v) | ||
| 101 | { | ||
| 102 | long flags; | ||
| 103 | |||
| 104 | local_irq_save_hw(flags); | ||
| 105 | v->counter -= i; | ||
| 106 | local_irq_restore_hw(flags); | ||
| 107 | |||
| 108 | } | ||
| 109 | |||
| 110 | static inline int atomic_add_return(int i, atomic_t *v) | ||
| 111 | { | ||
| 112 | int __temp = 0; | ||
| 113 | long flags; | ||
| 114 | |||
| 115 | local_irq_save_hw(flags); | ||
| 116 | v->counter += i; | ||
| 117 | __temp = v->counter; | ||
| 118 | local_irq_restore_hw(flags); | ||
| 119 | |||
| 120 | |||
| 121 | return __temp; | ||
| 122 | } | ||
| 123 | |||
| 124 | static inline int atomic_sub_return(int i, atomic_t *v) | ||
| 125 | { | ||
| 126 | int __temp = 0; | ||
| 127 | long flags; | ||
| 128 | |||
| 129 | local_irq_save_hw(flags); | ||
| 130 | v->counter -= i; | ||
| 131 | __temp = v->counter; | ||
| 132 | local_irq_restore_hw(flags); | ||
| 133 | |||
| 134 | return __temp; | ||
| 135 | } | ||
| 136 | |||
| 137 | static inline void atomic_inc(volatile atomic_t *v) | ||
| 138 | { | ||
| 139 | long flags; | ||
| 140 | |||
| 141 | local_irq_save_hw(flags); | ||
| 142 | v->counter++; | ||
| 143 | local_irq_restore_hw(flags); | ||
| 144 | } | ||
| 145 | |||
| 146 | static inline void atomic_dec(volatile atomic_t *v) | ||
| 147 | { | ||
| 148 | long flags; | ||
| 149 | |||
| 150 | local_irq_save_hw(flags); | ||
| 151 | v->counter--; | ||
| 152 | local_irq_restore_hw(flags); | ||
| 153 | } | ||
| 154 | |||
| 155 | static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) | ||
| 156 | { | ||
| 157 | long flags; | ||
| 158 | |||
| 159 | local_irq_save_hw(flags); | ||
| 160 | v->counter &= ~mask; | ||
| 161 | local_irq_restore_hw(flags); | ||
| 162 | } | ||
| 163 | |||
| 164 | static inline void atomic_set_mask(unsigned int mask, atomic_t *v) | ||
| 165 | { | ||
| 166 | long flags; | ||
| 167 | |||
| 168 | local_irq_save_hw(flags); | ||
| 169 | v->counter |= mask; | ||
| 170 | local_irq_restore_hw(flags); | ||
| 171 | } | ||
| 172 | |||
| 173 | /* Atomic operations are already serializing */ | ||
| 174 | #define smp_mb__before_atomic_dec() barrier() | ||
| 175 | #define smp_mb__after_atomic_dec() barrier() | ||
| 176 | #define smp_mb__before_atomic_inc() barrier() | ||
| 177 | #define smp_mb__after_atomic_inc() barrier() | ||
| 178 | |||
| 179 | #endif /* !CONFIG_SMP */ | ||
| 180 | |||
| 181 | #define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) | 84 | #define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) |
| 182 | #define atomic_dec_return(v) atomic_sub_return(1,(v)) | 85 | #define atomic_dec_return(v) atomic_sub_return(1,(v)) |
| 183 | #define atomic_inc_return(v) atomic_add_return(1,(v)) | 86 | #define atomic_inc_return(v) atomic_add_return(1,(v)) |
| @@ -208,6 +111,8 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v) | |||
| 208 | #define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) | 111 | #define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) |
| 209 | #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) | 112 | #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) |
| 210 | 113 | ||
| 211 | #include <asm-generic/atomic.h> | 114 | #include <asm-generic/atomic-long.h> |
| 115 | |||
| 116 | #endif | ||
| 212 | 117 | ||
| 213 | #endif /* __ARCH_BLACKFIN_ATOMIC __ */ | 118 | #endif |
diff --git a/arch/blackfin/include/asm/auxvec.h b/arch/blackfin/include/asm/auxvec.h index 215506cd87b7..41fa68b71287 100644 --- a/arch/blackfin/include/asm/auxvec.h +++ b/arch/blackfin/include/asm/auxvec.h | |||
| @@ -1,4 +1 @@ | |||
| 1 | #ifndef __ASMBFIN_AUXVEC_H | #include <asm-generic/auxvec.h> | |
| 2 | #define __ASMBFIN_AUXVEC_H | ||
| 3 | |||
| 4 | #endif | ||
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h index daffc0684e75..e39277ea43e8 100644 --- a/arch/blackfin/include/asm/bfin-global.h +++ b/arch/blackfin/include/asm/bfin-global.h | |||
| @@ -31,7 +31,7 @@ | |||
| 31 | 31 | ||
| 32 | #ifndef __ASSEMBLY__ | 32 | #ifndef __ASSEMBLY__ |
| 33 | 33 | ||
| 34 | #include <asm-generic/sections.h> | 34 | #include <asm/sections.h> |
| 35 | #include <asm/ptrace.h> | 35 | #include <asm/ptrace.h> |
| 36 | #include <asm/user.h> | 36 | #include <asm/user.h> |
| 37 | #include <linux/linkage.h> | 37 | #include <linux/linkage.h> |
| @@ -99,15 +99,6 @@ extern const char bfin_board_name[]; | |||
| 99 | extern unsigned long bfin_sic_iwr[]; | 99 | extern unsigned long bfin_sic_iwr[]; |
| 100 | extern unsigned vr_wakeup; | 100 | extern unsigned vr_wakeup; |
| 101 | extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ | 101 | extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ |
| 102 | extern unsigned long _ramstart, _ramend, _rambase; | ||
| 103 | extern unsigned long memory_start, memory_end, physical_mem_end; | ||
| 104 | extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[], | ||
| 105 | _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _sbss_b_l1[], _ebss_b_l1[], | ||
| 106 | _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[], | ||
| 107 | _ebss_l2[], _l2_lma_start[]; | ||
| 108 | |||
| 109 | /* only used when MTD_UCLINUX */ | ||
| 110 | extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size; | ||
| 111 | 102 | ||
| 112 | #ifdef CONFIG_BFIN_ICACHE_LOCK | 103 | #ifdef CONFIG_BFIN_ICACHE_LOCK |
| 113 | extern void cache_grab_lock(int way); | 104 | extern void cache_grab_lock(int way); |
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index 21b036eadab1..daffa71576d4 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h | |||
| @@ -1,26 +1,22 @@ | |||
| 1 | #ifndef _BLACKFIN_BITOPS_H | 1 | #ifndef _BLACKFIN_BITOPS_H |
| 2 | #define _BLACKFIN_BITOPS_H | 2 | #define _BLACKFIN_BITOPS_H |
| 3 | 3 | ||
| 4 | /* | 4 | #ifndef CONFIG_SMP |
| 5 | * Copyright 1992, Linus Torvalds. | 5 | # include <asm-generic/bitops.h> |
| 6 | */ | 6 | #else |
| 7 | |||
| 8 | #include <linux/compiler.h> | ||
| 9 | #include <asm/byteorder.h> /* swab32 */ | ||
| 10 | |||
| 11 | #ifdef __KERNEL__ | ||
| 12 | 7 | ||
| 13 | #ifndef _LINUX_BITOPS_H | 8 | #ifndef _LINUX_BITOPS_H |
| 14 | #error only <linux/bitops.h> can be included directly | 9 | #error only <linux/bitops.h> can be included directly |
| 15 | #endif | 10 | #endif |
| 16 | 11 | ||
| 12 | #include <linux/compiler.h> | ||
| 13 | #include <asm/byteorder.h> /* swab32 */ | ||
| 14 | |||
| 17 | #include <asm-generic/bitops/ffs.h> | 15 | #include <asm-generic/bitops/ffs.h> |
| 18 | #include <asm-generic/bitops/__ffs.h> | 16 | #include <asm-generic/bitops/__ffs.h> |
| 19 | #include <asm-generic/bitops/sched.h> | 17 | #include <asm-generic/bitops/sched.h> |
| 20 | #include <asm-generic/bitops/ffz.h> | 18 | #include <asm-generic/bitops/ffz.h> |
| 21 | 19 | ||
| 22 | #ifdef CONFIG_SMP | ||
| 23 | |||
| 24 | #include <linux/linkage.h> | 20 | #include <linux/linkage.h> |
| 25 | 21 | ||
| 26 | asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr); | 22 | asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr); |
| @@ -79,188 +75,13 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr) | |||
| 79 | return __raw_bit_test_toggle_asm(a, nr & 0x1f); | 75 | return __raw_bit_test_toggle_asm(a, nr & 0x1f); |
| 80 | } | 76 | } |
| 81 | 77 | ||
| 82 | #else /* !CONFIG_SMP */ | ||
| 83 | |||
| 84 | #include <asm/system.h> /* save_flags */ | ||
| 85 | |||
| 86 | static inline void set_bit(int nr, volatile unsigned long *addr) | ||
| 87 | { | ||
| 88 | int *a = (int *)addr; | ||
| 89 | int mask; | ||
| 90 | unsigned long flags; | ||
| 91 | a += nr >> 5; | ||
| 92 | mask = 1 << (nr & 0x1f); | ||
| 93 | local_irq_save_hw(flags); | ||
| 94 | *a |= mask; | ||
| 95 | local_irq_restore_hw(flags); | ||
| 96 | } | ||
| 97 | |||
| 98 | static inline void clear_bit(int nr, volatile unsigned long *addr) | ||
| 99 | { | ||
| 100 | int *a = (int *)addr; | ||
| 101 | int mask; | ||
| 102 | unsigned long flags; | ||
| 103 | a += nr >> 5; | ||
| 104 | mask = 1 << (nr & 0x1f); | ||
| 105 | local_irq_save_hw(flags); | ||
| 106 | *a &= ~mask; | ||
| 107 | local_irq_restore_hw(flags); | ||
| 108 | } | ||
| 109 | |||
| 110 | static inline void change_bit(int nr, volatile unsigned long *addr) | ||
| 111 | { | ||
| 112 | int mask, flags; | ||
| 113 | unsigned long *ADDR = (unsigned long *)addr; | ||
| 114 | |||
| 115 | ADDR += nr >> 5; | ||
| 116 | mask = 1 << (nr & 31); | ||
| 117 | local_irq_save_hw(flags); | ||
| 118 | *ADDR ^= mask; | ||
| 119 | local_irq_restore_hw(flags); | ||
| 120 | } | ||
| 121 | |||
| 122 | static inline int test_and_set_bit(int nr, volatile unsigned long *addr) | ||
| 123 | { | ||
| 124 | int mask, retval; | ||
| 125 | volatile unsigned int *a = (volatile unsigned int *)addr; | ||
| 126 | unsigned long flags; | ||
| 127 | |||
| 128 | a += nr >> 5; | ||
| 129 | mask = 1 << (nr & 0x1f); | ||
| 130 | local_irq_save_hw(flags); | ||
| 131 | retval = (mask & *a) != 0; | ||
| 132 | *a |= mask; | ||
| 133 | local_irq_restore_hw(flags); | ||
| 134 | |||
| 135 | return retval; | ||
| 136 | } | ||
| 137 | |||
| 138 | static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) | ||
| 139 | { | ||
| 140 | int mask, retval; | ||
| 141 | volatile unsigned int *a = (volatile unsigned int *)addr; | ||
| 142 | unsigned long flags; | ||
| 143 | |||
| 144 | a += nr >> 5; | ||
| 145 | mask = 1 << (nr & 0x1f); | ||
| 146 | local_irq_save_hw(flags); | ||
| 147 | retval = (mask & *a) != 0; | ||
| 148 | *a &= ~mask; | ||
| 149 | local_irq_restore_hw(flags); | ||
| 150 | |||
| 151 | return retval; | ||
| 152 | } | ||
| 153 | |||
| 154 | static inline int test_and_change_bit(int nr, volatile unsigned long *addr) | ||
| 155 | { | ||
| 156 | int mask, retval; | ||
| 157 | volatile unsigned int *a = (volatile unsigned int *)addr; | ||
| 158 | unsigned long flags; | ||
| 159 | |||
| 160 | a += nr >> 5; | ||
| 161 | mask = 1 << (nr & 0x1f); | ||
| 162 | local_irq_save_hw(flags); | ||
| 163 | retval = (mask & *a) != 0; | ||
| 164 | *a ^= mask; | ||
| 165 | local_irq_restore_hw(flags); | ||
| 166 | return retval; | ||
| 167 | } | ||
| 168 | |||
| 169 | #endif /* CONFIG_SMP */ | ||
| 170 | |||
| 171 | /* | 78 | /* |
| 172 | * clear_bit() doesn't provide any barrier for the compiler. | 79 | * clear_bit() doesn't provide any barrier for the compiler. |
| 173 | */ | 80 | */ |
| 174 | #define smp_mb__before_clear_bit() barrier() | 81 | #define smp_mb__before_clear_bit() barrier() |
| 175 | #define smp_mb__after_clear_bit() barrier() | 82 | #define smp_mb__after_clear_bit() barrier() |
| 176 | 83 | ||
| 177 | static inline void __set_bit(int nr, volatile unsigned long *addr) | 84 | #include <asm-generic/bitops/non-atomic.h> |
| 178 | { | ||
| 179 | int *a = (int *)addr; | ||
| 180 | int mask; | ||
| 181 | |||
| 182 | a += nr >> 5; | ||
| 183 | mask = 1 << (nr & 0x1f); | ||
| 184 | *a |= mask; | ||
| 185 | } | ||
| 186 | |||
| 187 | static inline void __clear_bit(int nr, volatile unsigned long *addr) | ||
| 188 | { | ||
| 189 | int *a = (int *)addr; | ||
| 190 | int mask; | ||
| 191 | |||
| 192 | a += nr >> 5; | ||
| 193 | mask = 1 << (nr & 0x1f); | ||
| 194 | *a &= ~mask; | ||
| 195 | } | ||
| 196 | |||
| 197 | static inline void __change_bit(int nr, volatile unsigned long *addr) | ||
| 198 | { | ||
| 199 | int mask; | ||
| 200 | unsigned long *ADDR = (unsigned long *)addr; | ||
| 201 | |||
| 202 | ADDR += nr >> 5; | ||
| 203 | mask = 1 << (nr & 31); | ||
| 204 | *ADDR ^= mask; | ||
| 205 | } | ||
| 206 | |||
| 207 | static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) | ||
| 208 | { | ||
| 209 | int mask, retval; | ||
| 210 | volatile unsigned int *a = (volatile unsigned int *)addr; | ||
| 211 | |||
| 212 | a += nr >> 5; | ||
| 213 | mask = 1 << (nr & 0x1f); | ||
| 214 | retval = (mask & *a) != 0; | ||
| 215 | *a |= mask; | ||
| 216 | return retval; | ||
| 217 | } | ||
| 218 | |||
| 219 | static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) | ||
| 220 | { | ||
| 221 | int mask, retval; | ||
| 222 | volatile unsigned int *a = (volatile unsigned int *)addr; | ||
| 223 | |||
| 224 | a += nr >> 5; | ||
| 225 | mask = 1 << (nr & 0x1f); | ||
| 226 | retval = (mask & *a) != 0; | ||
| 227 | *a &= ~mask; | ||
| 228 | return retval; | ||
| 229 | } | ||
| 230 | |||
| 231 | static inline int __test_and_change_bit(int nr, | ||
| 232 | volatile unsigned long *addr) | ||
| 233 | { | ||
| 234 | int mask, retval; | ||
| 235 | volatile unsigned int *a = (volatile unsigned int *)addr; | ||
| 236 | |||
| 237 | a += nr >> 5; | ||
| 238 | mask = 1 << (nr & 0x1f); | ||
| 239 | retval = (mask & *a) != 0; | ||
| 240 | *a ^= mask; | ||
| 241 | return retval; | ||
| 242 | } | ||
| 243 | |||
| 244 | static inline int __test_bit(int nr, const void *addr) | ||
| 245 | { | ||
| 246 | int *a = (int *)addr; | ||
| 247 | int mask; | ||
| 248 | |||
| 249 | a += nr >> 5; | ||
| 250 | mask = 1 << (nr & 0x1f); | ||
| 251 | return ((mask & *a) != 0); | ||
| 252 | } | ||
| 253 | |||
| 254 | #ifndef CONFIG_SMP | ||
| 255 | /* | ||
| 256 | * This routine doesn't need irq save and restore ops in UP | ||
| 257 | * context. | ||
| 258 | */ | ||
| 259 | static inline int test_bit(int nr, const void *addr) | ||
| 260 | { | ||
| 261 | return __test_bit(nr, addr); | ||
| 262 | } | ||
| 263 | #endif | ||
| 264 | 85 | ||
| 265 | #include <asm-generic/bitops/find.h> | 86 | #include <asm-generic/bitops/find.h> |
| 266 | #include <asm-generic/bitops/hweight.h> | 87 | #include <asm-generic/bitops/hweight.h> |
| @@ -271,10 +92,10 @@ static inline int test_bit(int nr, const void *addr) | |||
| 271 | 92 | ||
| 272 | #include <asm-generic/bitops/minix.h> | 93 | #include <asm-generic/bitops/minix.h> |
| 273 | 94 | ||
| 274 | #endif /* __KERNEL__ */ | ||
| 275 | |||
| 276 | #include <asm-generic/bitops/fls.h> | 95 | #include <asm-generic/bitops/fls.h> |
| 277 | #include <asm-generic/bitops/__fls.h> | 96 | #include <asm-generic/bitops/__fls.h> |
| 278 | #include <asm-generic/bitops/fls64.h> | 97 | #include <asm-generic/bitops/fls64.h> |
| 279 | 98 | ||
| 99 | #endif /* CONFIG_SMP */ | ||
| 100 | |||
| 280 | #endif /* _BLACKFIN_BITOPS_H */ | 101 | #endif /* _BLACKFIN_BITOPS_H */ |
diff --git a/arch/blackfin/include/asm/bitsperlong.h b/arch/blackfin/include/asm/bitsperlong.h new file mode 100644 index 000000000000..6dc0bb0c13b2 --- /dev/null +++ b/arch/blackfin/include/asm/bitsperlong.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/bitsperlong.h> | |||
diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h index 6d3e11b1fc57..655e49540e41 100644 --- a/arch/blackfin/include/asm/bug.h +++ b/arch/blackfin/include/asm/bug.h | |||
| @@ -2,13 +2,58 @@ | |||
| 2 | #define _BLACKFIN_BUG_H | 2 | #define _BLACKFIN_BUG_H |
| 3 | 3 | ||
| 4 | #ifdef CONFIG_BUG | 4 | #ifdef CONFIG_BUG |
| 5 | #define HAVE_ARCH_BUG | ||
| 6 | 5 | ||
| 7 | #define BUG() do { \ | 6 | #define BFIN_BUG_OPCODE 0xefcd |
| 8 | dump_bfin_trace_buffer(); \ | 7 | |
| 9 | printk(KERN_EMERG "BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \ | 8 | #ifdef CONFIG_DEBUG_BUGVERBOSE |
| 10 | panic("BUG!"); \ | 9 | |
| 11 | } while (0) | 10 | #define _BUG_OR_WARN(flags) \ |
| 11 | asm volatile( \ | ||
| 12 | "1: .hword %0\n" \ | ||
| 13 | " .section __bug_table,\"a\",@progbits\n" \ | ||
| 14 | "2: .long 1b\n" \ | ||
| 15 | " .long %1\n" \ | ||
| 16 | " .short %2\n" \ | ||
| 17 | " .short %3\n" \ | ||
| 18 | " .org 2b + %4\n" \ | ||
| 19 | " .previous" \ | ||
| 20 | : \ | ||
| 21 | : "i"(BFIN_BUG_OPCODE), "i"(__FILE__), \ | ||
| 22 | "i"(__LINE__), "i"(flags), \ | ||
| 23 | "i"(sizeof(struct bug_entry))) | ||
| 24 | |||
| 25 | #else | ||
| 26 | |||
| 27 | #define _BUG_OR_WARN(flags) \ | ||
| 28 | asm volatile( \ | ||
| 29 | "1: .hword %0\n" \ | ||
| 30 | " .section __bug_table,\"a\",@progbits\n" \ | ||
| 31 | "2: .long 1b\n" \ | ||
| 32 | " .short %1\n" \ | ||
| 33 | " .org 2b + %2\n" \ | ||
| 34 | " .previous" \ | ||
| 35 | : \ | ||
| 36 | : "i"(BFIN_BUG_OPCODE), "i"(flags), \ | ||
| 37 | "i"(sizeof(struct bug_entry))) | ||
| 38 | |||
| 39 | #endif /* CONFIG_DEBUG_BUGVERBOSE */ | ||
| 40 | |||
| 41 | #define BUG() \ | ||
| 42 | do { \ | ||
| 43 | _BUG_OR_WARN(0); \ | ||
| 44 | for (;;); \ | ||
| 45 | } while (0) | ||
| 46 | |||
| 47 | #define WARN_ON(condition) \ | ||
| 48 | ({ \ | ||
| 49 | int __ret_warn_on = !!(condition); \ | ||
| 50 | if (unlikely(__ret_warn_on)) \ | ||
| 51 | _BUG_OR_WARN(BUGFLAG_WARNING); \ | ||
| 52 | unlikely(__ret_warn_on); \ | ||
| 53 | }) | ||
| 54 | |||
| 55 | #define HAVE_ARCH_BUG | ||
| 56 | #define HAVE_ARCH_WARN_ON | ||
| 12 | 57 | ||
| 13 | #endif | 58 | #endif |
| 14 | 59 | ||
diff --git a/arch/blackfin/include/asm/bugs.h b/arch/blackfin/include/asm/bugs.h index 9093c9c1fb81..61791e1ad9f5 100644 --- a/arch/blackfin/include/asm/bugs.h +++ b/arch/blackfin/include/asm/bugs.h | |||
| @@ -1,16 +1 @@ | |||
| 1 | /* | #include <asm-generic/bugs.h> | |
| 2 | * include/asm-blackfin/bugs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1994 Linus Torvalds | ||
| 5 | */ | ||
| 6 | |||
| 7 | /* | ||
| 8 | * This is included by init/main.c to check for architecture-dependent bugs. | ||
| 9 | * | ||
| 10 | * Needs: | ||
| 11 | * void check_bugs(void); | ||
| 12 | */ | ||
| 13 | |||
| 14 | static void check_bugs(void) | ||
| 15 | { | ||
| 16 | } | ||
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h index 86637814cf25..2ef669ed9222 100644 --- a/arch/blackfin/include/asm/cache.h +++ b/arch/blackfin/include/asm/cache.h | |||
| @@ -34,9 +34,13 @@ | |||
| 34 | #define L1_CACHE_SHIFT_MAX 5 | 34 | #define L1_CACHE_SHIFT_MAX 5 |
| 35 | 35 | ||
| 36 | #if defined(CONFIG_SMP) && \ | 36 | #if defined(CONFIG_SMP) && \ |
| 37 | !defined(CONFIG_BFIN_CACHE_COHERENT) && \ | 37 | !defined(CONFIG_BFIN_CACHE_COHERENT) |
| 38 | defined(CONFIG_BFIN_DCACHE) | 38 | # if defined(CONFIG_BFIN_ICACHE) |
| 39 | #define __ARCH_SYNC_CORE_DCACHE | 39 | # define __ARCH_SYNC_CORE_ICACHE |
| 40 | # endif | ||
| 41 | # if defined(CONFIG_BFIN_DCACHE) | ||
| 42 | # define __ARCH_SYNC_CORE_DCACHE | ||
| 43 | # endif | ||
| 40 | #ifndef __ASSEMBLY__ | 44 | #ifndef __ASSEMBLY__ |
| 41 | asmlinkage void __raw_smp_mark_barrier_asm(void); | 45 | asmlinkage void __raw_smp_mark_barrier_asm(void); |
| 42 | asmlinkage void __raw_smp_check_barrier_asm(void); | 46 | asmlinkage void __raw_smp_check_barrier_asm(void); |
| @@ -51,6 +55,7 @@ static inline void smp_check_barrier(void) | |||
| 51 | } | 55 | } |
| 52 | 56 | ||
| 53 | void resync_core_dcache(void); | 57 | void resync_core_dcache(void); |
| 58 | void resync_core_icache(void); | ||
| 54 | #endif | 59 | #endif |
| 55 | #endif | 60 | #endif |
| 56 | 61 | ||
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h index 1b040f5b4feb..5c17dee53b5d 100644 --- a/arch/blackfin/include/asm/cacheflush.h +++ b/arch/blackfin/include/asm/cacheflush.h | |||
| @@ -30,12 +30,14 @@ | |||
| 30 | #ifndef _BLACKFIN_CACHEFLUSH_H | 30 | #ifndef _BLACKFIN_CACHEFLUSH_H |
| 31 | #define _BLACKFIN_CACHEFLUSH_H | 31 | #define _BLACKFIN_CACHEFLUSH_H |
| 32 | 32 | ||
| 33 | extern void blackfin_icache_dcache_flush_range(unsigned long start_address, unsigned long end_address); | 33 | #include <asm/blackfin.h> /* for SSYNC() */ |
| 34 | |||
| 34 | extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); | 35 | extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); |
| 35 | extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); | 36 | extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); |
| 36 | extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address); | 37 | extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address); |
| 37 | extern void blackfin_dflush_page(void *page); | 38 | extern void blackfin_dflush_page(void *page); |
| 38 | extern void blackfin_invalidate_entire_dcache(void); | 39 | extern void blackfin_invalidate_entire_dcache(void); |
| 40 | extern void blackfin_invalidate_entire_icache(void); | ||
| 39 | 41 | ||
| 40 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | 42 | #define flush_dcache_mmap_lock(mapping) do { } while (0) |
| 41 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | 43 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) |
| @@ -54,32 +56,28 @@ extern void blackfin_invalidate_entire_dcache(void); | |||
| 54 | 56 | ||
| 55 | static inline void flush_icache_range(unsigned start, unsigned end) | 57 | static inline void flush_icache_range(unsigned start, unsigned end) |
| 56 | { | 58 | { |
| 57 | #if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE) | 59 | #if defined(CONFIG_BFIN_WB) |
| 58 | 60 | blackfin_dcache_flush_range(start, end); | |
| 59 | # if defined(CONFIG_BFIN_WT) | 61 | #endif |
| 60 | blackfin_icache_flush_range((start), (end)); | ||
| 61 | flush_icache_range_others(start, end); | ||
| 62 | # else | ||
| 63 | blackfin_icache_dcache_flush_range((start), (end)); | ||
| 64 | # endif | ||
| 65 | |||
| 66 | #else | ||
| 67 | 62 | ||
| 68 | # if defined(CONFIG_BFIN_ICACHE) | 63 | /* Make sure all write buffers in the data side of the core |
| 69 | blackfin_icache_flush_range((start), (end)); | 64 | * are flushed before trying to invalidate the icache. This |
| 65 | * needs to be after the data flush and before the icache | ||
| 66 | * flush so that the SSYNC does the right thing in preventing | ||
| 67 | * the instruction prefetcher from hitting things in cached | ||
| 68 | * memory at the wrong time -- it runs much further ahead than | ||
| 69 | * the pipeline. | ||
| 70 | */ | ||
| 71 | SSYNC(); | ||
| 72 | #if defined(CONFIG_BFIN_ICACHE) | ||
| 73 | blackfin_icache_flush_range(start, end); | ||
| 70 | flush_icache_range_others(start, end); | 74 | flush_icache_range_others(start, end); |
| 71 | # endif | ||
| 72 | # if defined(CONFIG_BFIN_DCACHE) | ||
| 73 | blackfin_dcache_flush_range((start), (end)); | ||
| 74 | # endif | ||
| 75 | |||
| 76 | #endif | 75 | #endif |
| 77 | } | 76 | } |
| 78 | 77 | ||
| 79 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ | 78 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ |
| 80 | do { memcpy(dst, src, len); \ | 79 | do { memcpy(dst, src, len); \ |
| 81 | flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ | 80 | flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ |
| 82 | flush_icache_range_others((unsigned long) (dst), (unsigned long) (dst) + (len));\ | ||
| 83 | } while (0) | 81 | } while (0) |
| 84 | 82 | ||
| 85 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) | 83 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) |
| @@ -100,7 +98,7 @@ do { memcpy(dst, src, len); \ | |||
| 100 | extern unsigned long reserved_mem_dcache_on; | 98 | extern unsigned long reserved_mem_dcache_on; |
| 101 | extern unsigned long reserved_mem_icache_on; | 99 | extern unsigned long reserved_mem_icache_on; |
| 102 | 100 | ||
| 103 | static inline int bfin_addr_dcachable(unsigned long addr) | 101 | static inline int bfin_addr_dcacheable(unsigned long addr) |
| 104 | { | 102 | { |
| 105 | #ifdef CONFIG_BFIN_DCACHE | 103 | #ifdef CONFIG_BFIN_DCACHE |
| 106 | if (addr < (_ramend - DMA_UNCACHED_REGION)) | 104 | if (addr < (_ramend - DMA_UNCACHED_REGION)) |
| @@ -111,6 +109,11 @@ static inline int bfin_addr_dcachable(unsigned long addr) | |||
| 111 | addr >= _ramend && addr < physical_mem_end) | 109 | addr >= _ramend && addr < physical_mem_end) |
| 112 | return 1; | 110 | return 1; |
| 113 | 111 | ||
| 112 | #ifndef CONFIG_BFIN_L2_NOT_CACHED | ||
| 113 | if (addr >= L2_START && addr < L2_START + L2_LENGTH) | ||
| 114 | return 1; | ||
| 115 | #endif | ||
| 116 | |||
| 114 | return 0; | 117 | return 0; |
| 115 | } | 118 | } |
| 116 | 119 | ||
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index ad566ff9ad16..a75a6a9f0949 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h | |||
| @@ -53,29 +53,32 @@ | |||
| 53 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) | 53 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) |
| 54 | #endif | 54 | #endif |
| 55 | 55 | ||
| 56 | #define SDRAM_DNON_CHBL (CPLB_COMMON) | ||
| 57 | #define SDRAM_EBIU (CPLB_COMMON) | ||
| 58 | #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) | ||
| 59 | |||
| 56 | #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) | 60 | #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) |
| 57 | 61 | ||
| 58 | #ifdef CONFIG_SMP | 62 | #ifdef CONFIG_SMP |
| 59 | #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) | 63 | #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) |
| 60 | #define L2_IMEMORY (CPLB_COMMON | CPLB_LOCK) | 64 | #define L2_IMEMORY (CPLB_COMMON) |
| 61 | #define L2_DMEMORY (CPLB_COMMON | CPLB_LOCK) | 65 | #define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON) |
| 62 | 66 | ||
| 63 | #else | 67 | #else |
| 64 | #ifdef CONFIG_BFIN_L2_CACHEABLE | 68 | #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) |
| 65 | #define L2_IMEMORY (SDRAM_IGENERIC) | 69 | #define L2_IMEMORY (SDRAM_IGENERIC) |
| 66 | #define L2_DMEMORY (SDRAM_DGENERIC) | 70 | |
| 67 | #else | 71 | # if defined(CONFIG_BFIN_L2_WB) |
| 68 | #define L2_IMEMORY (CPLB_COMMON) | 72 | # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON) |
| 69 | #define L2_DMEMORY (CPLB_COMMON) | 73 | # elif defined(CONFIG_BFIN_L2_WT) |
| 70 | #endif /* CONFIG_BFIN_L2_CACHEABLE */ | 74 | # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) |
| 71 | 75 | # elif defined(CONFIG_BFIN_L2_NOT_CACHED) | |
| 72 | #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) | 76 | # define L2_DMEMORY (CPLB_COMMON) |
| 77 | # else | ||
| 78 | # define L2_DMEMORY (0) | ||
| 79 | # endif | ||
| 73 | #endif /* CONFIG_SMP */ | 80 | #endif /* CONFIG_SMP */ |
| 74 | 81 | ||
| 75 | #define SDRAM_DNON_CHBL (CPLB_COMMON) | ||
| 76 | #define SDRAM_EBIU (CPLB_COMMON) | ||
| 77 | #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) | ||
| 78 | |||
| 79 | #define SIZE_1K 0x00000400 /* 1K */ | 82 | #define SIZE_1K 0x00000400 /* 1K */ |
| 80 | #define SIZE_4K 0x00001000 /* 4K */ | 83 | #define SIZE_4K 0x00001000 /* 4K */ |
| 81 | #define SIZE_1M 0x00100000 /* 1M */ | 84 | #define SIZE_1M 0x00100000 /* 1M */ |
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h index c2594ef877f6..565b8136855e 100644 --- a/arch/blackfin/include/asm/cpu.h +++ b/arch/blackfin/include/asm/cpu.h | |||
| @@ -34,6 +34,7 @@ struct blackfin_cpudata { | |||
| 34 | unsigned int dmemctl; | 34 | unsigned int dmemctl; |
| 35 | unsigned long loops_per_jiffy; | 35 | unsigned long loops_per_jiffy; |
| 36 | unsigned long dcache_invld_count; | 36 | unsigned long dcache_invld_count; |
| 37 | unsigned long icache_invld_count; | ||
| 37 | }; | 38 | }; |
| 38 | 39 | ||
| 39 | DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data); | 40 | DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data); |
diff --git a/arch/blackfin/include/asm/cputime.h b/arch/blackfin/include/asm/cputime.h index 2b19705f9885..6d68ad7e0ea3 100644 --- a/arch/blackfin/include/asm/cputime.h +++ b/arch/blackfin/include/asm/cputime.h | |||
| @@ -1,6 +1 @@ | |||
| 1 | #ifndef __BLACKFIN_CPUTIME_H | ||
| 2 | #define __BLACKFIN_CPUTIME_H | ||
| 3 | |||
| 4 | #include <asm-generic/cputime.h> | #include <asm-generic/cputime.h> | |
| 5 | |||
| 6 | #endif /* __BLACKFIN_CPUTIME_H */ | ||
diff --git a/arch/blackfin/include/asm/current.h b/arch/blackfin/include/asm/current.h index 31918d29122c..4c51401b5537 100644 --- a/arch/blackfin/include/asm/current.h +++ b/arch/blackfin/include/asm/current.h | |||
| @@ -1,23 +1 @@ | |||
| 1 | #ifndef _BLACKFIN_CURRENT_H | #include <asm-generic/current.h> | |
| 2 | #define _BLACKFIN_CURRENT_H | ||
| 3 | /* | ||
| 4 | * current.h | ||
| 5 | * (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com> | ||
| 6 | * | ||
| 7 | * rather than dedicate a register (as the m68k source does), we | ||
| 8 | * just keep a global, we should probably just change it all to be | ||
| 9 | * current and lose _current_task. | ||
| 10 | */ | ||
| 11 | #include <linux/thread_info.h> | ||
| 12 | |||
| 13 | struct task_struct; | ||
| 14 | |||
| 15 | static inline struct task_struct *get_current(void) __attribute__ ((__const__)); | ||
| 16 | static inline struct task_struct *get_current(void) | ||
| 17 | { | ||
| 18 | return (current_thread_info()->task); | ||
| 19 | } | ||
| 20 | |||
| 21 | #define current (get_current()) | ||
| 22 | |||
| 23 | #endif /* _BLACKFIN_CURRENT_H */ | ||
diff --git a/arch/blackfin/include/asm/device.h b/arch/blackfin/include/asm/device.h index d8f9872b0e2d..f0a4c256403b 100644 --- a/arch/blackfin/include/asm/device.h +++ b/arch/blackfin/include/asm/device.h | |||
| @@ -1,7 +1 @@ | |||
| 1 | /* | ||
| 2 | * Arch specific extensions to struct device | ||
| 3 | * | ||
| 4 | * This file is released under the GPLv2 | ||
| 5 | */ | ||
| 6 | #include <asm-generic/device.h> | #include <asm-generic/device.h> | |
| 7 | |||
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h index e4f7b8043f02..c9a59622e23f 100644 --- a/arch/blackfin/include/asm/dma.h +++ b/arch/blackfin/include/asm/dma.h | |||
| @@ -206,10 +206,16 @@ static inline unsigned long get_dma_curr_addr(unsigned int channel) | |||
| 206 | 206 | ||
| 207 | static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize) | 207 | static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize) |
| 208 | { | 208 | { |
| 209 | /* Make sure the internal data buffers in the core are drained | ||
| 210 | * so that the DMA descriptors are completely written when the | ||
| 211 | * DMA engine goes to fetch them below. | ||
| 212 | */ | ||
| 213 | SSYNC(); | ||
| 214 | |||
| 215 | dma_ch[channel].regs->next_desc_ptr = sg; | ||
| 209 | dma_ch[channel].regs->cfg = | 216 | dma_ch[channel].regs->cfg = |
| 210 | (dma_ch[channel].regs->cfg & ~(0xf << 8)) | | 217 | (dma_ch[channel].regs->cfg & ~(0xf << 8)) | |
| 211 | ((ndsize & 0xf) << 8); | 218 | ((ndsize & 0xf) << 8); |
| 212 | dma_ch[channel].regs->next_desc_ptr = sg; | ||
| 213 | } | 219 | } |
| 214 | 220 | ||
| 215 | static inline int dma_channel_active(unsigned int channel) | 221 | static inline int dma_channel_active(unsigned int channel) |
| @@ -253,5 +259,7 @@ static inline void clear_dma_irqstat(unsigned int channel) | |||
| 253 | void *dma_memcpy(void *dest, const void *src, size_t count); | 259 | void *dma_memcpy(void *dest, const void *src, size_t count); |
| 254 | void *safe_dma_memcpy(void *dest, const void *src, size_t count); | 260 | void *safe_dma_memcpy(void *dest, const void *src, size_t count); |
| 255 | void blackfin_dma_early_init(void); | 261 | void blackfin_dma_early_init(void); |
| 262 | void early_dma_memcpy(void *dest, const void *src, size_t count); | ||
| 263 | void early_dma_memcpy_done(void); | ||
| 256 | 264 | ||
| 257 | #endif | 265 | #endif |
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h index cdbfcfc30f6a..5a87baf0659d 100644 --- a/arch/blackfin/include/asm/elf.h +++ b/arch/blackfin/include/asm/elf.h | |||
| @@ -20,7 +20,7 @@ | |||
| 20 | 20 | ||
| 21 | typedef unsigned long elf_greg_t; | 21 | typedef unsigned long elf_greg_t; |
| 22 | 22 | ||
| 23 | #define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) | 23 | #define ELF_NGREG 40 /* (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) */ |
| 24 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | 24 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; |
| 25 | 25 | ||
| 26 | typedef struct user_bfinfp_struct elf_fpregset_t; | 26 | typedef struct user_bfinfp_struct elf_fpregset_t; |
| @@ -55,50 +55,50 @@ do { \ | |||
| 55 | #define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC | 55 | #define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC |
| 56 | #define ELF_EXEC_PAGESIZE 4096 | 56 | #define ELF_EXEC_PAGESIZE 4096 |
| 57 | 57 | ||
| 58 | #define R_unused0 0 /* relocation type 0 is not defined */ | 58 | #define R_BFIN_UNUSED0 0 /* relocation type 0 is not defined */ |
| 59 | #define R_pcrel5m2 1 /*LSETUP part a */ | 59 | #define R_BFIN_PCREL5M2 1 /* LSETUP part a */ |
| 60 | #define R_unused1 2 /* relocation type 2 is not defined */ | 60 | #define R_BFIN_UNUSED1 2 /* relocation type 2 is not defined */ |
| 61 | #define R_pcrel10 3 /* type 3, if cc jump <target> */ | 61 | #define R_BFIN_PCREL10 3 /* type 3, if cc jump <target> */ |
| 62 | #define R_pcrel12_jump 4 /* type 4, jump <target> */ | 62 | #define R_BFIN_PCREL12_JUMP 4 /* type 4, jump <target> */ |
| 63 | #define R_rimm16 5 /* type 0x5, rN = <target> */ | 63 | #define R_BFIN_RIMM16 5 /* type 0x5, rN = <target> */ |
| 64 | #define R_luimm16 6 /* # 0x6, preg.l=<target> Load imm 16 to lower half */ | 64 | #define R_BFIN_LUIMM16 6 /* # 0x6, preg.l=<target> Load imm 16 to lower half */ |
| 65 | #define R_huimm16 7 /* # 0x7, preg.h=<target> Load imm 16 to upper half */ | 65 | #define R_BFIN_HUIMM16 7 /* # 0x7, preg.h=<target> Load imm 16 to upper half */ |
| 66 | #define R_pcrel12_jump_s 8 /* # 0x8 jump.s <target> */ | 66 | #define R_BFIN_PCREL12_JUMP_S 8 /* # 0x8 jump.s <target> */ |
| 67 | #define R_pcrel24_jump_x 9 /* # 0x9 jump.x <target> */ | 67 | #define R_BFIN_PCREL24_JUMP_X 9 /* # 0x9 jump.x <target> */ |
| 68 | #define R_pcrel24 10 /* # 0xa call <target> , not expandable */ | 68 | #define R_BFIN_PCREL24 10 /* # 0xa call <target> , not expandable */ |
| 69 | #define R_unusedb 11 /* # 0xb not generated */ | 69 | #define R_BFIN_UNUSEDB 11 /* # 0xb not generated */ |
| 70 | #define R_unusedc 12 /* # 0xc not used */ | 70 | #define R_BFIN_UNUSEDC 12 /* # 0xc not used */ |
| 71 | #define R_pcrel24_jump_l 13 /*0xd jump.l <target> */ | 71 | #define R_BFIN_PCREL24_JUMP_L 13 /* 0xd jump.l <target> */ |
| 72 | #define R_pcrel24_call_x 14 /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */ | 72 | #define R_BFIN_PCREL24_CALL_X 14 /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */ |
| 73 | #define R_var_eq_symb 15 /* 0xf, linker should treat it same as 0x12 */ | 73 | #define R_BFIN_VAR_EQ_SYMB 15 /* 0xf, linker should treat it same as 0x12 */ |
| 74 | #define R_byte_data 16 /* 0x10, .byte var = symbol */ | 74 | #define R_BFIN_BYTE_DATA 16 /* 0x10, .byte var = symbol */ |
| 75 | #define R_byte2_data 17 /* 0x11, .byte2 var = symbol */ | 75 | #define R_BFIN_BYTE2_DATA 17 /* 0x11, .byte2 var = symbol */ |
| 76 | #define R_byte4_data 18 /* 0x12, .byte4 var = symbol and .var var=symbol */ | 76 | #define R_BFIN_BYTE4_DATA 18 /* 0x12, .byte4 var = symbol and .var var=symbol */ |
| 77 | #define R_pcrel11 19 /* 0x13, lsetup part b */ | 77 | #define R_BFIN_PCREL11 19 /* 0x13, lsetup part b */ |
| 78 | #define R_unused14 20 /* 0x14, undefined */ | 78 | #define R_BFIN_UNUSED14 20 /* 0x14, undefined */ |
| 79 | #define R_unused15 21 /* not generated by VDSP 3.5 */ | 79 | #define R_BFIN_UNUSED15 21 /* not generated by VDSP 3.5 */ |
| 80 | 80 | ||
| 81 | /* arithmetic relocations */ | 81 | /* arithmetic relocations */ |
| 82 | #define R_push 0xE0 | 82 | #define R_BFIN_PUSH 0xE0 |
| 83 | #define R_const 0xE1 | 83 | #define R_BFIN_CONST 0xE1 |
| 84 | #define R_add 0xE2 | 84 | #define R_BFIN_ADD 0xE2 |
| 85 | #define R_sub 0xE3 | 85 | #define R_BFIN_SUB 0xE3 |
| 86 | #define R_mult 0xE4 | 86 | #define R_BFIN_MULT 0xE4 |
| 87 | #define R_div 0xE5 | 87 | #define R_BFIN_DIV 0xE5 |
| 88 | #define R_mod 0xE6 | 88 | #define R_BFIN_MOD 0xE6 |
| 89 | #define R_lshift 0xE7 | 89 | #define R_BFIN_LSHIFT 0xE7 |
| 90 | #define R_rshift 0xE8 | 90 | #define R_BFIN_RSHIFT 0xE8 |
| 91 | #define R_and 0xE9 | 91 | #define R_BFIN_AND 0xE9 |
| 92 | #define R_or 0xEA | 92 | #define R_BFIN_OR 0xEA |
| 93 | #define R_xor 0xEB | 93 | #define R_BFIN_XOR 0xEB |
| 94 | #define R_land 0xEC | 94 | #define R_BFIN_LAND 0xEC |
| 95 | #define R_lor 0xED | 95 | #define R_BFIN_LOR 0xED |
| 96 | #define R_len 0xEE | 96 | #define R_BFIN_LEN 0xEE |
| 97 | #define R_neg 0xEF | 97 | #define R_BFIN_NEG 0xEF |
| 98 | #define R_comp 0xF0 | 98 | #define R_BFIN_COMP 0xF0 |
| 99 | #define R_page 0xF1 | 99 | #define R_BFIN_PAGE 0xF1 |
| 100 | #define R_hwpage 0xF2 | 100 | #define R_BFIN_HWPAGE 0xF2 |
| 101 | #define R_addr 0xF3 | 101 | #define R_BFIN_ADDR 0xF3 |
| 102 | 102 | ||
| 103 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical | 103 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical |
| 104 | use of this is to invoke "./ld.so someprog" to test out a new version of | 104 | use of this is to invoke "./ld.so someprog" to test out a new version of |
diff --git a/arch/blackfin/include/asm/emergency-restart.h b/arch/blackfin/include/asm/emergency-restart.h index 27f6c785d103..3711bd9d50bd 100644 --- a/arch/blackfin/include/asm/emergency-restart.h +++ b/arch/blackfin/include/asm/emergency-restart.h | |||
| @@ -1,6 +1 @@ | |||
| 1 | #ifndef _ASM_EMERGENCY_RESTART_H | ||
| 2 | #define _ASM_EMERGENCY_RESTART_H | ||
| 3 | |||
| 4 | #include <asm-generic/emergency-restart.h> | #include <asm-generic/emergency-restart.h> | |
| 5 | |||
| 6 | #endif /* _ASM_EMERGENCY_RESTART_H */ | ||
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h index b30a2968e274..ec58efc130e6 100644 --- a/arch/blackfin/include/asm/entry.h +++ b/arch/blackfin/include/asm/entry.h | |||
| @@ -35,21 +35,39 @@ | |||
| 35 | #else | 35 | #else |
| 36 | # define LOAD_IPIPE_IPEND | 36 | # define LOAD_IPIPE_IPEND |
| 37 | #endif | 37 | #endif |
| 38 | |||
| 39 | #ifndef CONFIG_EXACT_HWERR | ||
| 40 | /* As a debugging aid - we save IPEND when DEBUG_KERNEL is on, | ||
| 41 | * otherwise it is a waste of cycles. | ||
| 42 | */ | ||
| 43 | # ifndef CONFIG_DEBUG_KERNEL | ||
| 44 | #define INTERRUPT_ENTRY(N) \ | ||
| 45 | [--sp] = SYSCFG; \ | ||
| 46 | [--sp] = P0; /*orig_p0*/ \ | ||
| 47 | [--sp] = R0; /*orig_r0*/ \ | ||
| 48 | [--sp] = (R7:0,P5:0); \ | ||
| 49 | R0 = (N); \ | ||
| 50 | LOAD_IPIPE_IPEND \ | ||
| 51 | jump __common_int_entry; | ||
| 52 | # else /* CONFIG_DEBUG_KERNEL */ | ||
| 38 | #define INTERRUPT_ENTRY(N) \ | 53 | #define INTERRUPT_ENTRY(N) \ |
| 39 | [--sp] = SYSCFG; \ | 54 | [--sp] = SYSCFG; \ |
| 40 | \ | ||
| 41 | [--sp] = P0; /*orig_p0*/ \ | 55 | [--sp] = P0; /*orig_p0*/ \ |
| 42 | [--sp] = R0; /*orig_r0*/ \ | 56 | [--sp] = R0; /*orig_r0*/ \ |
| 43 | [--sp] = (R7:0,P5:0); \ | 57 | [--sp] = (R7:0,P5:0); \ |
| 58 | p0.l = lo(IPEND); \ | ||
| 59 | p0.h = hi(IPEND); \ | ||
| 60 | r1 = [p0]; \ | ||
| 44 | R0 = (N); \ | 61 | R0 = (N); \ |
| 45 | LOAD_IPIPE_IPEND \ | 62 | LOAD_IPIPE_IPEND \ |
| 46 | jump __common_int_entry; | 63 | jump __common_int_entry; |
| 64 | # endif /* CONFIG_DEBUG_KERNEL */ | ||
| 47 | 65 | ||
| 48 | /* For timer interrupts, we need to save IPEND, since the user_mode | 66 | /* For timer interrupts, we need to save IPEND, since the user_mode |
| 49 | macro accesses it to determine where to account time. */ | 67 | *macro accesses it to determine where to account time. |
| 68 | */ | ||
| 50 | #define TIMER_INTERRUPT_ENTRY(N) \ | 69 | #define TIMER_INTERRUPT_ENTRY(N) \ |
| 51 | [--sp] = SYSCFG; \ | 70 | [--sp] = SYSCFG; \ |
| 52 | \ | ||
| 53 | [--sp] = P0; /*orig_p0*/ \ | 71 | [--sp] = P0; /*orig_p0*/ \ |
| 54 | [--sp] = R0; /*orig_r0*/ \ | 72 | [--sp] = R0; /*orig_r0*/ \ |
| 55 | [--sp] = (R7:0,P5:0); \ | 73 | [--sp] = (R7:0,P5:0); \ |
| @@ -58,6 +76,74 @@ | |||
| 58 | r1 = [p0]; \ | 76 | r1 = [p0]; \ |
| 59 | R0 = (N); \ | 77 | R0 = (N); \ |
| 60 | jump __common_int_entry; | 78 | jump __common_int_entry; |
| 79 | #else /* CONFIG_EXACT_HWERR is defined */ | ||
| 80 | |||
| 81 | /* if we want hardware error to be exact, we need to do a SSYNC (which forces | ||
| 82 | * read/writes to complete to the memory controllers), and check to see that | ||
| 83 | * caused a pending HW error condition. If so, we assume it was caused by user | ||
| 84 | * space, by setting the same interrupt that we are in (so it goes off again) | ||
| 85 | * and context restore, and a RTI (without servicing anything). This should | ||
| 86 | * cause the pending HWERR to fire, and when that is done, this interrupt will | ||
| 87 | * be re-serviced properly. | ||
| 88 | * As you can see by the code - we actually need to do two SSYNCS - one to | ||
| 89 | * make sure the read/writes complete, and another to make sure the hardware | ||
| 90 | * error is recognized by the core. | ||
| 91 | */ | ||
| 92 | #define INTERRUPT_ENTRY(N) \ | ||
| 93 | SSYNC; \ | ||
| 94 | SSYNC; \ | ||
| 95 | [--sp] = SYSCFG; \ | ||
| 96 | [--sp] = P0; /*orig_p0*/ \ | ||
| 97 | [--sp] = R0; /*orig_r0*/ \ | ||
| 98 | [--sp] = (R7:0,P5:0); \ | ||
| 99 | R1 = ASTAT; \ | ||
| 100 | P0.L = LO(ILAT); \ | ||
| 101 | P0.H = HI(ILAT); \ | ||
| 102 | R0 = [P0]; \ | ||
| 103 | CC = BITTST(R0, EVT_IVHW_P); \ | ||
| 104 | IF CC JUMP 1f; \ | ||
| 105 | ASTAT = R1; \ | ||
| 106 | p0.l = lo(IPEND); \ | ||
| 107 | p0.h = hi(IPEND); \ | ||
| 108 | r1 = [p0]; \ | ||
| 109 | R0 = (N); \ | ||
| 110 | LOAD_IPIPE_IPEND \ | ||
| 111 | jump __common_int_entry; \ | ||
| 112 | 1: ASTAT = R1; \ | ||
| 113 | RAISE N; \ | ||
| 114 | (R7:0, P5:0) = [SP++]; \ | ||
| 115 | SP += 0x8; \ | ||
| 116 | SYSCFG = [SP++]; \ | ||
| 117 | CSYNC; \ | ||
| 118 | RTI; | ||
| 119 | |||
| 120 | #define TIMER_INTERRUPT_ENTRY(N) \ | ||
| 121 | SSYNC; \ | ||
| 122 | SSYNC; \ | ||
| 123 | [--sp] = SYSCFG; \ | ||
| 124 | [--sp] = P0; /*orig_p0*/ \ | ||
| 125 | [--sp] = R0; /*orig_r0*/ \ | ||
| 126 | [--sp] = (R7:0,P5:0); \ | ||
| 127 | R1 = ASTAT; \ | ||
| 128 | P0.L = LO(ILAT); \ | ||
| 129 | P0.H = HI(ILAT); \ | ||
| 130 | R0 = [P0]; \ | ||
| 131 | CC = BITTST(R0, EVT_IVHW_P); \ | ||
| 132 | IF CC JUMP 1f; \ | ||
| 133 | ASTAT = R1; \ | ||
| 134 | p0.l = lo(IPEND); \ | ||
| 135 | p0.h = hi(IPEND); \ | ||
| 136 | r1 = [p0]; \ | ||
| 137 | R0 = (N); \ | ||
| 138 | jump __common_int_entry; \ | ||
| 139 | 1: ASTAT = R1; \ | ||
| 140 | RAISE N; \ | ||
| 141 | (R7:0, P5:0) = [SP++]; \ | ||
| 142 | SP += 0x8; \ | ||
| 143 | SYSCFG = [SP++]; \ | ||
| 144 | CSYNC; \ | ||
| 145 | RTI; | ||
| 146 | #endif /* CONFIG_EXACT_HWERR */ | ||
| 61 | 147 | ||
| 62 | /* This one pushes RETI without using CLI. Interrupts are enabled. */ | 148 | /* This one pushes RETI without using CLI. Interrupts are enabled. */ |
| 63 | #define SAVE_CONTEXT_SYSCALL save_context_syscall | 149 | #define SAVE_CONTEXT_SYSCALL save_context_syscall |
diff --git a/arch/blackfin/include/asm/errno.h b/arch/blackfin/include/asm/errno.h index 164e4f39bb57..4c82b503d92f 100644 --- a/arch/blackfin/include/asm/errno.h +++ b/arch/blackfin/include/asm/errno.h | |||
| @@ -1,6 +1 @@ | |||
| 1 | #ifndef _BFIN_ERRNO_H | #include <asm-generic/errno.h> | |
| 2 | #define _BFIN_ERRNO_H | ||
| 3 | |||
| 4 | #include<asm-generic/errno.h> | ||
| 5 | |||
| 6 | #endif /* _BFIN_ERRNO_H */ | ||
diff --git a/arch/blackfin/include/asm/fb.h b/arch/blackfin/include/asm/fb.h index c7df38030992..3a4988e8df45 100644 --- a/arch/blackfin/include/asm/fb.h +++ b/arch/blackfin/include/asm/fb.h | |||
| @@ -1,12 +1 @@ | |||
| 1 | #ifndef _ASM_FB_H_ | #include <asm-generic/fb.h> | |
| 2 | #define _ASM_FB_H_ | ||
| 3 | #include <linux/fb.h> | ||
| 4 | |||
| 5 | #define fb_pgprotect(...) do {} while (0) | ||
| 6 | |||
| 7 | static inline int fb_is_primary_device(struct fb_info *info) | ||
| 8 | { | ||
| 9 | return 0; | ||
| 10 | } | ||
| 11 | |||
| 12 | #endif /* _ASM_FB_H_ */ | ||
diff --git a/arch/blackfin/include/asm/flat.h b/arch/blackfin/include/asm/flat.h index e70074e05f4e..733a178d782d 100644 --- a/arch/blackfin/include/asm/flat.h +++ b/arch/blackfin/include/asm/flat.h | |||
| @@ -10,7 +10,6 @@ | |||
| 10 | 10 | ||
| 11 | #include <asm/unaligned.h> | 11 | #include <asm/unaligned.h> |
| 12 | 12 | ||
| 13 | #define flat_stack_align(sp) /* nothing needed */ | ||
| 14 | #define flat_argvp_envp_on_stack() 0 | 13 | #define flat_argvp_envp_on_stack() 0 |
| 15 | #define flat_old_ram_flag(flags) (flags) | 14 | #define flat_old_ram_flag(flags) (flags) |
| 16 | 15 | ||
diff --git a/arch/blackfin/include/asm/ftrace.h b/arch/blackfin/include/asm/ftrace.h index 40a8c178f10d..8643680f0f78 100644 --- a/arch/blackfin/include/asm/ftrace.h +++ b/arch/blackfin/include/asm/ftrace.h | |||
| @@ -1 +1,13 @@ | |||
| 1 | /* empty */ | 1 | /* |
| 2 | * Blackfin ftrace code | ||
| 3 | * | ||
| 4 | * Copyright 2009 Analog Devices Inc. | ||
| 5 | * Licensed under the GPL-2 or later. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __ASM_BFIN_FTRACE_H__ | ||
| 9 | #define __ASM_BFIN_FTRACE_H__ | ||
| 10 | |||
| 11 | #define MCOUNT_INSN_SIZE 8 /* sizeof mcount call: LINK + CALL */ | ||
| 12 | |||
| 13 | #endif | ||
diff --git a/arch/blackfin/include/asm/futex.h b/arch/blackfin/include/asm/futex.h index 6a332a9f099c..0b745828f42b 100644 --- a/arch/blackfin/include/asm/futex.h +++ b/arch/blackfin/include/asm/futex.h | |||
| @@ -1,6 +1 @@ | |||
| 1 | #ifndef _ASM_FUTEX_H | ||
| 2 | #define _ASM_FUTEX_H | ||
| 3 | |||
| 4 | #include <asm-generic/futex.h> | #include <asm-generic/futex.h> | |
| 5 | |||
| 6 | #endif | ||
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h index b0f847ae4bf4..89f08decb8e0 100644 --- a/arch/blackfin/include/asm/gptimers.h +++ b/arch/blackfin/include/asm/gptimers.h | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | # else | 30 | # else |
| 31 | # define MAX_BLACKFIN_GPTIMERS 11 | 31 | # define MAX_BLACKFIN_GPTIMERS 11 |
| 32 | # define TIMER8_GROUP_REG TIMER_ENABLE1 | 32 | # define TIMER8_GROUP_REG TIMER_ENABLE1 |
| 33 | # define TIMER_GROUP2 1 | ||
| 33 | # endif | 34 | # endif |
| 34 | # define TIMER0_GROUP_REG TIMER_ENABLE0 | 35 | # define TIMER0_GROUP_REG TIMER_ENABLE0 |
| 35 | #endif | 36 | #endif |
| @@ -40,10 +41,12 @@ | |||
| 40 | # define MAX_BLACKFIN_GPTIMERS 12 | 41 | # define MAX_BLACKFIN_GPTIMERS 12 |
| 41 | # define TIMER0_GROUP_REG TMRS8_ENABLE | 42 | # define TIMER0_GROUP_REG TMRS8_ENABLE |
| 42 | # define TIMER8_GROUP_REG TMRS4_ENABLE | 43 | # define TIMER8_GROUP_REG TMRS4_ENABLE |
| 44 | # define TIMER_GROUP2 1 | ||
| 43 | #endif | 45 | #endif |
| 44 | /* | 46 | /* |
| 45 | * All others: 3 timers: | 47 | * All others: 3 timers: |
| 46 | */ | 48 | */ |
| 49 | #define TIMER_GROUP1 0 | ||
| 47 | #if !defined(MAX_BLACKFIN_GPTIMERS) | 50 | #if !defined(MAX_BLACKFIN_GPTIMERS) |
| 48 | # define MAX_BLACKFIN_GPTIMERS 3 | 51 | # define MAX_BLACKFIN_GPTIMERS 3 |
| 49 | # define TIMER0_GROUP_REG TIMER_ENABLE | 52 | # define TIMER0_GROUP_REG TIMER_ENABLE |
| @@ -109,8 +112,8 @@ | |||
| 109 | #define TIMER_ERR_PROG_PER 0x8000 | 112 | #define TIMER_ERR_PROG_PER 0x8000 |
| 110 | #define TIMER_ERR_PROG_PW 0xC000 | 113 | #define TIMER_ERR_PROG_PW 0xC000 |
| 111 | #define TIMER_EMU_RUN 0x0200 | 114 | #define TIMER_EMU_RUN 0x0200 |
| 112 | #define TIMER_TOGGLE_HI 0x0100 | 115 | #define TIMER_TOGGLE_HI 0x0100 |
| 113 | #define TIMER_CLK_SEL 0x0080 | 116 | #define TIMER_CLK_SEL 0x0080 |
| 114 | #define TIMER_OUT_DIS 0x0040 | 117 | #define TIMER_OUT_DIS 0x0040 |
| 115 | #define TIMER_TIN_SEL 0x0020 | 118 | #define TIMER_TIN_SEL 0x0020 |
| 116 | #define TIMER_IRQ_ENA 0x0010 | 119 | #define TIMER_IRQ_ENA 0x0010 |
| @@ -169,23 +172,25 @@ | |||
| 169 | 172 | ||
| 170 | /* The actual gptimer API */ | 173 | /* The actual gptimer API */ |
| 171 | 174 | ||
| 172 | void set_gptimer_pwidth (int timer_id, uint32_t width); | 175 | void set_gptimer_pwidth(int timer_id, uint32_t width); |
| 173 | uint32_t get_gptimer_pwidth (int timer_id); | 176 | uint32_t get_gptimer_pwidth(int timer_id); |
| 174 | void set_gptimer_period (int timer_id, uint32_t period); | 177 | void set_gptimer_period(int timer_id, uint32_t period); |
| 175 | uint32_t get_gptimer_period (int timer_id); | 178 | uint32_t get_gptimer_period(int timer_id); |
| 176 | uint32_t get_gptimer_count (int timer_id); | 179 | uint32_t get_gptimer_count(int timer_id); |
| 177 | uint16_t get_gptimer_intr (int timer_id); | 180 | int get_gptimer_intr(int timer_id); |
| 178 | void clear_gptimer_intr (int timer_id); | 181 | void clear_gptimer_intr(int timer_id); |
| 179 | uint16_t get_gptimer_over (int timer_id); | 182 | int get_gptimer_over(int timer_id); |
| 180 | void clear_gptimer_over (int timer_id); | 183 | void clear_gptimer_over(int timer_id); |
| 181 | void set_gptimer_config (int timer_id, uint16_t config); | 184 | void set_gptimer_config(int timer_id, uint16_t config); |
| 182 | uint16_t get_gptimer_config (int timer_id); | 185 | uint16_t get_gptimer_config(int timer_id); |
| 183 | void set_gptimer_pulse_hi (int timer_id); | 186 | int get_gptimer_run(int timer_id); |
| 187 | void set_gptimer_pulse_hi(int timer_id); | ||
| 184 | void clear_gptimer_pulse_hi(int timer_id); | 188 | void clear_gptimer_pulse_hi(int timer_id); |
| 185 | void enable_gptimers (uint16_t mask); | 189 | void enable_gptimers(uint16_t mask); |
| 186 | void disable_gptimers (uint16_t mask); | 190 | void disable_gptimers(uint16_t mask); |
| 187 | uint16_t get_enabled_gptimers (void); | 191 | void disable_gptimers_sync(uint16_t mask); |
| 188 | uint32_t get_gptimer_status (int group); | 192 | uint16_t get_enabled_gptimers(void); |
| 189 | void set_gptimer_status (int group, uint32_t value); | 193 | uint32_t get_gptimer_status(int group); |
| 194 | void set_gptimer_status(int group, uint32_t value); | ||
| 190 | 195 | ||
| 191 | #endif | 196 | #endif |
diff --git a/arch/blackfin/include/asm/hardirq.h b/arch/blackfin/include/asm/hardirq.h index 717181a1749b..cbd52f86bb9f 100644 --- a/arch/blackfin/include/asm/hardirq.h +++ b/arch/blackfin/include/asm/hardirq.h | |||
| @@ -1,47 +1,11 @@ | |||
| 1 | #ifndef __BFIN_HARDIRQ_H | 1 | #ifndef __BFIN_HARDIRQ_H |
| 2 | #define __BFIN_HARDIRQ_H | 2 | #define __BFIN_HARDIRQ_H |
| 3 | 3 | ||
| 4 | #include <linux/cache.h> | ||
| 5 | #include <linux/threads.h> | ||
| 6 | #include <asm/irq.h> | ||
| 7 | |||
| 8 | typedef struct { | ||
| 9 | unsigned int __softirq_pending; | ||
| 10 | unsigned int __syscall_count; | ||
| 11 | struct task_struct *__ksoftirqd_task; | ||
| 12 | } ____cacheline_aligned irq_cpustat_t; | ||
| 13 | |||
| 14 | #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ | ||
| 15 | |||
| 16 | /* | ||
| 17 | * We put the hardirq and softirq counter into the preemption | ||
| 18 | * counter. The bitmask has the following meaning: | ||
| 19 | * | ||
| 20 | * - bits 0-7 are the preemption count (max preemption depth: 256) | ||
| 21 | * - bits 8-15 are the softirq count (max # of softirqs: 256) | ||
| 22 | * - bits 16-23 are the hardirq count (max # of hardirqs: 256) | ||
| 23 | * | ||
| 24 | * - ( bit 26 is the PREEMPT_ACTIVE flag. ) | ||
| 25 | * | ||
| 26 | * PREEMPT_MASK: 0x000000ff | ||
| 27 | * HARDIRQ_MASK: 0x0000ff00 | ||
| 28 | * SOFTIRQ_MASK: 0x00ff0000 | ||
| 29 | */ | ||
| 30 | |||
| 31 | #if NR_IRQS > 256 | ||
| 32 | #define HARDIRQ_BITS 9 | ||
| 33 | #else | ||
| 34 | #define HARDIRQ_BITS 8 | ||
| 35 | #endif | ||
| 36 | |||
| 37 | #ifdef NR_IRQS | ||
| 38 | # if (1 << HARDIRQ_BITS) < NR_IRQS | ||
| 39 | # error HARDIRQ_BITS is too low! | ||
| 40 | # endif | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #define __ARCH_IRQ_EXIT_IRQS_DISABLED 1 | 4 | #define __ARCH_IRQ_EXIT_IRQS_DISABLED 1 |
| 44 | 5 | ||
| 45 | extern void ack_bad_irq(unsigned int irq); | 6 | extern void ack_bad_irq(unsigned int irq); |
| 7 | #define ack_bad_irq ack_bad_irq | ||
| 8 | |||
| 9 | #include <asm-generic/hardirq.h> | ||
| 46 | 10 | ||
| 47 | #endif | 11 | #endif |
diff --git a/arch/blackfin/include/asm/hw_irq.h b/arch/blackfin/include/asm/hw_irq.h index 5b51eaec012c..1f5ef7da0045 100644 --- a/arch/blackfin/include/asm/hw_irq.h +++ b/arch/blackfin/include/asm/hw_irq.h | |||
| @@ -1,6 +1 @@ | |||
| 1 | #ifndef __ASM_BFIN_HW_IRQ_H | #include <asm-generic/hw_irq.h> | |
| 2 | #define __ASM_BFIN_HW_IRQ_H | ||
| 3 | |||
| 4 | /* Dummy include. */ | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h index 63b2d8c78570..37053eca200e 100644 --- a/arch/blackfin/include/asm/io.h +++ b/arch/blackfin/include/asm/io.h | |||
| @@ -80,19 +80,22 @@ static inline unsigned int readl(const volatile void __iomem *addr) | |||
| 80 | #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) | 80 | #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) |
| 81 | #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) | 81 | #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) |
| 82 | 82 | ||
| 83 | #define inb(addr) readb(addr) | 83 | /* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */ |
| 84 | #define inw(addr) readw(addr) | 84 | #define __io(port) ((void *)(unsigned long)(port)) |
| 85 | #define inl(addr) readl(addr) | 85 | |
| 86 | #define outb(x,addr) ((void) writeb(x,addr)) | 86 | #define inb(port) readb(__io(port)) |
| 87 | #define outw(x,addr) ((void) writew(x,addr)) | 87 | #define inw(port) readw(__io(port)) |
| 88 | #define outl(x,addr) ((void) writel(x,addr)) | 88 | #define inl(port) readl(__io(port)) |
| 89 | 89 | #define outb(x,port) writeb(x,__io(port)) | |
| 90 | #define inb_p(addr) inb(addr) | 90 | #define outw(x,port) writew(x,__io(port)) |
| 91 | #define inw_p(addr) inw(addr) | 91 | #define outl(x,port) writel(x,__io(port)) |
| 92 | #define inl_p(addr) inl(addr) | 92 | |
| 93 | #define outb_p(x,addr) outb(x,addr) | 93 | #define inb_p(port) inb(__io(port)) |
| 94 | #define outw_p(x,addr) outw(x,addr) | 94 | #define inw_p(port) inw(__io(port)) |
| 95 | #define outl_p(x,addr) outl(x,addr) | 95 | #define inl_p(port) inl(__io(port)) |
| 96 | #define outb_p(x,port) outb(x,__io(port)) | ||
| 97 | #define outw_p(x,port) outw(x,__io(port)) | ||
| 98 | #define outl_p(x,port) outl(x,__io(port)) | ||
| 96 | 99 | ||
| 97 | #define ioread8_rep(a,d,c) readsb(a,d,c) | 100 | #define ioread8_rep(a,d,c) readsb(a,d,c) |
| 98 | #define ioread16_rep(a,d,c) readsw(a,d,c) | 101 | #define ioread16_rep(a,d,c) readsw(a,d,c) |
| @@ -219,7 +222,6 @@ extern void blkfin_inv_cache_all(void); | |||
| 219 | #define ioport_unmap(addr) | 222 | #define ioport_unmap(addr) |
| 220 | 223 | ||
| 221 | /* Pages to physical address... */ | 224 | /* Pages to physical address... */ |
| 222 | #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) | ||
| 223 | #define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT) | 225 | #define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT) |
| 224 | 226 | ||
| 225 | #define phys_to_virt(vaddr) ((void *) (vaddr)) | 227 | #define phys_to_virt(vaddr) ((void *) (vaddr)) |
diff --git a/arch/blackfin/include/asm/ioctls.h b/arch/blackfin/include/asm/ioctls.h index 895e3173165d..eca8d75b0a8a 100644 --- a/arch/blackfin/include/asm/ioctls.h +++ b/arch/blackfin/include/asm/ioctls.h | |||
| @@ -1,87 +1,7 @@ | |||
| 1 | #ifndef __ARCH_BFIN_IOCTLS_H__ | 1 | #ifndef __ARCH_BFIN_IOCTLS_H__ |
| 2 | #define __ARCH_BFIN_IOCTLS_H__ | 2 | #define __ARCH_BFIN_IOCTLS_H__ |
| 3 | 3 | ||
| 4 | #include <asm/ioctl.h> | ||
| 5 | |||
| 6 | /* 0x54 is just a magic number to make these relatively unique ('T') */ | ||
| 7 | |||
| 8 | #define TCGETS 0x5401 | ||
| 9 | #define TCSETS 0x5402 | ||
| 10 | #define TCSETSW 0x5403 | ||
| 11 | #define TCSETSF 0x5404 | ||
| 12 | #define TCGETA 0x5405 | ||
| 13 | #define TCSETA 0x5406 | ||
| 14 | #define TCSETAW 0x5407 | ||
| 15 | #define TCSETAF 0x5408 | ||
| 16 | #define TCSBRK 0x5409 | ||
| 17 | #define TCXONC 0x540A | ||
| 18 | #define TCFLSH 0x540B | ||
| 19 | #define TIOCEXCL 0x540C | ||
| 20 | #define TIOCNXCL 0x540D | ||
| 21 | #define TIOCSCTTY 0x540E | ||
| 22 | #define TIOCGPGRP 0x540F | ||
| 23 | #define TIOCSPGRP 0x5410 | ||
| 24 | #define TIOCOUTQ 0x5411 | ||
| 25 | #define TIOCSTI 0x5412 | ||
| 26 | #define TIOCGWINSZ 0x5413 | ||
| 27 | #define TIOCSWINSZ 0x5414 | ||
| 28 | #define TIOCMGET 0x5415 | ||
| 29 | #define TIOCMBIS 0x5416 | ||
| 30 | #define TIOCMBIC 0x5417 | ||
| 31 | #define TIOCMSET 0x5418 | ||
| 32 | #define TIOCGSOFTCAR 0x5419 | ||
| 33 | #define TIOCSSOFTCAR 0x541A | ||
| 34 | #define FIONREAD 0x541B | ||
| 35 | #define TIOCINQ FIONREAD | ||
| 36 | #define TIOCLINUX 0x541C | ||
| 37 | #define TIOCCONS 0x541D | ||
| 38 | #define TIOCGSERIAL 0x541E | ||
| 39 | #define TIOCSSERIAL 0x541F | ||
| 40 | #define TIOCPKT 0x5420 | ||
| 41 | #define FIONBIO 0x5421 | ||
| 42 | #define TIOCNOTTY 0x5422 | ||
| 43 | #define TIOCSETD 0x5423 | ||
| 44 | #define TIOCGETD 0x5424 | ||
| 45 | #define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ | ||
| 46 | #define TIOCTTYGSTRUCT 0x5426 /* For debugging only */ | ||
| 47 | #define TIOCSBRK 0x5427 /* BSD compatibility */ | ||
| 48 | #define TIOCCBRK 0x5428 /* BSD compatibility */ | ||
| 49 | #define TIOCGSID 0x5429 /* Return the session ID of FD */ | ||
| 50 | #define TCGETS2 _IOR('T', 0x2A, struct termios2) | ||
| 51 | #define TCSETS2 _IOW('T', 0x2B, struct termios2) | ||
| 52 | #define TCSETSW2 _IOW('T', 0x2C, struct termios2) | ||
| 53 | #define TCSETSF2 _IOW('T', 0x2D, struct termios2) | ||
| 54 | /* Get Pty Number (of pty-mux device) */ | ||
| 55 | #define TIOCGPTN _IOR('T', 0x30, unsigned int) | ||
| 56 | #define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ | ||
| 57 | |||
| 58 | #define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ | ||
| 59 | #define FIOCLEX 0x5451 | ||
| 60 | #define FIOASYNC 0x5452 | ||
| 61 | #define TIOCSERCONFIG 0x5453 | ||
| 62 | #define TIOCSERGWILD 0x5454 | ||
| 63 | #define TIOCSERSWILD 0x5455 | ||
| 64 | #define TIOCGLCKTRMIOS 0x5456 | ||
| 65 | #define TIOCSLCKTRMIOS 0x5457 | ||
| 66 | #define TIOCSERGSTRUCT 0x5458 /* For debugging only */ | ||
| 67 | #define TIOCSERGETLSR 0x5459 /* Get line status register */ | ||
| 68 | #define TIOCSERGETMULTI 0x545A /* Get multiport config */ | ||
| 69 | #define TIOCSERSETMULTI 0x545B /* Set multiport config */ | ||
| 70 | |||
| 71 | #define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ | ||
| 72 | #define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ | ||
| 73 | |||
| 74 | #define FIOQSIZE 0x545E | 4 | #define FIOQSIZE 0x545E |
| 5 | #include <asm-generic/ioctls.h> | ||
| 75 | 6 | ||
| 76 | /* Used for packet mode */ | 7 | #endif |
| 77 | #define TIOCPKT_DATA 0 | ||
| 78 | #define TIOCPKT_FLUSHREAD 1 | ||
| 79 | #define TIOCPKT_FLUSHWRITE 2 | ||
| 80 | #define TIOCPKT_STOP 4 | ||
| 81 | #define TIOCPKT_START 8 | ||
| 82 | #define TIOCPKT_NOSTOP 16 | ||
| 83 | #define TIOCPKT_DOSTOP 32 | ||
| 84 | |||
| 85 | #define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ | ||
| 86 | |||
| 87 | #endif /* __ARCH_BFIN_IOCTLS_H__ */ | ||
diff --git a/arch/blackfin/include/asm/ipcbuf.h b/arch/blackfin/include/asm/ipcbuf.h index 8f0899cdf4d2..84c7e51cb6d0 100644 --- a/arch/blackfin/include/asm/ipcbuf.h +++ b/arch/blackfin/include/asm/ipcbuf.h | |||
| @@ -1,30 +1 @@ | |||
| 1 | /* Changes origined from m68k version. Lineo Inc. May 2001 */ | #include <asm-generic/ipcbuf.h> | |
| 2 | |||
| 3 | #ifndef __BFIN_IPCBUF_H__ | ||
| 4 | #define __BFIN_IPCBUF_H__ | ||
| 5 | |||
| 6 | /* | ||
| 7 | * The user_ipc_perm structure for m68k architecture. | ||
| 8 | * Note extra padding because this structure is passed back and forth | ||
| 9 | * between kernel and user space. | ||
| 10 | * | ||
| 11 | * Pad space is left for: | ||
| 12 | * - 32-bit mode_t and seq | ||
| 13 | * - 2 miscellaneous 32-bit values | ||
| 14 | */ | ||
| 15 | |||
| 16 | struct ipc64_perm { | ||
| 17 | __kernel_key_t key; | ||
| 18 | __kernel_uid32_t uid; | ||
| 19 | __kernel_gid32_t gid; | ||
| 20 | __kernel_uid32_t cuid; | ||
| 21 | __kernel_gid32_t cgid; | ||
| 22 | __kernel_mode_t mode; | ||
| 23 | unsigned short __pad1; | ||
| 24 | unsigned short seq; | ||
| 25 | unsigned short __pad2; | ||
| 26 | unsigned long __unused1; | ||
| 27 | unsigned long __unused2; | ||
| 28 | }; | ||
| 29 | |||
| 30 | #endif /* __BFIN_IPCBUF_H__ */ | ||
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h index 343b56361ec9..bbe1c3726b69 100644 --- a/arch/blackfin/include/asm/ipipe.h +++ b/arch/blackfin/include/asm/ipipe.h | |||
| @@ -35,9 +35,9 @@ | |||
| 35 | #include <asm/atomic.h> | 35 | #include <asm/atomic.h> |
| 36 | #include <asm/traps.h> | 36 | #include <asm/traps.h> |
| 37 | 37 | ||
| 38 | #define IPIPE_ARCH_STRING "1.9-00" | 38 | #define IPIPE_ARCH_STRING "1.10-00" |
| 39 | #define IPIPE_MAJOR_NUMBER 1 | 39 | #define IPIPE_MAJOR_NUMBER 1 |
| 40 | #define IPIPE_MINOR_NUMBER 9 | 40 | #define IPIPE_MINOR_NUMBER 10 |
| 41 | #define IPIPE_PATCH_NUMBER 0 | 41 | #define IPIPE_PATCH_NUMBER 0 |
| 42 | 42 | ||
| 43 | #ifdef CONFIG_SMP | 43 | #ifdef CONFIG_SMP |
| @@ -54,10 +54,11 @@ do { \ | |||
| 54 | 54 | ||
| 55 | #define task_hijacked(p) \ | 55 | #define task_hijacked(p) \ |
| 56 | ({ \ | 56 | ({ \ |
| 57 | int __x__ = ipipe_current_domain != ipipe_root_domain; \ | 57 | int __x__ = __ipipe_root_domain_p; \ |
| 58 | /* We would need to clear the SYNC flag for the root domain */ \ | 58 | __clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \ |
| 59 | /* over the current processor in SMP mode. */ \ | 59 | if (__x__) \ |
| 60 | local_irq_enable_hw(); __x__; \ | 60 | local_irq_enable_hw(); \ |
| 61 | !__x__; \ | ||
| 61 | }) | 62 | }) |
| 62 | 63 | ||
| 63 | struct ipipe_domain; | 64 | struct ipipe_domain; |
| @@ -179,23 +180,24 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul) | |||
| 179 | 180 | ||
| 180 | #define __ipipe_run_isr(ipd, irq) \ | 181 | #define __ipipe_run_isr(ipd, irq) \ |
| 181 | do { \ | 182 | do { \ |
| 182 | if (ipd == ipipe_root_domain) { \ | 183 | if (!__ipipe_pipeline_head_p(ipd)) \ |
| 183 | local_irq_enable_hw(); \ | 184 | local_irq_enable_hw(); \ |
| 184 | if (ipipe_virtual_irq_p(irq)) \ | 185 | if (ipd == ipipe_root_domain) { \ |
| 186 | if (unlikely(ipipe_virtual_irq_p(irq))) { \ | ||
| 187 | irq_enter(); \ | ||
| 185 | ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ | 188 | ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ |
| 186 | else \ | 189 | irq_exit(); \ |
| 190 | } else \ | ||
| 187 | ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \ | 191 | ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \ |
| 188 | local_irq_disable_hw(); \ | ||
| 189 | } else { \ | 192 | } else { \ |
| 190 | __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ | 193 | __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ |
| 191 | local_irq_enable_nohead(ipd); \ | ||
| 192 | ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ | 194 | ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ |
| 193 | /* Attempt to exit the outer interrupt level before \ | 195 | /* Attempt to exit the outer interrupt level before \ |
| 194 | * starting the deferred IRQ processing. */ \ | 196 | * starting the deferred IRQ processing. */ \ |
| 195 | local_irq_disable_nohead(ipd); \ | ||
| 196 | __ipipe_run_irqtail(); \ | 197 | __ipipe_run_irqtail(); \ |
| 197 | __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ | 198 | __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ |
| 198 | } \ | 199 | } \ |
| 200 | local_irq_disable_hw(); \ | ||
| 199 | } while (0) | 201 | } while (0) |
| 200 | 202 | ||
| 201 | #define __ipipe_syscall_watched_p(p, sc) \ | 203 | #define __ipipe_syscall_watched_p(p, sc) \ |
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h index 7645e85a5f6f..9a7f63a83c47 100644 --- a/arch/blackfin/include/asm/irq.h +++ b/arch/blackfin/include/asm/irq.h | |||
| @@ -17,270 +17,17 @@ | |||
| 17 | #ifndef _BFIN_IRQ_H_ | 17 | #ifndef _BFIN_IRQ_H_ |
| 18 | #define _BFIN_IRQ_H_ | 18 | #define _BFIN_IRQ_H_ |
| 19 | 19 | ||
| 20 | /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h>*/ | 20 | #include <linux/irqflags.h> |
| 21 | #include <mach/irq.h> | ||
| 22 | #include <asm/pda.h> | ||
| 23 | #include <asm/processor.h> | ||
| 24 | |||
| 25 | #ifdef CONFIG_SMP | ||
| 26 | /* Forward decl needed due to cdef inter dependencies */ | ||
| 27 | static inline uint32_t __pure bfin_dspid(void); | ||
| 28 | # define blackfin_core_id() (bfin_dspid() & 0xff) | ||
| 29 | # define bfin_irq_flags cpu_pda[blackfin_core_id()].imask | ||
| 30 | #else | ||
| 31 | extern unsigned long bfin_irq_flags; | ||
| 32 | #endif | ||
| 33 | |||
| 34 | #ifdef CONFIG_IPIPE | ||
| 35 | |||
| 36 | #include <linux/ipipe_trace.h> | ||
| 37 | |||
| 38 | void __ipipe_unstall_root(void); | ||
| 39 | |||
| 40 | void __ipipe_restore_root(unsigned long flags); | ||
| 41 | |||
| 42 | #ifdef CONFIG_DEBUG_HWERR | ||
| 43 | # define __all_masked_irq_flags 0x3f | ||
| 44 | # define __save_and_cli_hw(x) \ | ||
| 45 | __asm__ __volatile__( \ | ||
| 46 | "cli %0;" \ | ||
| 47 | "sti %1;" \ | ||
| 48 | : "=&d"(x) \ | ||
| 49 | : "d" (0x3F) \ | ||
| 50 | ) | ||
| 51 | #else | ||
| 52 | # define __all_masked_irq_flags 0x1f | ||
| 53 | # define __save_and_cli_hw(x) \ | ||
| 54 | __asm__ __volatile__( \ | ||
| 55 | "cli %0;" \ | ||
| 56 | : "=&d"(x) \ | ||
| 57 | ) | ||
| 58 | #endif | ||
| 59 | |||
| 60 | #define irqs_enabled_from_flags_hw(x) ((x) != __all_masked_irq_flags) | ||
| 61 | #define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags)) | ||
| 62 | #define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x) | ||
| 63 | |||
| 64 | #define local_save_flags(x) \ | ||
| 65 | do { \ | ||
| 66 | (x) = __ipipe_test_root() ? \ | ||
| 67 | __all_masked_irq_flags : bfin_irq_flags; \ | ||
| 68 | barrier(); \ | ||
| 69 | } while (0) | ||
| 70 | |||
| 71 | #define local_irq_save(x) \ | ||
| 72 | do { \ | ||
| 73 | (x) = __ipipe_test_and_stall_root() ? \ | ||
| 74 | __all_masked_irq_flags : bfin_irq_flags; \ | ||
| 75 | barrier(); \ | ||
| 76 | } while (0) | ||
| 77 | |||
| 78 | static inline void local_irq_restore(unsigned long x) | ||
| 79 | { | ||
| 80 | barrier(); | ||
| 81 | __ipipe_restore_root(x == __all_masked_irq_flags); | ||
| 82 | } | ||
| 83 | |||
| 84 | #define local_irq_disable() \ | ||
| 85 | do { \ | ||
| 86 | __ipipe_stall_root(); \ | ||
| 87 | barrier(); \ | ||
| 88 | } while (0) | ||
| 89 | |||
| 90 | static inline void local_irq_enable(void) | ||
| 91 | { | ||
| 92 | barrier(); | ||
| 93 | __ipipe_unstall_root(); | ||
| 94 | } | ||
| 95 | |||
| 96 | #define irqs_disabled() __ipipe_test_root() | ||
| 97 | |||
| 98 | #define local_save_flags_hw(x) \ | ||
| 99 | __asm__ __volatile__( \ | ||
| 100 | "cli %0;" \ | ||
| 101 | "sti %0;" \ | ||
| 102 | : "=d"(x) \ | ||
| 103 | ) | ||
| 104 | |||
| 105 | #define irqs_disabled_hw() \ | ||
| 106 | ({ \ | ||
| 107 | unsigned long flags; \ | ||
| 108 | local_save_flags_hw(flags); \ | ||
| 109 | !irqs_enabled_from_flags_hw(flags); \ | ||
| 110 | }) | ||
| 111 | |||
| 112 | static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real) | ||
| 113 | { | ||
| 114 | /* Merge virtual and real interrupt mask bits into a single | ||
| 115 | 32bit word. */ | ||
| 116 | return (real & ~(1 << 31)) | ((virt != 0) << 31); | ||
| 117 | } | ||
| 118 | |||
| 119 | static inline int raw_demangle_irq_bits(unsigned long *x) | ||
| 120 | { | ||
| 121 | int virt = (*x & (1 << 31)) != 0; | ||
| 122 | *x &= ~(1L << 31); | ||
| 123 | return virt; | ||
| 124 | } | ||
| 125 | |||
| 126 | #ifdef CONFIG_IPIPE_TRACE_IRQSOFF | ||
| 127 | |||
| 128 | #define local_irq_disable_hw() \ | ||
| 129 | do { \ | ||
| 130 | int _tmp_dummy; \ | ||
| 131 | if (!irqs_disabled_hw()) \ | ||
| 132 | ipipe_trace_begin(0x80000000); \ | ||
| 133 | __asm__ __volatile__ ("cli %0;" : "=d" (_tmp_dummy) : ); \ | ||
| 134 | } while (0) | ||
| 135 | |||
| 136 | #define local_irq_enable_hw() \ | ||
| 137 | do { \ | ||
| 138 | if (irqs_disabled_hw()) \ | ||
| 139 | ipipe_trace_end(0x80000000); \ | ||
| 140 | __asm__ __volatile__ ("sti %0;" : : "d"(bfin_irq_flags)); \ | ||
| 141 | } while (0) | ||
| 142 | |||
| 143 | #define local_irq_save_hw(x) \ | ||
| 144 | do { \ | ||
| 145 | __save_and_cli_hw(x); \ | ||
| 146 | if (local_test_iflag_hw(x)) \ | ||
| 147 | ipipe_trace_begin(0x80000001); \ | ||
| 148 | } while (0) | ||
| 149 | |||
| 150 | #define local_irq_restore_hw(x) \ | ||
| 151 | do { \ | ||
| 152 | if (local_test_iflag_hw(x)) { \ | ||
| 153 | ipipe_trace_end(0x80000001); \ | ||
| 154 | local_irq_enable_hw_notrace(); \ | ||
| 155 | } \ | ||
| 156 | } while (0) | ||
| 157 | |||
| 158 | #define local_irq_disable_hw_notrace() \ | ||
| 159 | do { \ | ||
| 160 | int _tmp_dummy; \ | ||
| 161 | __asm__ __volatile__ ("cli %0;" : "=d" (_tmp_dummy) : ); \ | ||
| 162 | } while (0) | ||
| 163 | |||
| 164 | #define local_irq_enable_hw_notrace() \ | ||
| 165 | __asm__ __volatile__( \ | ||
| 166 | "sti %0;" \ | ||
| 167 | : \ | ||
| 168 | : "d"(bfin_irq_flags) \ | ||
| 169 | ) | ||
| 170 | |||
| 171 | #define local_irq_save_hw_notrace(x) __save_and_cli_hw(x) | ||
| 172 | 21 | ||
| 173 | #define local_irq_restore_hw_notrace(x) \ | 22 | /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */ |
| 174 | do { \ | 23 | #include <mach/irq.h> |
| 175 | if (local_test_iflag_hw(x)) \ | ||
| 176 | local_irq_enable_hw_notrace(); \ | ||
| 177 | } while (0) | ||
| 178 | |||
| 179 | #else /* CONFIG_IPIPE_TRACE_IRQSOFF */ | ||
| 180 | |||
| 181 | #define local_irq_enable_hw() \ | ||
| 182 | __asm__ __volatile__( \ | ||
| 183 | "sti %0;" \ | ||
| 184 | : \ | ||
| 185 | : "d"(bfin_irq_flags) \ | ||
| 186 | ) | ||
| 187 | |||
| 188 | #define local_irq_disable_hw() \ | ||
| 189 | do { \ | ||
| 190 | int _tmp_dummy; \ | ||
| 191 | __asm__ __volatile__ ( \ | ||
| 192 | "cli %0;" \ | ||
| 193 | : "=d" (_tmp_dummy)); \ | ||
| 194 | } while (0) | ||
| 195 | |||
| 196 | #define local_irq_restore_hw(x) \ | ||
| 197 | do { \ | ||
| 198 | if (irqs_enabled_from_flags_hw(x)) \ | ||
| 199 | local_irq_enable_hw(); \ | ||
| 200 | } while (0) | ||
| 201 | |||
| 202 | #define local_irq_save_hw(x) __save_and_cli_hw(x) | ||
| 203 | |||
| 204 | #define local_irq_disable_hw_notrace() local_irq_disable_hw() | ||
| 205 | #define local_irq_enable_hw_notrace() local_irq_enable_hw() | ||
| 206 | #define local_irq_save_hw_notrace(x) local_irq_save_hw(x) | ||
| 207 | #define local_irq_restore_hw_notrace(x) local_irq_restore_hw(x) | ||
| 208 | |||
| 209 | #endif /* CONFIG_IPIPE_TRACE_IRQSOFF */ | ||
| 210 | |||
| 211 | #else /* !CONFIG_IPIPE */ | ||
| 212 | |||
| 213 | /* | ||
| 214 | * Interrupt configuring macros. | ||
| 215 | */ | ||
| 216 | #define local_irq_disable() \ | ||
| 217 | do { \ | ||
| 218 | int __tmp_dummy; \ | ||
| 219 | __asm__ __volatile__( \ | ||
| 220 | "cli %0;" \ | ||
| 221 | : "=d" (__tmp_dummy) \ | ||
| 222 | ); \ | ||
| 223 | } while (0) | ||
| 224 | |||
| 225 | #define local_irq_enable() \ | ||
| 226 | __asm__ __volatile__( \ | ||
| 227 | "sti %0;" \ | ||
| 228 | : \ | ||
| 229 | : "d" (bfin_irq_flags) \ | ||
| 230 | ) | ||
| 231 | |||
| 232 | #ifdef CONFIG_DEBUG_HWERR | ||
| 233 | # define __save_and_cli(x) \ | ||
| 234 | __asm__ __volatile__( \ | ||
| 235 | "cli %0;" \ | ||
| 236 | "sti %1;" \ | ||
| 237 | : "=&d" (x) \ | ||
| 238 | : "d" (0x3F) \ | ||
| 239 | ) | ||
| 240 | #else | ||
| 241 | # define __save_and_cli(x) \ | ||
| 242 | __asm__ __volatile__( \ | ||
| 243 | "cli %0;" \ | ||
| 244 | : "=&d" (x) \ | ||
| 245 | ) | ||
| 246 | #endif | ||
| 247 | |||
| 248 | #define local_save_flags(x) \ | ||
| 249 | __asm__ __volatile__( \ | ||
| 250 | "cli %0;" \ | ||
| 251 | "sti %0;" \ | ||
| 252 | : "=d" (x) \ | ||
| 253 | ) | ||
| 254 | |||
| 255 | #ifdef CONFIG_DEBUG_HWERR | ||
| 256 | #define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0) | ||
| 257 | #else | ||
| 258 | #define irqs_enabled_from_flags(x) ((x) != 0x1f) | ||
| 259 | #endif | ||
| 260 | |||
| 261 | #define local_irq_restore(x) \ | ||
| 262 | do { \ | ||
| 263 | if (irqs_enabled_from_flags(x)) \ | ||
| 264 | local_irq_enable(); \ | ||
| 265 | } while (0) | ||
| 266 | |||
| 267 | /* For spinlocks etc */ | ||
| 268 | #define local_irq_save(x) __save_and_cli(x) | ||
| 269 | |||
| 270 | #define irqs_disabled() \ | ||
| 271 | ({ \ | ||
| 272 | unsigned long flags; \ | ||
| 273 | local_save_flags(flags); \ | ||
| 274 | !irqs_enabled_from_flags(flags); \ | ||
| 275 | }) | ||
| 276 | |||
| 277 | #define local_irq_save_hw(x) local_irq_save(x) | ||
| 278 | #define local_irq_restore_hw(x) local_irq_restore(x) | ||
| 279 | #define local_irq_enable_hw() local_irq_enable() | ||
| 280 | #define local_irq_disable_hw() local_irq_disable() | ||
| 281 | #define irqs_disabled_hw() irqs_disabled() | ||
| 282 | 24 | ||
| 283 | #endif /* !CONFIG_IPIPE */ | 25 | /* Xenomai IPIPE helpers */ |
| 26 | #define local_irq_restore_hw(x) local_irq_restore(x) | ||
| 27 | #define local_irq_save_hw(x) local_irq_save(x) | ||
| 28 | #define local_irq_enable_hw(x) local_irq_enable(x) | ||
| 29 | #define local_irq_disable_hw(x) local_irq_disable(x) | ||
| 30 | #define irqs_disabled_hw(x) irqs_disabled(x) | ||
| 284 | 31 | ||
| 285 | #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) | 32 | #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) |
| 286 | # define NOP_PAD_ANOMALY_05000244 "nop; nop;" | 33 | # define NOP_PAD_ANOMALY_05000244 "nop; nop;" |
| @@ -298,9 +45,6 @@ static inline int raw_demangle_irq_bits(unsigned long *x) | |||
| 298 | : "d" (bfin_irq_flags) \ | 45 | : "d" (bfin_irq_flags) \ |
| 299 | ) | 46 | ) |
| 300 | 47 | ||
| 301 | static inline int irq_canonicalize(int irq) | 48 | #include <asm-generic/irq.h> |
| 302 | { | ||
| 303 | return irq; | ||
| 304 | } | ||
| 305 | 49 | ||
| 306 | #endif /* _BFIN_IRQ_H_ */ | 50 | #endif /* _BFIN_IRQ_H_ */ |
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h new file mode 100644 index 000000000000..139cba4651b1 --- /dev/null +++ b/arch/blackfin/include/asm/irqflags.h | |||
| @@ -0,0 +1,63 @@ | |||
| 1 | /* | ||
| 2 | * interface to Blackfin CEC | ||
| 3 | * | ||
| 4 | * Copyright 2009 Analog Devices Inc. | ||
| 5 | * Licensed under the GPL-2 or later. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __ASM_BFIN_IRQFLAGS_H__ | ||
| 9 | #define __ASM_BFIN_IRQFLAGS_H__ | ||
| 10 | |||
| 11 | #ifdef CONFIG_SMP | ||
| 12 | # include <asm/pda.h> | ||
| 13 | # include <asm/processor.h> | ||
| 14 | /* Forward decl needed due to cdef inter dependencies */ | ||
| 15 | static inline uint32_t __pure bfin_dspid(void); | ||
| 16 | # define blackfin_core_id() (bfin_dspid() & 0xff) | ||
| 17 | # define bfin_irq_flags cpu_pda[blackfin_core_id()].imask | ||
| 18 | #else | ||
| 19 | extern unsigned long bfin_irq_flags; | ||
| 20 | #endif | ||
| 21 | |||
| 22 | static inline void bfin_sti(unsigned long flags) | ||
| 23 | { | ||
| 24 | asm volatile("sti %0;" : : "d" (flags)); | ||
| 25 | } | ||
| 26 | |||
| 27 | static inline unsigned long bfin_cli(void) | ||
| 28 | { | ||
| 29 | unsigned long flags; | ||
| 30 | asm volatile("cli %0;" : "=d" (flags)); | ||
| 31 | return flags; | ||
| 32 | } | ||
| 33 | |||
| 34 | static inline void raw_local_irq_disable(void) | ||
| 35 | { | ||
| 36 | bfin_cli(); | ||
| 37 | } | ||
| 38 | static inline void raw_local_irq_enable(void) | ||
| 39 | { | ||
| 40 | bfin_sti(bfin_irq_flags); | ||
| 41 | } | ||
| 42 | |||
| 43 | #define raw_local_save_flags(flags) do { (flags) = bfin_read_IMASK(); } while (0) | ||
| 44 | |||
| 45 | #define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0) | ||
| 46 | |||
| 47 | static inline void raw_local_irq_restore(unsigned long flags) | ||
| 48 | { | ||
| 49 | if (!raw_irqs_disabled_flags(flags)) | ||
| 50 | raw_local_irq_enable(); | ||
| 51 | } | ||
| 52 | |||
| 53 | static inline unsigned long __raw_local_irq_save(void) | ||
| 54 | { | ||
| 55 | unsigned long flags = bfin_cli(); | ||
| 56 | #ifdef CONFIG_DEBUG_HWERR | ||
| 57 | bfin_sti(0x3f); | ||
| 58 | #endif | ||
| 59 | return flags; | ||
| 60 | } | ||
| 61 | #define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0) | ||
| 62 | |||
| 63 | #endif | ||
diff --git a/arch/blackfin/include/asm/kmap_types.h b/arch/blackfin/include/asm/kmap_types.h index e215f7104974..3575c64af42a 100644 --- a/arch/blackfin/include/asm/kmap_types.h +++ b/arch/blackfin/include/asm/kmap_types.h | |||
| @@ -1,21 +1 @@ | |||
| 1 | #ifndef _ASM_KMAP_TYPES_H | #include <asm-generic/kmap_types.h> | |
| 2 | #define _ASM_KMAP_TYPES_H | ||
| 3 | |||
| 4 | enum km_type { | ||
| 5 | KM_BOUNCE_READ, | ||
| 6 | KM_SKB_SUNRPC_DATA, | ||
| 7 | KM_SKB_DATA_SOFTIRQ, | ||
| 8 | KM_USER0, | ||
| 9 | KM_USER1, | ||
| 10 | KM_BIO_SRC_IRQ, | ||
| 11 | KM_BIO_DST_IRQ, | ||
| 12 | KM_PTE0, | ||
| 13 | KM_PTE1, | ||
| 14 | KM_IRQ0, | ||
| 15 | KM_IRQ1, | ||
| 16 | KM_SOFTIRQ0, | ||
| 17 | KM_SOFTIRQ1, | ||
| 18 | KM_TYPE_NR | ||
| 19 | }; | ||
| 20 | |||
| 21 | #endif | ||
diff --git a/arch/blackfin/include/asm/local.h b/arch/blackfin/include/asm/local.h index 75afffbc6421..c11c530f74d0 100644 --- a/arch/blackfin/include/asm/local.h +++ b/arch/blackfin/include/asm/local.h | |||
| @@ -1,6 +1 @@ | |||
| 1 | #ifndef __BLACKFIN_LOCAL_H | ||
| 2 | #define __BLACKFIN_LOCAL_H | ||
| 3 | |||
| 4 | #include <asm-generic/local.h> | #include <asm-generic/local.h> | |
| 5 | |||
| 6 | #endif /* __BLACKFIN_LOCAL_H */ | ||
diff --git a/arch/blackfin/include/asm/mman.h b/arch/blackfin/include/asm/mman.h index b58f5ad3f024..8eebf89f5ab1 100644 --- a/arch/blackfin/include/asm/mman.h +++ b/arch/blackfin/include/asm/mman.h | |||
| @@ -1,43 +1 @@ | |||
| 1 | #ifndef __BFIN_MMAN_H__ | #include <asm-generic/mman.h> | |
| 2 | #define __BFIN_MMAN_H__ | ||
| 3 | |||
| 4 | #define PROT_READ 0x1 /* page can be read */ | ||
| 5 | #define PROT_WRITE 0x2 /* page can be written */ | ||
| 6 | #define PROT_EXEC 0x4 /* page can be executed */ | ||
| 7 | #define PROT_SEM 0x8 /* page may be used for atomic ops */ | ||
| 8 | #define PROT_NONE 0x0 /* page can not be accessed */ | ||
| 9 | #define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */ | ||
| 10 | #define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */ | ||
| 11 | |||
| 12 | #define MAP_SHARED 0x01 /* Share changes */ | ||
| 13 | #define MAP_PRIVATE 0x02 /* Changes are private */ | ||
| 14 | #define MAP_TYPE 0x0f /* Mask for type of mapping */ | ||
| 15 | #define MAP_FIXED 0x10 /* Interpret addr exactly */ | ||
| 16 | #define MAP_ANONYMOUS 0x20 /* don't use a file */ | ||
| 17 | |||
| 18 | #define MAP_GROWSDOWN 0x0100 /* stack-like segment */ | ||
| 19 | #define MAP_DENYWRITE 0x0800 /* ETXTBSY */ | ||
| 20 | #define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ | ||
| 21 | #define MAP_LOCKED 0x2000 /* pages are locked */ | ||
| 22 | #define MAP_NORESERVE 0x4000 /* don't check for reservations */ | ||
| 23 | #define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ | ||
| 24 | #define MAP_NONBLOCK 0x10000 /* do not block on IO */ | ||
| 25 | |||
| 26 | #define MS_ASYNC 1 /* sync memory asynchronously */ | ||
| 27 | #define MS_INVALIDATE 2 /* invalidate the caches */ | ||
| 28 | #define MS_SYNC 4 /* synchronous memory sync */ | ||
| 29 | |||
| 30 | #define MCL_CURRENT 1 /* lock all current mappings */ | ||
| 31 | #define MCL_FUTURE 2 /* lock all future mappings */ | ||
| 32 | |||
| 33 | #define MADV_NORMAL 0x0 /* default page-in behavior */ | ||
| 34 | #define MADV_RANDOM 0x1 /* page-in minimum required */ | ||
| 35 | #define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */ | ||
| 36 | #define MADV_WILLNEED 0x3 /* pre-fault pages */ | ||
| 37 | #define MADV_DONTNEED 0x4 /* discard these pages */ | ||
| 38 | |||
| 39 | /* compatibility flags */ | ||
| 40 | #define MAP_ANON MAP_ANONYMOUS | ||
| 41 | #define MAP_FILE 0 | ||
| 42 | |||
| 43 | #endif /* __BFIN_MMAN_H__ */ | ||
diff --git a/arch/blackfin/include/asm/msgbuf.h b/arch/blackfin/include/asm/msgbuf.h index 6fcbe8cd801d..809134c644a6 100644 --- a/arch/blackfin/include/asm/msgbuf.h +++ b/arch/blackfin/include/asm/msgbuf.h | |||
| @@ -1,31 +1 @@ | |||
| 1 | #ifndef _BFIN_MSGBUF_H | #include <asm-generic/msgbuf.h> | |
| 2 | #define _BFIN_MSGBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The msqid64_ds structure for bfin architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 64-bit time_t to solve y2038 problem | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct msqid64_ds { | ||
| 15 | struct ipc64_perm msg_perm; | ||
| 16 | __kernel_time_t msg_stime; /* last msgsnd time */ | ||
| 17 | unsigned long __unused1; | ||
| 18 | __kernel_time_t msg_rtime; /* last msgrcv time */ | ||
| 19 | unsigned long __unused2; | ||
| 20 | __kernel_time_t msg_ctime; /* last change time */ | ||
| 21 | unsigned long __unused3; | ||
| 22 | unsigned long msg_cbytes; /* current number of bytes on queue */ | ||
| 23 | unsigned long msg_qnum; /* number of messages in queue */ | ||
| 24 | unsigned long msg_qbytes; /* max number of bytes on queue */ | ||
| 25 | __kernel_pid_t msg_lspid; /* pid of last msgsnd */ | ||
| 26 | __kernel_pid_t msg_lrpid; /* last receive pid */ | ||
| 27 | unsigned long __unused4; | ||
| 28 | unsigned long __unused5; | ||
| 29 | }; | ||
| 30 | |||
| 31 | #endif /* _BFIN_MSGBUF_H */ | ||
diff --git a/arch/blackfin/include/asm/mutex-dec.h b/arch/blackfin/include/asm/mutex-dec.h deleted file mode 100644 index 0134151656af..000000000000 --- a/arch/blackfin/include/asm/mutex-dec.h +++ /dev/null | |||
| @@ -1,112 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-generic/mutex-dec.h | ||
| 3 | * | ||
| 4 | * Generic implementation of the mutex fastpath, based on atomic | ||
| 5 | * decrement/increment. | ||
| 6 | */ | ||
| 7 | #ifndef _ASM_GENERIC_MUTEX_DEC_H | ||
| 8 | #define _ASM_GENERIC_MUTEX_DEC_H | ||
| 9 | |||
| 10 | /** | ||
| 11 | * __mutex_fastpath_lock - try to take the lock by moving the count | ||
| 12 | * from 1 to a 0 value | ||
| 13 | * @count: pointer of type atomic_t | ||
| 14 | * @fail_fn: function to call if the original value was not 1 | ||
| 15 | * | ||
| 16 | * Change the count from 1 to a value lower than 1, and call <fail_fn> if | ||
| 17 | * it wasn't 1 originally. This function MUST leave the value lower than | ||
| 18 | * 1 even when the "1" assertion wasn't true. | ||
| 19 | */ | ||
| 20 | static inline void | ||
| 21 | __mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) | ||
| 22 | { | ||
| 23 | if (unlikely(atomic_dec_return(count) < 0)) | ||
| 24 | fail_fn(count); | ||
| 25 | else | ||
| 26 | smp_mb(); | ||
| 27 | } | ||
| 28 | |||
| 29 | /** | ||
| 30 | * __mutex_fastpath_lock_retval - try to take the lock by moving the count | ||
| 31 | * from 1 to a 0 value | ||
| 32 | * @count: pointer of type atomic_t | ||
| 33 | * @fail_fn: function to call if the original value was not 1 | ||
| 34 | * | ||
| 35 | * Change the count from 1 to a value lower than 1, and call <fail_fn> if | ||
| 36 | * it wasn't 1 originally. This function returns 0 if the fastpath succeeds, | ||
| 37 | * or anything the slow path function returns. | ||
| 38 | */ | ||
| 39 | static inline int | ||
| 40 | __mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *)) | ||
| 41 | { | ||
| 42 | if (unlikely(atomic_dec_return(count) < 0)) | ||
| 43 | return fail_fn(count); | ||
| 44 | else { | ||
| 45 | smp_mb(); | ||
| 46 | return 0; | ||
| 47 | } | ||
| 48 | } | ||
| 49 | |||
| 50 | /** | ||
| 51 | * __mutex_fastpath_unlock - try to promote the count from 0 to 1 | ||
| 52 | * @count: pointer of type atomic_t | ||
| 53 | * @fail_fn: function to call if the original value was not 0 | ||
| 54 | * | ||
| 55 | * Try to promote the count from 0 to 1. If it wasn't 0, call <fail_fn>. | ||
| 56 | * In the failure case, this function is allowed to either set the value to | ||
| 57 | * 1, or to set it to a value lower than 1. | ||
| 58 | * | ||
| 59 | * If the implementation sets it to a value of lower than 1, then the | ||
| 60 | * __mutex_slowpath_needs_to_unlock() macro needs to return 1, it needs | ||
| 61 | * to return 0 otherwise. | ||
| 62 | */ | ||
| 63 | static inline void | ||
| 64 | __mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) | ||
| 65 | { | ||
| 66 | smp_mb(); | ||
| 67 | if (unlikely(atomic_inc_return(count) <= 0)) | ||
| 68 | fail_fn(count); | ||
| 69 | } | ||
| 70 | |||
| 71 | #define __mutex_slowpath_needs_to_unlock() 1 | ||
| 72 | |||
| 73 | /** | ||
| 74 | * __mutex_fastpath_trylock - try to acquire the mutex, without waiting | ||
| 75 | * | ||
| 76 | * @count: pointer of type atomic_t | ||
| 77 | * @fail_fn: fallback function | ||
| 78 | * | ||
| 79 | * Change the count from 1 to a value lower than 1, and return 0 (failure) | ||
| 80 | * if it wasn't 1 originally, or return 1 (success) otherwise. This function | ||
| 81 | * MUST leave the value lower than 1 even when the "1" assertion wasn't true. | ||
| 82 | * Additionally, if the value was < 0 originally, this function must not leave | ||
| 83 | * it to 0 on failure. | ||
| 84 | * | ||
| 85 | * If the architecture has no effective trylock variant, it should call the | ||
| 86 | * <fail_fn> spinlock-based trylock variant unconditionally. | ||
| 87 | */ | ||
| 88 | static inline int | ||
| 89 | __mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *)) | ||
| 90 | { | ||
| 91 | /* | ||
| 92 | * We have two variants here. The cmpxchg based one is the best one | ||
| 93 | * because it never induce a false contention state. It is included | ||
| 94 | * here because architectures using the inc/dec algorithms over the | ||
| 95 | * xchg ones are much more likely to support cmpxchg natively. | ||
| 96 | * | ||
| 97 | * If not we fall back to the spinlock based variant - that is | ||
| 98 | * just as efficient (and simpler) as a 'destructive' probing of | ||
| 99 | * the mutex state would be. | ||
| 100 | */ | ||
| 101 | #ifdef __HAVE_ARCH_CMPXCHG | ||
| 102 | if (likely(atomic_cmpxchg(count, 1, 0) == 1)) { | ||
| 103 | smp_mb(); | ||
| 104 | return 1; | ||
| 105 | } | ||
| 106 | return 0; | ||
| 107 | #else | ||
| 108 | return fail_fn(count); | ||
| 109 | #endif | ||
| 110 | } | ||
| 111 | |||
| 112 | #endif | ||
diff --git a/arch/blackfin/include/asm/mutex.h b/arch/blackfin/include/asm/mutex.h index 5d399256bf06..5cc641c50834 100644 --- a/arch/blackfin/include/asm/mutex.h +++ b/arch/blackfin/include/asm/mutex.h | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | #define _ASM_MUTEX_H | 10 | #define _ASM_MUTEX_H |
| 11 | 11 | ||
| 12 | #ifndef CONFIG_SMP | 12 | #ifndef CONFIG_SMP |
| 13 | #include <asm-generic/mutex-dec.h> | 13 | #include <asm-generic/mutex.h> |
| 14 | #else | 14 | #else |
| 15 | 15 | ||
| 16 | static inline void | 16 | static inline void |
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h index 344f6a8c1f22..29dcf75c6112 100644 --- a/arch/blackfin/include/asm/page.h +++ b/arch/blackfin/include/asm/page.h | |||
| @@ -1,88 +1,7 @@ | |||
| 1 | #ifndef _BLACKFIN_PAGE_H | 1 | #ifndef _BLACKFIN_PAGE_H |
| 2 | #define _BLACKFIN_PAGE_H | 2 | #define _BLACKFIN_PAGE_H |
| 3 | 3 | ||
| 4 | /* PAGE_SHIFT determines the page size */ | ||
| 5 | |||
| 6 | #define PAGE_SHIFT 12 | ||
| 7 | #ifdef __ASSEMBLY__ | ||
| 8 | #define PAGE_SIZE (1 << PAGE_SHIFT) | ||
| 9 | #else | ||
| 10 | #define PAGE_SIZE (1UL << PAGE_SHIFT) | ||
| 11 | #endif | ||
| 12 | #define PAGE_MASK (~(PAGE_SIZE-1)) | ||
| 13 | |||
| 14 | #include <asm/setup.h> | ||
| 15 | |||
| 16 | #ifndef __ASSEMBLY__ | ||
| 17 | |||
| 18 | #define get_user_page(vaddr) __get_free_page(GFP_KERNEL) | ||
| 19 | #define free_user_page(page, addr) free_page(addr) | ||
| 20 | |||
| 21 | #define clear_page(page) memset((page), 0, PAGE_SIZE) | ||
| 22 | #define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) | ||
| 23 | |||
| 24 | #define clear_user_page(page, vaddr,pg) clear_page(page) | ||
| 25 | #define copy_user_page(to, from, vaddr,pg) copy_page(to, from) | ||
| 26 | |||
| 27 | /* | ||
| 28 | * These are used to make use of C type-checking.. | ||
| 29 | */ | ||
| 30 | typedef struct { | ||
| 31 | unsigned long pte; | ||
| 32 | } pte_t; | ||
| 33 | typedef struct { | ||
| 34 | unsigned long pmd[16]; | ||
| 35 | } pmd_t; | ||
| 36 | typedef struct { | ||
| 37 | unsigned long pgd; | ||
| 38 | } pgd_t; | ||
| 39 | typedef struct { | ||
| 40 | unsigned long pgprot; | ||
| 41 | } pgprot_t; | ||
| 42 | typedef struct page *pgtable_t; | ||
| 43 | |||
| 44 | #define pte_val(x) ((x).pte) | ||
| 45 | #define pmd_val(x) ((&x)->pmd[0]) | ||
| 46 | #define pgd_val(x) ((x).pgd) | ||
| 47 | #define pgprot_val(x) ((x).pgprot) | ||
| 48 | |||
| 49 | #define __pte(x) ((pte_t) { (x) } ) | ||
| 50 | #define __pmd(x) ((pmd_t) { (x) } ) | ||
| 51 | #define __pgd(x) ((pgd_t) { (x) } ) | ||
| 52 | #define __pgprot(x) ((pgprot_t) { (x) } ) | ||
| 53 | |||
| 54 | extern unsigned long memory_start; | ||
| 55 | extern unsigned long memory_end; | ||
| 56 | |||
| 57 | #endif /* !__ASSEMBLY__ */ | ||
| 58 | |||
| 59 | #include <asm/page_offset.h> | ||
| 60 | #include <asm/io.h> | ||
| 61 | |||
| 62 | #define PAGE_OFFSET (PAGE_OFFSET_RAW) | ||
| 63 | |||
| 64 | #ifndef __ASSEMBLY__ | ||
| 65 | |||
| 66 | #define __pa(vaddr) virt_to_phys((void *)(vaddr)) | ||
| 67 | #define __va(paddr) phys_to_virt((unsigned long)(paddr)) | ||
| 68 | |||
| 69 | #define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) | ||
| 70 | |||
| 71 | #define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT) | ||
| 72 | #define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT) | ||
| 73 | #define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) | ||
| 74 | #define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) | ||
| 75 | #define VALID_PAGE(page) ((page - mem_map) < max_mapnr) | ||
| 76 | |||
| 77 | #define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn)) | ||
| 78 | #define page_to_pfn(page) virt_to_pfn(page_to_virt(page)) | ||
| 79 | #define pfn_valid(pfn) ((pfn) < max_mapnr) | ||
| 80 | |||
| 81 | #define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \ | ||
| 82 | ((void *)(kaddr) < (void *)memory_end)) | ||
| 83 | |||
| 84 | #include <asm-generic/page.h> | 4 | #include <asm-generic/page.h> |
| 5 | #define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) | ||
| 85 | 6 | ||
| 86 | #endif /* __ASSEMBLY__ */ | 7 | #endif |
| 87 | |||
| 88 | #endif /* _BLACKFIN_PAGE_H */ | ||
diff --git a/arch/blackfin/include/asm/param.h b/arch/blackfin/include/asm/param.h index 41564a6347f8..965d45427975 100644 --- a/arch/blackfin/include/asm/param.h +++ b/arch/blackfin/include/asm/param.h | |||
| @@ -1,22 +1 @@ | |||
| 1 | #ifndef _BLACKFIN_PARAM_H | #include <asm-generic/param.h> | |
| 2 | #define _BLACKFIN_PARAM_H | ||
| 3 | |||
| 4 | #ifdef __KERNEL__ | ||
| 5 | #define HZ CONFIG_HZ | ||
| 6 | #define USER_HZ 100 | ||
| 7 | #define CLOCKS_PER_SEC (USER_HZ) | ||
| 8 | #endif | ||
| 9 | |||
| 10 | #ifndef HZ | ||
| 11 | #define HZ 100 | ||
| 12 | #endif | ||
| 13 | |||
| 14 | #define EXEC_PAGESIZE 4096 | ||
| 15 | |||
| 16 | #ifndef NOGROUP | ||
| 17 | #define NOGROUP (-1) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #define MAXHOSTNAMELEN 64 /* max length of hostname */ | ||
| 21 | |||
| 22 | #endif /* _BLACKFIN_PARAM_H */ | ||
diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h index a67142740df0..b42555c1431c 100644 --- a/arch/blackfin/include/asm/pda.h +++ b/arch/blackfin/include/asm/pda.h | |||
| @@ -64,8 +64,6 @@ struct blackfin_pda { /* Per-processor Data Area */ | |||
| 64 | 64 | ||
| 65 | extern struct blackfin_pda cpu_pda[]; | 65 | extern struct blackfin_pda cpu_pda[]; |
| 66 | 66 | ||
| 67 | void reserve_pda(void); | ||
| 68 | |||
| 69 | #endif /* __ASSEMBLY__ */ | 67 | #endif /* __ASSEMBLY__ */ |
| 70 | 68 | ||
| 71 | #endif /* _ASM_BLACKFIN_PDA_H */ | 69 | #endif /* _ASM_BLACKFIN_PDA_H */ |
diff --git a/arch/blackfin/include/asm/percpu.h b/arch/blackfin/include/asm/percpu.h index c94c7bc88c71..06a959d67234 100644 --- a/arch/blackfin/include/asm/percpu.h +++ b/arch/blackfin/include/asm/percpu.h | |||
| @@ -1,6 +1 @@ | |||
| 1 | #ifndef __ARCH_BLACKFIN_PERCPU__ | ||
| 2 | #define __ARCH_BLACKFIN_PERCPU__ | ||
| 3 | |||
| 4 | #include <asm-generic/percpu.h> | #include <asm-generic/percpu.h> | |
| 5 | |||
| 6 | #endif /* __ARCH_BLACKFIN_PERCPU__ */ | ||
diff --git a/arch/blackfin/include/asm/pgalloc.h b/arch/blackfin/include/asm/pgalloc.h index c686e0542fd0..f261cb7dda06 100644 --- a/arch/blackfin/include/asm/pgalloc.h +++ b/arch/blackfin/include/asm/pgalloc.h | |||
| @@ -1,8 +1 @@ | |||
| 1 | #ifndef _BLACKFIN_PGALLOC_H | #include <asm-generic/pgalloc.h> | |
| 2 | #define _BLACKFIN_PGALLOC_H | ||
| 3 | |||
| 4 | #include <asm/setup.h> | ||
| 5 | |||
| 6 | #define check_pgt_cache() do { } while (0) | ||
| 7 | |||
| 8 | #endif /* _BLACKFIN_PGALLOC_H */ | ||
diff --git a/arch/blackfin/include/asm/poll.h b/arch/blackfin/include/asm/poll.h index 94cc2636e0e2..a0556671357b 100644 --- a/arch/blackfin/include/asm/poll.h +++ b/arch/blackfin/include/asm/poll.h | |||
| @@ -1,24 +1,9 @@ | |||
| 1 | #ifndef __BFIN_POLL_H | 1 | #ifndef __BFIN_POLL_H |
| 2 | #define __BFIN_POLL_H | 2 | #define __BFIN_POLL_H |
| 3 | 3 | ||
| 4 | #define POLLIN 1 | 4 | #define POLLWRNORM 4 /* POLLOUT */ |
| 5 | #define POLLPRI 2 | ||
| 6 | #define POLLOUT 4 | ||
| 7 | #define POLLERR 8 | ||
| 8 | #define POLLHUP 16 | ||
| 9 | #define POLLNVAL 32 | ||
| 10 | #define POLLRDNORM 64 | ||
| 11 | #define POLLWRNORM POLLOUT | ||
| 12 | #define POLLRDBAND 128 | ||
| 13 | #define POLLWRBAND 256 | 5 | #define POLLWRBAND 256 |
| 14 | #define POLLMSG 0x0400 | ||
| 15 | #define POLLREMOVE 0x1000 | ||
| 16 | #define POLLRDHUP 0x2000 | ||
| 17 | 6 | ||
| 18 | struct pollfd { | 7 | #include <asm-generic/poll.h> |
| 19 | int fd; | ||
| 20 | short events; | ||
| 21 | short revents; | ||
| 22 | }; | ||
| 23 | 8 | ||
| 24 | #endif /* __BFIN_POLL_H */ | 9 | #endif |
diff --git a/arch/blackfin/include/asm/posix_types.h b/arch/blackfin/include/asm/posix_types.h index 23aa1f8c1bd1..80c9d64eb26c 100644 --- a/arch/blackfin/include/asm/posix_types.h +++ b/arch/blackfin/include/asm/posix_types.h | |||
| @@ -1,61 +1,27 @@ | |||
| 1 | #ifndef __ARCH_BFIN_POSIX_TYPES_H | 1 | #ifndef __ARCH_BFIN_POSIX_TYPES_H |
| 2 | #define __ARCH_BFIN_POSIX_TYPES_H | 2 | #define __ARCH_BFIN_POSIX_TYPES_H |
| 3 | 3 | ||
| 4 | /* | ||
| 5 | * This file is generally used by user-level software, so you need to | ||
| 6 | * be a little careful about namespace pollution etc. Also, we cannot | ||
| 7 | * assume GCC is being used. | ||
| 8 | */ | ||
| 9 | |||
| 10 | typedef unsigned long __kernel_ino_t; | ||
| 11 | typedef unsigned short __kernel_mode_t; | 4 | typedef unsigned short __kernel_mode_t; |
| 5 | #define __kernel_mode_t __kernel_mode_t | ||
| 6 | |||
| 12 | typedef unsigned short __kernel_nlink_t; | 7 | typedef unsigned short __kernel_nlink_t; |
| 13 | typedef long __kernel_off_t; | 8 | #define __kernel_nlink_t __kernel_nlink_t |
| 14 | typedef int __kernel_pid_t; | 9 | |
| 15 | typedef unsigned int __kernel_ipc_pid_t; | 10 | typedef unsigned int __kernel_ipc_pid_t; |
| 16 | typedef unsigned int __kernel_uid_t; | 11 | #define __kernel_ipc_pid_t __kernel_ipc_pid_t |
| 17 | typedef unsigned int __kernel_gid_t; | 12 | |
| 18 | typedef unsigned long __kernel_size_t; | 13 | typedef unsigned long __kernel_size_t; |
| 19 | typedef long __kernel_ssize_t; | 14 | typedef long __kernel_ssize_t; |
| 20 | typedef int __kernel_ptrdiff_t; | 15 | typedef int __kernel_ptrdiff_t; |
| 21 | typedef long __kernel_time_t; | 16 | #define __kernel_size_t __kernel_size_t |
| 22 | typedef long __kernel_suseconds_t; | ||
| 23 | typedef long __kernel_clock_t; | ||
| 24 | typedef int __kernel_timer_t; | ||
| 25 | typedef int __kernel_clockid_t; | ||
| 26 | typedef int __kernel_daddr_t; | ||
| 27 | typedef char *__kernel_caddr_t; | ||
| 28 | typedef unsigned short __kernel_uid16_t; | ||
| 29 | typedef unsigned short __kernel_gid16_t; | ||
| 30 | typedef unsigned int __kernel_uid32_t; | ||
| 31 | typedef unsigned int __kernel_gid32_t; | ||
| 32 | 17 | ||
| 33 | typedef unsigned short __kernel_old_uid_t; | 18 | typedef unsigned short __kernel_old_uid_t; |
| 34 | typedef unsigned short __kernel_old_gid_t; | 19 | typedef unsigned short __kernel_old_gid_t; |
| 35 | typedef unsigned short __kernel_old_dev_t; | 20 | #define __kernel_old_uid_t __kernel_old_uid_t |
| 36 | |||
| 37 | #ifdef __GNUC__ | ||
| 38 | typedef long long __kernel_loff_t; | ||
| 39 | #endif | ||
| 40 | 21 | ||
| 41 | typedef struct { | 22 | typedef unsigned short __kernel_old_dev_t; |
| 42 | int val[2]; | 23 | #define __kernel_old_dev_t __kernel_old_dev_t |
| 43 | } __kernel_fsid_t; | ||
| 44 | |||
| 45 | #if defined(__KERNEL__) | ||
| 46 | |||
| 47 | #undef __FD_SET | ||
| 48 | #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) | ||
| 49 | |||
| 50 | #undef __FD_CLR | ||
| 51 | #define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) | ||
| 52 | |||
| 53 | #undef __FD_ISSET | ||
| 54 | #define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) | ||
| 55 | |||
| 56 | #undef __FD_ZERO | ||
| 57 | #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) | ||
| 58 | 24 | ||
| 59 | #endif /* defined(__KERNEL__) */ | 25 | #include <asm-generic/posix_types.h> |
| 60 | 26 | ||
| 61 | #endif | 27 | #endif |
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h index 0eece23b41c7..d0be99be8308 100644 --- a/arch/blackfin/include/asm/processor.h +++ b/arch/blackfin/include/asm/processor.h | |||
| @@ -7,9 +7,8 @@ | |||
| 7 | */ | 7 | */ |
| 8 | #define current_text_addr() ({ __label__ _l; _l: &&_l;}) | 8 | #define current_text_addr() ({ __label__ _l; _l: &&_l;}) |
| 9 | 9 | ||
| 10 | #include <asm/ptrace.h> | ||
| 10 | #include <asm/blackfin.h> | 11 | #include <asm/blackfin.h> |
| 11 | #include <asm/segment.h> | ||
| 12 | #include <linux/compiler.h> | ||
| 13 | 12 | ||
| 14 | static inline unsigned long rdusp(void) | 13 | static inline unsigned long rdusp(void) |
| 15 | { | 14 | { |
| @@ -59,36 +58,8 @@ struct thread_struct { | |||
| 59 | PS_S, 0, 0 \ | 58 | PS_S, 0, 0 \ |
| 60 | } | 59 | } |
| 61 | 60 | ||
| 62 | /* | 61 | extern void start_thread(struct pt_regs *regs, unsigned long new_ip, |
| 63 | * Do necessary setup to start up a newly executed thread. | 62 | unsigned long new_sp); |
| 64 | * | ||
| 65 | * pass the data segment into user programs if it exists, | ||
| 66 | * it can't hurt anything as far as I can tell | ||
| 67 | */ | ||
| 68 | #ifndef CONFIG_SMP | ||
| 69 | #define start_thread(_regs, _pc, _usp) \ | ||
| 70 | do { \ | ||
| 71 | set_fs(USER_DS); \ | ||
| 72 | (_regs)->pc = (_pc); \ | ||
| 73 | if (current->mm) \ | ||
| 74 | (_regs)->p5 = current->mm->start_data; \ | ||
| 75 | task_thread_info(current)->l1_task_info.stack_start \ | ||
| 76 | = (void *)current->mm->context.stack_start; \ | ||
| 77 | task_thread_info(current)->l1_task_info.lowest_sp = (void *)(_usp); \ | ||
| 78 | memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info, \ | ||
| 79 | sizeof(*L1_SCRATCH_TASK_INFO)); \ | ||
| 80 | wrusp(_usp); \ | ||
| 81 | } while(0) | ||
| 82 | #else | ||
| 83 | #define start_thread(_regs, _pc, _usp) \ | ||
| 84 | do { \ | ||
| 85 | set_fs(USER_DS); \ | ||
| 86 | (_regs)->pc = (_pc); \ | ||
| 87 | if (current->mm) \ | ||
| 88 | (_regs)->p5 = current->mm->start_data; \ | ||
| 89 | wrusp(_usp); \ | ||
| 90 | } while (0) | ||
| 91 | #endif | ||
| 92 | 63 | ||
| 93 | /* Forward declaration, a strange C thing */ | 64 | /* Forward declaration, a strange C thing */ |
| 94 | struct task_struct; | 65 | struct task_struct; |
| @@ -131,8 +102,8 @@ unsigned long get_wchan(struct task_struct *p); | |||
| 131 | /* Get the Silicon Revision of the chip */ | 102 | /* Get the Silicon Revision of the chip */ |
| 132 | static inline uint32_t __pure bfin_revid(void) | 103 | static inline uint32_t __pure bfin_revid(void) |
| 133 | { | 104 | { |
| 134 | /* stored in the upper 4 bits */ | 105 | /* Always use CHIPID, to work around ANOMALY_05000234 */ |
| 135 | uint32_t revid = bfin_read_CHIPID() >> 28; | 106 | uint32_t revid = (bfin_read_CHIPID() & CHIPID_VERSION) >> 28; |
| 136 | 107 | ||
| 137 | #ifdef CONFIG_BF52x | 108 | #ifdef CONFIG_BF52x |
| 138 | /* ANOMALY_05000357 | 109 | /* ANOMALY_05000357 |
diff --git a/arch/blackfin/include/asm/resource.h b/arch/blackfin/include/asm/resource.h index 091355ab3495..04bc4db8921b 100644 --- a/arch/blackfin/include/asm/resource.h +++ b/arch/blackfin/include/asm/resource.h | |||
| @@ -1,6 +1 @@ | |||
| 1 | #ifndef _BFIN_RESOURCE_H | ||
| 2 | #define _BFIN_RESOURCE_H | ||
| 3 | |||
| 4 | #include <asm-generic/resource.h> | #include <asm-generic/resource.h> | |
| 5 | |||
| 6 | #endif /* _BFIN_RESOURCE_H */ | ||
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h index 1443c3353a8c..e7fd0ecd73f7 100644 --- a/arch/blackfin/include/asm/sections.h +++ b/arch/blackfin/include/asm/sections.h | |||
| @@ -4,4 +4,15 @@ | |||
| 4 | /* nothing to see, move along */ | 4 | /* nothing to see, move along */ |
| 5 | #include <asm-generic/sections.h> | 5 | #include <asm-generic/sections.h> |
| 6 | 6 | ||
| 7 | /* only used when MTD_UCLINUX */ | ||
| 8 | extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size; | ||
| 9 | |||
| 10 | extern unsigned long _ramstart, _ramend, _rambase; | ||
| 11 | extern unsigned long memory_start, memory_end, physical_mem_end; | ||
| 12 | |||
| 13 | extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[], | ||
| 14 | _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _sbss_b_l1[], _ebss_b_l1[], | ||
| 15 | _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[], | ||
| 16 | _ebss_l2[], _l2_lma_start[]; | ||
| 17 | |||
| 7 | #endif | 18 | #endif |
diff --git a/arch/blackfin/include/asm/sembuf.h b/arch/blackfin/include/asm/sembuf.h index 18deb5c7fa5d..7673b83cfef7 100644 --- a/arch/blackfin/include/asm/sembuf.h +++ b/arch/blackfin/include/asm/sembuf.h | |||
| @@ -1,25 +1 @@ | |||
| 1 | #ifndef _BFIN_SEMBUF_H | #include <asm-generic/sembuf.h> | |
| 2 | #define _BFIN_SEMBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The semid64_ds structure for bfin architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 64-bit time_t to solve y2038 problem | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct semid64_ds { | ||
| 15 | struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ | ||
| 16 | __kernel_time_t sem_otime; /* last semop time */ | ||
| 17 | unsigned long __unused1; | ||
| 18 | __kernel_time_t sem_ctime; /* last change time */ | ||
| 19 | unsigned long __unused2; | ||
| 20 | unsigned long sem_nsems; /* no. of semaphores in array */ | ||
| 21 | unsigned long __unused3; | ||
| 22 | unsigned long __unused4; | ||
| 23 | }; | ||
| 24 | |||
| 25 | #endif /* _BFIN_SEMBUF_H */ | ||
diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h index 3a47606c858b..94a4a12e3bf2 100644 --- a/arch/blackfin/include/asm/serial.h +++ b/arch/blackfin/include/asm/serial.h | |||
| @@ -1,6 +1,2 @@ | |||
| 1 | /* | 1 | #include <asm-generic/serial.h> |
| 2 | * include/asm-blackfin/serial.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH | 2 | #define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH |
| 6 | #define BASE_BAUD (1843200 / 16) | ||
diff --git a/arch/blackfin/include/asm/setup.h b/arch/blackfin/include/asm/setup.h index 01c8c6cbe6fc..552df83f1a49 100644 --- a/arch/blackfin/include/asm/setup.h +++ b/arch/blackfin/include/asm/setup.h | |||
| @@ -1,17 +1 @@ | |||
| 1 | /* | #include <asm-generic/setup.h> | |
| 2 | ** asm/setup.h -- Definition of the Linux/bfin setup information | ||
| 3 | ** | ||
| 4 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 5 | ** License. See the file COPYING in the main directory of this archive | ||
| 6 | ** for more details. | ||
| 7 | ** | ||
| 8 | ** Copyright Lineo, Inc 2001 Tony Kou | ||
| 9 | ** | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _BFIN_SETUP_H | ||
| 13 | #define _BFIN_SETUP_H | ||
| 14 | |||
| 15 | #define COMMAND_LINE_SIZE 512 | ||
| 16 | |||
| 17 | #endif /* _BFIN_SETUP_H */ | ||
diff --git a/arch/blackfin/include/asm/shmbuf.h b/arch/blackfin/include/asm/shmbuf.h index 612436303e89..83c05fc2de38 100644 --- a/arch/blackfin/include/asm/shmbuf.h +++ b/arch/blackfin/include/asm/shmbuf.h | |||
| @@ -1,42 +1 @@ | |||
| 1 | #ifndef _BFIN_SHMBUF_H | #include <asm-generic/shmbuf.h> | |
| 2 | #define _BFIN_SHMBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The shmid64_ds structure for bfin architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 64-bit time_t to solve y2038 problem | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct shmid64_ds { | ||
| 15 | struct ipc64_perm shm_perm; /* operation perms */ | ||
| 16 | size_t shm_segsz; /* size of segment (bytes) */ | ||
| 17 | __kernel_time_t shm_atime; /* last attach time */ | ||
| 18 | unsigned long __unused1; | ||
| 19 | __kernel_time_t shm_dtime; /* last detach time */ | ||
| 20 | unsigned long __unused2; | ||
| 21 | __kernel_time_t shm_ctime; /* last change time */ | ||
| 22 | unsigned long __unused3; | ||
| 23 | __kernel_pid_t shm_cpid; /* pid of creator */ | ||
| 24 | __kernel_pid_t shm_lpid; /* pid of last operator */ | ||
| 25 | unsigned long shm_nattch; /* no. of current attaches */ | ||
| 26 | unsigned long __unused4; | ||
| 27 | unsigned long __unused5; | ||
| 28 | }; | ||
| 29 | |||
| 30 | struct shminfo64 { | ||
| 31 | unsigned long shmmax; | ||
| 32 | unsigned long shmmin; | ||
| 33 | unsigned long shmmni; | ||
| 34 | unsigned long shmseg; | ||
| 35 | unsigned long shmall; | ||
| 36 | unsigned long __unused1; | ||
| 37 | unsigned long __unused2; | ||
| 38 | unsigned long __unused3; | ||
| 39 | unsigned long __unused4; | ||
| 40 | }; | ||
| 41 | |||
| 42 | #endif /* _BFIN_SHMBUF_H */ | ||
diff --git a/arch/blackfin/include/asm/shmparam.h b/arch/blackfin/include/asm/shmparam.h index 3c03906b7664..93f30deb95d0 100644 --- a/arch/blackfin/include/asm/shmparam.h +++ b/arch/blackfin/include/asm/shmparam.h | |||
| @@ -1,6 +1 @@ | |||
| 1 | #ifndef _BFIN_SHMPARAM_H | #include <asm-generic/shmparam.h> | |
| 2 | #define _BFIN_SHMPARAM_H | ||
| 3 | |||
| 4 | #define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ | ||
| 5 | |||
| 6 | #endif /* _BFIN_SHMPARAM_H */ | ||
diff --git a/arch/blackfin/include/asm/signal.h b/arch/blackfin/include/asm/signal.h index 87951d251458..77a3bf37b69d 100644 --- a/arch/blackfin/include/asm/signal.h +++ b/arch/blackfin/include/asm/signal.h | |||
| @@ -1,160 +1,7 @@ | |||
| 1 | #ifndef _BLACKFIN_SIGNAL_H | 1 | #ifndef _BLACKFIN_SIGNAL_H |
| 2 | #define _BLACKFIN_SIGNAL_H | 2 | #define _BLACKFIN_SIGNAL_H |
| 3 | 3 | ||
| 4 | #include <linux/types.h> | 4 | #define SA_RESTORER 0x04000000 |
| 5 | |||
| 6 | /* Avoid too many header ordering problems. */ | ||
| 7 | struct siginfo; | ||
| 8 | |||
| 9 | #ifdef __KERNEL__ | ||
| 10 | /* Most things should be clean enough to redefine this at will, if care | ||
| 11 | is taken to make libc match. */ | ||
| 12 | |||
| 13 | #define _NSIG 64 | ||
| 14 | #define _NSIG_BPW 32 | ||
| 15 | #define _NSIG_WORDS (_NSIG / _NSIG_BPW) | ||
| 16 | |||
| 17 | typedef unsigned long old_sigset_t; /* at least 32 bits */ | ||
| 18 | |||
| 19 | typedef struct { | ||
| 20 | unsigned long sig[_NSIG_WORDS]; | ||
| 21 | } sigset_t; | ||
| 22 | |||
| 23 | #else | ||
| 24 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 25 | |||
| 26 | #define NSIG 32 | ||
| 27 | typedef unsigned long sigset_t; | ||
| 28 | |||
| 29 | #endif /* __KERNEL__ */ | ||
| 30 | |||
| 31 | #define SIGHUP 1 | ||
| 32 | #define SIGINT 2 | ||
| 33 | #define SIGQUIT 3 | ||
| 34 | #define SIGILL 4 | ||
| 35 | #define SIGTRAP 5 | ||
| 36 | #define SIGABRT 6 | ||
| 37 | #define SIGIOT 6 | ||
| 38 | #define SIGBUS 7 | ||
| 39 | #define SIGFPE 8 | ||
| 40 | #define SIGKILL 9 | ||
| 41 | #define SIGUSR1 10 | ||
| 42 | #define SIGSEGV 11 | ||
| 43 | #define SIGUSR2 12 | ||
| 44 | #define SIGPIPE 13 | ||
| 45 | #define SIGALRM 14 | ||
| 46 | #define SIGTERM 15 | ||
| 47 | #define SIGSTKFLT 16 | ||
| 48 | #define SIGCHLD 17 | ||
| 49 | #define SIGCONT 18 | ||
| 50 | #define SIGSTOP 19 | ||
| 51 | #define SIGTSTP 20 | ||
| 52 | #define SIGTTIN 21 | ||
| 53 | #define SIGTTOU 22 | ||
| 54 | #define SIGURG 23 | ||
| 55 | #define SIGXCPU 24 | ||
| 56 | #define SIGXFSZ 25 | ||
| 57 | #define SIGVTALRM 26 | ||
| 58 | #define SIGPROF 27 | ||
| 59 | #define SIGWINCH 28 | ||
| 60 | #define SIGIO 29 | ||
| 61 | #define SIGPOLL SIGIO | ||
| 62 | /* | ||
| 63 | #define SIGLOST 29 | ||
| 64 | */ | ||
| 65 | #define SIGPWR 30 | ||
| 66 | #define SIGSYS 31 | ||
| 67 | #define SIGUNUSED 31 | ||
| 68 | |||
| 69 | /* These should not be considered constants from userland. */ | ||
| 70 | #define SIGRTMIN 32 | ||
| 71 | #define SIGRTMAX _NSIG | ||
| 72 | |||
| 73 | /* | ||
| 74 | * SA_FLAGS values: | ||
| 75 | * | ||
| 76 | * SA_ONSTACK indicates that a registered stack_t will be used. | ||
| 77 | * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the | ||
| 78 | * SA_RESTART flag to get restarting signals (which were the default long ago) | ||
| 79 | * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. | ||
| 80 | * SA_RESETHAND clears the handler when the signal is delivered. | ||
| 81 | * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. | ||
| 82 | * SA_NODEFER prevents the current signal from being masked in the handler. | ||
| 83 | * | ||
| 84 | * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single | ||
| 85 | * Unix names RESETHAND and NODEFER respectively. | ||
| 86 | */ | ||
| 87 | #define SA_NOCLDSTOP 0x00000001 | ||
| 88 | #define SA_NOCLDWAIT 0x00000002 /* not supported yet */ | ||
| 89 | #define SA_SIGINFO 0x00000004 | ||
| 90 | #define SA_ONSTACK 0x08000000 | ||
| 91 | #define SA_RESTART 0x10000000 | ||
| 92 | #define SA_NODEFER 0x40000000 | ||
| 93 | #define SA_RESETHAND 0x80000000 | ||
| 94 | |||
| 95 | #define SA_NOMASK SA_NODEFER | ||
| 96 | #define SA_ONESHOT SA_RESETHAND | ||
| 97 | |||
| 98 | /* | ||
| 99 | * sigaltstack controls | ||
| 100 | */ | ||
| 101 | #define SS_ONSTACK 1 | ||
| 102 | #define SS_DISABLE 2 | ||
| 103 | |||
| 104 | #define MINSIGSTKSZ 2048 | ||
| 105 | #define SIGSTKSZ 8192 | ||
| 106 | |||
| 107 | #include <asm-generic/signal.h> | 5 | #include <asm-generic/signal.h> |
| 108 | 6 | ||
| 109 | #ifdef __KERNEL__ | 7 | #endif |
| 110 | struct old_sigaction { | ||
| 111 | __sighandler_t sa_handler; | ||
| 112 | old_sigset_t sa_mask; | ||
| 113 | unsigned long sa_flags; | ||
| 114 | void (*sa_restorer) (void); | ||
| 115 | }; | ||
| 116 | |||
| 117 | struct sigaction { | ||
| 118 | __sighandler_t sa_handler; | ||
| 119 | unsigned long sa_flags; | ||
| 120 | void (*sa_restorer) (void); | ||
| 121 | sigset_t sa_mask; /* mask last for extensibility */ | ||
| 122 | }; | ||
| 123 | |||
| 124 | struct k_sigaction { | ||
| 125 | struct sigaction sa; | ||
| 126 | }; | ||
| 127 | #else | ||
| 128 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 129 | |||
| 130 | struct sigaction { | ||
| 131 | union { | ||
| 132 | __sighandler_t _sa_handler; | ||
| 133 | void (*_sa_sigaction) (int, struct siginfo *, void *); | ||
| 134 | } _u; | ||
| 135 | sigset_t sa_mask; | ||
| 136 | unsigned long sa_flags; | ||
| 137 | void (*sa_restorer) (void); | ||
| 138 | }; | ||
| 139 | |||
| 140 | #define sa_handler _u._sa_handler | ||
| 141 | #define sa_sigaction _u._sa_sigaction | ||
| 142 | |||
| 143 | #endif /* __KERNEL__ */ | ||
| 144 | |||
| 145 | typedef struct sigaltstack { | ||
| 146 | void __user *ss_sp; | ||
| 147 | int ss_flags; | ||
| 148 | size_t ss_size; | ||
| 149 | } stack_t; | ||
| 150 | |||
| 151 | #ifdef __KERNEL__ | ||
| 152 | |||
| 153 | #include <asm/sigcontext.h> | ||
| 154 | #undef __HAVE_ARCH_SIG_BITOPS | ||
| 155 | |||
| 156 | #define ptrace_signal_deliver(regs, cookie) do { } while (0) | ||
| 157 | |||
| 158 | #endif /* __KERNEL__ */ | ||
| 159 | |||
| 160 | #endif /* _BLACKFIN_SIGNAL_H */ | ||
diff --git a/arch/blackfin/include/asm/socket.h b/arch/blackfin/include/asm/socket.h index fac7fe9e1f8a..6b71384b9d8b 100644 --- a/arch/blackfin/include/asm/socket.h +++ b/arch/blackfin/include/asm/socket.h | |||
| @@ -1,59 +1 @@ | |||
| 1 | #ifndef _ASM_SOCKET_H | #include <asm-generic/socket.h> | |
| 2 | #define _ASM_SOCKET_H | ||
| 3 | |||
| 4 | #include <asm/sockios.h> | ||
| 5 | |||
| 6 | /* For setsockoptions(2) */ | ||
| 7 | #define SOL_SOCKET 1 | ||
| 8 | |||
| 9 | #define SO_DEBUG 1 | ||
| 10 | #define SO_REUSEADDR 2 | ||
| 11 | #define SO_TYPE 3 | ||
| 12 | #define SO_ERROR 4 | ||
| 13 | #define SO_DONTROUTE 5 | ||
| 14 | #define SO_BROADCAST 6 | ||
| 15 | #define SO_SNDBUF 7 | ||
| 16 | #define SO_RCVBUF 8 | ||
| 17 | #define SO_SNDBUFFORCE 32 | ||
| 18 | #define SO_RCVBUFFORCE 33 | ||
| 19 | #define SO_KEEPALIVE 9 | ||
| 20 | #define SO_OOBINLINE 10 | ||
| 21 | #define SO_NO_CHECK 11 | ||
| 22 | #define SO_PRIORITY 12 | ||
| 23 | #define SO_LINGER 13 | ||
| 24 | #define SO_BSDCOMPAT 14 | ||
| 25 | /* To add :#define SO_REUSEPORT 15 */ | ||
| 26 | #define SO_PASSCRED 16 | ||
| 27 | #define SO_PEERCRED 17 | ||
| 28 | #define SO_RCVLOWAT 18 | ||
| 29 | #define SO_SNDLOWAT 19 | ||
| 30 | #define SO_RCVTIMEO 20 | ||
| 31 | #define SO_SNDTIMEO 21 | ||
| 32 | |||
| 33 | /* Security levels - as per NRL IPv6 - don't actually do anything */ | ||
| 34 | #define SO_SECURITY_AUTHENTICATION 22 | ||
| 35 | #define SO_SECURITY_ENCRYPTION_TRANSPORT 23 | ||
| 36 | #define SO_SECURITY_ENCRYPTION_NETWORK 24 | ||
| 37 | |||
| 38 | #define SO_BINDTODEVICE 25 | ||
| 39 | |||
| 40 | /* Socket filtering */ | ||
| 41 | #define SO_ATTACH_FILTER 26 | ||
| 42 | #define SO_DETACH_FILTER 27 | ||
| 43 | |||
| 44 | #define SO_PEERNAME 28 | ||
| 45 | #define SO_TIMESTAMP 29 | ||
| 46 | #define SCM_TIMESTAMP SO_TIMESTAMP | ||
| 47 | |||
| 48 | #define SO_ACCEPTCONN 30 | ||
| 49 | #define SO_PEERSEC 31 | ||
| 50 | #define SO_PASSSEC 34 | ||
| 51 | #define SO_TIMESTAMPNS 35 | ||
| 52 | #define SCM_TIMESTAMPNS SO_TIMESTAMPNS | ||
| 53 | |||
| 54 | #define SO_MARK 36 | ||
| 55 | |||
| 56 | #define SO_TIMESTAMPING 37 | ||
| 57 | #define SCM_TIMESTAMPING SO_TIMESTAMPING | ||
| 58 | |||
| 59 | #endif /* _ASM_SOCKET_H */ | ||
diff --git a/arch/blackfin/include/asm/sockios.h b/arch/blackfin/include/asm/sockios.h index 426b89bfaa8b..def6d4746ee7 100644 --- a/arch/blackfin/include/asm/sockios.h +++ b/arch/blackfin/include/asm/sockios.h | |||
| @@ -1,13 +1 @@ | |||
| 1 | #ifndef __ARCH_BFIN_SOCKIOS__ | #include <asm-generic/sockios.h> | |
| 2 | #define __ARCH_BFIN_SOCKIOS__ | ||
| 3 | |||
| 4 | /* Socket-level I/O control calls. */ | ||
| 5 | #define FIOSETOWN 0x8901 | ||
| 6 | #define SIOCSPGRP 0x8902 | ||
| 7 | #define FIOGETOWN 0x8903 | ||
| 8 | #define SIOCGPGRP 0x8904 | ||
| 9 | #define SIOCATMARK 0x8905 | ||
| 10 | #define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ | ||
| 11 | #define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ | ||
| 12 | |||
| 13 | #endif /* __ARCH_BFIN_SOCKIOS__ */ | ||
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h index 0249ac319476..d6ff4b59fcb1 100644 --- a/arch/blackfin/include/asm/spinlock.h +++ b/arch/blackfin/include/asm/spinlock.h | |||
| @@ -1,6 +1,10 @@ | |||
| 1 | #ifndef __BFIN_SPINLOCK_H | 1 | #ifndef __BFIN_SPINLOCK_H |
| 2 | #define __BFIN_SPINLOCK_H | 2 | #define __BFIN_SPINLOCK_H |
| 3 | 3 | ||
| 4 | #ifndef CONFIG_SMP | ||
| 5 | # include <asm-generic/spinlock.h> | ||
| 6 | #else | ||
| 7 | |||
| 4 | #include <asm/atomic.h> | 8 | #include <asm/atomic.h> |
| 5 | 9 | ||
| 6 | asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr); | 10 | asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr); |
| @@ -86,4 +90,6 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw) | |||
| 86 | #define _raw_read_relax(lock) cpu_relax() | 90 | #define _raw_read_relax(lock) cpu_relax() |
| 87 | #define _raw_write_relax(lock) cpu_relax() | 91 | #define _raw_write_relax(lock) cpu_relax() |
| 88 | 92 | ||
| 93 | #endif | ||
| 94 | |||
| 89 | #endif /* !__BFIN_SPINLOCK_H */ | 95 | #endif /* !__BFIN_SPINLOCK_H */ |
diff --git a/arch/blackfin/include/asm/statfs.h b/arch/blackfin/include/asm/statfs.h index 350672091ba3..0b91fe198c20 100644 --- a/arch/blackfin/include/asm/statfs.h +++ b/arch/blackfin/include/asm/statfs.h | |||
| @@ -1,6 +1 @@ | |||
| 1 | #ifndef _BFIN_STATFS_H | ||
| 2 | #define _BFIN_STATFS_H | ||
| 3 | |||
| 4 | #include <asm-generic/statfs.h> | #include <asm-generic/statfs.h> | |
| 5 | |||
| 6 | #endif /* _BFIN_STATFS_H */ | ||
diff --git a/arch/blackfin/include/asm/swab.h b/arch/blackfin/include/asm/swab.h index 6403ad2932eb..d442113de515 100644 --- a/arch/blackfin/include/asm/swab.h +++ b/arch/blackfin/include/asm/swab.h | |||
| @@ -2,11 +2,7 @@ | |||
| 2 | #define _BLACKFIN_SWAB_H | 2 | #define _BLACKFIN_SWAB_H |
| 3 | 3 | ||
| 4 | #include <linux/types.h> | 4 | #include <linux/types.h> |
| 5 | #include <linux/compiler.h> | 5 | #include <asm-generic/swab.h> |
| 6 | |||
| 7 | #if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) | ||
| 8 | # define __SWAB_64_THRU_32__ | ||
| 9 | #endif | ||
| 10 | 6 | ||
| 11 | #ifdef __GNUC__ | 7 | #ifdef __GNUC__ |
| 12 | 8 | ||
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h index a4c8254bec55..294dbda24164 100644 --- a/arch/blackfin/include/asm/system.h +++ b/arch/blackfin/include/asm/system.h | |||
| @@ -35,10 +35,10 @@ | |||
| 35 | #define _BLACKFIN_SYSTEM_H | 35 | #define _BLACKFIN_SYSTEM_H |
| 36 | 36 | ||
| 37 | #include <linux/linkage.h> | 37 | #include <linux/linkage.h> |
| 38 | #include <linux/compiler.h> | 38 | #include <linux/irqflags.h> |
| 39 | #include <mach/anomaly.h> | 39 | #include <mach/anomaly.h> |
| 40 | #include <asm/cache.h> | ||
| 40 | #include <asm/pda.h> | 41 | #include <asm/pda.h> |
| 41 | #include <asm/processor.h> | ||
| 42 | #include <asm/irq.h> | 42 | #include <asm/irq.h> |
| 43 | 43 | ||
| 44 | /* | 44 | /* |
diff --git a/arch/blackfin/include/asm/termbits.h b/arch/blackfin/include/asm/termbits.h index f37feb7cf895..3935b106de79 100644 --- a/arch/blackfin/include/asm/termbits.h +++ b/arch/blackfin/include/asm/termbits.h | |||
| @@ -1,198 +1 @@ | |||
| 1 | #ifndef __ARCH_BFIN_TERMBITS_H__ | #include <asm-generic/termbits.h> | |
| 2 | #define __ARCH_BFIN_TERMBITS_H__ | ||
| 3 | |||
| 4 | #include <linux/posix_types.h> | ||
| 5 | |||
| 6 | typedef unsigned char cc_t; | ||
| 7 | typedef unsigned int speed_t; | ||
| 8 | typedef unsigned int tcflag_t; | ||
| 9 | |||
| 10 | #define NCCS 19 | ||
| 11 | struct termios { | ||
| 12 | tcflag_t c_iflag; /* input mode flags */ | ||
| 13 | tcflag_t c_oflag; /* output mode flags */ | ||
| 14 | tcflag_t c_cflag; /* control mode flags */ | ||
| 15 | tcflag_t c_lflag; /* local mode flags */ | ||
| 16 | cc_t c_line; /* line discipline */ | ||
| 17 | cc_t c_cc[NCCS]; /* control characters */ | ||
| 18 | }; | ||
| 19 | |||
| 20 | struct termios2 { | ||
| 21 | tcflag_t c_iflag; /* input mode flags */ | ||
| 22 | tcflag_t c_oflag; /* output mode flags */ | ||
| 23 | tcflag_t c_cflag; /* control mode flags */ | ||
| 24 | tcflag_t c_lflag; /* local mode flags */ | ||
| 25 | cc_t c_line; /* line discipline */ | ||
| 26 | cc_t c_cc[NCCS]; /* control characters */ | ||
| 27 | speed_t c_ispeed; /* input speed */ | ||
| 28 | speed_t c_ospeed; /* output speed */ | ||
| 29 | }; | ||
| 30 | |||
| 31 | struct ktermios { | ||
| 32 | tcflag_t c_iflag; /* input mode flags */ | ||
| 33 | tcflag_t c_oflag; /* output mode flags */ | ||
| 34 | tcflag_t c_cflag; /* control mode flags */ | ||
| 35 | tcflag_t c_lflag; /* local mode flags */ | ||
| 36 | cc_t c_line; /* line discipline */ | ||
| 37 | cc_t c_cc[NCCS]; /* control characters */ | ||
| 38 | speed_t c_ispeed; /* input speed */ | ||
| 39 | speed_t c_ospeed; /* output speed */ | ||
| 40 | }; | ||
| 41 | |||
| 42 | /* c_cc characters */ | ||
| 43 | #define VINTR 0 | ||
| 44 | #define VQUIT 1 | ||
| 45 | #define VERASE 2 | ||
| 46 | #define VKILL 3 | ||
| 47 | #define VEOF 4 | ||
| 48 | #define VTIME 5 | ||
| 49 | #define VMIN 6 | ||
| 50 | #define VSWTC 7 | ||
| 51 | #define VSTART 8 | ||
| 52 | #define VSTOP 9 | ||
| 53 | #define VSUSP 10 | ||
| 54 | #define VEOL 11 | ||
| 55 | #define VREPRINT 12 | ||
| 56 | #define VDISCARD 13 | ||
| 57 | #define VWERASE 14 | ||
| 58 | #define VLNEXT 15 | ||
| 59 | #define VEOL2 16 | ||
| 60 | |||
| 61 | /* c_iflag bits */ | ||
| 62 | #define IGNBRK 0000001 | ||
| 63 | #define BRKINT 0000002 | ||
| 64 | #define IGNPAR 0000004 | ||
| 65 | #define PARMRK 0000010 | ||
| 66 | #define INPCK 0000020 | ||
| 67 | #define ISTRIP 0000040 | ||
| 68 | #define INLCR 0000100 | ||
| 69 | #define IGNCR 0000200 | ||
| 70 | #define ICRNL 0000400 | ||
| 71 | #define IUCLC 0001000 | ||
| 72 | #define IXON 0002000 | ||
| 73 | #define IXANY 0004000 | ||
| 74 | #define IXOFF 0010000 | ||
| 75 | #define IMAXBEL 0020000 | ||
| 76 | #define IUTF8 0040000 | ||
| 77 | |||
| 78 | /* c_oflag bits */ | ||
| 79 | #define OPOST 0000001 | ||
| 80 | #define OLCUC 0000002 | ||
| 81 | #define ONLCR 0000004 | ||
| 82 | #define OCRNL 0000010 | ||
| 83 | #define ONOCR 0000020 | ||
| 84 | #define ONLRET 0000040 | ||
| 85 | #define OFILL 0000100 | ||
| 86 | #define OFDEL 0000200 | ||
| 87 | #define NLDLY 0000400 | ||
| 88 | #define NL0 0000000 | ||
| 89 | #define NL1 0000400 | ||
| 90 | #define CRDLY 0003000 | ||
| 91 | #define CR0 0000000 | ||
| 92 | #define CR1 0001000 | ||
| 93 | #define CR2 0002000 | ||
| 94 | #define CR3 0003000 | ||
| 95 | #define TABDLY 0014000 | ||
| 96 | #define TAB0 0000000 | ||
| 97 | #define TAB1 0004000 | ||
| 98 | #define TAB2 0010000 | ||
| 99 | #define TAB3 0014000 | ||
| 100 | #define XTABS 0014000 | ||
| 101 | #define BSDLY 0020000 | ||
| 102 | #define BS0 0000000 | ||
| 103 | #define BS1 0020000 | ||
| 104 | #define VTDLY 0040000 | ||
| 105 | #define VT0 0000000 | ||
| 106 | #define VT1 0040000 | ||
| 107 | #define FFDLY 0100000 | ||
| 108 | #define FF0 0000000 | ||
| 109 | #define FF1 0100000 | ||
| 110 | |||
| 111 | /* c_cflag bit meaning */ | ||
| 112 | #define CBAUD 0010017 | ||
| 113 | #define B0 0000000 /* hang up */ | ||
| 114 | #define B50 0000001 | ||
| 115 | #define B75 0000002 | ||
| 116 | #define B110 0000003 | ||
| 117 | #define B134 0000004 | ||
| 118 | #define B150 0000005 | ||
| 119 | #define B200 0000006 | ||
| 120 | #define B300 0000007 | ||
| 121 | #define B600 0000010 | ||
| 122 | #define B1200 0000011 | ||
| 123 | #define B1800 0000012 | ||
| 124 | #define B2400 0000013 | ||
| 125 | #define B4800 0000014 | ||
| 126 | #define B9600 0000015 | ||
| 127 | #define B19200 0000016 | ||
| 128 | #define B38400 0000017 | ||
| 129 | #define EXTA B19200 | ||
| 130 | #define EXTB B38400 | ||
| 131 | #define CSIZE 0000060 | ||
| 132 | #define CS5 0000000 | ||
| 133 | #define CS6 0000020 | ||
| 134 | #define CS7 0000040 | ||
| 135 | #define CS8 0000060 | ||
| 136 | #define CSTOPB 0000100 | ||
| 137 | #define CREAD 0000200 | ||
| 138 | #define PARENB 0000400 | ||
| 139 | #define PARODD 0001000 | ||
| 140 | #define HUPCL 0002000 | ||
| 141 | #define CLOCAL 0004000 | ||
| 142 | #define CBAUDEX 0010000 | ||
| 143 | #define BOTHER 0010000 | ||
| 144 | #define B57600 0010001 | ||
| 145 | #define B115200 0010002 | ||
| 146 | #define B230400 0010003 | ||
| 147 | #define B460800 0010004 | ||
| 148 | #define B500000 0010005 | ||
| 149 | #define B576000 0010006 | ||
| 150 | #define B921600 0010007 | ||
| 151 | #define B1000000 0010010 | ||
| 152 | #define B1152000 0010011 | ||
| 153 | #define B1500000 0010012 | ||
| 154 | #define B2000000 0010013 | ||
| 155 | #define B2500000 0010014 | ||
| 156 | #define B3000000 0010015 | ||
| 157 | #define B3500000 0010016 | ||
| 158 | #define B4000000 0010017 | ||
| 159 | #define CIBAUD 002003600000 /* input baud rate */ | ||
| 160 | #define CMSPAR 010000000000 /* mark or space (stick) parity */ | ||
| 161 | #define CRTSCTS 020000000000 /* flow control */ | ||
| 162 | |||
| 163 | #define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ | ||
| 164 | |||
| 165 | /* c_lflag bits */ | ||
| 166 | #define ISIG 0000001 | ||
| 167 | #define ICANON 0000002 | ||
| 168 | #define XCASE 0000004 | ||
| 169 | #define ECHO 0000010 | ||
| 170 | #define ECHOE 0000020 | ||
| 171 | #define ECHOK 0000040 | ||
| 172 | #define ECHONL 0000100 | ||
| 173 | #define NOFLSH 0000200 | ||
| 174 | #define TOSTOP 0000400 | ||
| 175 | #define ECHOCTL 0001000 | ||
| 176 | #define ECHOPRT 0002000 | ||
| 177 | #define ECHOKE 0004000 | ||
| 178 | #define FLUSHO 0010000 | ||
| 179 | #define PENDIN 0040000 | ||
| 180 | #define IEXTEN 0100000 | ||
| 181 | |||
| 182 | /* tcflow() and TCXONC use these */ | ||
| 183 | #define TCOOFF 0 | ||
| 184 | #define TCOON 1 | ||
| 185 | #define TCIOFF 2 | ||
| 186 | #define TCION 3 | ||
| 187 | |||
| 188 | /* tcflush() and TCFLSH use these */ | ||
| 189 | #define TCIFLUSH 0 | ||
| 190 | #define TCOFLUSH 1 | ||
| 191 | #define TCIOFLUSH 2 | ||
| 192 | |||
| 193 | /* tcsetattr uses these */ | ||
| 194 | #define TCSANOW 0 | ||
| 195 | #define TCSADRAIN 1 | ||
| 196 | #define TCSAFLUSH 2 | ||
| 197 | |||
| 198 | #endif /* __ARCH_BFIN_TERMBITS_H__ */ | ||
diff --git a/arch/blackfin/include/asm/termios.h b/arch/blackfin/include/asm/termios.h index d50d063c605a..280d78a9d966 100644 --- a/arch/blackfin/include/asm/termios.h +++ b/arch/blackfin/include/asm/termios.h | |||
| @@ -1,94 +1 @@ | |||
| 1 | #ifndef __BFIN_TERMIOS_H__ | #include <asm-generic/termios.h> | |
| 2 | #define __BFIN_TERMIOS_H__ | ||
| 3 | |||
| 4 | #include <asm/termbits.h> | ||
| 5 | #include <asm/ioctls.h> | ||
| 6 | |||
| 7 | struct winsize { | ||
| 8 | unsigned short ws_row; | ||
| 9 | unsigned short ws_col; | ||
| 10 | unsigned short ws_xpixel; | ||
| 11 | unsigned short ws_ypixel; | ||
| 12 | }; | ||
| 13 | |||
| 14 | #define NCC 8 | ||
| 15 | struct termio { | ||
| 16 | unsigned short c_iflag; /* input mode flags */ | ||
| 17 | unsigned short c_oflag; /* output mode flags */ | ||
| 18 | unsigned short c_cflag; /* control mode flags */ | ||
| 19 | unsigned short c_lflag; /* local mode flags */ | ||
| 20 | unsigned char c_line; /* line discipline */ | ||
| 21 | unsigned char c_cc[NCC]; /* control characters */ | ||
| 22 | }; | ||
| 23 | |||
| 24 | /* modem lines */ | ||
| 25 | #define TIOCM_LE 0x001 | ||
| 26 | #define TIOCM_DTR 0x002 | ||
| 27 | #define TIOCM_RTS 0x004 | ||
| 28 | #define TIOCM_ST 0x008 | ||
| 29 | #define TIOCM_SR 0x010 | ||
| 30 | #define TIOCM_CTS 0x020 | ||
| 31 | #define TIOCM_CAR 0x040 | ||
| 32 | #define TIOCM_RNG 0x080 | ||
| 33 | #define TIOCM_DSR 0x100 | ||
| 34 | #define TIOCM_CD TIOCM_CAR | ||
| 35 | #define TIOCM_RI TIOCM_RNG | ||
| 36 | #define TIOCM_OUT1 0x2000 | ||
| 37 | #define TIOCM_OUT2 0x4000 | ||
| 38 | #define TIOCM_LOOP 0x8000 | ||
| 39 | |||
| 40 | /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ | ||
| 41 | |||
| 42 | #ifdef __KERNEL__ | ||
| 43 | |||
| 44 | /* intr=^C quit=^\ erase=del kill=^U | ||
| 45 | eof=^D vtime=\0 vmin=\1 sxtc=\0 | ||
| 46 | start=^Q stop=^S susp=^Z eol=\0 | ||
| 47 | reprint=^R discard=^U werase=^W lnext=^V | ||
| 48 | eol2=\0 | ||
| 49 | */ | ||
| 50 | #define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" | ||
| 51 | |||
| 52 | /* | ||
| 53 | * Translate a "termio" structure into a "termios". Ugh. | ||
| 54 | */ | ||
| 55 | #define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ | ||
| 56 | unsigned short __tmp; \ | ||
| 57 | get_user(__tmp,&(termio)->x); \ | ||
| 58 | *(unsigned short *) &(termios)->x = __tmp; \ | ||
| 59 | } | ||
| 60 | |||
| 61 | #define user_termio_to_kernel_termios(termios, termio) \ | ||
| 62 | ({ \ | ||
| 63 | SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ | ||
| 64 | SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ | ||
| 65 | SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ | ||
| 66 | SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ | ||
| 67 | copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ | ||
| 68 | }) | ||
| 69 | |||
| 70 | /* | ||
| 71 | * Translate a "termios" structure into a "termio". Ugh. | ||
| 72 | */ | ||
| 73 | #define kernel_termios_to_user_termio(termio, termios) \ | ||
| 74 | ({ \ | ||
| 75 | put_user((termios)->c_iflag, &(termio)->c_iflag); \ | ||
| 76 | put_user((termios)->c_oflag, &(termio)->c_oflag); \ | ||
| 77 | put_user((termios)->c_cflag, &(termio)->c_cflag); \ | ||
| 78 | put_user((termios)->c_lflag, &(termio)->c_lflag); \ | ||
| 79 | put_user((termios)->c_line, &(termio)->c_line); \ | ||
| 80 | copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ | ||
| 81 | }) | ||
| 82 | |||
| 83 | #define user_termios_to_kernel_termios(k, u) \ | ||
| 84 | copy_from_user(k, u, sizeof(struct termios2)) | ||
| 85 | #define kernel_termios_to_user_termios(u, k) \ | ||
| 86 | copy_to_user(u, k, sizeof(struct termios2)) | ||
| 87 | #define user_termios_to_kernel_termios_1(k, u) \ | ||
| 88 | copy_from_user(k, u, sizeof(struct termios)) | ||
| 89 | #define kernel_termios_to_user_termios_1(u, k) \ | ||
| 90 | copy_to_user(u, k, sizeof(struct termios)) | ||
| 91 | |||
| 92 | #endif /* __KERNEL__ */ | ||
| 93 | |||
| 94 | #endif /* __BFIN_TERMIOS_H__ */ | ||
diff --git a/arch/blackfin/include/asm/time.h b/arch/blackfin/include/asm/time.h index ddc43ce38533..589e937ed1eb 100644 --- a/arch/blackfin/include/asm/time.h +++ b/arch/blackfin/include/asm/time.h | |||
| @@ -37,4 +37,5 @@ extern unsigned long long __bfin_cycles_off; | |||
| 37 | extern unsigned int __bfin_cycles_mod; | 37 | extern unsigned int __bfin_cycles_mod; |
| 38 | #endif | 38 | #endif |
| 39 | 39 | ||
| 40 | extern void __init setup_core_timer(void); | ||
| 40 | #endif | 41 | #endif |
diff --git a/arch/blackfin/include/asm/tlbflush.h b/arch/blackfin/include/asm/tlbflush.h index 277b400924b8..f1a06c006ed0 100644 --- a/arch/blackfin/include/asm/tlbflush.h +++ b/arch/blackfin/include/asm/tlbflush.h | |||
| @@ -1,56 +1 @@ | |||
| 1 | #ifndef _BLACKFIN_TLBFLUSH_H | #include <asm-generic/tlbflush.h> | |
| 2 | #define _BLACKFIN_TLBFLUSH_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Copyright (C) 2000 Lineo, David McCullough <davidm@uclinux.org> | ||
| 6 | * Copyright (C) 2000-2002, Greg Ungerer <gerg@snapgear.com> | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <asm/setup.h> | ||
| 10 | |||
| 11 | /* | ||
| 12 | * flush all user-space atc entries. | ||
| 13 | */ | ||
| 14 | static inline void __flush_tlb(void) | ||
| 15 | { | ||
| 16 | BUG(); | ||
| 17 | } | ||
| 18 | |||
| 19 | static inline void __flush_tlb_one(unsigned long addr) | ||
| 20 | { | ||
| 21 | BUG(); | ||
| 22 | } | ||
| 23 | |||
| 24 | #define flush_tlb() __flush_tlb() | ||
| 25 | |||
| 26 | /* | ||
| 27 | * flush all atc entries (both kernel and user-space entries). | ||
| 28 | */ | ||
| 29 | static inline void flush_tlb_all(void) | ||
| 30 | { | ||
| 31 | BUG(); | ||
| 32 | } | ||
| 33 | |||
| 34 | static inline void flush_tlb_mm(struct mm_struct *mm) | ||
| 35 | { | ||
| 36 | BUG(); | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline void flush_tlb_page(struct vm_area_struct *vma, | ||
| 40 | unsigned long addr) | ||
| 41 | { | ||
| 42 | BUG(); | ||
| 43 | } | ||
| 44 | |||
| 45 | static inline void flush_tlb_range(struct mm_struct *mm, | ||
| 46 | unsigned long start, unsigned long end) | ||
| 47 | { | ||
| 48 | BUG(); | ||
| 49 | } | ||
| 50 | |||
| 51 | static inline void flush_tlb_kernel_page(unsigned long addr) | ||
| 52 | { | ||
| 53 | BUG(); | ||
| 54 | } | ||
| 55 | |||
| 56 | #endif | ||
diff --git a/arch/blackfin/include/asm/topology.h b/arch/blackfin/include/asm/topology.h index acee23987897..5428f333a02c 100644 --- a/arch/blackfin/include/asm/topology.h +++ b/arch/blackfin/include/asm/topology.h | |||
| @@ -1,6 +1 @@ | |||
| 1 | #ifndef _ASM_BLACKFIN_TOPOLOGY_H | ||
| 2 | #define _ASM_BLACKFIN_TOPOLOGY_H | ||
| 3 | |||
| 4 | #include <asm-generic/topology.h> | #include <asm-generic/topology.h> | |
| 5 | |||
| 6 | #endif /* _ASM_BLACKFIN_TOPOLOGY_H */ | ||
diff --git a/arch/blackfin/include/asm/types.h b/arch/blackfin/include/asm/types.h index 8441cbc2bf9e..b9e79bc580dd 100644 --- a/arch/blackfin/include/asm/types.h +++ b/arch/blackfin/include/asm/types.h | |||
| @@ -1,36 +1 @@ | |||
| 1 | #ifndef _BFIN_TYPES_H | #include <asm-generic/types.h> | |
| 2 | #define _BFIN_TYPES_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is never included by application software unless | ||
| 6 | * explicitly requested (e.g., via linux/types.h) in which case the | ||
| 7 | * application is Linux specific so (user-) name space pollution is | ||
| 8 | * not a major issue. However, for interoperability, libraries still | ||
| 9 | * need to be careful to avoid a name clashes. | ||
| 10 | */ | ||
| 11 | #include <asm-generic/int-ll64.h> | ||
| 12 | |||
| 13 | #ifndef __ASSEMBLY__ | ||
| 14 | |||
| 15 | typedef unsigned short umode_t; | ||
| 16 | |||
| 17 | #endif /* __ASSEMBLY__ */ | ||
| 18 | /* | ||
| 19 | * These aren't exported outside the kernel to avoid name space clashes | ||
| 20 | */ | ||
| 21 | #ifdef __KERNEL__ | ||
| 22 | |||
| 23 | #define BITS_PER_LONG 32 | ||
| 24 | |||
| 25 | #ifndef __ASSEMBLY__ | ||
| 26 | |||
| 27 | /* Dma addresses are 32-bits wide. */ | ||
| 28 | |||
| 29 | typedef u32 dma_addr_t; | ||
| 30 | typedef u64 dma64_addr_t; | ||
| 31 | |||
| 32 | #endif /* __ASSEMBLY__ */ | ||
| 33 | |||
| 34 | #endif /* __KERNEL__ */ | ||
| 35 | |||
| 36 | #endif /* _BFIN_TYPES_H */ | ||
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h index 3248033531e6..8894e9ffbb57 100644 --- a/arch/blackfin/include/asm/uaccess.h +++ b/arch/blackfin/include/asm/uaccess.h | |||
| @@ -59,12 +59,8 @@ static inline int is_in_rom(unsigned long addr) | |||
| 59 | #ifndef CONFIG_ACCESS_CHECK | 59 | #ifndef CONFIG_ACCESS_CHECK |
| 60 | static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; } | 60 | static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; } |
| 61 | #else | 61 | #else |
| 62 | #ifdef CONFIG_ACCESS_OK_L1 | ||
| 63 | extern int _access_ok(unsigned long addr, unsigned long size)__attribute__((l1_text)); | ||
| 64 | #else | ||
| 65 | extern int _access_ok(unsigned long addr, unsigned long size); | 62 | extern int _access_ok(unsigned long addr, unsigned long size); |
| 66 | #endif | 63 | #endif |
| 67 | #endif | ||
| 68 | 64 | ||
| 69 | /* | 65 | /* |
| 70 | * The exception table consists of pairs of addresses: the first is the | 66 | * The exception table consists of pairs of addresses: the first is the |
| @@ -83,9 +79,6 @@ struct exception_table_entry { | |||
| 83 | unsigned long insn, fixup; | 79 | unsigned long insn, fixup; |
| 84 | }; | 80 | }; |
| 85 | 81 | ||
| 86 | /* Returns 0 if exception not found and fixup otherwise. */ | ||
| 87 | extern unsigned long search_exception_table(unsigned long); | ||
| 88 | |||
| 89 | /* | 82 | /* |
| 90 | * These are the main single-value transfer routines. They automatically | 83 | * These are the main single-value transfer routines. They automatically |
| 91 | * use the right size if we just have the right pointer type. | 84 | * use the right size if we just have the right pointer type. |
| @@ -233,16 +226,29 @@ strncpy_from_user(char *dst, const char *src, long count) | |||
| 233 | } | 226 | } |
| 234 | 227 | ||
| 235 | /* | 228 | /* |
| 236 | * Return the size of a string (including the ending 0) | 229 | * Get the size of a string in user space. |
| 230 | * src: The string to measure | ||
| 231 | * n: The maximum valid length | ||
| 237 | * | 232 | * |
| 238 | * Return 0 on exception, a value greater than N if too long | 233 | * Get the size of a NUL-terminated string in user space. |
| 234 | * | ||
| 235 | * Returns the size of the string INCLUDING the terminating NUL. | ||
| 236 | * On exception, returns 0. | ||
| 237 | * If the string is too long, returns a value greater than n. | ||
| 239 | */ | 238 | */ |
| 240 | static inline long strnlen_user(const char *src, long n) | 239 | static inline long __must_check strnlen_user(const char *src, long n) |
| 241 | { | 240 | { |
| 242 | return (strlen(src) + 1); | 241 | if (!access_ok(VERIFY_READ, src, 1)) |
| 242 | return 0; | ||
| 243 | return strnlen(src, n) + 1; | ||
| 243 | } | 244 | } |
| 244 | 245 | ||
| 245 | #define strlen_user(str) strnlen_user(str, 32767) | 246 | static inline long __must_check strlen_user(const char *src) |
| 247 | { | ||
| 248 | if (!access_ok(VERIFY_READ, src, 1)) | ||
| 249 | return 0; | ||
| 250 | return strlen(src) + 1; | ||
| 251 | } | ||
| 246 | 252 | ||
| 247 | /* | 253 | /* |
| 248 | * Zero Userspace | 254 | * Zero Userspace |
| @@ -251,6 +257,8 @@ static inline long strnlen_user(const char *src, long n) | |||
| 251 | static inline unsigned long __must_check | 257 | static inline unsigned long __must_check |
| 252 | __clear_user(void *to, unsigned long n) | 258 | __clear_user(void *to, unsigned long n) |
| 253 | { | 259 | { |
| 260 | if (!access_ok(VERIFY_WRITE, to, n)) | ||
| 261 | return n; | ||
| 254 | memset(to, 0, n); | 262 | memset(to, 0, n); |
| 255 | return 0; | 263 | return 0; |
| 256 | } | 264 | } |
diff --git a/arch/blackfin/include/asm/ucontext.h b/arch/blackfin/include/asm/ucontext.h index 4a4e3856beba..9bc07b9f30fb 100644 --- a/arch/blackfin/include/asm/ucontext.h +++ b/arch/blackfin/include/asm/ucontext.h | |||
| @@ -1,17 +1 @@ | |||
| 1 | /** Changes made by Tony Kou Lineo Inc. May 2001 | #include <asm-generic/ucontext.h> | |
| 2 | * | ||
| 3 | * Based on: include/m68knommu/ucontext.h | ||
| 4 | */ | ||
| 5 | |||
| 6 | #ifndef _BLACKFIN_UCONTEXT_H | ||
| 7 | #define _BLACKFIN_UCONTEXT_H | ||
| 8 | |||
| 9 | struct ucontext { | ||
| 10 | unsigned long uc_flags; /* the others are necessary */ | ||
| 11 | struct ucontext *uc_link; | ||
| 12 | stack_t uc_stack; | ||
| 13 | struct sigcontext uc_mcontext; | ||
| 14 | sigset_t uc_sigmask; /* mask last for extensibility */ | ||
| 15 | }; | ||
| 16 | |||
| 17 | #endif /* _BLACKFIN_UCONTEXT_H */ | ||
diff --git a/arch/blackfin/include/asm/unaligned.h b/arch/blackfin/include/asm/unaligned.h index fd8a1d634945..6cecbbb2111f 100644 --- a/arch/blackfin/include/asm/unaligned.h +++ b/arch/blackfin/include/asm/unaligned.h | |||
| @@ -1,11 +1 @@ | |||
| 1 | #ifndef _ASM_BLACKFIN_UNALIGNED_H | #include <asm-generic/unaligned.h> | |
| 2 | #define _ASM_BLACKFIN_UNALIGNED_H | ||
| 3 | |||
| 4 | #include <linux/unaligned/le_struct.h> | ||
| 5 | #include <linux/unaligned/be_byteshift.h> | ||
| 6 | #include <linux/unaligned/generic.h> | ||
| 7 | |||
| 8 | #define get_unaligned __get_unaligned_le | ||
| 9 | #define put_unaligned __put_unaligned_le | ||
| 10 | |||
| 11 | #endif /* _ASM_BLACKFIN_UNALIGNED_H */ | ||
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h index 1e57b636e0bc..da35133c171d 100644 --- a/arch/blackfin/include/asm/unistd.h +++ b/arch/blackfin/include/asm/unistd.h | |||
| @@ -378,8 +378,11 @@ | |||
| 378 | #define __NR_dup3 363 | 378 | #define __NR_dup3 363 |
| 379 | #define __NR_pipe2 364 | 379 | #define __NR_pipe2 364 |
| 380 | #define __NR_inotify_init1 365 | 380 | #define __NR_inotify_init1 365 |
| 381 | #define __NR_preadv 366 | ||
| 382 | #define __NR_pwritev 367 | ||
| 383 | #define __NR_rt_tgsigqueueinfo 368 | ||
| 381 | 384 | ||
| 382 | #define __NR_syscall 366 | 385 | #define __NR_syscall 369 |
| 383 | #define NR_syscalls __NR_syscall | 386 | #define NR_syscalls __NR_syscall |
| 384 | 387 | ||
| 385 | /* Old optional stuff no one actually uses */ | 388 | /* Old optional stuff no one actually uses */ |
diff --git a/arch/blackfin/include/asm/user.h b/arch/blackfin/include/asm/user.h index afe6a0e1f7ce..4792a60831e4 100644 --- a/arch/blackfin/include/asm/user.h +++ b/arch/blackfin/include/asm/user.h | |||
| @@ -1,89 +1 @@ | |||
| 1 | #ifndef _BFIN_USER_H | #include <asm-generic/user.h> | |
| 2 | #define _BFIN_USER_H | ||
| 3 | |||
| 4 | /* Changes by Tony Kou Lineo, Inc. July, 2001 | ||
| 5 | * | ||
| 6 | * Based include/asm-m68knommu/user.h | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | /* Core file format: The core file is written in such a way that gdb | ||
| 11 | can understand it and provide useful information to the user (under | ||
| 12 | linux we use the 'trad-core' bfd). There are quite a number of | ||
| 13 | obstacles to being able to view the contents of the floating point | ||
| 14 | registers, and until these are solved you will not be able to view the | ||
| 15 | contents of them. Actually, you can read in the core file and look at | ||
| 16 | the contents of the user struct to find out what the floating point | ||
| 17 | registers contain. | ||
| 18 | The actual file contents are as follows: | ||
| 19 | UPAGE: 1 page consisting of a user struct that tells gdb what is present | ||
| 20 | in the file. Directly after this is a copy of the task_struct, which | ||
| 21 | is currently not used by gdb, but it may come in useful at some point. | ||
| 22 | All of the registers are stored as part of the upage. The upage should | ||
| 23 | always be only one page. | ||
| 24 | DATA: The data area is stored. We use current->end_text to | ||
| 25 | current->brk to pick up all of the user variables, plus any memory | ||
| 26 | that may have been malloced. No attempt is made to determine if a page | ||
| 27 | is demand-zero or if a page is totally unused, we just cover the entire | ||
| 28 | range. All of the addresses are rounded in such a way that an integral | ||
| 29 | number of pages is written. | ||
| 30 | STACK: We need the stack information in order to get a meaningful | ||
| 31 | backtrace. We need to write the data from (esp) to | ||
| 32 | current->start_stack, so we round each of these off in order to be able | ||
| 33 | to write an integer number of pages. | ||
| 34 | The minimum core file size is 3 pages, or 12288 bytes. | ||
| 35 | */ | ||
| 36 | struct user_bfinfp_struct { | ||
| 37 | }; | ||
| 38 | |||
| 39 | /* This is the old layout of "struct pt_regs" as of Linux 1.x, and | ||
| 40 | is still the layout used by user (the new pt_regs doesn't have | ||
| 41 | all registers). */ | ||
| 42 | struct user_regs_struct { | ||
| 43 | long r0, r1, r2, r3, r4, r5, r6, r7; | ||
| 44 | long p0, p1, p2, p3, p4, p5, usp, fp; | ||
| 45 | long i0, i1, i2, i3; | ||
| 46 | long l0, l1, l2, l3; | ||
| 47 | long b0, b1, b2, b3; | ||
| 48 | long m0, m1, m2, m3; | ||
| 49 | long a0w, a1w; | ||
| 50 | long a0x, a1x; | ||
| 51 | unsigned long rets; | ||
| 52 | unsigned long astat; | ||
| 53 | unsigned long pc; | ||
| 54 | unsigned long orig_p0; | ||
| 55 | }; | ||
| 56 | |||
| 57 | /* When the kernel dumps core, it starts by dumping the user struct - | ||
| 58 | this will be used by gdb to figure out where the data and stack segments | ||
| 59 | are within the file, and what virtual addresses to use. */ | ||
| 60 | |||
| 61 | struct user { | ||
| 62 | /* We start with the registers, to mimic the way that "memory" is returned | ||
| 63 | from the ptrace(3,...) function. */ | ||
| 64 | |||
| 65 | struct user_regs_struct regs; /* Where the registers are actually stored */ | ||
| 66 | |||
| 67 | /* The rest of this junk is to help gdb figure out what goes where */ | ||
| 68 | unsigned long int u_tsize; /* Text segment size (pages). */ | ||
| 69 | unsigned long int u_dsize; /* Data segment size (pages). */ | ||
| 70 | unsigned long int u_ssize; /* Stack segment size (pages). */ | ||
| 71 | unsigned long start_code; /* Starting virtual address of text. */ | ||
| 72 | unsigned long start_stack; /* Starting virtual address of stack area. | ||
| 73 | This is actually the bottom of the stack, | ||
| 74 | the top of the stack is always found in the | ||
| 75 | esp register. */ | ||
| 76 | long int signal; /* Signal that caused the core dump. */ | ||
| 77 | int reserved; /* No longer used */ | ||
| 78 | unsigned long u_ar0; | ||
| 79 | /* Used by gdb to help find the values for */ | ||
| 80 | /* the registers. */ | ||
| 81 | unsigned long magic; /* To uniquely identify a core file */ | ||
| 82 | char u_comm[32]; /* User command that was responsible */ | ||
| 83 | }; | ||
| 84 | #define NBPG PAGE_SIZE | ||
| 85 | #define UPAGES 1 | ||
| 86 | #define HOST_TEXT_START_ADDR (u.start_code) | ||
| 87 | #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) | ||
| 88 | |||
| 89 | #endif | ||
diff --git a/arch/blackfin/kernel/.gitignore b/arch/blackfin/kernel/.gitignore new file mode 100644 index 000000000000..c5f676c3c224 --- /dev/null +++ b/arch/blackfin/kernel/.gitignore | |||
| @@ -0,0 +1 @@ | |||
| vmlinux.lds | |||
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index fd4d4328a0f2..3731088e181b 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile | |||
| @@ -15,6 +15,10 @@ else | |||
| 15 | obj-y += time.o | 15 | obj-y += time.o |
| 16 | endif | 16 | endif |
| 17 | 17 | ||
| 18 | obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o | ||
| 19 | obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o | ||
| 20 | CFLAGS_REMOVE_ftrace.o = -pg | ||
| 21 | |||
| 18 | obj-$(CONFIG_IPIPE) += ipipe.o | 22 | obj-$(CONFIG_IPIPE) += ipipe.o |
| 19 | obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o | 23 | obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o |
| 20 | obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o | 24 | obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o |
| @@ -23,6 +27,7 @@ obj-$(CONFIG_MODULES) += module.o | |||
| 23 | obj-$(CONFIG_KGDB) += kgdb.o | 27 | obj-$(CONFIG_KGDB) += kgdb.o |
| 24 | obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o | 28 | obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o |
| 25 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o | 29 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o |
| 30 | obj-$(CONFIG_STACKTRACE) += stacktrace.o | ||
| 26 | 31 | ||
| 27 | # the kgdb test puts code into L2 and without linker | 32 | # the kgdb test puts code into L2 and without linker |
| 28 | # relaxation, we need to force long calls to/from it | 33 | # relaxation, we need to force long calls to/from it |
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c index 8531693fb48d..e0bf8cc06907 100644 --- a/arch/blackfin/kernel/bfin_dma_5xx.c +++ b/arch/blackfin/kernel/bfin_dma_5xx.c | |||
| @@ -20,6 +20,11 @@ | |||
| 20 | #include <asm/dma.h> | 20 | #include <asm/dma.h> |
| 21 | #include <asm/uaccess.h> | 21 | #include <asm/uaccess.h> |
| 22 | 22 | ||
| 23 | /* | ||
| 24 | * To make sure we work around 05000119 - we always check DMA_DONE bit, | ||
| 25 | * never the DMA_RUN bit | ||
| 26 | */ | ||
| 27 | |||
| 23 | struct dma_channel dma_ch[MAX_DMA_CHANNELS]; | 28 | struct dma_channel dma_ch[MAX_DMA_CHANNELS]; |
| 24 | EXPORT_SYMBOL(dma_ch); | 29 | EXPORT_SYMBOL(dma_ch); |
| 25 | 30 | ||
| @@ -232,6 +237,87 @@ void blackfin_dma_resume(void) | |||
| 232 | void __init blackfin_dma_early_init(void) | 237 | void __init blackfin_dma_early_init(void) |
| 233 | { | 238 | { |
| 234 | bfin_write_MDMA_S0_CONFIG(0); | 239 | bfin_write_MDMA_S0_CONFIG(0); |
| 240 | bfin_write_MDMA_S1_CONFIG(0); | ||
| 241 | } | ||
| 242 | |||
| 243 | void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size) | ||
| 244 | { | ||
| 245 | unsigned long dst = (unsigned long)pdst; | ||
| 246 | unsigned long src = (unsigned long)psrc; | ||
| 247 | struct dma_register *dst_ch, *src_ch; | ||
| 248 | |||
| 249 | /* We assume that everything is 4 byte aligned, so include | ||
| 250 | * a basic sanity check | ||
| 251 | */ | ||
| 252 | BUG_ON(dst % 4); | ||
| 253 | BUG_ON(src % 4); | ||
| 254 | BUG_ON(size % 4); | ||
| 255 | |||
| 256 | /* Force a sync in case a previous config reset on this channel | ||
| 257 | * occurred. This is needed so subsequent writes to DMA registers | ||
| 258 | * are not spuriously lost/corrupted. | ||
| 259 | */ | ||
| 260 | __builtin_bfin_ssync(); | ||
| 261 | |||
| 262 | src_ch = 0; | ||
| 263 | /* Find an avalible memDMA channel */ | ||
| 264 | while (1) { | ||
| 265 | if (!src_ch || src_ch == (struct dma_register *)MDMA_S1_NEXT_DESC_PTR) { | ||
| 266 | dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR; | ||
| 267 | src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR; | ||
| 268 | } else { | ||
| 269 | dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR; | ||
| 270 | src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR; | ||
| 271 | } | ||
| 272 | |||
| 273 | if (!bfin_read16(&src_ch->cfg)) { | ||
| 274 | break; | ||
| 275 | } else { | ||
| 276 | if (bfin_read16(&src_ch->irq_status) & DMA_DONE) | ||
| 277 | bfin_write16(&src_ch->cfg, 0); | ||
| 278 | } | ||
| 279 | |||
| 280 | } | ||
| 281 | |||
| 282 | /* Destination */ | ||
| 283 | bfin_write32(&dst_ch->start_addr, dst); | ||
| 284 | bfin_write16(&dst_ch->x_count, size >> 2); | ||
| 285 | bfin_write16(&dst_ch->x_modify, 1 << 2); | ||
| 286 | bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR); | ||
| 287 | |||
| 288 | /* Source */ | ||
| 289 | bfin_write32(&src_ch->start_addr, src); | ||
| 290 | bfin_write16(&src_ch->x_count, size >> 2); | ||
| 291 | bfin_write16(&src_ch->x_modify, 1 << 2); | ||
| 292 | bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR); | ||
| 293 | |||
| 294 | /* Enable */ | ||
| 295 | bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32); | ||
| 296 | bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32); | ||
| 297 | |||
| 298 | /* Since we are atomic now, don't use the workaround ssync */ | ||
| 299 | __builtin_bfin_ssync(); | ||
| 300 | } | ||
| 301 | |||
| 302 | void __init early_dma_memcpy_done(void) | ||
| 303 | { | ||
| 304 | while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) || | ||
| 305 | (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE))) | ||
| 306 | continue; | ||
| 307 | |||
| 308 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 309 | bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 310 | /* | ||
| 311 | * Now that DMA is done, we would normally flush cache, but | ||
| 312 | * i/d cache isn't running this early, so we don't bother, | ||
| 313 | * and just clear out the DMA channel for next time | ||
| 314 | */ | ||
| 315 | bfin_write_MDMA_S0_CONFIG(0); | ||
| 316 | bfin_write_MDMA_S1_CONFIG(0); | ||
| 317 | bfin_write_MDMA_D0_CONFIG(0); | ||
| 318 | bfin_write_MDMA_D1_CONFIG(0); | ||
| 319 | |||
| 320 | __builtin_bfin_ssync(); | ||
| 235 | } | 321 | } |
| 236 | 322 | ||
| 237 | /** | 323 | /** |
| @@ -367,10 +453,10 @@ void *dma_memcpy(void *pdst, const void *psrc, size_t size) | |||
| 367 | unsigned long src = (unsigned long)psrc; | 453 | unsigned long src = (unsigned long)psrc; |
| 368 | size_t bulk, rest; | 454 | size_t bulk, rest; |
| 369 | 455 | ||
| 370 | if (bfin_addr_dcachable(src)) | 456 | if (bfin_addr_dcacheable(src)) |
| 371 | blackfin_dcache_flush_range(src, src + size); | 457 | blackfin_dcache_flush_range(src, src + size); |
| 372 | 458 | ||
| 373 | if (bfin_addr_dcachable(dst)) | 459 | if (bfin_addr_dcacheable(dst)) |
| 374 | blackfin_dcache_invalidate_range(dst, dst + size); | 460 | blackfin_dcache_invalidate_range(dst, dst + size); |
| 375 | 461 | ||
| 376 | bulk = size & ~0xffff; | 462 | bulk = size & ~0xffff; |
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index a0678da40532..beffa00a93c3 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c | |||
| @@ -313,15 +313,6 @@ inline void portmux_setup(unsigned short per) | |||
| 313 | # define portmux_setup(...) do { } while (0) | 313 | # define portmux_setup(...) do { } while (0) |
| 314 | #endif | 314 | #endif |
| 315 | 315 | ||
| 316 | static int __init bfin_gpio_init(void) | ||
| 317 | { | ||
| 318 | printk(KERN_INFO "Blackfin GPIO Controller\n"); | ||
| 319 | |||
| 320 | return 0; | ||
| 321 | } | ||
| 322 | arch_initcall(bfin_gpio_init); | ||
| 323 | |||
| 324 | |||
| 325 | #ifndef CONFIG_BF54x | 316 | #ifndef CONFIG_BF54x |
| 326 | /*********************************************************** | 317 | /*********************************************************** |
| 327 | * | 318 | * |
| @@ -1021,15 +1012,6 @@ int bfin_gpio_irq_request(unsigned gpio, const char *label) | |||
| 1021 | 1012 | ||
| 1022 | local_irq_save_hw(flags); | 1013 | local_irq_save_hw(flags); |
| 1023 | 1014 | ||
| 1024 | if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) { | ||
| 1025 | if (system_state == SYSTEM_BOOTING) | ||
| 1026 | dump_stack(); | ||
| 1027 | printk(KERN_ERR | ||
| 1028 | "bfin-gpio: GPIO %d is already reserved as gpio-irq !\n", | ||
| 1029 | gpio); | ||
| 1030 | local_irq_restore_hw(flags); | ||
| 1031 | return -EBUSY; | ||
| 1032 | } | ||
| 1033 | if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { | 1015 | if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { |
| 1034 | if (system_state == SYSTEM_BOOTING) | 1016 | if (system_state == SYSTEM_BOOTING) |
| 1035 | dump_stack(); | 1017 | dump_stack(); |
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c index 01f917d58b59..ed8392c117ea 100644 --- a/arch/blackfin/kernel/bfin_ksyms.c +++ b/arch/blackfin/kernel/bfin_ksyms.c | |||
| @@ -10,13 +10,13 @@ | |||
| 10 | #include <linux/uaccess.h> | 10 | #include <linux/uaccess.h> |
| 11 | 11 | ||
| 12 | #include <asm/cacheflush.h> | 12 | #include <asm/cacheflush.h> |
| 13 | #include <asm/io.h> | ||
| 13 | 14 | ||
| 14 | /* Allow people to have their own Blackfin exception handler in a module */ | 15 | /* Allow people to have their own Blackfin exception handler in a module */ |
| 15 | EXPORT_SYMBOL(bfin_return_from_exception); | 16 | EXPORT_SYMBOL(bfin_return_from_exception); |
| 16 | 17 | ||
| 17 | /* All the Blackfin cache functions: mach-common/cache.S */ | 18 | /* All the Blackfin cache functions: mach-common/cache.S */ |
| 18 | EXPORT_SYMBOL(blackfin_dcache_invalidate_range); | 19 | EXPORT_SYMBOL(blackfin_dcache_invalidate_range); |
| 19 | EXPORT_SYMBOL(blackfin_icache_dcache_flush_range); | ||
| 20 | EXPORT_SYMBOL(blackfin_icache_flush_range); | 20 | EXPORT_SYMBOL(blackfin_icache_flush_range); |
| 21 | EXPORT_SYMBOL(blackfin_dcache_flush_range); | 21 | EXPORT_SYMBOL(blackfin_dcache_flush_range); |
| 22 | EXPORT_SYMBOL(blackfin_dflush_page); | 22 | EXPORT_SYMBOL(blackfin_dflush_page); |
| @@ -104,3 +104,8 @@ EXPORT_SYMBOL(__raw_smp_mark_barrier_asm); | |||
| 104 | EXPORT_SYMBOL(__raw_smp_check_barrier_asm); | 104 | EXPORT_SYMBOL(__raw_smp_check_barrier_asm); |
| 105 | #endif | 105 | #endif |
| 106 | #endif | 106 | #endif |
| 107 | |||
| 108 | #ifdef CONFIG_FUNCTION_TRACER | ||
| 109 | extern void _mcount(void); | ||
| 110 | EXPORT_SYMBOL(_mcount); | ||
| 111 | #endif | ||
diff --git a/arch/blackfin/kernel/cplb-mpu/cacheinit.c b/arch/blackfin/kernel/cplb-mpu/cacheinit.c index c6ff947f9d37..d5a86c3017f7 100644 --- a/arch/blackfin/kernel/cplb-mpu/cacheinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cacheinit.c | |||
| @@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) | |||
| 55 | } | 55 | } |
| 56 | 56 | ||
| 57 | ctrl = bfin_read_DMEM_CONTROL(); | 57 | ctrl = bfin_read_DMEM_CONTROL(); |
| 58 | ctrl |= DMEM_CNTR; | 58 | |
| 59 | /* | ||
| 60 | * Anomaly notes: | ||
| 61 | * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL | ||
| 62 | * register, so that the port preferences for DAG0 and DAG1 are set | ||
| 63 | * to port B | ||
| 64 | */ | ||
| 65 | ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0); | ||
| 59 | bfin_write_DMEM_CONTROL(ctrl); | 66 | bfin_write_DMEM_CONTROL(ctrl); |
| 60 | SSYNC(); | 67 | SSYNC(); |
| 61 | } | 68 | } |
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c index 3e329a6ce041..c006a44527bf 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c | |||
| @@ -64,7 +64,7 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) | |||
| 64 | dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; | 64 | dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; |
| 65 | 65 | ||
| 66 | icplb_tbl[cpu][i_i].addr = 0; | 66 | icplb_tbl[cpu][i_i].addr = 0; |
| 67 | icplb_tbl[cpu][i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_1KB; | 67 | icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB; |
| 68 | 68 | ||
| 69 | /* Cover kernel memory with 4M pages. */ | 69 | /* Cover kernel memory with 4M pages. */ |
| 70 | addr = 0; | 70 | addr = 0; |
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index 87463ce87f5a..784923e52a9a 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c | |||
| @@ -151,7 +151,7 @@ static noinline int dcplb_miss(unsigned int cpu) | |||
| 151 | 151 | ||
| 152 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; | 152 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; |
| 153 | #ifdef CONFIG_BFIN_DCACHE | 153 | #ifdef CONFIG_BFIN_DCACHE |
| 154 | if (bfin_addr_dcachable(addr)) { | 154 | if (bfin_addr_dcacheable(addr)) { |
| 155 | d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; | 155 | d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; |
| 156 | #ifdef CONFIG_BFIN_WT | 156 | #ifdef CONFIG_BFIN_WT |
| 157 | d_data |= CPLB_L1_AOW | CPLB_WT; | 157 | d_data |= CPLB_L1_AOW | CPLB_WT; |
diff --git a/arch/blackfin/kernel/cplb-nompu/cacheinit.c b/arch/blackfin/kernel/cplb-nompu/cacheinit.c index c6ff947f9d37..d5a86c3017f7 100644 --- a/arch/blackfin/kernel/cplb-nompu/cacheinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cacheinit.c | |||
| @@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) | |||
| 55 | } | 55 | } |
| 56 | 56 | ||
| 57 | ctrl = bfin_read_DMEM_CONTROL(); | 57 | ctrl = bfin_read_DMEM_CONTROL(); |
| 58 | ctrl |= DMEM_CNTR; | 58 | |
| 59 | /* | ||
| 60 | * Anomaly notes: | ||
| 61 | * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL | ||
| 62 | * register, so that the port preferences for DAG0 and DAG1 are set | ||
| 63 | * to port B | ||
| 64 | */ | ||
| 65 | ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0); | ||
| 59 | bfin_write_DMEM_CONTROL(ctrl); | 66 | bfin_write_DMEM_CONTROL(ctrl); |
| 60 | SSYNC(); | 67 | SSYNC(); |
| 61 | } | 68 | } |
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c index 8cbb47c7b663..12b030842fdb 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | #include <asm/cplbinit.h> | 28 | #include <asm/cplbinit.h> |
| 29 | #include <asm/cplb.h> | 29 | #include <asm/cplb.h> |
| 30 | #include <asm/mmu_context.h> | 30 | #include <asm/mmu_context.h> |
| 31 | #include <asm/traps.h> | ||
| 31 | 32 | ||
| 32 | /* | 33 | /* |
| 33 | * WARNING | 34 | * WARNING |
| @@ -100,28 +101,6 @@ static inline void write_icplb_data(int cpu, int idx, unsigned long data, | |||
| 100 | #endif | 101 | #endif |
| 101 | } | 102 | } |
| 102 | 103 | ||
| 103 | /* | ||
| 104 | * Given the contents of the status register, return the index of the | ||
| 105 | * CPLB that caused the fault. | ||
| 106 | */ | ||
| 107 | static inline int faulting_cplb_index(int status) | ||
| 108 | { | ||
| 109 | int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF); | ||
| 110 | return 30 - signbits; | ||
| 111 | } | ||
| 112 | |||
| 113 | /* | ||
| 114 | * Given the contents of the status register and the DCPLB_DATA contents, | ||
| 115 | * return true if a write access should be permitted. | ||
| 116 | */ | ||
| 117 | static inline int write_permitted(int status, unsigned long data) | ||
| 118 | { | ||
| 119 | if (status & FAULT_USERSUPV) | ||
| 120 | return !!(data & CPLB_SUPV_WR); | ||
| 121 | else | ||
| 122 | return !!(data & CPLB_USER_WR); | ||
| 123 | } | ||
| 124 | |||
| 125 | /* Counters to implement round-robin replacement. */ | 104 | /* Counters to implement round-robin replacement. */ |
| 126 | static int icplb_rr_index[NR_CPUS] PDT_ATTR; | 105 | static int icplb_rr_index[NR_CPUS] PDT_ATTR; |
| 127 | static int dcplb_rr_index[NR_CPUS] PDT_ATTR; | 106 | static int dcplb_rr_index[NR_CPUS] PDT_ATTR; |
| @@ -245,43 +224,16 @@ MGR_ATTR static int dcplb_miss(int cpu) | |||
| 245 | return CPLB_RELOADED; | 224 | return CPLB_RELOADED; |
| 246 | } | 225 | } |
| 247 | 226 | ||
| 248 | MGR_ATTR static noinline int dcplb_protection_fault(int cpu) | ||
| 249 | { | ||
| 250 | int status = bfin_read_DCPLB_STATUS(); | ||
| 251 | |||
| 252 | nr_dcplb_prot[cpu]++; | ||
| 253 | |||
| 254 | if (likely(status & FAULT_RW)) { | ||
| 255 | int idx = faulting_cplb_index(status); | ||
| 256 | unsigned long regaddr = DCPLB_DATA0 + idx * 4; | ||
| 257 | unsigned long data = bfin_read32(regaddr); | ||
| 258 | |||
| 259 | /* Check if fault is to dirty a clean page */ | ||
| 260 | if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) && | ||
| 261 | write_permitted(status, data)) { | ||
| 262 | |||
| 263 | dcplb_tbl[cpu][idx].data = data; | ||
| 264 | bfin_write32(regaddr, data); | ||
| 265 | return CPLB_RELOADED; | ||
| 266 | } | ||
| 267 | } | ||
| 268 | |||
| 269 | return CPLB_PROT_VIOL; | ||
| 270 | } | ||
| 271 | |||
| 272 | MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs) | 227 | MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs) |
| 273 | { | 228 | { |
| 274 | int cause = seqstat & 0x3f; | 229 | int cause = seqstat & 0x3f; |
| 275 | unsigned int cpu = smp_processor_id(); | 230 | unsigned int cpu = smp_processor_id(); |
| 276 | switch (cause) { | 231 | switch (cause) { |
| 277 | case 0x2C: | 232 | case VEC_CPLB_I_M: |
| 278 | return icplb_miss(cpu); | 233 | return icplb_miss(cpu); |
| 279 | case 0x26: | 234 | case VEC_CPLB_M: |
| 280 | return dcplb_miss(cpu); | 235 | return dcplb_miss(cpu); |
| 281 | default: | 236 | default: |
| 282 | if (unlikely(cause == 0x23)) | ||
| 283 | return dcplb_protection_fault(cpu); | ||
| 284 | |||
| 285 | return CPLB_UNKNOWN_ERR; | 237 | return CPLB_UNKNOWN_ERR; |
| 286 | } | 238 | } |
| 287 | } | 239 | } |
diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c index c8ad051742e2..2ab56811841c 100644 --- a/arch/blackfin/kernel/early_printk.c +++ b/arch/blackfin/kernel/early_printk.c | |||
| @@ -178,25 +178,15 @@ int __init setup_early_printk(char *buf) | |||
| 178 | 178 | ||
| 179 | asmlinkage void __init init_early_exception_vectors(void) | 179 | asmlinkage void __init init_early_exception_vectors(void) |
| 180 | { | 180 | { |
| 181 | u32 evt; | ||
| 181 | SSYNC(); | 182 | SSYNC(); |
| 182 | 183 | ||
| 183 | /* cannot program in software: | 184 | /* cannot program in software: |
| 184 | * evt0 - emulation (jtag) | 185 | * evt0 - emulation (jtag) |
| 185 | * evt1 - reset | 186 | * evt1 - reset |
| 186 | */ | 187 | */ |
| 187 | bfin_write_EVT2(early_trap); | 188 | for (evt = EVT2; evt <= EVT15; evt += 4) |
| 188 | bfin_write_EVT3(early_trap); | 189 | bfin_write32(evt, early_trap); |
| 189 | bfin_write_EVT5(early_trap); | ||
| 190 | bfin_write_EVT6(early_trap); | ||
| 191 | bfin_write_EVT7(early_trap); | ||
| 192 | bfin_write_EVT8(early_trap); | ||
| 193 | bfin_write_EVT9(early_trap); | ||
| 194 | bfin_write_EVT10(early_trap); | ||
| 195 | bfin_write_EVT11(early_trap); | ||
| 196 | bfin_write_EVT12(early_trap); | ||
| 197 | bfin_write_EVT13(early_trap); | ||
| 198 | bfin_write_EVT14(early_trap); | ||
| 199 | bfin_write_EVT15(early_trap); | ||
| 200 | CSYNC(); | 190 | CSYNC(); |
| 201 | 191 | ||
| 202 | /* Set all the return from interrupt, exception, NMI to a known place | 192 | /* Set all the return from interrupt, exception, NMI to a known place |
| @@ -212,11 +202,15 @@ asmlinkage void __init init_early_exception_vectors(void) | |||
| 212 | asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr) | 202 | asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr) |
| 213 | { | 203 | { |
| 214 | /* This can happen before the uart is initialized, so initialize | 204 | /* This can happen before the uart is initialized, so initialize |
| 215 | * the UART now | 205 | * the UART now (but only if we are running on the processor we think |
| 206 | * we are compiled for - otherwise we write to MMRs that don't exist, | ||
| 207 | * and cause other problems. Nothing comes out the UART, but it does | ||
| 208 | * end up in the __buf_log. | ||
| 216 | */ | 209 | */ |
| 217 | if (likely(early_console == NULL)) | 210 | if (likely(early_console == NULL) && CPUID == bfin_cpuid()) |
| 218 | setup_early_printk(DEFAULT_EARLY_PORT); | 211 | setup_early_printk(DEFAULT_EARLY_PORT); |
| 219 | 212 | ||
| 213 | printk(KERN_EMERG "Early panic\n"); | ||
| 220 | dump_bfin_mem(fp); | 214 | dump_bfin_mem(fp); |
| 221 | show_regs(fp); | 215 | show_regs(fp); |
| 222 | dump_bfin_trace_buffer(); | 216 | dump_bfin_trace_buffer(); |
diff --git a/arch/blackfin/kernel/ftrace-entry.S b/arch/blackfin/kernel/ftrace-entry.S new file mode 100644 index 000000000000..6980b7a0615d --- /dev/null +++ b/arch/blackfin/kernel/ftrace-entry.S | |||
| @@ -0,0 +1,140 @@ | |||
| 1 | /* | ||
| 2 | * mcount and friends -- ftrace stuff | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Analog Devices Inc. | ||
| 5 | * Licensed under the GPL-2 or later. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/linkage.h> | ||
| 9 | #include <asm/ftrace.h> | ||
| 10 | |||
| 11 | .text | ||
| 12 | |||
| 13 | /* GCC will have called us before setting up the function prologue, so we | ||
| 14 | * can clobber the normal scratch registers, but we need to make sure to | ||
| 15 | * save/restore the registers used for argument passing (R0-R2) in case | ||
| 16 | * the profiled function is using them. With data registers, R3 is the | ||
| 17 | * only one we can blow away. With pointer registers, we have P0-P2. | ||
| 18 | * | ||
| 19 | * Upon entry, the RETS will point to the top of the current profiled | ||
| 20 | * function. And since GCC setup the frame for us, the previous function | ||
| 21 | * will be waiting there. mmmm pie. | ||
| 22 | */ | ||
| 23 | ENTRY(__mcount) | ||
| 24 | /* save third function arg early so we can do testing below */ | ||
| 25 | [--sp] = r2; | ||
| 26 | |||
| 27 | /* load the function pointer to the tracer */ | ||
| 28 | p0.l = _ftrace_trace_function; | ||
| 29 | p0.h = _ftrace_trace_function; | ||
| 30 | r3 = [p0]; | ||
| 31 | |||
| 32 | /* optional micro optimization: don't call the stub tracer */ | ||
| 33 | r2.l = _ftrace_stub; | ||
| 34 | r2.h = _ftrace_stub; | ||
| 35 | cc = r2 == r3; | ||
| 36 | if ! cc jump .Ldo_trace; | ||
| 37 | |||
| 38 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 39 | /* if the ftrace_graph_return function pointer is not set to | ||
| 40 | * the ftrace_stub entry, call prepare_ftrace_return(). | ||
| 41 | */ | ||
| 42 | p0.l = _ftrace_graph_return; | ||
| 43 | p0.h = _ftrace_graph_return; | ||
| 44 | r3 = [p0]; | ||
| 45 | cc = r2 == r3; | ||
| 46 | if ! cc jump _ftrace_graph_caller; | ||
| 47 | |||
| 48 | /* similarly, if the ftrace_graph_entry function pointer is not | ||
| 49 | * set to the ftrace_graph_entry_stub entry, ... | ||
| 50 | */ | ||
| 51 | p0.l = _ftrace_graph_entry; | ||
| 52 | p0.h = _ftrace_graph_entry; | ||
| 53 | r2.l = _ftrace_graph_entry_stub; | ||
| 54 | r2.h = _ftrace_graph_entry_stub; | ||
| 55 | r3 = [p0]; | ||
| 56 | cc = r2 == r3; | ||
| 57 | if ! cc jump _ftrace_graph_caller; | ||
| 58 | #endif | ||
| 59 | |||
| 60 | r2 = [sp++]; | ||
| 61 | rts; | ||
| 62 | |||
| 63 | .Ldo_trace: | ||
| 64 | |||
| 65 | /* save first/second function arg and the return register */ | ||
| 66 | [--sp] = r0; | ||
| 67 | [--sp] = r1; | ||
| 68 | [--sp] = rets; | ||
| 69 | |||
| 70 | /* setup the tracer function */ | ||
| 71 | p0 = r3; | ||
| 72 | |||
| 73 | /* tracer(ulong frompc, ulong selfpc): | ||
| 74 | * frompc: the pc that did the call to ... | ||
| 75 | * selfpc: ... this location | ||
| 76 | * the selfpc itself will need adjusting for the mcount call | ||
| 77 | */ | ||
| 78 | r1 = rets; | ||
| 79 | r0 = [fp + 4]; | ||
| 80 | r1 += -MCOUNT_INSN_SIZE; | ||
| 81 | |||
| 82 | /* call the tracer */ | ||
| 83 | call (p0); | ||
| 84 | |||
| 85 | /* restore state and get out of dodge */ | ||
| 86 | .Lfinish_trace: | ||
| 87 | rets = [sp++]; | ||
| 88 | r1 = [sp++]; | ||
| 89 | r0 = [sp++]; | ||
| 90 | r2 = [sp++]; | ||
| 91 | |||
| 92 | .globl _ftrace_stub | ||
| 93 | _ftrace_stub: | ||
| 94 | rts; | ||
| 95 | ENDPROC(__mcount) | ||
| 96 | |||
| 97 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 98 | /* The prepare_ftrace_return() function is similar to the trace function | ||
| 99 | * except it takes a pointer to the location of the frompc. This is so | ||
| 100 | * the prepare_ftrace_return() can hijack it temporarily for probing | ||
| 101 | * purposes. | ||
| 102 | */ | ||
| 103 | ENTRY(_ftrace_graph_caller) | ||
| 104 | /* save first/second function arg and the return register */ | ||
| 105 | [--sp] = r0; | ||
| 106 | [--sp] = r1; | ||
| 107 | [--sp] = rets; | ||
| 108 | |||
| 109 | r0 = fp; | ||
| 110 | r1 = rets; | ||
| 111 | r0 += 4; | ||
| 112 | r1 += -MCOUNT_INSN_SIZE; | ||
| 113 | call _prepare_ftrace_return; | ||
| 114 | |||
| 115 | jump .Lfinish_trace; | ||
| 116 | ENDPROC(_ftrace_graph_caller) | ||
| 117 | |||
| 118 | /* Undo the rewrite caused by ftrace_graph_caller(). The common function | ||
| 119 | * ftrace_return_to_handler() will return the original rets so we can | ||
| 120 | * restore it and be on our way. | ||
| 121 | */ | ||
| 122 | ENTRY(_return_to_handler) | ||
| 123 | /* make sure original return values are saved */ | ||
| 124 | [--sp] = p0; | ||
| 125 | [--sp] = r0; | ||
| 126 | [--sp] = r1; | ||
| 127 | |||
| 128 | /* get original return address */ | ||
| 129 | call _ftrace_return_to_handler; | ||
| 130 | rets = r0; | ||
| 131 | |||
| 132 | /* anomaly 05000371 - make sure we have at least three instructions | ||
| 133 | * between rets setting and the return | ||
| 134 | */ | ||
| 135 | r1 = [sp++]; | ||
| 136 | r0 = [sp++]; | ||
| 137 | p0 = [sp++]; | ||
| 138 | rts; | ||
| 139 | ENDPROC(_return_to_handler) | ||
| 140 | #endif | ||
diff --git a/arch/blackfin/kernel/ftrace.c b/arch/blackfin/kernel/ftrace.c new file mode 100644 index 000000000000..905bfc40a00b --- /dev/null +++ b/arch/blackfin/kernel/ftrace.c | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * ftrace graph code | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Analog Devices Inc. | ||
| 5 | * Licensed under the GPL-2 or later. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/ftrace.h> | ||
| 9 | #include <linux/kernel.h> | ||
| 10 | #include <linux/sched.h> | ||
| 11 | #include <asm/atomic.h> | ||
| 12 | |||
| 13 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Hook the return address and push it in the stack of return addrs | ||
| 17 | * in current thread info. | ||
| 18 | */ | ||
| 19 | void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr) | ||
| 20 | { | ||
| 21 | struct ftrace_graph_ent trace; | ||
| 22 | unsigned long return_hooker = (unsigned long)&return_to_handler; | ||
| 23 | |||
| 24 | if (unlikely(atomic_read(¤t->tracing_graph_pause))) | ||
| 25 | return; | ||
| 26 | |||
| 27 | if (ftrace_push_return_trace(*parent, self_addr, &trace.depth) == -EBUSY) | ||
| 28 | return; | ||
| 29 | |||
| 30 | trace.func = self_addr; | ||
| 31 | |||
| 32 | /* Only trace if the calling function expects to */ | ||
| 33 | if (!ftrace_graph_entry(&trace)) { | ||
| 34 | current->curr_ret_stack--; | ||
| 35 | return; | ||
| 36 | } | ||
| 37 | |||
| 38 | /* all is well in the world ! hijack RETS ... */ | ||
| 39 | *parent = return_hooker; | ||
| 40 | } | ||
| 41 | |||
| 42 | #endif | ||
diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c index 3a3e9615b002..7281a91d26b5 100644 --- a/arch/blackfin/kernel/gptimers.c +++ b/arch/blackfin/kernel/gptimers.c | |||
| @@ -189,10 +189,10 @@ void set_gptimer_status(int group, uint32_t value) | |||
| 189 | } | 189 | } |
| 190 | EXPORT_SYMBOL(set_gptimer_status); | 190 | EXPORT_SYMBOL(set_gptimer_status); |
| 191 | 191 | ||
| 192 | uint16_t get_gptimer_intr(int timer_id) | 192 | int get_gptimer_intr(int timer_id) |
| 193 | { | 193 | { |
| 194 | tassert(timer_id < MAX_BLACKFIN_GPTIMERS); | 194 | tassert(timer_id < MAX_BLACKFIN_GPTIMERS); |
| 195 | return (group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]) ? 1 : 0; | 195 | return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]); |
| 196 | } | 196 | } |
| 197 | EXPORT_SYMBOL(get_gptimer_intr); | 197 | EXPORT_SYMBOL(get_gptimer_intr); |
| 198 | 198 | ||
| @@ -203,10 +203,10 @@ void clear_gptimer_intr(int timer_id) | |||
| 203 | } | 203 | } |
| 204 | EXPORT_SYMBOL(clear_gptimer_intr); | 204 | EXPORT_SYMBOL(clear_gptimer_intr); |
| 205 | 205 | ||
| 206 | uint16_t get_gptimer_over(int timer_id) | 206 | int get_gptimer_over(int timer_id) |
| 207 | { | 207 | { |
| 208 | tassert(timer_id < MAX_BLACKFIN_GPTIMERS); | 208 | tassert(timer_id < MAX_BLACKFIN_GPTIMERS); |
| 209 | return (group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]) ? 1 : 0; | 209 | return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]); |
| 210 | } | 210 | } |
| 211 | EXPORT_SYMBOL(get_gptimer_over); | 211 | EXPORT_SYMBOL(get_gptimer_over); |
| 212 | 212 | ||
| @@ -217,6 +217,13 @@ void clear_gptimer_over(int timer_id) | |||
| 217 | } | 217 | } |
| 218 | EXPORT_SYMBOL(clear_gptimer_over); | 218 | EXPORT_SYMBOL(clear_gptimer_over); |
| 219 | 219 | ||
| 220 | int get_gptimer_run(int timer_id) | ||
| 221 | { | ||
| 222 | tassert(timer_id < MAX_BLACKFIN_GPTIMERS); | ||
| 223 | return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & trun_mask[timer_id]); | ||
| 224 | } | ||
| 225 | EXPORT_SYMBOL(get_gptimer_run); | ||
| 226 | |||
| 220 | void set_gptimer_config(int timer_id, uint16_t config) | 227 | void set_gptimer_config(int timer_id, uint16_t config) |
| 221 | { | 228 | { |
| 222 | tassert(timer_id < MAX_BLACKFIN_GPTIMERS); | 229 | tassert(timer_id < MAX_BLACKFIN_GPTIMERS); |
| @@ -244,7 +251,7 @@ void enable_gptimers(uint16_t mask) | |||
| 244 | } | 251 | } |
| 245 | EXPORT_SYMBOL(enable_gptimers); | 252 | EXPORT_SYMBOL(enable_gptimers); |
| 246 | 253 | ||
| 247 | void disable_gptimers(uint16_t mask) | 254 | static void _disable_gptimers(uint16_t mask) |
| 248 | { | 255 | { |
| 249 | int i; | 256 | int i; |
| 250 | uint16_t m = mask; | 257 | uint16_t m = mask; |
| @@ -253,6 +260,12 @@ void disable_gptimers(uint16_t mask) | |||
| 253 | group_regs[i]->disable = m & 0xFF; | 260 | group_regs[i]->disable = m & 0xFF; |
| 254 | m >>= 8; | 261 | m >>= 8; |
| 255 | } | 262 | } |
| 263 | } | ||
| 264 | |||
| 265 | void disable_gptimers(uint16_t mask) | ||
| 266 | { | ||
| 267 | int i; | ||
| 268 | _disable_gptimers(mask); | ||
| 256 | for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i) | 269 | for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i) |
| 257 | if (mask & (1 << i)) | 270 | if (mask & (1 << i)) |
| 258 | group_regs[BFIN_TIMER_OCTET(i)]->status |= trun_mask[i]; | 271 | group_regs[BFIN_TIMER_OCTET(i)]->status |= trun_mask[i]; |
| @@ -260,6 +273,13 @@ void disable_gptimers(uint16_t mask) | |||
| 260 | } | 273 | } |
| 261 | EXPORT_SYMBOL(disable_gptimers); | 274 | EXPORT_SYMBOL(disable_gptimers); |
| 262 | 275 | ||
| 276 | void disable_gptimers_sync(uint16_t mask) | ||
| 277 | { | ||
| 278 | _disable_gptimers(mask); | ||
| 279 | SSYNC(); | ||
| 280 | } | ||
| 281 | EXPORT_SYMBOL(disable_gptimers_sync); | ||
| 282 | |||
| 263 | void set_gptimer_pulse_hi(int timer_id) | 283 | void set_gptimer_pulse_hi(int timer_id) |
| 264 | { | 284 | { |
| 265 | tassert(timer_id < MAX_BLACKFIN_GPTIMERS); | 285 | tassert(timer_id < MAX_BLACKFIN_GPTIMERS); |
diff --git a/arch/blackfin/kernel/init_task.c b/arch/blackfin/kernel/init_task.c index 2c228c020978..c26c34de9f3c 100644 --- a/arch/blackfin/kernel/init_task.c +++ b/arch/blackfin/kernel/init_task.c | |||
| @@ -35,10 +35,6 @@ | |||
| 35 | 35 | ||
| 36 | static struct signal_struct init_signals = INIT_SIGNALS(init_signals); | 36 | static struct signal_struct init_signals = INIT_SIGNALS(init_signals); |
| 37 | static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); | 37 | static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); |
| 38 | |||
| 39 | struct mm_struct init_mm = INIT_MM(init_mm); | ||
| 40 | EXPORT_SYMBOL(init_mm); | ||
| 41 | |||
| 42 | /* | 38 | /* |
| 43 | * Initial task structure. | 39 | * Initial task structure. |
| 44 | * | 40 | * |
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c index a5de8d45424c..d8cde1fc5cb9 100644 --- a/arch/blackfin/kernel/ipipe.c +++ b/arch/blackfin/kernel/ipipe.c | |||
| @@ -99,7 +99,7 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) | |||
| 99 | * interrupt. | 99 | * interrupt. |
| 100 | */ | 100 | */ |
| 101 | m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR); | 101 | m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR); |
| 102 | this_domain = ipipe_current_domain; | 102 | this_domain = __ipipe_current_domain; |
| 103 | 103 | ||
| 104 | if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))) | 104 | if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))) |
| 105 | head = &this_domain->p_link; | 105 | head = &this_domain->p_link; |
| @@ -167,7 +167,7 @@ int __ipipe_check_root(void) | |||
| 167 | void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq) | 167 | void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq) |
| 168 | { | 168 | { |
| 169 | struct irq_desc *desc = irq_to_desc(irq); | 169 | struct irq_desc *desc = irq_to_desc(irq); |
| 170 | int prio = desc->ic_prio; | 170 | int prio = __ipipe_get_irq_priority(irq); |
| 171 | 171 | ||
| 172 | desc->depth = 0; | 172 | desc->depth = 0; |
| 173 | if (ipd != &ipipe_root && | 173 | if (ipd != &ipipe_root && |
| @@ -178,8 +178,7 @@ EXPORT_SYMBOL(__ipipe_enable_irqdesc); | |||
| 178 | 178 | ||
| 179 | void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq) | 179 | void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq) |
| 180 | { | 180 | { |
| 181 | struct irq_desc *desc = irq_to_desc(irq); | 181 | int prio = __ipipe_get_irq_priority(irq); |
| 182 | int prio = desc->ic_prio; | ||
| 183 | 182 | ||
| 184 | if (ipd != &ipipe_root && | 183 | if (ipd != &ipipe_root && |
| 185 | atomic_dec_and_test(&__ipipe_irq_lvdepth[prio])) | 184 | atomic_dec_and_test(&__ipipe_irq_lvdepth[prio])) |
| @@ -213,7 +212,9 @@ void __ipipe_unstall_root_raw(void) | |||
| 213 | 212 | ||
| 214 | int __ipipe_syscall_root(struct pt_regs *regs) | 213 | int __ipipe_syscall_root(struct pt_regs *regs) |
| 215 | { | 214 | { |
| 215 | struct ipipe_percpu_domain_data *p; | ||
| 216 | unsigned long flags; | 216 | unsigned long flags; |
| 217 | int ret; | ||
| 217 | 218 | ||
| 218 | /* | 219 | /* |
| 219 | * We need to run the IRQ tail hook whenever we don't | 220 | * We need to run the IRQ tail hook whenever we don't |
| @@ -232,29 +233,31 @@ int __ipipe_syscall_root(struct pt_regs *regs) | |||
| 232 | /* | 233 | /* |
| 233 | * This routine either returns: | 234 | * This routine either returns: |
| 234 | * 0 -- if the syscall is to be passed to Linux; | 235 | * 0 -- if the syscall is to be passed to Linux; |
| 235 | * 1 -- if the syscall should not be passed to Linux, and no | 236 | * >0 -- if the syscall should not be passed to Linux, and no |
| 236 | * tail work should be performed; | 237 | * tail work should be performed; |
| 237 | * -1 -- if the syscall should not be passed to Linux but the | 238 | * <0 -- if the syscall should not be passed to Linux but the |
| 238 | * tail work has to be performed (for handling signals etc). | 239 | * tail work has to be performed (for handling signals etc). |
| 239 | */ | 240 | */ |
| 240 | 241 | ||
| 241 | if (__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL) && | 242 | if (!__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL)) |
| 242 | __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs) > 0) { | 243 | return 0; |
| 243 | if (ipipe_root_domain_p && !in_atomic()) { | 244 | |
| 244 | /* | 245 | ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs); |
| 245 | * Sync pending VIRQs before _TIF_NEED_RESCHED | 246 | |
| 246 | * is tested. | 247 | local_irq_save_hw(flags); |
| 247 | */ | 248 | |
| 248 | local_irq_save_hw(flags); | 249 | if (!__ipipe_root_domain_p) { |
| 249 | if ((ipipe_root_cpudom_var(irqpend_himask) & IPIPE_IRQMASK_VIRT) != 0) | 250 | local_irq_restore_hw(flags); |
| 250 | __ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT); | ||
| 251 | local_irq_restore_hw(flags); | ||
| 252 | return -1; | ||
| 253 | } | ||
| 254 | return 1; | 251 | return 1; |
| 255 | } | 252 | } |
| 256 | 253 | ||
| 257 | return 0; | 254 | p = ipipe_root_cpudom_ptr(); |
| 255 | if ((p->irqpend_himask & IPIPE_IRQMASK_VIRT) != 0) | ||
| 256 | __ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT); | ||
| 257 | |||
| 258 | local_irq_restore_hw(flags); | ||
| 259 | |||
| 260 | return -ret; | ||
| 258 | } | 261 | } |
| 259 | 262 | ||
| 260 | unsigned long ipipe_critical_enter(void (*syncfn) (void)) | 263 | unsigned long ipipe_critical_enter(void (*syncfn) (void)) |
| @@ -310,12 +313,16 @@ int ipipe_trigger_irq(unsigned irq) | |||
| 310 | 313 | ||
| 311 | asmlinkage void __ipipe_sync_root(void) | 314 | asmlinkage void __ipipe_sync_root(void) |
| 312 | { | 315 | { |
| 316 | void (*irq_tail_hook)(void) = (void (*)(void))__ipipe_irq_tail_hook; | ||
| 313 | unsigned long flags; | 317 | unsigned long flags; |
| 314 | 318 | ||
| 315 | BUG_ON(irqs_disabled()); | 319 | BUG_ON(irqs_disabled()); |
| 316 | 320 | ||
| 317 | local_irq_save_hw(flags); | 321 | local_irq_save_hw(flags); |
| 318 | 322 | ||
| 323 | if (irq_tail_hook) | ||
| 324 | irq_tail_hook(); | ||
| 325 | |||
| 319 | clear_thread_flag(TIF_IRQ_SYNC); | 326 | clear_thread_flag(TIF_IRQ_SYNC); |
| 320 | 327 | ||
| 321 | if (ipipe_root_cpudom_var(irqpend_himask) != 0) | 328 | if (ipipe_root_cpudom_var(irqpend_himask) != 0) |
| @@ -326,9 +333,7 @@ asmlinkage void __ipipe_sync_root(void) | |||
| 326 | 333 | ||
| 327 | void ___ipipe_sync_pipeline(unsigned long syncmask) | 334 | void ___ipipe_sync_pipeline(unsigned long syncmask) |
| 328 | { | 335 | { |
| 329 | struct ipipe_domain *ipd = ipipe_current_domain; | 336 | if (__ipipe_root_domain_p) { |
| 330 | |||
| 331 | if (ipd == ipipe_root_domain) { | ||
| 332 | if (test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status))) | 337 | if (test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status))) |
| 333 | return; | 338 | return; |
| 334 | } | 339 | } |
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c index 401bd32aa499..6e31e935bb31 100644 --- a/arch/blackfin/kernel/irqchip.c +++ b/arch/blackfin/kernel/irqchip.c | |||
| @@ -59,12 +59,14 @@ static struct irq_chip bad_chip = { | |||
| 59 | .unmask = dummy_mask_unmask_irq, | 59 | .unmask = dummy_mask_unmask_irq, |
| 60 | }; | 60 | }; |
| 61 | 61 | ||
| 62 | static int bad_stats; | ||
| 62 | static struct irq_desc bad_irq_desc = { | 63 | static struct irq_desc bad_irq_desc = { |
| 63 | .status = IRQ_DISABLED, | 64 | .status = IRQ_DISABLED, |
| 64 | .chip = &bad_chip, | 65 | .chip = &bad_chip, |
| 65 | .handle_irq = handle_bad_irq, | 66 | .handle_irq = handle_bad_irq, |
| 66 | .depth = 1, | 67 | .depth = 1, |
| 67 | .lock = __SPIN_LOCK_UNLOCKED(irq_desc->lock), | 68 | .lock = __SPIN_LOCK_UNLOCKED(irq_desc->lock), |
| 69 | .kstat_irqs = &bad_stats, | ||
| 68 | #ifdef CONFIG_SMP | 70 | #ifdef CONFIG_SMP |
| 69 | .affinity = CPU_MASK_ALL | 71 | .affinity = CPU_MASK_ALL |
| 70 | #endif | 72 | #endif |
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c index b163f6d3330d..da28f796ad78 100644 --- a/arch/blackfin/kernel/kgdb.c +++ b/arch/blackfin/kernel/kgdb.c | |||
| @@ -466,7 +466,7 @@ static int validate_memory_access_address(unsigned long addr, int size) | |||
| 466 | int cpu = raw_smp_processor_id(); | 466 | int cpu = raw_smp_processor_id(); |
| 467 | 467 | ||
| 468 | if (size < 0) | 468 | if (size < 0) |
| 469 | return EFAULT; | 469 | return -EFAULT; |
| 470 | if (addr >= 0x1000 && (addr + size) <= physical_mem_end) | 470 | if (addr >= 0x1000 && (addr + size) <= physical_mem_end) |
| 471 | return 0; | 471 | return 0; |
| 472 | if (addr >= SYSMMR_BASE) | 472 | if (addr >= SYSMMR_BASE) |
| @@ -498,7 +498,7 @@ static int validate_memory_access_address(unsigned long addr, int size) | |||
| 498 | if (IN_MEM(addr, size, L2_START, L2_LENGTH)) | 498 | if (IN_MEM(addr, size, L2_START, L2_LENGTH)) |
| 499 | return 0; | 499 | return 0; |
| 500 | 500 | ||
| 501 | return EFAULT; | 501 | return -EFAULT; |
| 502 | } | 502 | } |
| 503 | 503 | ||
| 504 | /* | 504 | /* |
| @@ -508,14 +508,15 @@ static int validate_memory_access_address(unsigned long addr, int size) | |||
| 508 | int kgdb_mem2hex(char *mem, char *buf, int count) | 508 | int kgdb_mem2hex(char *mem, char *buf, int count) |
| 509 | { | 509 | { |
| 510 | char *tmp; | 510 | char *tmp; |
| 511 | int err = 0; | 511 | int err; |
| 512 | unsigned char *pch; | 512 | unsigned char *pch; |
| 513 | unsigned short mmr16; | 513 | unsigned short mmr16; |
| 514 | unsigned long mmr32; | 514 | unsigned long mmr32; |
| 515 | int cpu = raw_smp_processor_id(); | 515 | int cpu = raw_smp_processor_id(); |
| 516 | 516 | ||
| 517 | if (validate_memory_access_address((unsigned long)mem, count)) | 517 | err = validate_memory_access_address((unsigned long)mem, count); |
| 518 | return EFAULT; | 518 | if (err) |
| 519 | return err; | ||
| 519 | 520 | ||
| 520 | /* | 521 | /* |
| 521 | * We use the upper half of buf as an intermediate buffer for the | 522 | * We use the upper half of buf as an intermediate buffer for the |
| @@ -533,7 +534,7 @@ int kgdb_mem2hex(char *mem, char *buf, int count) | |||
| 533 | *tmp++ = *pch++; | 534 | *tmp++ = *pch++; |
| 534 | tmp -= 2; | 535 | tmp -= 2; |
| 535 | } else | 536 | } else |
| 536 | err = EFAULT; | 537 | err = -EFAULT; |
| 537 | break; | 538 | break; |
| 538 | case 4: | 539 | case 4: |
| 539 | if ((unsigned int)mem % 4 == 0) { | 540 | if ((unsigned int)mem % 4 == 0) { |
| @@ -545,10 +546,10 @@ int kgdb_mem2hex(char *mem, char *buf, int count) | |||
| 545 | *tmp++ = *pch++; | 546 | *tmp++ = *pch++; |
| 546 | tmp -= 4; | 547 | tmp -= 4; |
| 547 | } else | 548 | } else |
| 548 | err = EFAULT; | 549 | err = -EFAULT; |
| 549 | break; | 550 | break; |
| 550 | default: | 551 | default: |
| 551 | err = EFAULT; | 552 | err = -EFAULT; |
| 552 | } | 553 | } |
| 553 | } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) | 554 | } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) |
| 554 | #ifdef CONFIG_SMP | 555 | #ifdef CONFIG_SMP |
| @@ -557,7 +558,7 @@ int kgdb_mem2hex(char *mem, char *buf, int count) | |||
| 557 | ) { | 558 | ) { |
| 558 | /* access L1 instruction SRAM*/ | 559 | /* access L1 instruction SRAM*/ |
| 559 | if (dma_memcpy(tmp, mem, count) == NULL) | 560 | if (dma_memcpy(tmp, mem, count) == NULL) |
| 560 | err = EFAULT; | 561 | err = -EFAULT; |
| 561 | } else | 562 | } else |
| 562 | err = probe_kernel_read(tmp, mem, count); | 563 | err = probe_kernel_read(tmp, mem, count); |
| 563 | 564 | ||
| @@ -585,24 +586,24 @@ int kgdb_ebin2mem(char *buf, char *mem, int count) | |||
| 585 | char *tmp_new; | 586 | char *tmp_new; |
| 586 | unsigned short *mmr16; | 587 | unsigned short *mmr16; |
| 587 | unsigned long *mmr32; | 588 | unsigned long *mmr32; |
| 588 | int err = 0; | 589 | int err; |
| 589 | int size = 0; | 590 | int size; |
| 590 | int cpu = raw_smp_processor_id(); | 591 | int cpu = raw_smp_processor_id(); |
| 591 | 592 | ||
| 592 | tmp_old = tmp_new = buf; | 593 | tmp_old = tmp_new = buf; |
| 593 | 594 | ||
| 594 | while (count-- > 0) { | 595 | for (size = 0; size < count; ++size) { |
| 595 | if (*tmp_old == 0x7d) | 596 | if (*tmp_old == 0x7d) |
| 596 | *tmp_new = *(++tmp_old) ^ 0x20; | 597 | *tmp_new = *(++tmp_old) ^ 0x20; |
| 597 | else | 598 | else |
| 598 | *tmp_new = *tmp_old; | 599 | *tmp_new = *tmp_old; |
| 599 | tmp_new++; | 600 | tmp_new++; |
| 600 | tmp_old++; | 601 | tmp_old++; |
| 601 | size++; | ||
| 602 | } | 602 | } |
| 603 | 603 | ||
| 604 | if (validate_memory_access_address((unsigned long)mem, size)) | 604 | err = validate_memory_access_address((unsigned long)mem, size); |
| 605 | return EFAULT; | 605 | if (err) |
| 606 | return err; | ||
| 606 | 607 | ||
| 607 | if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/ | 608 | if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/ |
| 608 | switch (size) { | 609 | switch (size) { |
| @@ -611,17 +612,17 @@ int kgdb_ebin2mem(char *buf, char *mem, int count) | |||
| 611 | mmr16 = (unsigned short *)buf; | 612 | mmr16 = (unsigned short *)buf; |
| 612 | *(unsigned short *)mem = *mmr16; | 613 | *(unsigned short *)mem = *mmr16; |
| 613 | } else | 614 | } else |
| 614 | return EFAULT; | 615 | err = -EFAULT; |
| 615 | break; | 616 | break; |
| 616 | case 4: | 617 | case 4: |
| 617 | if ((unsigned int)mem % 4 == 0) { | 618 | if ((unsigned int)mem % 4 == 0) { |
| 618 | mmr32 = (unsigned long *)buf; | 619 | mmr32 = (unsigned long *)buf; |
| 619 | *(unsigned long *)mem = *mmr32; | 620 | *(unsigned long *)mem = *mmr32; |
| 620 | } else | 621 | } else |
| 621 | return EFAULT; | 622 | err = -EFAULT; |
| 622 | break; | 623 | break; |
| 623 | default: | 624 | default: |
| 624 | return EFAULT; | 625 | err = -EFAULT; |
| 625 | } | 626 | } |
| 626 | } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) | 627 | } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) |
| 627 | #ifdef CONFIG_SMP | 628 | #ifdef CONFIG_SMP |
| @@ -630,7 +631,7 @@ int kgdb_ebin2mem(char *buf, char *mem, int count) | |||
| 630 | ) { | 631 | ) { |
| 631 | /* access L1 instruction SRAM */ | 632 | /* access L1 instruction SRAM */ |
| 632 | if (dma_memcpy(mem, buf, size) == NULL) | 633 | if (dma_memcpy(mem, buf, size) == NULL) |
| 633 | err = EFAULT; | 634 | err = -EFAULT; |
| 634 | } else | 635 | } else |
| 635 | err = probe_kernel_write(mem, buf, size); | 636 | err = probe_kernel_write(mem, buf, size); |
| 636 | 637 | ||
| @@ -648,10 +649,12 @@ int kgdb_hex2mem(char *buf, char *mem, int count) | |||
| 648 | char *tmp_hex; | 649 | char *tmp_hex; |
| 649 | unsigned short *mmr16; | 650 | unsigned short *mmr16; |
| 650 | unsigned long *mmr32; | 651 | unsigned long *mmr32; |
| 652 | int err; | ||
| 651 | int cpu = raw_smp_processor_id(); | 653 | int cpu = raw_smp_processor_id(); |
| 652 | 654 | ||
| 653 | if (validate_memory_access_address((unsigned long)mem, count)) | 655 | err = validate_memory_access_address((unsigned long)mem, count); |
| 654 | return EFAULT; | 656 | if (err) |
| 657 | return err; | ||
| 655 | 658 | ||
| 656 | /* | 659 | /* |
| 657 | * We use the upper half of buf as an intermediate buffer for the | 660 | * We use the upper half of buf as an intermediate buffer for the |
| @@ -673,17 +676,17 @@ int kgdb_hex2mem(char *buf, char *mem, int count) | |||
| 673 | mmr16 = (unsigned short *)tmp_raw; | 676 | mmr16 = (unsigned short *)tmp_raw; |
| 674 | *(unsigned short *)mem = *mmr16; | 677 | *(unsigned short *)mem = *mmr16; |
| 675 | } else | 678 | } else |
| 676 | return EFAULT; | 679 | err = -EFAULT; |
| 677 | break; | 680 | break; |
| 678 | case 4: | 681 | case 4: |
| 679 | if ((unsigned int)mem % 4 == 0) { | 682 | if ((unsigned int)mem % 4 == 0) { |
| 680 | mmr32 = (unsigned long *)tmp_raw; | 683 | mmr32 = (unsigned long *)tmp_raw; |
| 681 | *(unsigned long *)mem = *mmr32; | 684 | *(unsigned long *)mem = *mmr32; |
| 682 | } else | 685 | } else |
| 683 | return EFAULT; | 686 | err = -EFAULT; |
| 684 | break; | 687 | break; |
| 685 | default: | 688 | default: |
| 686 | return EFAULT; | 689 | err = -EFAULT; |
| 687 | } | 690 | } |
| 688 | } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) | 691 | } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) |
| 689 | #ifdef CONFIG_SMP | 692 | #ifdef CONFIG_SMP |
| @@ -692,10 +695,11 @@ int kgdb_hex2mem(char *buf, char *mem, int count) | |||
| 692 | ) { | 695 | ) { |
| 693 | /* access L1 instruction SRAM */ | 696 | /* access L1 instruction SRAM */ |
| 694 | if (dma_memcpy(mem, tmp_raw, count) == NULL) | 697 | if (dma_memcpy(mem, tmp_raw, count) == NULL) |
| 695 | return EFAULT; | 698 | err = -EFAULT; |
| 696 | } else | 699 | } else |
| 697 | return probe_kernel_write(mem, tmp_raw, count); | 700 | err = probe_kernel_write(mem, tmp_raw, count); |
| 698 | return 0; | 701 | |
| 702 | return err; | ||
| 699 | } | 703 | } |
| 700 | 704 | ||
| 701 | int kgdb_validate_break_address(unsigned long addr) | 705 | int kgdb_validate_break_address(unsigned long addr) |
| @@ -715,7 +719,7 @@ int kgdb_validate_break_address(unsigned long addr) | |||
| 715 | if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH)) | 719 | if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH)) |
| 716 | return 0; | 720 | return 0; |
| 717 | 721 | ||
| 718 | return EFAULT; | 722 | return -EFAULT; |
| 719 | } | 723 | } |
| 720 | 724 | ||
| 721 | int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr) | 725 | int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr) |
diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c index 1bd7f2d018a8..d5aee3626688 100644 --- a/arch/blackfin/kernel/module.c +++ b/arch/blackfin/kernel/module.c | |||
| @@ -201,8 +201,8 @@ apply_relocate(Elf_Shdr * sechdrs, const char *strtab, | |||
| 201 | /* Arithmetic relocations are handled. */ | 201 | /* Arithmetic relocations are handled. */ |
| 202 | /* We do not expect LSETUP to be split and hence is not */ | 202 | /* We do not expect LSETUP to be split and hence is not */ |
| 203 | /* handled. */ | 203 | /* handled. */ |
| 204 | /* R_byte and R_byte2 are also not handled as the gas */ | 204 | /* R_BFIN_BYTE and R_BFIN_BYTE2 are also not handled as the */ |
| 205 | /* does not generate it. */ | 205 | /* gas does not generate it. */ |
| 206 | /*************************************************************************/ | 206 | /*************************************************************************/ |
| 207 | int | 207 | int |
| 208 | apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab, | 208 | apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab, |
| @@ -243,8 +243,8 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab, | |||
| 243 | #endif | 243 | #endif |
| 244 | switch (ELF32_R_TYPE(rel[i].r_info)) { | 244 | switch (ELF32_R_TYPE(rel[i].r_info)) { |
| 245 | 245 | ||
| 246 | case R_pcrel24: | 246 | case R_BFIN_PCREL24: |
| 247 | case R_pcrel24_jump_l: | 247 | case R_BFIN_PCREL24_JUMP_L: |
| 248 | /* Add the value, subtract its postition */ | 248 | /* Add the value, subtract its postition */ |
| 249 | location16 = | 249 | location16 = |
| 250 | (uint16_t *) (sechdrs[sechdrs[relsec].sh_info]. | 250 | (uint16_t *) (sechdrs[sechdrs[relsec].sh_info]. |
| @@ -266,18 +266,18 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab, | |||
| 266 | (*location16 & 0xff00) | (value >> 16 & 0x00ff); | 266 | (*location16 & 0xff00) | (value >> 16 & 0x00ff); |
| 267 | *(location16 + 1) = value & 0xffff; | 267 | *(location16 + 1) = value & 0xffff; |
| 268 | break; | 268 | break; |
| 269 | case R_pcrel12_jump: | 269 | case R_BFIN_PCREL12_JUMP: |
| 270 | case R_pcrel12_jump_s: | 270 | case R_BFIN_PCREL12_JUMP_S: |
| 271 | value -= (uint32_t) location32; | 271 | value -= (uint32_t) location32; |
| 272 | value >>= 1; | 272 | value >>= 1; |
| 273 | *location16 = (value & 0xfff); | 273 | *location16 = (value & 0xfff); |
| 274 | break; | 274 | break; |
| 275 | case R_pcrel10: | 275 | case R_BFIN_PCREL10: |
| 276 | value -= (uint32_t) location32; | 276 | value -= (uint32_t) location32; |
| 277 | value >>= 1; | 277 | value >>= 1; |
| 278 | *location16 = (value & 0x3ff); | 278 | *location16 = (value & 0x3ff); |
| 279 | break; | 279 | break; |
| 280 | case R_luimm16: | 280 | case R_BFIN_LUIMM16: |
| 281 | pr_debug("before %x after %x\n", *location16, | 281 | pr_debug("before %x after %x\n", *location16, |
| 282 | (value & 0xffff)); | 282 | (value & 0xffff)); |
| 283 | tmp = (value & 0xffff); | 283 | tmp = (value & 0xffff); |
| @@ -286,7 +286,7 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab, | |||
| 286 | } else | 286 | } else |
| 287 | *location16 = tmp; | 287 | *location16 = tmp; |
| 288 | break; | 288 | break; |
| 289 | case R_huimm16: | 289 | case R_BFIN_HUIMM16: |
| 290 | pr_debug("before %x after %x\n", *location16, | 290 | pr_debug("before %x after %x\n", *location16, |
| 291 | ((value >> 16) & 0xffff)); | 291 | ((value >> 16) & 0xffff)); |
| 292 | tmp = ((value >> 16) & 0xffff); | 292 | tmp = ((value >> 16) & 0xffff); |
| @@ -295,10 +295,10 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab, | |||
| 295 | } else | 295 | } else |
| 296 | *location16 = tmp; | 296 | *location16 = tmp; |
| 297 | break; | 297 | break; |
| 298 | case R_rimm16: | 298 | case R_BFIN_RIMM16: |
| 299 | *location16 = (value & 0xffff); | 299 | *location16 = (value & 0xffff); |
| 300 | break; | 300 | break; |
| 301 | case R_byte4_data: | 301 | case R_BFIN_BYTE4_DATA: |
| 302 | pr_debug("before %x after %x\n", *location32, value); | 302 | pr_debug("before %x after %x\n", *location32, value); |
| 303 | *location32 = value; | 303 | *location32 = value; |
| 304 | break; | 304 | break; |
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index e040e03335ea..3e1d86e456f6 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c | |||
| @@ -160,6 +160,29 @@ pid_t kernel_thread(int (*fn) (void *), void *arg, unsigned long flags) | |||
| 160 | } | 160 | } |
| 161 | EXPORT_SYMBOL(kernel_thread); | 161 | EXPORT_SYMBOL(kernel_thread); |
| 162 | 162 | ||
| 163 | /* | ||
| 164 | * Do necessary setup to start up a newly executed thread. | ||
| 165 | * | ||
| 166 | * pass the data segment into user programs if it exists, | ||
| 167 | * it can't hurt anything as far as I can tell | ||
| 168 | */ | ||
| 169 | void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp) | ||
| 170 | { | ||
| 171 | set_fs(USER_DS); | ||
| 172 | regs->pc = new_ip; | ||
| 173 | if (current->mm) | ||
| 174 | regs->p5 = current->mm->start_data; | ||
| 175 | #ifdef CONFIG_SMP | ||
| 176 | task_thread_info(current)->l1_task_info.stack_start = | ||
| 177 | (void *)current->mm->context.stack_start; | ||
| 178 | task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp; | ||
| 179 | memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info, | ||
| 180 | sizeof(*L1_SCRATCH_TASK_INFO)); | ||
| 181 | #endif | ||
| 182 | wrusp(new_sp); | ||
| 183 | } | ||
| 184 | EXPORT_SYMBOL_GPL(start_thread); | ||
| 185 | |||
| 163 | void flush_thread(void) | 186 | void flush_thread(void) |
| 164 | { | 187 | { |
| 165 | } | 188 | } |
| @@ -322,6 +345,9 @@ void finish_atomic_sections (struct pt_regs *regs) | |||
| 322 | } | 345 | } |
| 323 | 346 | ||
| 324 | #if defined(CONFIG_ACCESS_CHECK) | 347 | #if defined(CONFIG_ACCESS_CHECK) |
| 348 | #ifdef CONFIG_ACCESS_OK_L1 | ||
| 349 | __attribute__((l1_text)) | ||
| 350 | #endif | ||
| 325 | /* Return 1 if access to memory range is OK, 0 otherwise */ | 351 | /* Return 1 if access to memory range is OK, 0 otherwise */ |
| 326 | int _access_ok(unsigned long addr, unsigned long size) | 352 | int _access_ok(unsigned long addr, unsigned long size) |
| 327 | { | 353 | { |
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index a58687bdee6a..6454babdfaff 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c | |||
| @@ -18,9 +18,12 @@ | |||
| 18 | #include <linux/tty.h> | 18 | #include <linux/tty.h> |
| 19 | #include <linux/pfn.h> | 19 | #include <linux/pfn.h> |
| 20 | 20 | ||
| 21 | #ifdef CONFIG_MTD_UCLINUX | ||
| 22 | #include <linux/mtd/map.h> | ||
| 21 | #include <linux/ext2_fs.h> | 23 | #include <linux/ext2_fs.h> |
| 22 | #include <linux/cramfs_fs.h> | 24 | #include <linux/cramfs_fs.h> |
| 23 | #include <linux/romfs_fs.h> | 25 | #include <linux/romfs_fs.h> |
| 26 | #endif | ||
| 24 | 27 | ||
| 25 | #include <asm/cplb.h> | 28 | #include <asm/cplb.h> |
| 26 | #include <asm/cacheflush.h> | 29 | #include <asm/cacheflush.h> |
| @@ -45,6 +48,7 @@ EXPORT_SYMBOL(_ramend); | |||
| 45 | EXPORT_SYMBOL(reserved_mem_dcache_on); | 48 | EXPORT_SYMBOL(reserved_mem_dcache_on); |
| 46 | 49 | ||
| 47 | #ifdef CONFIG_MTD_UCLINUX | 50 | #ifdef CONFIG_MTD_UCLINUX |
| 51 | extern struct map_info uclinux_ram_map; | ||
| 48 | unsigned long memory_mtd_end, memory_mtd_start, mtd_size; | 52 | unsigned long memory_mtd_end, memory_mtd_start, mtd_size; |
| 49 | unsigned long _ebss; | 53 | unsigned long _ebss; |
| 50 | EXPORT_SYMBOL(memory_mtd_end); | 54 | EXPORT_SYMBOL(memory_mtd_end); |
| @@ -150,40 +154,45 @@ void __init bfin_relocate_l1_mem(void) | |||
| 150 | unsigned long l1_data_b_length; | 154 | unsigned long l1_data_b_length; |
| 151 | unsigned long l2_length; | 155 | unsigned long l2_length; |
| 152 | 156 | ||
| 157 | /* | ||
| 158 | * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S | ||
| 159 | * we know that everything about l1 text/data is nice and aligned, | ||
| 160 | * so copy by 4 byte chunks, and don't worry about overlapping | ||
| 161 | * src/dest. | ||
| 162 | * | ||
| 163 | * We can't use the dma_memcpy functions, since they can call | ||
| 164 | * scheduler functions which might be in L1 :( and core writes | ||
| 165 | * into L1 instruction cause bad access errors, so we are stuck, | ||
| 166 | * we are required to use DMA, but can't use the common dma | ||
| 167 | * functions. We can't use memcpy either - since that might be | ||
| 168 | * going to be in the relocated L1 | ||
| 169 | */ | ||
| 170 | |||
| 153 | blackfin_dma_early_init(); | 171 | blackfin_dma_early_init(); |
| 154 | 172 | ||
| 173 | /* if necessary, copy _stext_l1 to _etext_l1 to L1 instruction SRAM */ | ||
| 155 | l1_code_length = _etext_l1 - _stext_l1; | 174 | l1_code_length = _etext_l1 - _stext_l1; |
| 156 | if (l1_code_length > L1_CODE_LENGTH) | 175 | if (l1_code_length) |
| 157 | panic("L1 Instruction SRAM Overflow\n"); | 176 | early_dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length); |
| 158 | /* cannot complain as printk is not available as yet. | ||
| 159 | * But we can continue booting and complain later! | ||
| 160 | */ | ||
| 161 | |||
| 162 | /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */ | ||
| 163 | dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length); | ||
| 164 | 177 | ||
| 178 | /* if necessary, copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */ | ||
| 165 | l1_data_a_length = _sbss_l1 - _sdata_l1; | 179 | l1_data_a_length = _sbss_l1 - _sdata_l1; |
| 166 | if (l1_data_a_length > L1_DATA_A_LENGTH) | 180 | if (l1_data_a_length) |
| 167 | panic("L1 Data SRAM Bank A Overflow\n"); | 181 | early_dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length); |
| 168 | |||
| 169 | /* Copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */ | ||
| 170 | dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length); | ||
| 171 | 182 | ||
| 183 | /* if necessary, copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */ | ||
| 172 | l1_data_b_length = _sbss_b_l1 - _sdata_b_l1; | 184 | l1_data_b_length = _sbss_b_l1 - _sdata_b_l1; |
| 173 | if (l1_data_b_length > L1_DATA_B_LENGTH) | 185 | if (l1_data_b_length) |
| 174 | panic("L1 Data SRAM Bank B Overflow\n"); | 186 | early_dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length + |
| 175 | |||
| 176 | /* Copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */ | ||
| 177 | dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length + | ||
| 178 | l1_data_a_length, l1_data_b_length); | 187 | l1_data_a_length, l1_data_b_length); |
| 179 | 188 | ||
| 189 | early_dma_memcpy_done(); | ||
| 190 | |||
| 191 | /* if necessary, copy _stext_l2 to _edata_l2 to L2 SRAM */ | ||
| 180 | if (L2_LENGTH != 0) { | 192 | if (L2_LENGTH != 0) { |
| 181 | l2_length = _sbss_l2 - _stext_l2; | 193 | l2_length = _sbss_l2 - _stext_l2; |
| 182 | if (l2_length > L2_LENGTH) | 194 | if (l2_length) |
| 183 | panic("L2 SRAM Overflow\n"); | 195 | memcpy(_stext_l2, _l2_lma_start, l2_length); |
| 184 | |||
| 185 | /* Copy _stext_l2 to _edata_l2 to L2 SRAM */ | ||
| 186 | dma_memcpy(_stext_l2, _l2_lma_start, l2_length); | ||
| 187 | } | 196 | } |
| 188 | } | 197 | } |
| 189 | 198 | ||
| @@ -472,7 +481,7 @@ static __init void memory_setup(void) | |||
| 472 | 481 | ||
| 473 | if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) { | 482 | if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) { |
| 474 | console_init(); | 483 | console_init(); |
| 475 | panic("DMA region exceeds memory limit: %lu.\n", | 484 | panic("DMA region exceeds memory limit: %lu.", |
| 476 | _ramend - _ramstart); | 485 | _ramend - _ramstart); |
| 477 | } | 486 | } |
| 478 | memory_end = _ramend - DMA_UNCACHED_REGION; | 487 | memory_end = _ramend - DMA_UNCACHED_REGION; |
| @@ -526,14 +535,13 @@ static __init void memory_setup(void) | |||
| 526 | 535 | ||
| 527 | if (mtd_size == 0) { | 536 | if (mtd_size == 0) { |
| 528 | console_init(); | 537 | console_init(); |
| 529 | panic("Don't boot kernel without rootfs attached.\n"); | 538 | panic("Don't boot kernel without rootfs attached."); |
| 530 | } | 539 | } |
| 531 | 540 | ||
| 532 | /* Relocate MTD image to the top of memory after the uncached memory area */ | 541 | /* Relocate MTD image to the top of memory after the uncached memory area */ |
| 533 | dma_memcpy((char *)memory_end, _end, mtd_size); | 542 | uclinux_ram_map.phys = memory_mtd_start = memory_end; |
| 534 | 543 | uclinux_ram_map.size = mtd_size; | |
| 535 | memory_mtd_start = memory_end; | 544 | dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); |
| 536 | _ebss = memory_mtd_start; /* define _ebss for compatible */ | ||
| 537 | #endif /* CONFIG_MTD_UCLINUX */ | 545 | #endif /* CONFIG_MTD_UCLINUX */ |
| 538 | 546 | ||
| 539 | #if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) | 547 | #if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) |
| @@ -796,10 +804,8 @@ void __init setup_arch(char **cmdline_p) | |||
| 796 | cclk = get_cclk(); | 804 | cclk = get_cclk(); |
| 797 | sclk = get_sclk(); | 805 | sclk = get_sclk(); |
| 798 | 806 | ||
| 799 | #if !defined(CONFIG_BFIN_KERNEL_CLOCK) | 807 | if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk) |
| 800 | if (ANOMALY_05000273 && cclk == sclk) | 808 | panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK"); |
| 801 | panic("ANOMALY 05000273, SCLK can not be same as CCLK"); | ||
| 802 | #endif | ||
| 803 | 809 | ||
| 804 | #ifdef BF561_FAMILY | 810 | #ifdef BF561_FAMILY |
| 805 | if (ANOMALY_05000266) { | 811 | if (ANOMALY_05000266) { |
| @@ -881,7 +887,7 @@ void __init setup_arch(char **cmdline_p) | |||
| 881 | printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", | 887 | printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", |
| 882 | bfin_compiled_revid(), bfin_revid()); | 888 | bfin_compiled_revid(), bfin_revid()); |
| 883 | if (bfin_compiled_revid() > bfin_revid()) | 889 | if (bfin_compiled_revid() > bfin_revid()) |
| 884 | panic("Error: you are missing anomaly workarounds for this rev\n"); | 890 | panic("Error: you are missing anomaly workarounds for this rev"); |
| 885 | } | 891 | } |
| 886 | } | 892 | } |
| 887 | if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) | 893 | if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) |
| @@ -891,16 +897,13 @@ void __init setup_arch(char **cmdline_p) | |||
| 891 | 897 | ||
| 892 | /* We can't run on BF548-0.1 due to ANOMALY 05000448 */ | 898 | /* We can't run on BF548-0.1 due to ANOMALY 05000448 */ |
| 893 | if (bfin_cpuid() == 0x27de && bfin_revid() == 1) | 899 | if (bfin_cpuid() == 0x27de && bfin_revid() == 1) |
| 894 | panic("You can't run on this processor due to 05000448\n"); | 900 | panic("You can't run on this processor due to 05000448"); |
| 895 | 901 | ||
| 896 | printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); | 902 | printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); |
| 897 | 903 | ||
| 898 | printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", | 904 | printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", |
| 899 | cclk / 1000000, sclk / 1000000); | 905 | cclk / 1000000, sclk / 1000000); |
| 900 | 906 | ||
| 901 | if (ANOMALY_05000273 && (cclk >> 1) <= sclk) | ||
| 902 | printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n"); | ||
| 903 | |||
| 904 | setup_bootmem_allocator(); | 907 | setup_bootmem_allocator(); |
| 905 | 908 | ||
| 906 | paging_init(); | 909 | paging_init(); |
| @@ -1095,7 +1098,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
| 1095 | CPUID, bfin_cpuid()); | 1098 | CPUID, bfin_cpuid()); |
| 1096 | 1099 | ||
| 1097 | seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n" | 1100 | seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n" |
| 1098 | "stepping\t: %d\n", | 1101 | "stepping\t: %d ", |
| 1099 | cpu, cclk/1000000, sclk/1000000, | 1102 | cpu, cclk/1000000, sclk/1000000, |
| 1100 | #ifdef CONFIG_MPU | 1103 | #ifdef CONFIG_MPU |
| 1101 | "mpu on", | 1104 | "mpu on", |
| @@ -1104,7 +1107,16 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
| 1104 | #endif | 1107 | #endif |
| 1105 | revid); | 1108 | revid); |
| 1106 | 1109 | ||
| 1107 | seq_printf(m, "cpu MHz\t\t: %lu.%03lu/%lu.%03lu\n", | 1110 | if (bfin_revid() != bfin_compiled_revid()) { |
| 1111 | if (bfin_compiled_revid() == -1) | ||
| 1112 | seq_printf(m, "(Compiled for Rev none)"); | ||
| 1113 | else if (bfin_compiled_revid() == 0xffff) | ||
| 1114 | seq_printf(m, "(Compiled for Rev any)"); | ||
| 1115 | else | ||
| 1116 | seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid()); | ||
| 1117 | } | ||
| 1118 | |||
| 1119 | seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n", | ||
| 1108 | cclk/1000000, cclk%1000000, | 1120 | cclk/1000000, cclk%1000000, |
| 1109 | sclk/1000000, sclk%1000000); | 1121 | sclk/1000000, sclk%1000000); |
| 1110 | seq_printf(m, "bogomips\t: %lu.%02lu\n" | 1122 | seq_printf(m, "bogomips\t: %lu.%02lu\n" |
| @@ -1169,6 +1181,9 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
| 1169 | #ifdef __ARCH_SYNC_CORE_DCACHE | 1181 | #ifdef __ARCH_SYNC_CORE_DCACHE |
| 1170 | seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count); | 1182 | seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count); |
| 1171 | #endif | 1183 | #endif |
| 1184 | #ifdef __ARCH_SYNC_CORE_ICACHE | ||
| 1185 | seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", cpudata->icache_invld_count); | ||
| 1186 | #endif | ||
| 1172 | #ifdef CONFIG_BFIN_ICACHE_LOCK | 1187 | #ifdef CONFIG_BFIN_ICACHE_LOCK |
| 1173 | switch ((cpudata->imemctl >> 3) & WAYALL_L) { | 1188 | switch ((cpudata->imemctl >> 3) & WAYALL_L) { |
| 1174 | case WAY0_L: | 1189 | case WAY0_L: |
diff --git a/arch/blackfin/kernel/stacktrace.c b/arch/blackfin/kernel/stacktrace.c new file mode 100644 index 000000000000..30301e1eace5 --- /dev/null +++ b/arch/blackfin/kernel/stacktrace.c | |||
| @@ -0,0 +1,53 @@ | |||
| 1 | /* | ||
| 2 | * Blackfin stacktrace code (mostly copied from avr32) | ||
| 3 | * | ||
| 4 | * Copyright 2009 Analog Devices Inc. | ||
| 5 | * Licensed under the GPL-2 or later. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/sched.h> | ||
| 9 | #include <linux/stacktrace.h> | ||
| 10 | #include <linux/thread_info.h> | ||
| 11 | #include <linux/module.h> | ||
| 12 | |||
| 13 | register unsigned long current_frame_pointer asm("FP"); | ||
| 14 | |||
| 15 | struct stackframe { | ||
| 16 | unsigned long fp; | ||
| 17 | unsigned long rets; | ||
| 18 | }; | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Save stack-backtrace addresses into a stack_trace buffer. | ||
| 22 | */ | ||
| 23 | void save_stack_trace(struct stack_trace *trace) | ||
| 24 | { | ||
| 25 | unsigned long low, high; | ||
| 26 | unsigned long fp; | ||
| 27 | struct stackframe *frame; | ||
| 28 | int skip = trace->skip; | ||
| 29 | |||
| 30 | low = (unsigned long)task_stack_page(current); | ||
| 31 | high = low + THREAD_SIZE; | ||
| 32 | fp = current_frame_pointer; | ||
| 33 | |||
| 34 | while (fp >= low && fp <= (high - sizeof(*frame))) { | ||
| 35 | frame = (struct stackframe *)fp; | ||
| 36 | |||
| 37 | if (skip) { | ||
| 38 | skip--; | ||
| 39 | } else { | ||
| 40 | trace->entries[trace->nr_entries++] = frame->rets; | ||
| 41 | if (trace->nr_entries >= trace->max_entries) | ||
| 42 | break; | ||
| 43 | } | ||
| 44 | |||
| 45 | /* | ||
| 46 | * The next frame must be at a higher address than the | ||
| 47 | * current frame. | ||
| 48 | */ | ||
| 49 | low = fp + sizeof(*frame); | ||
| 50 | fp = frame->fp; | ||
| 51 | } | ||
| 52 | } | ||
| 53 | EXPORT_SYMBOL_GPL(save_stack_trace); | ||
diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c index fce49d7cf001..a8f1329c15a4 100644 --- a/arch/blackfin/kernel/sys_bfin.c +++ b/arch/blackfin/kernel/sys_bfin.c | |||
| @@ -78,11 +78,6 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len, | |||
| 78 | return do_mmap2(addr, len, prot, flags, fd, pgoff); | 78 | return do_mmap2(addr, len, prot, flags, fd, pgoff); |
| 79 | } | 79 | } |
| 80 | 80 | ||
| 81 | asmlinkage int sys_getpagesize(void) | ||
| 82 | { | ||
| 83 | return PAGE_SIZE; | ||
| 84 | } | ||
| 85 | |||
| 86 | asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags) | 81 | asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags) |
| 87 | { | 82 | { |
| 88 | return sram_alloc_with_lsl(size, flags); | 83 | return sram_alloc_with_lsl(size, flags); |
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c index 27646121280a..0791eba40d9f 100644 --- a/arch/blackfin/kernel/time-ts.c +++ b/arch/blackfin/kernel/time-ts.c | |||
| @@ -20,8 +20,9 @@ | |||
| 20 | 20 | ||
| 21 | #include <asm/blackfin.h> | 21 | #include <asm/blackfin.h> |
| 22 | #include <asm/time.h> | 22 | #include <asm/time.h> |
| 23 | #include <asm/gptimers.h> | ||
| 23 | 24 | ||
| 24 | #ifdef CONFIG_CYCLES_CLOCKSOURCE | 25 | #if defined(CONFIG_CYCLES_CLOCKSOURCE) |
| 25 | 26 | ||
| 26 | /* Accelerators for sched_clock() | 27 | /* Accelerators for sched_clock() |
| 27 | * convert from cycles(64bits) => nanoseconds (64bits) | 28 | * convert from cycles(64bits) => nanoseconds (64bits) |
| @@ -58,15 +59,15 @@ static inline unsigned long long cycles_2_ns(cycle_t cyc) | |||
| 58 | return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR; | 59 | return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR; |
| 59 | } | 60 | } |
| 60 | 61 | ||
| 61 | static cycle_t read_cycles(struct clocksource *cs) | 62 | static cycle_t bfin_read_cycles(struct clocksource *cs) |
| 62 | { | 63 | { |
| 63 | return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod); | 64 | return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod); |
| 64 | } | 65 | } |
| 65 | 66 | ||
| 66 | static struct clocksource clocksource_bfin = { | 67 | static struct clocksource bfin_cs_cycles = { |
| 67 | .name = "bfin_cycles", | 68 | .name = "bfin_cs_cycles", |
| 68 | .rating = 350, | 69 | .rating = 350, |
| 69 | .read = read_cycles, | 70 | .read = bfin_read_cycles, |
| 70 | .mask = CLOCKSOURCE_MASK(64), | 71 | .mask = CLOCKSOURCE_MASK(64), |
| 71 | .shift = 22, | 72 | .shift = 22, |
| 72 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 73 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| @@ -74,53 +75,198 @@ static struct clocksource clocksource_bfin = { | |||
| 74 | 75 | ||
| 75 | unsigned long long sched_clock(void) | 76 | unsigned long long sched_clock(void) |
| 76 | { | 77 | { |
| 77 | return cycles_2_ns(read_cycles(&clocksource_bfin)); | 78 | return cycles_2_ns(bfin_read_cycles(&bfin_cs_cycles)); |
| 78 | } | 79 | } |
| 79 | 80 | ||
| 80 | static int __init bfin_clocksource_init(void) | 81 | static int __init bfin_cs_cycles_init(void) |
| 81 | { | 82 | { |
| 82 | set_cyc2ns_scale(get_cclk() / 1000); | 83 | set_cyc2ns_scale(get_cclk() / 1000); |
| 83 | 84 | ||
| 84 | clocksource_bfin.mult = clocksource_hz2mult(get_cclk(), clocksource_bfin.shift); | 85 | bfin_cs_cycles.mult = \ |
| 86 | clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift); | ||
| 85 | 87 | ||
| 86 | if (clocksource_register(&clocksource_bfin)) | 88 | if (clocksource_register(&bfin_cs_cycles)) |
| 87 | panic("failed to register clocksource"); | 89 | panic("failed to register clocksource"); |
| 88 | 90 | ||
| 89 | return 0; | 91 | return 0; |
| 90 | } | 92 | } |
| 93 | #else | ||
| 94 | # define bfin_cs_cycles_init() | ||
| 95 | #endif | ||
| 96 | |||
| 97 | #ifdef CONFIG_GPTMR0_CLOCKSOURCE | ||
| 98 | |||
| 99 | void __init setup_gptimer0(void) | ||
| 100 | { | ||
| 101 | disable_gptimers(TIMER0bit); | ||
| 102 | |||
| 103 | set_gptimer_config(TIMER0_id, \ | ||
| 104 | TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM); | ||
| 105 | set_gptimer_period(TIMER0_id, -1); | ||
| 106 | set_gptimer_pwidth(TIMER0_id, -2); | ||
| 107 | SSYNC(); | ||
| 108 | enable_gptimers(TIMER0bit); | ||
| 109 | } | ||
| 110 | |||
| 111 | static cycle_t bfin_read_gptimer0(void) | ||
| 112 | { | ||
| 113 | return bfin_read_TIMER0_COUNTER(); | ||
| 114 | } | ||
| 115 | |||
| 116 | static struct clocksource bfin_cs_gptimer0 = { | ||
| 117 | .name = "bfin_cs_gptimer0", | ||
| 118 | .rating = 400, | ||
| 119 | .read = bfin_read_gptimer0, | ||
| 120 | .mask = CLOCKSOURCE_MASK(32), | ||
| 121 | .shift = 22, | ||
| 122 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 123 | }; | ||
| 124 | |||
| 125 | static int __init bfin_cs_gptimer0_init(void) | ||
| 126 | { | ||
| 127 | setup_gptimer0(); | ||
| 91 | 128 | ||
| 129 | bfin_cs_gptimer0.mult = \ | ||
| 130 | clocksource_hz2mult(get_sclk(), bfin_cs_gptimer0.shift); | ||
| 131 | |||
| 132 | if (clocksource_register(&bfin_cs_gptimer0)) | ||
| 133 | panic("failed to register clocksource"); | ||
| 134 | |||
| 135 | return 0; | ||
| 136 | } | ||
| 92 | #else | 137 | #else |
| 93 | # define bfin_clocksource_init() | 138 | # define bfin_cs_gptimer0_init() |
| 94 | #endif | 139 | #endif |
| 95 | 140 | ||
| 141 | #ifdef CONFIG_CORE_TIMER_IRQ_L1 | ||
| 142 | __attribute__((l1_text)) | ||
| 143 | #endif | ||
| 144 | irqreturn_t timer_interrupt(int irq, void *dev_id); | ||
| 145 | |||
| 146 | static int bfin_timer_set_next_event(unsigned long, \ | ||
| 147 | struct clock_event_device *); | ||
| 148 | |||
| 149 | static void bfin_timer_set_mode(enum clock_event_mode, \ | ||
| 150 | struct clock_event_device *); | ||
| 151 | |||
| 152 | static struct clock_event_device clockevent_bfin = { | ||
| 153 | #if defined(CONFIG_TICKSOURCE_GPTMR0) | ||
| 154 | .name = "bfin_gptimer0", | ||
| 155 | .rating = 300, | ||
| 156 | .irq = IRQ_TIMER0, | ||
| 157 | #else | ||
| 158 | .name = "bfin_core_timer", | ||
| 159 | .rating = 350, | ||
| 160 | .irq = IRQ_CORETMR, | ||
| 161 | #endif | ||
| 162 | .shift = 32, | ||
| 163 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | ||
| 164 | .set_next_event = bfin_timer_set_next_event, | ||
| 165 | .set_mode = bfin_timer_set_mode, | ||
| 166 | }; | ||
| 167 | |||
| 168 | static struct irqaction bfin_timer_irq = { | ||
| 169 | #if defined(CONFIG_TICKSOURCE_GPTMR0) | ||
| 170 | .name = "Blackfin GPTimer0", | ||
| 171 | #else | ||
| 172 | .name = "Blackfin CoreTimer", | ||
| 173 | #endif | ||
| 174 | .flags = IRQF_DISABLED | IRQF_TIMER | \ | ||
| 175 | IRQF_IRQPOLL | IRQF_PERCPU, | ||
| 176 | .handler = timer_interrupt, | ||
| 177 | .dev_id = &clockevent_bfin, | ||
| 178 | }; | ||
| 179 | |||
| 180 | #if defined(CONFIG_TICKSOURCE_GPTMR0) | ||
| 96 | static int bfin_timer_set_next_event(unsigned long cycles, | 181 | static int bfin_timer_set_next_event(unsigned long cycles, |
| 97 | struct clock_event_device *evt) | 182 | struct clock_event_device *evt) |
| 98 | { | 183 | { |
| 184 | disable_gptimers(TIMER0bit); | ||
| 185 | |||
| 186 | /* it starts counting three SCLK cycles after the TIMENx bit is set */ | ||
| 187 | set_gptimer_pwidth(TIMER0_id, cycles - 3); | ||
| 188 | enable_gptimers(TIMER0bit); | ||
| 189 | return 0; | ||
| 190 | } | ||
| 191 | |||
| 192 | static void bfin_timer_set_mode(enum clock_event_mode mode, | ||
| 193 | struct clock_event_device *evt) | ||
| 194 | { | ||
| 195 | switch (mode) { | ||
| 196 | case CLOCK_EVT_MODE_PERIODIC: { | ||
| 197 | set_gptimer_config(TIMER0_id, \ | ||
| 198 | TIMER_OUT_DIS | TIMER_IRQ_ENA | \ | ||
| 199 | TIMER_PERIOD_CNT | TIMER_MODE_PWM); | ||
| 200 | set_gptimer_period(TIMER0_id, get_sclk() / HZ); | ||
| 201 | set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1); | ||
| 202 | enable_gptimers(TIMER0bit); | ||
| 203 | break; | ||
| 204 | } | ||
| 205 | case CLOCK_EVT_MODE_ONESHOT: | ||
| 206 | disable_gptimers(TIMER0bit); | ||
| 207 | set_gptimer_config(TIMER0_id, \ | ||
| 208 | TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM); | ||
| 209 | set_gptimer_period(TIMER0_id, 0); | ||
| 210 | break; | ||
| 211 | case CLOCK_EVT_MODE_UNUSED: | ||
| 212 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
| 213 | disable_gptimers(TIMER0bit); | ||
| 214 | break; | ||
| 215 | case CLOCK_EVT_MODE_RESUME: | ||
| 216 | break; | ||
| 217 | } | ||
| 218 | } | ||
| 219 | |||
| 220 | static void bfin_timer_ack(void) | ||
| 221 | { | ||
| 222 | set_gptimer_status(TIMER_GROUP1, TIMER_STATUS_TIMIL0); | ||
| 223 | } | ||
| 224 | |||
| 225 | static void __init bfin_timer_init(void) | ||
| 226 | { | ||
| 227 | disable_gptimers(TIMER0bit); | ||
| 228 | } | ||
| 229 | |||
| 230 | static unsigned long __init bfin_clockevent_check(void) | ||
| 231 | { | ||
| 232 | setup_irq(IRQ_TIMER0, &bfin_timer_irq); | ||
| 233 | return get_sclk(); | ||
| 234 | } | ||
| 235 | |||
| 236 | #else /* CONFIG_TICKSOURCE_CORETMR */ | ||
| 237 | |||
| 238 | static int bfin_timer_set_next_event(unsigned long cycles, | ||
| 239 | struct clock_event_device *evt) | ||
| 240 | { | ||
| 241 | bfin_write_TCNTL(TMPWR); | ||
| 242 | CSYNC(); | ||
| 99 | bfin_write_TCOUNT(cycles); | 243 | bfin_write_TCOUNT(cycles); |
| 100 | CSYNC(); | 244 | CSYNC(); |
| 245 | bfin_write_TCNTL(TMPWR | TMREN); | ||
| 101 | return 0; | 246 | return 0; |
| 102 | } | 247 | } |
| 103 | 248 | ||
| 104 | static void bfin_timer_set_mode(enum clock_event_mode mode, | 249 | static void bfin_timer_set_mode(enum clock_event_mode mode, |
| 105 | struct clock_event_device *evt) | 250 | struct clock_event_device *evt) |
| 106 | { | 251 | { |
| 107 | switch (mode) { | 252 | switch (mode) { |
| 108 | case CLOCK_EVT_MODE_PERIODIC: { | 253 | case CLOCK_EVT_MODE_PERIODIC: { |
| 109 | unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1); | 254 | unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1); |
| 110 | bfin_write_TCNTL(TMPWR); | 255 | bfin_write_TCNTL(TMPWR); |
| 111 | bfin_write_TSCALE(TIME_SCALE - 1); | ||
| 112 | CSYNC(); | 256 | CSYNC(); |
| 257 | bfin_write_TSCALE(TIME_SCALE - 1); | ||
| 113 | bfin_write_TPERIOD(tcount); | 258 | bfin_write_TPERIOD(tcount); |
| 114 | bfin_write_TCOUNT(tcount); | 259 | bfin_write_TCOUNT(tcount); |
| 115 | bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD); | ||
| 116 | CSYNC(); | 260 | CSYNC(); |
| 261 | bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD); | ||
| 117 | break; | 262 | break; |
| 118 | } | 263 | } |
| 119 | case CLOCK_EVT_MODE_ONESHOT: | 264 | case CLOCK_EVT_MODE_ONESHOT: |
| 265 | bfin_write_TCNTL(TMPWR); | ||
| 266 | CSYNC(); | ||
| 120 | bfin_write_TSCALE(TIME_SCALE - 1); | 267 | bfin_write_TSCALE(TIME_SCALE - 1); |
| 268 | bfin_write_TPERIOD(0); | ||
| 121 | bfin_write_TCOUNT(0); | 269 | bfin_write_TCOUNT(0); |
| 122 | bfin_write_TCNTL(TMPWR | TMREN); | ||
| 123 | CSYNC(); | ||
| 124 | break; | 270 | break; |
| 125 | case CLOCK_EVT_MODE_UNUSED: | 271 | case CLOCK_EVT_MODE_UNUSED: |
| 126 | case CLOCK_EVT_MODE_SHUTDOWN: | 272 | case CLOCK_EVT_MODE_SHUTDOWN: |
| @@ -132,6 +278,10 @@ static void bfin_timer_set_mode(enum clock_event_mode mode, | |||
| 132 | } | 278 | } |
| 133 | } | 279 | } |
| 134 | 280 | ||
| 281 | static void bfin_timer_ack(void) | ||
| 282 | { | ||
| 283 | } | ||
| 284 | |||
| 135 | static void __init bfin_timer_init(void) | 285 | static void __init bfin_timer_init(void) |
| 136 | { | 286 | { |
| 137 | /* power up the timer, but don't enable it just yet */ | 287 | /* power up the timer, but don't enable it just yet */ |
| @@ -145,38 +295,32 @@ static void __init bfin_timer_init(void) | |||
| 145 | bfin_write_TPERIOD(0); | 295 | bfin_write_TPERIOD(0); |
| 146 | bfin_write_TCOUNT(0); | 296 | bfin_write_TCOUNT(0); |
| 147 | 297 | ||
| 148 | /* now enable the timer */ | ||
| 149 | CSYNC(); | 298 | CSYNC(); |
| 150 | } | 299 | } |
| 151 | 300 | ||
| 301 | static unsigned long __init bfin_clockevent_check(void) | ||
| 302 | { | ||
| 303 | setup_irq(IRQ_CORETMR, &bfin_timer_irq); | ||
| 304 | return get_cclk() / TIME_SCALE; | ||
| 305 | } | ||
| 306 | |||
| 307 | void __init setup_core_timer(void) | ||
| 308 | { | ||
| 309 | bfin_timer_init(); | ||
| 310 | bfin_timer_set_mode(CLOCK_EVT_MODE_PERIODIC, NULL); | ||
| 311 | } | ||
| 312 | #endif /* CONFIG_TICKSOURCE_GPTMR0 */ | ||
| 313 | |||
| 152 | /* | 314 | /* |
| 153 | * timer_interrupt() needs to keep up the real-time clock, | 315 | * timer_interrupt() needs to keep up the real-time clock, |
| 154 | * as well as call the "do_timer()" routine every clocktick | 316 | * as well as call the "do_timer()" routine every clocktick |
| 155 | */ | 317 | */ |
| 156 | #ifdef CONFIG_CORE_TIMER_IRQ_L1 | ||
| 157 | __attribute__((l1_text)) | ||
| 158 | #endif | ||
| 159 | irqreturn_t timer_interrupt(int irq, void *dev_id); | ||
| 160 | |||
| 161 | static struct clock_event_device clockevent_bfin = { | ||
| 162 | .name = "bfin_core_timer", | ||
| 163 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | ||
| 164 | .shift = 32, | ||
| 165 | .set_next_event = bfin_timer_set_next_event, | ||
| 166 | .set_mode = bfin_timer_set_mode, | ||
| 167 | }; | ||
| 168 | |||
| 169 | static struct irqaction bfin_timer_irq = { | ||
| 170 | .name = "Blackfin Core Timer", | ||
| 171 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
| 172 | .handler = timer_interrupt, | ||
| 173 | .dev_id = &clockevent_bfin, | ||
| 174 | }; | ||
| 175 | |||
| 176 | irqreturn_t timer_interrupt(int irq, void *dev_id) | 318 | irqreturn_t timer_interrupt(int irq, void *dev_id) |
| 177 | { | 319 | { |
| 178 | struct clock_event_device *evt = dev_id; | 320 | struct clock_event_device *evt = dev_id; |
| 321 | smp_mb(); | ||
| 179 | evt->event_handler(evt); | 322 | evt->event_handler(evt); |
| 323 | bfin_timer_ack(); | ||
| 180 | return IRQ_HANDLED; | 324 | return IRQ_HANDLED; |
| 181 | } | 325 | } |
| 182 | 326 | ||
| @@ -184,9 +328,8 @@ static int __init bfin_clockevent_init(void) | |||
| 184 | { | 328 | { |
| 185 | unsigned long timer_clk; | 329 | unsigned long timer_clk; |
| 186 | 330 | ||
| 187 | timer_clk = get_cclk() / TIME_SCALE; | 331 | timer_clk = bfin_clockevent_check(); |
| 188 | 332 | ||
| 189 | setup_irq(IRQ_CORETMR, &bfin_timer_irq); | ||
| 190 | bfin_timer_init(); | 333 | bfin_timer_init(); |
| 191 | 334 | ||
| 192 | clockevent_bfin.mult = div_sc(timer_clk, NSEC_PER_SEC, clockevent_bfin.shift); | 335 | clockevent_bfin.mult = div_sc(timer_clk, NSEC_PER_SEC, clockevent_bfin.shift); |
| @@ -218,6 +361,7 @@ void __init time_init(void) | |||
| 218 | xtime.tv_nsec = 0; | 361 | xtime.tv_nsec = 0; |
| 219 | set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec); | 362 | set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec); |
| 220 | 363 | ||
| 221 | bfin_clocksource_init(); | 364 | bfin_cs_cycles_init(); |
| 365 | bfin_cs_gptimer0_init(); | ||
| 222 | bfin_clockevent_init(); | 366 | bfin_clockevent_init(); |
| 223 | } | 367 | } |
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c index 1bbacfbd4c5d..adb54aa7d7c8 100644 --- a/arch/blackfin/kernel/time.c +++ b/arch/blackfin/kernel/time.c | |||
| @@ -24,14 +24,10 @@ | |||
| 24 | 24 | ||
| 25 | static struct irqaction bfin_timer_irq = { | 25 | static struct irqaction bfin_timer_irq = { |
| 26 | .name = "Blackfin Timer Tick", | 26 | .name = "Blackfin Timer Tick", |
| 27 | #ifdef CONFIG_IRQ_PER_CPU | ||
| 28 | .flags = IRQF_DISABLED | IRQF_PERCPU, | ||
| 29 | #else | ||
| 30 | .flags = IRQF_DISABLED | 27 | .flags = IRQF_DISABLED |
| 31 | #endif | ||
| 32 | }; | 28 | }; |
| 33 | 29 | ||
| 34 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) | 30 | #if defined(CONFIG_IPIPE) |
| 35 | void __init setup_system_timer0(void) | 31 | void __init setup_system_timer0(void) |
| 36 | { | 32 | { |
| 37 | /* Power down the core timer, just to play safe. */ | 33 | /* Power down the core timer, just to play safe. */ |
| @@ -74,7 +70,7 @@ void __init setup_core_timer(void) | |||
| 74 | static void __init | 70 | static void __init |
| 75 | time_sched_init(irqreturn_t(*timer_routine) (int, void *)) | 71 | time_sched_init(irqreturn_t(*timer_routine) (int, void *)) |
| 76 | { | 72 | { |
| 77 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) | 73 | #if defined(CONFIG_IPIPE) |
| 78 | setup_system_timer0(); | 74 | setup_system_timer0(); |
| 79 | bfin_timer_irq.handler = timer_routine; | 75 | bfin_timer_irq.handler = timer_routine; |
| 80 | setup_irq(IRQ_TIMER0, &bfin_timer_irq); | 76 | setup_irq(IRQ_TIMER0, &bfin_timer_irq); |
| @@ -94,7 +90,7 @@ static unsigned long gettimeoffset(void) | |||
| 94 | unsigned long offset; | 90 | unsigned long offset; |
| 95 | unsigned long clocks_per_jiffy; | 91 | unsigned long clocks_per_jiffy; |
| 96 | 92 | ||
| 97 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) | 93 | #if defined(CONFIG_IPIPE) |
| 98 | clocks_per_jiffy = bfin_read_TIMER0_PERIOD(); | 94 | clocks_per_jiffy = bfin_read_TIMER0_PERIOD(); |
| 99 | offset = bfin_read_TIMER0_COUNTER() / \ | 95 | offset = bfin_read_TIMER0_COUNTER() / \ |
| 100 | (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC); | 96 | (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC); |
| @@ -133,36 +129,25 @@ irqreturn_t timer_interrupt(int irq, void *dummy) | |||
| 133 | static long last_rtc_update; | 129 | static long last_rtc_update; |
| 134 | 130 | ||
| 135 | write_seqlock(&xtime_lock); | 131 | write_seqlock(&xtime_lock); |
| 136 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE) | 132 | do_timer(1); |
| 133 | |||
| 137 | /* | 134 | /* |
| 138 | * TIMIL0 is latched in __ipipe_grab_irq() when the I-Pipe is | 135 | * If we have an externally synchronized Linux clock, then update |
| 139 | * enabled. | 136 | * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be |
| 137 | * called as close as possible to 500 ms before the new second starts. | ||
| 140 | */ | 138 | */ |
| 141 | if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) { | 139 | if (ntp_synced() && |
| 142 | #endif | 140 | xtime.tv_sec > last_rtc_update + 660 && |
| 143 | do_timer(1); | 141 | (xtime.tv_nsec / NSEC_PER_USEC) >= |
| 144 | 142 | 500000 - ((unsigned)TICK_SIZE) / 2 | |
| 145 | /* | 143 | && (xtime.tv_nsec / NSEC_PER_USEC) <= |
| 146 | * If we have an externally synchronized Linux clock, then update | 144 | 500000 + ((unsigned)TICK_SIZE) / 2) { |
| 147 | * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be | 145 | if (set_rtc_mmss(xtime.tv_sec) == 0) |
| 148 | * called as close as possible to 500 ms before the new second starts. | 146 | last_rtc_update = xtime.tv_sec; |
| 149 | */ | 147 | else |
| 150 | if (ntp_synced() && | 148 | /* Do it again in 60s. */ |
| 151 | xtime.tv_sec > last_rtc_update + 660 && | 149 | last_rtc_update = xtime.tv_sec - 600; |
| 152 | (xtime.tv_nsec / NSEC_PER_USEC) >= | ||
| 153 | 500000 - ((unsigned)TICK_SIZE) / 2 | ||
| 154 | && (xtime.tv_nsec / NSEC_PER_USEC) <= | ||
| 155 | 500000 + ((unsigned)TICK_SIZE) / 2) { | ||
| 156 | if (set_rtc_mmss(xtime.tv_sec) == 0) | ||
| 157 | last_rtc_update = xtime.tv_sec; | ||
| 158 | else | ||
| 159 | /* Do it again in 60s. */ | ||
| 160 | last_rtc_update = xtime.tv_sec - 600; | ||
| 161 | } | ||
| 162 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE) | ||
| 163 | set_gptimer_status(0, TIMER_STATUS_TIMIL0); | ||
| 164 | } | 150 | } |
| 165 | #endif | ||
| 166 | write_sequnlock(&xtime_lock); | 151 | write_sequnlock(&xtime_lock); |
| 167 | 152 | ||
| 168 | #ifdef CONFIG_IPIPE | 153 | #ifdef CONFIG_IPIPE |
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index ffe7fb53eccb..d279552fe9b0 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 28 | */ | 28 | */ |
| 29 | 29 | ||
| 30 | #include <linux/bug.h> | ||
| 30 | #include <linux/uaccess.h> | 31 | #include <linux/uaccess.h> |
| 31 | #include <linux/interrupt.h> | 32 | #include <linux/interrupt.h> |
| 32 | #include <linux/module.h> | 33 | #include <linux/module.h> |
| @@ -68,6 +69,13 @@ | |||
| 68 | ({ if (0) printk(fmt, ##arg); 0; }) | 69 | ({ if (0) printk(fmt, ##arg); 0; }) |
| 69 | #endif | 70 | #endif |
| 70 | 71 | ||
| 72 | #if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE) | ||
| 73 | u32 last_seqstat; | ||
| 74 | #ifdef CONFIG_DEBUG_MMRS_MODULE | ||
| 75 | EXPORT_SYMBOL(last_seqstat); | ||
| 76 | #endif | ||
| 77 | #endif | ||
| 78 | |||
| 71 | /* Initiate the event table handler */ | 79 | /* Initiate the event table handler */ |
| 72 | void __init trap_init(void) | 80 | void __init trap_init(void) |
| 73 | { | 81 | { |
| @@ -79,7 +87,6 @@ void __init trap_init(void) | |||
| 79 | static void decode_address(char *buf, unsigned long address) | 87 | static void decode_address(char *buf, unsigned long address) |
| 80 | { | 88 | { |
| 81 | #ifdef CONFIG_DEBUG_VERBOSE | 89 | #ifdef CONFIG_DEBUG_VERBOSE |
| 82 | struct vm_list_struct *vml; | ||
| 83 | struct task_struct *p; | 90 | struct task_struct *p; |
| 84 | struct mm_struct *mm; | 91 | struct mm_struct *mm; |
| 85 | unsigned long flags, offset; | 92 | unsigned long flags, offset; |
| @@ -196,6 +203,11 @@ done: | |||
| 196 | 203 | ||
| 197 | asmlinkage void double_fault_c(struct pt_regs *fp) | 204 | asmlinkage void double_fault_c(struct pt_regs *fp) |
| 198 | { | 205 | { |
| 206 | #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON | ||
| 207 | int j; | ||
| 208 | trace_buffer_save(j); | ||
| 209 | #endif | ||
| 210 | |||
| 199 | console_verbose(); | 211 | console_verbose(); |
| 200 | oops_in_progress = 1; | 212 | oops_in_progress = 1; |
| 201 | #ifdef CONFIG_DEBUG_VERBOSE | 213 | #ifdef CONFIG_DEBUG_VERBOSE |
| @@ -220,10 +232,16 @@ asmlinkage void double_fault_c(struct pt_regs *fp) | |||
| 220 | dump_bfin_process(fp); | 232 | dump_bfin_process(fp); |
| 221 | dump_bfin_mem(fp); | 233 | dump_bfin_mem(fp); |
| 222 | show_regs(fp); | 234 | show_regs(fp); |
| 235 | dump_bfin_trace_buffer(); | ||
| 223 | } | 236 | } |
| 224 | #endif | 237 | #endif |
| 225 | panic("Double Fault - unrecoverable event\n"); | 238 | panic("Double Fault - unrecoverable event"); |
| 239 | |||
| 240 | } | ||
| 226 | 241 | ||
| 242 | static int kernel_mode_regs(struct pt_regs *regs) | ||
| 243 | { | ||
| 244 | return regs->ipend & 0xffc0; | ||
| 227 | } | 245 | } |
| 228 | 246 | ||
| 229 | asmlinkage void trap_c(struct pt_regs *fp) | 247 | asmlinkage void trap_c(struct pt_regs *fp) |
| @@ -234,37 +252,24 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 234 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO | 252 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO |
| 235 | unsigned int cpu = smp_processor_id(); | 253 | unsigned int cpu = smp_processor_id(); |
| 236 | #endif | 254 | #endif |
| 255 | const char *strerror = NULL; | ||
| 237 | int sig = 0; | 256 | int sig = 0; |
| 238 | siginfo_t info; | 257 | siginfo_t info; |
| 239 | unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE; | 258 | unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE; |
| 240 | 259 | ||
| 241 | trace_buffer_save(j); | 260 | trace_buffer_save(j); |
| 261 | #if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE) | ||
| 262 | last_seqstat = (u32)fp->seqstat; | ||
| 263 | #endif | ||
| 242 | 264 | ||
| 243 | /* Important - be very careful dereferncing pointers - will lead to | 265 | /* Important - be very careful dereferncing pointers - will lead to |
| 244 | * double faults if the stack has become corrupt | 266 | * double faults if the stack has become corrupt |
| 245 | */ | 267 | */ |
| 246 | 268 | ||
| 247 | /* If the fault was caused by a kernel thread, or interrupt handler | 269 | #ifndef CONFIG_KGDB |
| 248 | * we will kernel panic, so the system reboots. | 270 | /* IPEND is skipped if KGDB isn't enabled (see entry code) */ |
| 249 | * If KGDB is enabled, don't set this for kernel breakpoints | 271 | fp->ipend = bfin_read_IPEND(); |
| 250 | */ | ||
| 251 | |||
| 252 | /* TODO: check to see if we are in some sort of deferred HWERR | ||
| 253 | * that we should be able to recover from, not kernel panic | ||
| 254 | */ | ||
| 255 | if ((bfin_read_IPEND() & 0xFFC0) && (trapnr != VEC_STEP) | ||
| 256 | #ifdef CONFIG_KGDB | ||
| 257 | && (trapnr != VEC_EXCPT02) | ||
| 258 | #endif | 272 | #endif |
| 259 | ){ | ||
| 260 | console_verbose(); | ||
| 261 | oops_in_progress = 1; | ||
| 262 | } else if (current) { | ||
| 263 | if (current->mm == NULL) { | ||
| 264 | console_verbose(); | ||
| 265 | oops_in_progress = 1; | ||
| 266 | } | ||
| 267 | } | ||
| 268 | 273 | ||
| 269 | /* trap_c() will be called for exceptions. During exceptions | 274 | /* trap_c() will be called for exceptions. During exceptions |
| 270 | * processing, the pc value should be set with retx value. | 275 | * processing, the pc value should be set with retx value. |
| @@ -292,15 +297,15 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 292 | sig = SIGTRAP; | 297 | sig = SIGTRAP; |
| 293 | CHK_DEBUGGER_TRAP_MAYBE(); | 298 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 294 | /* Check if this is a breakpoint in kernel space */ | 299 | /* Check if this is a breakpoint in kernel space */ |
| 295 | if (fp->ipend & 0xffc0) | 300 | if (kernel_mode_regs(fp)) |
| 296 | return; | 301 | goto traps_done; |
| 297 | else | 302 | else |
| 298 | break; | 303 | break; |
| 299 | /* 0x03 - User Defined, userspace stack overflow */ | 304 | /* 0x03 - User Defined, userspace stack overflow */ |
| 300 | case VEC_EXCPT03: | 305 | case VEC_EXCPT03: |
| 301 | info.si_code = SEGV_STACKFLOW; | 306 | info.si_code = SEGV_STACKFLOW; |
| 302 | sig = SIGSEGV; | 307 | sig = SIGSEGV; |
| 303 | verbose_printk(KERN_NOTICE EXC_0x03(KERN_NOTICE)); | 308 | strerror = KERN_NOTICE EXC_0x03(KERN_NOTICE); |
| 304 | CHK_DEBUGGER_TRAP_MAYBE(); | 309 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 305 | break; | 310 | break; |
| 306 | /* 0x02 - KGDB initial connection and break signal trap */ | 311 | /* 0x02 - KGDB initial connection and break signal trap */ |
| @@ -309,7 +314,7 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 309 | info.si_code = TRAP_ILLTRAP; | 314 | info.si_code = TRAP_ILLTRAP; |
| 310 | sig = SIGTRAP; | 315 | sig = SIGTRAP; |
| 311 | CHK_DEBUGGER_TRAP(); | 316 | CHK_DEBUGGER_TRAP(); |
| 312 | return; | 317 | goto traps_done; |
| 313 | #endif | 318 | #endif |
| 314 | /* 0x04 - User Defined */ | 319 | /* 0x04 - User Defined */ |
| 315 | /* 0x05 - User Defined */ | 320 | /* 0x05 - User Defined */ |
| @@ -329,7 +334,7 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 329 | case VEC_EXCPT04 ... VEC_EXCPT15: | 334 | case VEC_EXCPT04 ... VEC_EXCPT15: |
| 330 | info.si_code = ILL_ILLPARAOP; | 335 | info.si_code = ILL_ILLPARAOP; |
| 331 | sig = SIGILL; | 336 | sig = SIGILL; |
| 332 | verbose_printk(KERN_NOTICE EXC_0x04(KERN_NOTICE)); | 337 | strerror = KERN_NOTICE EXC_0x04(KERN_NOTICE); |
| 333 | CHK_DEBUGGER_TRAP_MAYBE(); | 338 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 334 | break; | 339 | break; |
| 335 | /* 0x10 HW Single step, handled here */ | 340 | /* 0x10 HW Single step, handled here */ |
| @@ -338,15 +343,15 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 338 | sig = SIGTRAP; | 343 | sig = SIGTRAP; |
| 339 | CHK_DEBUGGER_TRAP_MAYBE(); | 344 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 340 | /* Check if this is a single step in kernel space */ | 345 | /* Check if this is a single step in kernel space */ |
| 341 | if (fp->ipend & 0xffc0) | 346 | if (kernel_mode_regs(fp)) |
| 342 | return; | 347 | goto traps_done; |
| 343 | else | 348 | else |
| 344 | break; | 349 | break; |
| 345 | /* 0x11 - Trace Buffer Full, handled here */ | 350 | /* 0x11 - Trace Buffer Full, handled here */ |
| 346 | case VEC_OVFLOW: | 351 | case VEC_OVFLOW: |
| 347 | info.si_code = TRAP_TRACEFLOW; | 352 | info.si_code = TRAP_TRACEFLOW; |
| 348 | sig = SIGTRAP; | 353 | sig = SIGTRAP; |
| 349 | verbose_printk(KERN_NOTICE EXC_0x11(KERN_NOTICE)); | 354 | strerror = KERN_NOTICE EXC_0x11(KERN_NOTICE); |
| 350 | CHK_DEBUGGER_TRAP_MAYBE(); | 355 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 351 | break; | 356 | break; |
| 352 | /* 0x12 - Reserved, Caught by default */ | 357 | /* 0x12 - Reserved, Caught by default */ |
| @@ -366,37 +371,54 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 366 | /* 0x20 - Reserved, Caught by default */ | 371 | /* 0x20 - Reserved, Caught by default */ |
| 367 | /* 0x21 - Undefined Instruction, handled here */ | 372 | /* 0x21 - Undefined Instruction, handled here */ |
| 368 | case VEC_UNDEF_I: | 373 | case VEC_UNDEF_I: |
| 374 | #ifdef CONFIG_BUG | ||
| 375 | if (kernel_mode_regs(fp)) { | ||
| 376 | switch (report_bug(fp->pc, fp)) { | ||
| 377 | case BUG_TRAP_TYPE_NONE: | ||
| 378 | break; | ||
| 379 | case BUG_TRAP_TYPE_WARN: | ||
| 380 | dump_bfin_trace_buffer(); | ||
| 381 | fp->pc += 2; | ||
| 382 | goto traps_done; | ||
| 383 | case BUG_TRAP_TYPE_BUG: | ||
| 384 | /* call to panic() will dump trace, and it is | ||
| 385 | * off at this point, so it won't be clobbered | ||
| 386 | */ | ||
| 387 | panic("BUG()"); | ||
| 388 | } | ||
| 389 | } | ||
| 390 | #endif | ||
| 369 | info.si_code = ILL_ILLOPC; | 391 | info.si_code = ILL_ILLOPC; |
| 370 | sig = SIGILL; | 392 | sig = SIGILL; |
| 371 | verbose_printk(KERN_NOTICE EXC_0x21(KERN_NOTICE)); | 393 | strerror = KERN_NOTICE EXC_0x21(KERN_NOTICE); |
| 372 | CHK_DEBUGGER_TRAP_MAYBE(); | 394 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 373 | break; | 395 | break; |
| 374 | /* 0x22 - Illegal Instruction Combination, handled here */ | 396 | /* 0x22 - Illegal Instruction Combination, handled here */ |
| 375 | case VEC_ILGAL_I: | 397 | case VEC_ILGAL_I: |
| 376 | info.si_code = ILL_ILLPARAOP; | 398 | info.si_code = ILL_ILLPARAOP; |
| 377 | sig = SIGILL; | 399 | sig = SIGILL; |
| 378 | verbose_printk(KERN_NOTICE EXC_0x22(KERN_NOTICE)); | 400 | strerror = KERN_NOTICE EXC_0x22(KERN_NOTICE); |
| 379 | CHK_DEBUGGER_TRAP_MAYBE(); | 401 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 380 | break; | 402 | break; |
| 381 | /* 0x23 - Data CPLB protection violation, handled here */ | 403 | /* 0x23 - Data CPLB protection violation, handled here */ |
| 382 | case VEC_CPLB_VL: | 404 | case VEC_CPLB_VL: |
| 383 | info.si_code = ILL_CPLB_VI; | 405 | info.si_code = ILL_CPLB_VI; |
| 384 | sig = SIGBUS; | 406 | sig = SIGBUS; |
| 385 | verbose_printk(KERN_NOTICE EXC_0x23(KERN_NOTICE)); | 407 | strerror = KERN_NOTICE EXC_0x23(KERN_NOTICE); |
| 386 | CHK_DEBUGGER_TRAP_MAYBE(); | 408 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 387 | break; | 409 | break; |
| 388 | /* 0x24 - Data access misaligned, handled here */ | 410 | /* 0x24 - Data access misaligned, handled here */ |
| 389 | case VEC_MISALI_D: | 411 | case VEC_MISALI_D: |
| 390 | info.si_code = BUS_ADRALN; | 412 | info.si_code = BUS_ADRALN; |
| 391 | sig = SIGBUS; | 413 | sig = SIGBUS; |
| 392 | verbose_printk(KERN_NOTICE EXC_0x24(KERN_NOTICE)); | 414 | strerror = KERN_NOTICE EXC_0x24(KERN_NOTICE); |
| 393 | CHK_DEBUGGER_TRAP_MAYBE(); | 415 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 394 | break; | 416 | break; |
| 395 | /* 0x25 - Unrecoverable Event, handled here */ | 417 | /* 0x25 - Unrecoverable Event, handled here */ |
| 396 | case VEC_UNCOV: | 418 | case VEC_UNCOV: |
| 397 | info.si_code = ILL_ILLEXCPT; | 419 | info.si_code = ILL_ILLEXCPT; |
| 398 | sig = SIGILL; | 420 | sig = SIGILL; |
| 399 | verbose_printk(KERN_NOTICE EXC_0x25(KERN_NOTICE)); | 421 | strerror = KERN_NOTICE EXC_0x25(KERN_NOTICE); |
| 400 | CHK_DEBUGGER_TRAP_MAYBE(); | 422 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 401 | break; | 423 | break; |
| 402 | /* 0x26 - Data CPLB Miss, normal case is handled in _cplb_hdr, | 424 | /* 0x26 - Data CPLB Miss, normal case is handled in _cplb_hdr, |
| @@ -404,7 +426,7 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 404 | case VEC_CPLB_M: | 426 | case VEC_CPLB_M: |
| 405 | info.si_code = BUS_ADRALN; | 427 | info.si_code = BUS_ADRALN; |
| 406 | sig = SIGBUS; | 428 | sig = SIGBUS; |
| 407 | verbose_printk(KERN_NOTICE EXC_0x26(KERN_NOTICE)); | 429 | strerror = KERN_NOTICE EXC_0x26(KERN_NOTICE); |
| 408 | break; | 430 | break; |
| 409 | /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero, handled here */ | 431 | /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero, handled here */ |
| 410 | case VEC_CPLB_MHIT: | 432 | case VEC_CPLB_MHIT: |
| @@ -412,10 +434,10 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 412 | sig = SIGSEGV; | 434 | sig = SIGSEGV; |
| 413 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO | 435 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO |
| 414 | if (cpu_pda[cpu].dcplb_fault_addr < FIXED_CODE_START) | 436 | if (cpu_pda[cpu].dcplb_fault_addr < FIXED_CODE_START) |
| 415 | verbose_printk(KERN_NOTICE "NULL pointer access\n"); | 437 | strerror = KERN_NOTICE "NULL pointer access\n"; |
| 416 | else | 438 | else |
| 417 | #endif | 439 | #endif |
| 418 | verbose_printk(KERN_NOTICE EXC_0x27(KERN_NOTICE)); | 440 | strerror = KERN_NOTICE EXC_0x27(KERN_NOTICE); |
| 419 | CHK_DEBUGGER_TRAP_MAYBE(); | 441 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 420 | break; | 442 | break; |
| 421 | /* 0x28 - Emulation Watchpoint, handled here */ | 443 | /* 0x28 - Emulation Watchpoint, handled here */ |
| @@ -425,8 +447,8 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 425 | pr_debug(EXC_0x28(KERN_DEBUG)); | 447 | pr_debug(EXC_0x28(KERN_DEBUG)); |
| 426 | CHK_DEBUGGER_TRAP_MAYBE(); | 448 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 427 | /* Check if this is a watchpoint in kernel space */ | 449 | /* Check if this is a watchpoint in kernel space */ |
| 428 | if (fp->ipend & 0xffc0) | 450 | if (kernel_mode_regs(fp)) |
| 429 | return; | 451 | goto traps_done; |
| 430 | else | 452 | else |
| 431 | break; | 453 | break; |
| 432 | #ifdef CONFIG_BF535 | 454 | #ifdef CONFIG_BF535 |
| @@ -434,7 +456,7 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 434 | case VEC_ISTRU_VL: /* ADSP-BF535 only (MH) */ | 456 | case VEC_ISTRU_VL: /* ADSP-BF535 only (MH) */ |
| 435 | info.si_code = BUS_OPFETCH; | 457 | info.si_code = BUS_OPFETCH; |
| 436 | sig = SIGBUS; | 458 | sig = SIGBUS; |
| 437 | verbose_printk(KERN_NOTICE "BF535: VEC_ISTRU_VL\n"); | 459 | strerror = KERN_NOTICE "BF535: VEC_ISTRU_VL\n"; |
| 438 | CHK_DEBUGGER_TRAP_MAYBE(); | 460 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 439 | break; | 461 | break; |
| 440 | #else | 462 | #else |
| @@ -444,21 +466,21 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 444 | case VEC_MISALI_I: | 466 | case VEC_MISALI_I: |
| 445 | info.si_code = BUS_ADRALN; | 467 | info.si_code = BUS_ADRALN; |
| 446 | sig = SIGBUS; | 468 | sig = SIGBUS; |
| 447 | verbose_printk(KERN_NOTICE EXC_0x2A(KERN_NOTICE)); | 469 | strerror = KERN_NOTICE EXC_0x2A(KERN_NOTICE); |
| 448 | CHK_DEBUGGER_TRAP_MAYBE(); | 470 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 449 | break; | 471 | break; |
| 450 | /* 0x2B - Instruction CPLB protection violation, handled here */ | 472 | /* 0x2B - Instruction CPLB protection violation, handled here */ |
| 451 | case VEC_CPLB_I_VL: | 473 | case VEC_CPLB_I_VL: |
| 452 | info.si_code = ILL_CPLB_VI; | 474 | info.si_code = ILL_CPLB_VI; |
| 453 | sig = SIGBUS; | 475 | sig = SIGBUS; |
| 454 | verbose_printk(KERN_NOTICE EXC_0x2B(KERN_NOTICE)); | 476 | strerror = KERN_NOTICE EXC_0x2B(KERN_NOTICE); |
| 455 | CHK_DEBUGGER_TRAP_MAYBE(); | 477 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 456 | break; | 478 | break; |
| 457 | /* 0x2C - Instruction CPLB miss, handled in _cplb_hdr */ | 479 | /* 0x2C - Instruction CPLB miss, handled in _cplb_hdr */ |
| 458 | case VEC_CPLB_I_M: | 480 | case VEC_CPLB_I_M: |
| 459 | info.si_code = ILL_CPLB_MISS; | 481 | info.si_code = ILL_CPLB_MISS; |
| 460 | sig = SIGBUS; | 482 | sig = SIGBUS; |
| 461 | verbose_printk(KERN_NOTICE EXC_0x2C(KERN_NOTICE)); | 483 | strerror = KERN_NOTICE EXC_0x2C(KERN_NOTICE); |
| 462 | break; | 484 | break; |
| 463 | /* 0x2D - Instruction CPLB Multiple Hits, handled here */ | 485 | /* 0x2D - Instruction CPLB Multiple Hits, handled here */ |
| 464 | case VEC_CPLB_I_MHIT: | 486 | case VEC_CPLB_I_MHIT: |
| @@ -466,17 +488,17 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 466 | sig = SIGSEGV; | 488 | sig = SIGSEGV; |
| 467 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO | 489 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO |
| 468 | if (cpu_pda[cpu].icplb_fault_addr < FIXED_CODE_START) | 490 | if (cpu_pda[cpu].icplb_fault_addr < FIXED_CODE_START) |
| 469 | verbose_printk(KERN_NOTICE "Jump to NULL address\n"); | 491 | strerror = KERN_NOTICE "Jump to NULL address\n"; |
| 470 | else | 492 | else |
| 471 | #endif | 493 | #endif |
| 472 | verbose_printk(KERN_NOTICE EXC_0x2D(KERN_NOTICE)); | 494 | strerror = KERN_NOTICE EXC_0x2D(KERN_NOTICE); |
| 473 | CHK_DEBUGGER_TRAP_MAYBE(); | 495 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 474 | break; | 496 | break; |
| 475 | /* 0x2E - Illegal use of Supervisor Resource, handled here */ | 497 | /* 0x2E - Illegal use of Supervisor Resource, handled here */ |
| 476 | case VEC_ILL_RES: | 498 | case VEC_ILL_RES: |
| 477 | info.si_code = ILL_PRVOPC; | 499 | info.si_code = ILL_PRVOPC; |
| 478 | sig = SIGILL; | 500 | sig = SIGILL; |
| 479 | verbose_printk(KERN_NOTICE EXC_0x2E(KERN_NOTICE)); | 501 | strerror = KERN_NOTICE EXC_0x2E(KERN_NOTICE); |
| 480 | CHK_DEBUGGER_TRAP_MAYBE(); | 502 | CHK_DEBUGGER_TRAP_MAYBE(); |
| 481 | break; | 503 | break; |
| 482 | /* 0x2F - Reserved, Caught by default */ | 504 | /* 0x2F - Reserved, Caught by default */ |
| @@ -504,17 +526,17 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 504 | case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR): | 526 | case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR): |
| 505 | info.si_code = BUS_ADRALN; | 527 | info.si_code = BUS_ADRALN; |
| 506 | sig = SIGBUS; | 528 | sig = SIGBUS; |
| 507 | verbose_printk(KERN_NOTICE HWC_x2(KERN_NOTICE)); | 529 | strerror = KERN_NOTICE HWC_x2(KERN_NOTICE); |
| 508 | break; | 530 | break; |
| 509 | /* External Memory Addressing Error */ | 531 | /* External Memory Addressing Error */ |
| 510 | case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR): | 532 | case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR): |
| 511 | info.si_code = BUS_ADRERR; | 533 | info.si_code = BUS_ADRERR; |
| 512 | sig = SIGBUS; | 534 | sig = SIGBUS; |
| 513 | verbose_printk(KERN_NOTICE HWC_x3(KERN_NOTICE)); | 535 | strerror = KERN_NOTICE HWC_x3(KERN_NOTICE); |
| 514 | break; | 536 | break; |
| 515 | /* Performance Monitor Overflow */ | 537 | /* Performance Monitor Overflow */ |
| 516 | case (SEQSTAT_HWERRCAUSE_PERF_FLOW): | 538 | case (SEQSTAT_HWERRCAUSE_PERF_FLOW): |
| 517 | verbose_printk(KERN_NOTICE HWC_x12(KERN_NOTICE)); | 539 | strerror = KERN_NOTICE HWC_x12(KERN_NOTICE); |
| 518 | break; | 540 | break; |
| 519 | /* RAISE 5 instruction */ | 541 | /* RAISE 5 instruction */ |
| 520 | case (SEQSTAT_HWERRCAUSE_RAISE_5): | 542 | case (SEQSTAT_HWERRCAUSE_RAISE_5): |
| @@ -531,7 +553,6 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 531 | * if we get here we hit a reserved one, so panic | 553 | * if we get here we hit a reserved one, so panic |
| 532 | */ | 554 | */ |
| 533 | default: | 555 | default: |
| 534 | oops_in_progress = 1; | ||
| 535 | info.si_code = ILL_ILLPARAOP; | 556 | info.si_code = ILL_ILLPARAOP; |
| 536 | sig = SIGILL; | 557 | sig = SIGILL; |
| 537 | verbose_printk(KERN_EMERG "Caught Unhandled Exception, code = %08lx\n", | 558 | verbose_printk(KERN_EMERG "Caught Unhandled Exception, code = %08lx\n", |
| @@ -542,6 +563,16 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 542 | 563 | ||
| 543 | BUG_ON(sig == 0); | 564 | BUG_ON(sig == 0); |
| 544 | 565 | ||
| 566 | /* If the fault was caused by a kernel thread, or interrupt handler | ||
| 567 | * we will kernel panic, so the system reboots. | ||
| 568 | */ | ||
| 569 | if (kernel_mode_regs(fp) || (current && !current->mm)) { | ||
| 570 | console_verbose(); | ||
| 571 | oops_in_progress = 1; | ||
| 572 | if (strerror) | ||
| 573 | verbose_printk(strerror); | ||
| 574 | } | ||
| 575 | |||
| 545 | if (sig != SIGTRAP) { | 576 | if (sig != SIGTRAP) { |
| 546 | dump_bfin_process(fp); | 577 | dump_bfin_process(fp); |
| 547 | dump_bfin_mem(fp); | 578 | dump_bfin_mem(fp); |
| @@ -588,8 +619,11 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 588 | force_sig_info(sig, &info, current); | 619 | force_sig_info(sig, &info, current); |
| 589 | } | 620 | } |
| 590 | 621 | ||
| 622 | if (ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8)) | ||
| 623 | fp->pc = SAFE_USER_INSTRUCTION; | ||
| 624 | |||
| 625 | traps_done: | ||
| 591 | trace_buffer_restore(j); | 626 | trace_buffer_restore(j); |
| 592 | return; | ||
| 593 | } | 627 | } |
| 594 | 628 | ||
| 595 | /* Typical exception handling routines */ | 629 | /* Typical exception handling routines */ |
| @@ -774,6 +808,18 @@ void dump_bfin_trace_buffer(void) | |||
| 774 | } | 808 | } |
| 775 | EXPORT_SYMBOL(dump_bfin_trace_buffer); | 809 | EXPORT_SYMBOL(dump_bfin_trace_buffer); |
| 776 | 810 | ||
| 811 | #ifdef CONFIG_BUG | ||
| 812 | int is_valid_bugaddr(unsigned long addr) | ||
| 813 | { | ||
| 814 | unsigned short opcode; | ||
| 815 | |||
| 816 | if (!get_instruction(&opcode, (unsigned short *)addr)) | ||
| 817 | return 0; | ||
| 818 | |||
| 819 | return opcode == BFIN_BUG_OPCODE; | ||
| 820 | } | ||
| 821 | #endif | ||
| 822 | |||
| 777 | /* | 823 | /* |
| 778 | * Checks to see if the address pointed to is either a | 824 | * Checks to see if the address pointed to is either a |
| 779 | * 16-bit CALL instruction, or a 32-bit CALL instruction | 825 | * 16-bit CALL instruction, or a 32-bit CALL instruction |
| @@ -832,6 +878,11 @@ void show_stack(struct task_struct *task, unsigned long *stack) | |||
| 832 | decode_address(buf, (unsigned int)stack); | 878 | decode_address(buf, (unsigned int)stack); |
| 833 | printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf); | 879 | printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf); |
| 834 | 880 | ||
| 881 | if (!access_ok(VERIFY_READ, stack, (unsigned int)endstack - (unsigned int)stack)) { | ||
| 882 | printk(KERN_NOTICE "Invalid stack pointer\n"); | ||
| 883 | return; | ||
| 884 | } | ||
| 885 | |||
| 835 | /* First thing is to look for a frame pointer */ | 886 | /* First thing is to look for a frame pointer */ |
| 836 | for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) { | 887 | for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) { |
| 837 | if (*addr & 0x1) | 888 | if (*addr & 0x1) |
| @@ -1066,6 +1117,29 @@ void show_regs(struct pt_regs *fp) | |||
| 1066 | unsigned int cpu = smp_processor_id(); | 1117 | unsigned int cpu = smp_processor_id(); |
| 1067 | unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic(); | 1118 | unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic(); |
| 1068 | 1119 | ||
| 1120 | verbose_printk(KERN_NOTICE "\n"); | ||
| 1121 | if (CPUID != bfin_cpuid()) | ||
| 1122 | verbose_printk(KERN_NOTICE "Compiled for cpu family 0x%04x (Rev %d), " | ||
| 1123 | "but running on:0x%04x (Rev %d)\n", | ||
| 1124 | CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid()); | ||
| 1125 | |||
| 1126 | verbose_printk(KERN_NOTICE "ADSP-%s-0.%d", | ||
| 1127 | CPU, bfin_compiled_revid()); | ||
| 1128 | |||
| 1129 | if (bfin_compiled_revid() != bfin_revid()) | ||
| 1130 | verbose_printk("(Detected 0.%d)", bfin_revid()); | ||
| 1131 | |||
| 1132 | verbose_printk(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n", | ||
| 1133 | get_cclk()/1000000, get_sclk()/1000000, | ||
| 1134 | #ifdef CONFIG_MPU | ||
| 1135 | "mpu on" | ||
| 1136 | #else | ||
| 1137 | "mpu off" | ||
| 1138 | #endif | ||
| 1139 | ); | ||
| 1140 | |||
| 1141 | verbose_printk(KERN_NOTICE "%s", linux_banner); | ||
| 1142 | |||
| 1069 | verbose_printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted()); | 1143 | verbose_printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted()); |
| 1070 | verbose_printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", | 1144 | verbose_printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", |
| 1071 | (long)fp->seqstat, fp->ipend, fp->syscfg); | 1145 | (long)fp->seqstat, fp->ipend, fp->syscfg); |
| @@ -1246,5 +1320,5 @@ void panic_cplb_error(int cplb_panic, struct pt_regs *fp) | |||
| 1246 | dump_bfin_mem(fp); | 1320 | dump_bfin_mem(fp); |
| 1247 | show_regs(fp); | 1321 | show_regs(fp); |
| 1248 | dump_stack(); | 1322 | dump_stack(); |
| 1249 | panic("Unrecoverable event\n"); | 1323 | panic("Unrecoverable event"); |
| 1250 | } | 1324 | } |
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S index 27952ae047d8..6ac307ca0d80 100644 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ b/arch/blackfin/kernel/vmlinux.lds.S | |||
| @@ -50,8 +50,11 @@ SECTIONS | |||
| 50 | _text = .; | 50 | _text = .; |
| 51 | __stext = .; | 51 | __stext = .; |
| 52 | TEXT_TEXT | 52 | TEXT_TEXT |
| 53 | #ifndef CONFIG_SCHEDULE_L1 | ||
| 53 | SCHED_TEXT | 54 | SCHED_TEXT |
| 55 | #endif | ||
| 54 | LOCK_TEXT | 56 | LOCK_TEXT |
| 57 | IRQENTRY_TEXT | ||
| 55 | KPROBES_TEXT | 58 | KPROBES_TEXT |
| 56 | *(.text.*) | 59 | *(.text.*) |
| 57 | *(.fixup) | 60 | *(.fixup) |
| @@ -164,6 +167,20 @@ SECTIONS | |||
| 164 | } | 167 | } |
| 165 | PERCPU(4) | 168 | PERCPU(4) |
| 166 | SECURITY_INIT | 169 | SECURITY_INIT |
| 170 | |||
| 171 | /* we have to discard exit text and such at runtime, not link time, to | ||
| 172 | * handle embedded cross-section references (alt instructions, bug | ||
| 173 | * table, eh_frame, etc...) | ||
| 174 | */ | ||
| 175 | .exit.text : | ||
| 176 | { | ||
| 177 | EXIT_TEXT | ||
| 178 | } | ||
| 179 | .exit.data : | ||
| 180 | { | ||
| 181 | EXIT_DATA | ||
| 182 | } | ||
| 183 | |||
| 167 | .init.ramfs : | 184 | .init.ramfs : |
| 168 | { | 185 | { |
| 169 | . = ALIGN(4); | 186 | . = ALIGN(4); |
| @@ -180,6 +197,9 @@ SECTIONS | |||
| 180 | . = ALIGN(4); | 197 | . = ALIGN(4); |
| 181 | __stext_l1 = .; | 198 | __stext_l1 = .; |
| 182 | *(.l1.text) | 199 | *(.l1.text) |
| 200 | #ifdef CONFIG_SCHEDULE_L1 | ||
| 201 | SCHED_TEXT | ||
| 202 | #endif | ||
| 183 | . = ALIGN(4); | 203 | . = ALIGN(4); |
| 184 | __etext_l1 = .; | 204 | __etext_l1 = .; |
| 185 | } | 205 | } |
| @@ -259,8 +279,6 @@ SECTIONS | |||
| 259 | 279 | ||
| 260 | /DISCARD/ : | 280 | /DISCARD/ : |
| 261 | { | 281 | { |
| 262 | EXIT_TEXT | ||
| 263 | EXIT_DATA | ||
| 264 | *(.exitcall.exit) | 282 | *(.exitcall.exit) |
| 265 | } | 283 | } |
| 266 | } | 284 | } |
diff --git a/arch/blackfin/lib/checksum.c b/arch/blackfin/lib/checksum.c index 762a7f02970a..cd605e7d8518 100644 --- a/arch/blackfin/lib/checksum.c +++ b/arch/blackfin/lib/checksum.c | |||
| @@ -116,6 +116,7 @@ __sum16 ip_compute_csum(const void *buff, int len) | |||
| 116 | { | 116 | { |
| 117 | return (__force __sum16)~do_csum(buff, len); | 117 | return (__force __sum16)~do_csum(buff, len); |
| 118 | } | 118 | } |
| 119 | EXPORT_SYMBOL(ip_compute_csum); | ||
| 119 | 120 | ||
| 120 | /* | 121 | /* |
| 121 | * copy from fs while checksumming, otherwise like csum_partial | 122 | * copy from fs while checksumming, otherwise like csum_partial |
| @@ -130,6 +131,7 @@ csum_partial_copy_from_user(const void __user *src, void *dst, | |||
| 130 | memcpy(dst, (__force void *)src, len); | 131 | memcpy(dst, (__force void *)src, len); |
| 131 | return csum_partial(dst, len, sum); | 132 | return csum_partial(dst, len, sum); |
| 132 | } | 133 | } |
| 134 | EXPORT_SYMBOL(csum_partial_copy_from_user); | ||
| 133 | 135 | ||
| 134 | /* | 136 | /* |
| 135 | * copy from ds while checksumming, otherwise like csum_partial | 137 | * copy from ds while checksumming, otherwise like csum_partial |
diff --git a/arch/blackfin/lib/strncmp.c b/arch/blackfin/lib/strncmp.c index 2aaae78a68e0..46518b1d2983 100644 --- a/arch/blackfin/lib/strncmp.c +++ b/arch/blackfin/lib/strncmp.c | |||
| @@ -8,9 +8,8 @@ | |||
| 8 | 8 | ||
| 9 | #define strncmp __inline_strncmp | 9 | #define strncmp __inline_strncmp |
| 10 | #include <asm/string.h> | 10 | #include <asm/string.h> |
| 11 | #undef strncmp | ||
| 12 | |||
| 13 | #include <linux/module.h> | 11 | #include <linux/module.h> |
| 12 | #undef strncmp | ||
| 14 | 13 | ||
| 15 | int strncmp(const char *cs, const char *ct, size_t count) | 14 | int strncmp(const char *cs, const char *ct, size_t count) |
| 16 | { | 15 | { |
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig index f397ede006bf..4c76fefb7a3b 100644 --- a/arch/blackfin/mach-bf518/Kconfig +++ b/arch/blackfin/mach-bf518/Kconfig | |||
| @@ -156,6 +156,7 @@ config IRQ_PORTH_INTB | |||
| 156 | default 11 | 156 | default 11 |
| 157 | config IRQ_TIMER0 | 157 | config IRQ_TIMER0 |
| 158 | int "IRQ_TIMER0" | 158 | int "IRQ_TIMER0" |
| 159 | default 7 if TICKSOURCE_GPTMR0 | ||
| 159 | default 8 | 160 | default 8 |
| 160 | config IRQ_TIMER1 | 161 | config IRQ_TIMER1 |
| 161 | int "IRQ_TIMER1" | 162 | int "IRQ_TIMER1" |
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c index 41f2eacfef20..1382f0382359 100644 --- a/arch/blackfin/mach-bf518/boards/ezbrd.c +++ b/arch/blackfin/mach-bf518/boards/ezbrd.c | |||
| @@ -82,7 +82,11 @@ static struct physmap_flash_data ezbrd_flash_data = { | |||
| 82 | 82 | ||
| 83 | static struct resource ezbrd_flash_resource = { | 83 | static struct resource ezbrd_flash_resource = { |
| 84 | .start = 0x20000000, | 84 | .start = 0x20000000, |
| 85 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | ||
| 86 | .end = 0x202fffff, | ||
| 87 | #else | ||
| 85 | .end = 0x203fffff, | 88 | .end = 0x203fffff, |
| 89 | #endif | ||
| 86 | .flags = IORESOURCE_MEM, | 90 | .flags = IORESOURCE_MEM, |
| 87 | }; | 91 | }; |
| 88 | 92 | ||
| @@ -162,8 +166,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 162 | }; | 166 | }; |
| 163 | #endif | 167 | #endif |
| 164 | 168 | ||
| 165 | #if defined(CONFIG_SPI_ADC_BF533) \ | 169 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
| 166 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | 170 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 167 | /* SPI ADC chip */ | 171 | /* SPI ADC chip */ |
| 168 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | 172 | static struct bfin5xx_spi_chip spi_adc_chip_info = { |
| 169 | .enable_dma = 1, /* use dma transfer with this chip*/ | 173 | .enable_dma = 1, /* use dma transfer with this chip*/ |
| @@ -242,15 +246,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 242 | .modalias = "m25p80", /* Name of spi_driver for this device */ | 246 | .modalias = "m25p80", /* Name of spi_driver for this device */ |
| 243 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | 247 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ |
| 244 | .bus_num = 0, /* Framework bus number */ | 248 | .bus_num = 0, /* Framework bus number */ |
| 245 | .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ | 249 | .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */ |
| 246 | .platform_data = &bfin_spi_flash_data, | 250 | .platform_data = &bfin_spi_flash_data, |
| 247 | .controller_data = &spi_flash_chip_info, | 251 | .controller_data = &spi_flash_chip_info, |
| 248 | .mode = SPI_MODE_3, | 252 | .mode = SPI_MODE_3, |
| 249 | }, | 253 | }, |
| 250 | #endif | 254 | #endif |
| 251 | 255 | ||
| 252 | #if defined(CONFIG_SPI_ADC_BF533) \ | 256 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
| 253 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | 257 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 254 | { | 258 | { |
| 255 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | 259 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ |
| 256 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | 260 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ |
| @@ -365,6 +369,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 365 | [1] = { | 369 | [1] = { |
| 366 | .start = CH_SPI0, | 370 | .start = CH_SPI0, |
| 367 | .end = CH_SPI0, | 371 | .end = CH_SPI0, |
| 372 | .flags = IORESOURCE_DMA, | ||
| 373 | }, | ||
| 374 | [2] = { | ||
| 375 | .start = IRQ_SPI0, | ||
| 376 | .end = IRQ_SPI0, | ||
| 368 | .flags = IORESOURCE_IRQ, | 377 | .flags = IORESOURCE_IRQ, |
| 369 | }, | 378 | }, |
| 370 | }; | 379 | }; |
| @@ -395,6 +404,11 @@ static struct resource bfin_spi1_resource[] = { | |||
| 395 | [1] = { | 404 | [1] = { |
| 396 | .start = CH_SPI1, | 405 | .start = CH_SPI1, |
| 397 | .end = CH_SPI1, | 406 | .end = CH_SPI1, |
| 407 | .flags = IORESOURCE_DMA, | ||
| 408 | }, | ||
| 409 | [2] = { | ||
| 410 | .start = IRQ_SPI1, | ||
| 411 | .end = IRQ_SPI1, | ||
| 398 | .flags = IORESOURCE_IRQ, | 412 | .flags = IORESOURCE_IRQ, |
| 399 | }, | 413 | }, |
| 400 | }; | 414 | }; |
| @@ -514,7 +528,7 @@ static struct platform_device i2c_bfin_twi_device = { | |||
| 514 | #endif | 528 | #endif |
| 515 | 529 | ||
| 516 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | 530 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { |
| 517 | #if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) | 531 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) |
| 518 | { | 532 | { |
| 519 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 533 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
| 520 | }, | 534 | }, |
| @@ -678,6 +692,11 @@ static int __init ezbrd_init(void) | |||
| 678 | ARRAY_SIZE(bfin_i2c_board_info)); | 692 | ARRAY_SIZE(bfin_i2c_board_info)); |
| 679 | platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); | 693 | platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); |
| 680 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | 694 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); |
| 695 | /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */ | ||
| 696 | peripheral_request(P_AMS2, "ParaFlash"); | ||
| 697 | #if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE) | ||
| 698 | peripheral_request(P_AMS3, "ParaFlash"); | ||
| 699 | #endif | ||
| 681 | return 0; | 700 | return 0; |
| 682 | } | 701 | } |
| 683 | 702 | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h index c847bb101076..b69bd9af38dd 100644 --- a/arch/blackfin/mach-bf518/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h | |||
| @@ -6,14 +6,19 @@ | |||
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file shoule be up to date with: | 9 | /* This file should be up to date with: |
| 10 | * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List | 10 | * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ | ||
| 14 | #if __SILICON_REVISION__ < 0 | ||
| 15 | # error will not work on BF518 silicon version | ||
| 16 | #endif | ||
| 17 | |||
| 13 | #ifndef _MACH_ANOMALY_H_ | 18 | #ifndef _MACH_ANOMALY_H_ |
| 14 | #define _MACH_ANOMALY_H_ | 19 | #define _MACH_ANOMALY_H_ |
| 15 | 20 | ||
| 16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | 21 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ |
| 17 | #define ANOMALY_05000074 (1) | 22 | #define ANOMALY_05000074 (1) |
| 18 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 23 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 19 | #define ANOMALY_05000122 (1) | 24 | #define ANOMALY_05000122 (1) |
| @@ -47,7 +52,7 @@ | |||
| 47 | #define ANOMALY_05000435 (1) | 52 | #define ANOMALY_05000435 (1) |
| 48 | /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ | 53 | /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ |
| 49 | #define ANOMALY_05000438 (1) | 54 | #define ANOMALY_05000438 (1) |
| 50 | /* Preboot Cannot be Used to Program the PLL_DIV Register */ | 55 | /* Preboot Cannot be Used to Alter the PLL_DIV Register */ |
| 51 | #define ANOMALY_05000439 (1) | 56 | #define ANOMALY_05000439 (1) |
| 52 | /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ | 57 | /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ |
| 53 | #define ANOMALY_05000440 (1) | 58 | #define ANOMALY_05000440 (1) |
| @@ -61,32 +66,56 @@ | |||
| 61 | #define ANOMALY_05000453 (1) | 66 | #define ANOMALY_05000453 (1) |
| 62 | /* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ | 67 | /* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ |
| 63 | #define ANOMALY_05000455 (1) | 68 | #define ANOMALY_05000455 (1) |
| 69 | /* False Hardware Error when RETI points to invalid memory */ | ||
| 70 | #define ANOMALY_05000461 (1) | ||
| 64 | 71 | ||
| 65 | /* Anomalies that don't exist on this proc */ | 72 | /* Anomalies that don't exist on this proc */ |
| 73 | #define ANOMALY_05000099 (0) | ||
| 74 | #define ANOMALY_05000119 (0) | ||
| 75 | #define ANOMALY_05000120 (0) | ||
| 66 | #define ANOMALY_05000125 (0) | 76 | #define ANOMALY_05000125 (0) |
| 77 | #define ANOMALY_05000149 (0) | ||
| 67 | #define ANOMALY_05000158 (0) | 78 | #define ANOMALY_05000158 (0) |
| 79 | #define ANOMALY_05000171 (0) | ||
| 80 | #define ANOMALY_05000179 (0) | ||
| 68 | #define ANOMALY_05000183 (0) | 81 | #define ANOMALY_05000183 (0) |
| 69 | #define ANOMALY_05000198 (0) | 82 | #define ANOMALY_05000198 (0) |
| 83 | #define ANOMALY_05000215 (0) | ||
| 84 | #define ANOMALY_05000220 (0) | ||
| 85 | #define ANOMALY_05000227 (0) | ||
| 70 | #define ANOMALY_05000230 (0) | 86 | #define ANOMALY_05000230 (0) |
| 87 | #define ANOMALY_05000231 (0) | ||
| 88 | #define ANOMALY_05000233 (0) | ||
| 89 | #define ANOMALY_05000242 (0) | ||
| 71 | #define ANOMALY_05000244 (0) | 90 | #define ANOMALY_05000244 (0) |
| 91 | #define ANOMALY_05000248 (0) | ||
| 92 | #define ANOMALY_05000250 (0) | ||
| 72 | #define ANOMALY_05000261 (0) | 93 | #define ANOMALY_05000261 (0) |
| 73 | #define ANOMALY_05000263 (0) | 94 | #define ANOMALY_05000263 (0) |
| 74 | #define ANOMALY_05000266 (0) | 95 | #define ANOMALY_05000266 (0) |
| 75 | #define ANOMALY_05000273 (0) | 96 | #define ANOMALY_05000273 (0) |
| 97 | #define ANOMALY_05000274 (0) | ||
| 76 | #define ANOMALY_05000278 (0) | 98 | #define ANOMALY_05000278 (0) |
| 77 | #define ANOMALY_05000285 (0) | 99 | #define ANOMALY_05000285 (0) |
| 100 | #define ANOMALY_05000287 (0) | ||
| 101 | #define ANOMALY_05000301 (0) | ||
| 78 | #define ANOMALY_05000305 (0) | 102 | #define ANOMALY_05000305 (0) |
| 79 | #define ANOMALY_05000307 (0) | 103 | #define ANOMALY_05000307 (0) |
| 80 | #define ANOMALY_05000311 (0) | 104 | #define ANOMALY_05000311 (0) |
| 81 | #define ANOMALY_05000312 (0) | 105 | #define ANOMALY_05000312 (0) |
| 82 | #define ANOMALY_05000323 (0) | 106 | #define ANOMALY_05000323 (0) |
| 83 | #define ANOMALY_05000353 (0) | 107 | #define ANOMALY_05000353 (0) |
| 108 | #define ANOMALY_05000362 (1) | ||
| 84 | #define ANOMALY_05000363 (0) | 109 | #define ANOMALY_05000363 (0) |
| 85 | #define ANOMALY_05000380 (0) | 110 | #define ANOMALY_05000380 (0) |
| 86 | #define ANOMALY_05000386 (0) | 111 | #define ANOMALY_05000386 (0) |
| 112 | #define ANOMALY_05000389 (0) | ||
| 113 | #define ANOMALY_05000400 (0) | ||
| 87 | #define ANOMALY_05000412 (0) | 114 | #define ANOMALY_05000412 (0) |
| 88 | #define ANOMALY_05000432 (0) | 115 | #define ANOMALY_05000432 (0) |
| 89 | #define ANOMALY_05000447 (0) | 116 | #define ANOMALY_05000447 (0) |
| 90 | #define ANOMALY_05000448 (0) | 117 | #define ANOMALY_05000448 (0) |
| 118 | #define ANOMALY_05000456 (0) | ||
| 119 | #define ANOMALY_05000450 (0) | ||
| 91 | 120 | ||
| 92 | #endif | 121 | #endif |
diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h index f618b487b2b0..a0fc77fd3315 100644 --- a/arch/blackfin/mach-bf518/include/mach/portmux.h +++ b/arch/blackfin/mach-bf518/include/mach/portmux.h | |||
| @@ -185,6 +185,10 @@ | |||
| 185 | #define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2)) | 185 | #define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2)) |
| 186 | #define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2)) | 186 | #define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2)) |
| 187 | 187 | ||
| 188 | #define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG000000000) | P_FUNCT(1)) | 188 | /* AMS */ |
| 189 | #define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) | ||
| 190 | #define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2)) | ||
| 191 | |||
| 192 | #define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG000000000) | P_FUNCT(1)) | ||
| 189 | 193 | ||
| 190 | #endif /* _MACH_PORTMUX_H_ */ | 194 | #endif /* _MACH_PORTMUX_H_ */ |
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig index 8438ec6d6679..848ac6f86823 100644 --- a/arch/blackfin/mach-bf527/Kconfig +++ b/arch/blackfin/mach-bf527/Kconfig | |||
| @@ -170,6 +170,7 @@ config IRQ_PORTH_INTB | |||
| 170 | default 11 | 170 | default 11 |
| 171 | config IRQ_TIMER0 | 171 | config IRQ_TIMER0 |
| 172 | int "IRQ_TIMER0" | 172 | int "IRQ_TIMER0" |
| 173 | default 7 if TICKSOURCE_GPTMR0 | ||
| 173 | default 8 | 174 | default 8 |
| 174 | config IRQ_TIMER1 | 175 | config IRQ_TIMER1 |
| 175 | int "IRQ_TIMER1" | 176 | int "IRQ_TIMER1" |
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c index 48e69eecdba4..1eaf27ff722e 100644 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c | |||
| @@ -463,8 +463,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 463 | }; | 463 | }; |
| 464 | #endif | 464 | #endif |
| 465 | 465 | ||
| 466 | #if defined(CONFIG_SPI_ADC_BF533) \ | 466 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
| 467 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | 467 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 468 | /* SPI ADC chip */ | 468 | /* SPI ADC chip */ |
| 469 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | 469 | static struct bfin5xx_spi_chip spi_adc_chip_info = { |
| 470 | .enable_dma = 1, /* use dma transfer with this chip*/ | 470 | .enable_dma = 1, /* use dma transfer with this chip*/ |
| @@ -554,8 +554,8 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 554 | }, | 554 | }, |
| 555 | #endif | 555 | #endif |
| 556 | 556 | ||
| 557 | #if defined(CONFIG_SPI_ADC_BF533) \ | 557 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
| 558 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | 558 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 559 | { | 559 | { |
| 560 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | 560 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ |
| 561 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | 561 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ |
| @@ -664,6 +664,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 664 | [1] = { | 664 | [1] = { |
| 665 | .start = CH_SPI, | 665 | .start = CH_SPI, |
| 666 | .end = CH_SPI, | 666 | .end = CH_SPI, |
| 667 | .flags = IORESOURCE_DMA, | ||
| 668 | }, | ||
| 669 | [2] = { | ||
| 670 | .start = IRQ_SPI, | ||
| 671 | .end = IRQ_SPI, | ||
| 667 | .flags = IORESOURCE_IRQ, | 672 | .flags = IORESOURCE_IRQ, |
| 668 | }, | 673 | }, |
| 669 | }; | 674 | }; |
| @@ -789,7 +794,7 @@ static struct platform_device i2c_bfin_twi_device = { | |||
| 789 | #endif | 794 | #endif |
| 790 | 795 | ||
| 791 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | 796 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { |
| 792 | #if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) | 797 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) |
| 793 | { | 798 | { |
| 794 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 799 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
| 795 | .type = "pcf8574_lcd", | 800 | .type = "pcf8574_lcd", |
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c index 7fe480e4ebe8..9f9c0005dcf1 100644 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ b/arch/blackfin/mach-bf527/boards/ezbrd.c | |||
| @@ -247,8 +247,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 247 | }; | 247 | }; |
| 248 | #endif | 248 | #endif |
| 249 | 249 | ||
| 250 | #if defined(CONFIG_SPI_ADC_BF533) \ | 250 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
| 251 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | 251 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 252 | /* SPI ADC chip */ | 252 | /* SPI ADC chip */ |
| 253 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | 253 | static struct bfin5xx_spi_chip spi_adc_chip_info = { |
| 254 | .enable_dma = 1, /* use dma transfer with this chip*/ | 254 | .enable_dma = 1, /* use dma transfer with this chip*/ |
| @@ -354,8 +354,8 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 354 | }, | 354 | }, |
| 355 | #endif | 355 | #endif |
| 356 | 356 | ||
| 357 | #if defined(CONFIG_SPI_ADC_BF533) \ | 357 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
| 358 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | 358 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 359 | { | 359 | { |
| 360 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | 360 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ |
| 361 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | 361 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ |
| @@ -467,6 +467,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 467 | [1] = { | 467 | [1] = { |
| 468 | .start = CH_SPI, | 468 | .start = CH_SPI, |
| 469 | .end = CH_SPI, | 469 | .end = CH_SPI, |
| 470 | .flags = IORESOURCE_DMA, | ||
| 471 | }, | ||
| 472 | [2] = { | ||
| 473 | .start = IRQ_SPI, | ||
| 474 | .end = IRQ_SPI, | ||
| 470 | .flags = IORESOURCE_IRQ, | 475 | .flags = IORESOURCE_IRQ, |
| 471 | }, | 476 | }, |
| 472 | }; | 477 | }; |
| @@ -586,7 +591,7 @@ static struct platform_device i2c_bfin_twi_device = { | |||
| 586 | #endif | 591 | #endif |
| 587 | 592 | ||
| 588 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | 593 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { |
| 589 | #if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) | 594 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) |
| 590 | { | 595 | { |
| 591 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 596 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
| 592 | }, | 597 | }, |
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index d0864111ef59..3e5b7db6b065 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c | |||
| @@ -485,8 +485,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 485 | }; | 485 | }; |
| 486 | #endif | 486 | #endif |
| 487 | 487 | ||
| 488 | #if defined(CONFIG_SPI_ADC_BF533) \ | 488 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
| 489 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | 489 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 490 | /* SPI ADC chip */ | 490 | /* SPI ADC chip */ |
| 491 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | 491 | static struct bfin5xx_spi_chip spi_adc_chip_info = { |
| 492 | .enable_dma = 1, /* use dma transfer with this chip*/ | 492 | .enable_dma = 1, /* use dma transfer with this chip*/ |
| @@ -509,6 +509,13 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | |||
| 509 | }; | 509 | }; |
| 510 | #endif | 510 | #endif |
| 511 | 511 | ||
| 512 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | ||
| 513 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | ||
| 514 | .enable_dma = 0, | ||
| 515 | .bits_per_word = 8, | ||
| 516 | }; | ||
| 517 | #endif | ||
| 518 | |||
| 512 | #if defined(CONFIG_PBX) | 519 | #if defined(CONFIG_PBX) |
| 513 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | 520 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { |
| 514 | .ctl_reg = 0x4, /* send zero */ | 521 | .ctl_reg = 0x4, /* send zero */ |
| @@ -593,8 +600,8 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 593 | }, | 600 | }, |
| 594 | #endif | 601 | #endif |
| 595 | 602 | ||
| 596 | #if defined(CONFIG_SPI_ADC_BF533) \ | 603 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
| 597 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | 604 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 598 | { | 605 | { |
| 599 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | 606 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ |
| 600 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | 607 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ |
| @@ -624,6 +631,17 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 624 | .controller_data = &ad9960_spi_chip_info, | 631 | .controller_data = &ad9960_spi_chip_info, |
| 625 | }, | 632 | }, |
| 626 | #endif | 633 | #endif |
| 634 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | ||
| 635 | { | ||
| 636 | .modalias = "mmc_spi", | ||
| 637 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | ||
| 638 | .bus_num = 0, | ||
| 639 | .chip_select = 3, | ||
| 640 | .controller_data = &mmc_spi_chip_info, | ||
| 641 | .mode = SPI_MODE_0, | ||
| 642 | }, | ||
| 643 | #endif | ||
| 644 | |||
| 627 | #if defined(CONFIG_PBX) | 645 | #if defined(CONFIG_PBX) |
| 628 | { | 646 | { |
| 629 | .modalias = "fxs-spi", | 647 | .modalias = "fxs-spi", |
| @@ -705,6 +723,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 705 | [1] = { | 723 | [1] = { |
| 706 | .start = CH_SPI, | 724 | .start = CH_SPI, |
| 707 | .end = CH_SPI, | 725 | .end = CH_SPI, |
| 726 | .flags = IORESOURCE_DMA, | ||
| 727 | }, | ||
| 728 | [2] = { | ||
| 729 | .start = IRQ_SPI, | ||
| 730 | .end = IRQ_SPI, | ||
| 708 | .flags = IORESOURCE_IRQ, | 731 | .flags = IORESOURCE_IRQ, |
| 709 | }, | 732 | }, |
| 710 | }; | 733 | }; |
| @@ -836,7 +859,7 @@ static struct platform_device i2c_bfin_twi_device = { | |||
| 836 | #endif | 859 | #endif |
| 837 | 860 | ||
| 838 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | 861 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { |
| 839 | #if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) | 862 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) |
| 840 | { | 863 | { |
| 841 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 864 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
| 842 | }, | 865 | }, |
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index df6808d8a6ef..c84ddea95749 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h | |||
| @@ -6,14 +6,19 @@ | |||
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file shoule be up to date with: | 9 | /* This file should be up to date with: |
| 10 | * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List | 10 | * - Revision C, 03/13/2009; ADSP-BF526 Blackfin Processor Anomaly List |
| 11 | * - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List | 11 | * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List |
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #ifndef _MACH_ANOMALY_H_ | 14 | #ifndef _MACH_ANOMALY_H_ |
| 15 | #define _MACH_ANOMALY_H_ | 15 | #define _MACH_ANOMALY_H_ |
| 16 | 16 | ||
| 17 | /* We do not support old silicon - sorry */ | ||
| 18 | #if __SILICON_REVISION__ < 0 | ||
| 19 | # error will not work on BF526/BF527 silicon version | ||
| 20 | #endif | ||
| 21 | |||
| 17 | #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) | 22 | #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) |
| 18 | # define ANOMALY_BF526 1 | 23 | # define ANOMALY_BF526 1 |
| 19 | #else | 24 | #else |
| @@ -25,158 +30,203 @@ | |||
| 25 | # define ANOMALY_BF527 0 | 30 | # define ANOMALY_BF527 0 |
| 26 | #endif | 31 | #endif |
| 27 | 32 | ||
| 28 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | 33 | #define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526) |
| 34 | #define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) | ||
| 35 | #define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) | ||
| 36 | |||
| 37 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ | ||
| 29 | #define ANOMALY_05000074 (1) | 38 | #define ANOMALY_05000074 (1) |
| 30 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | 39 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
| 31 | #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ | 40 | #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ |
| 32 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 41 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 33 | #define ANOMALY_05000122 (1) | 42 | #define ANOMALY_05000122 (1) |
| 34 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | 43 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
| 35 | #define ANOMALY_05000245 (1) | 44 | #define ANOMALY_05000245 (1) |
| 45 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ | ||
| 46 | #define ANOMALY_05000254 (1) | ||
| 36 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | 47 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
| 37 | #define ANOMALY_05000265 (1) | 48 | #define ANOMALY_05000265 (1) |
| 38 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | 49 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 39 | #define ANOMALY_05000310 (1) | 50 | #define ANOMALY_05000310 (1) |
| 40 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ | 51 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
| 41 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 2) | 52 | #define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 42 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ | 53 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ |
| 43 | #define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 54 | #define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) |
| 55 | /* Host DMA Boot Modes Are Not Functional */ | ||
| 56 | #define ANOMALY_05000330 (__SILICON_REVISION__ < 2) | ||
| 44 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ | 57 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ |
| 45 | #define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 58 | #define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) |
| 46 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ | 59 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ |
| 47 | #define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 60 | #define ANOMALY_05000341 (_ANOMALY_BF527(< 2)) |
| 48 | /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ | 61 | /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ |
| 49 | #define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 62 | #define ANOMALY_05000342 (_ANOMALY_BF527(< 2)) |
| 50 | /* USB Calibration Value Is Not Initialized */ | 63 | /* USB Calibration Value Is Not Initialized */ |
| 51 | #define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 64 | #define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 52 | /* USB Calibration Value to use */ | 65 | /* USB Calibration Value to use */ |
| 53 | #define ANOMALY_05000346_value 0xE510 | 66 | #define ANOMALY_05000346_value 0xE510 |
| 54 | /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ | 67 | /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ |
| 55 | #define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 68 | #define ANOMALY_05000347 (_ANOMALY_BF527(< 2)) |
| 56 | /* Security Features Are Not Functional */ | 69 | /* Security Features Are Not Functional */ |
| 57 | #define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1) | 70 | #define ANOMALY_05000348 (_ANOMALY_BF527(< 1)) |
| 58 | /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ | 71 | /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ |
| 59 | #define ANOMALY_05000353 (ANOMALY_BF526) | 72 | #define ANOMALY_05000353 (_ANOMALY_BF526(< 1)) |
| 60 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ | 73 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ |
| 61 | #define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 74 | #define ANOMALY_05000355 (_ANOMALY_BF527(< 2)) |
| 62 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ | 75 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ |
| 63 | #define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 76 | #define ANOMALY_05000357 (_ANOMALY_BF527(< 2)) |
| 64 | /* Incorrect Revision Number in DSPID Register */ | 77 | /* Incorrect Revision Number in DSPID Register */ |
| 65 | #define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1) | 78 | #define ANOMALY_05000364 (_ANOMALY_BF527(== 1)) |
| 66 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ | 79 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ |
| 67 | #define ANOMALY_05000366 (1) | 80 | #define ANOMALY_05000366 (1) |
| 68 | /* Incorrect Default CSEL Value in PLL_DIV */ | 81 | /* Incorrect Default CSEL Value in PLL_DIV */ |
| 69 | #define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 82 | #define ANOMALY_05000368 (_ANOMALY_BF527(< 2)) |
| 70 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | 83 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
| 71 | #define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 84 | #define ANOMALY_05000371 (_ANOMALY_BF527(< 2)) |
| 72 | /* Authentication Fails To Initiate */ | 85 | /* Authentication Fails To Initiate */ |
| 73 | #define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 86 | #define ANOMALY_05000376 (_ANOMALY_BF527(< 2)) |
| 74 | /* Data Read From L3 Memory by USB DMA May be Corrupted */ | 87 | /* Data Read From L3 Memory by USB DMA May be Corrupted */ |
| 75 | #define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 88 | #define ANOMALY_05000380 (_ANOMALY_BF527(< 2)) |
| 76 | /* 8-Bit NAND Flash Boot Mode Not Functional */ | 89 | /* 8-Bit NAND Flash Boot Mode Not Functional */ |
| 77 | #define ANOMALY_05000382 (__SILICON_REVISION__ < 2) | 90 | #define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 78 | /* Host Must Not Read Back During Host DMA Boot */ | ||
| 79 | #define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | ||
| 80 | /* Boot from OTP Memory Not Functional */ | 91 | /* Boot from OTP Memory Not Functional */ |
| 81 | #define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 92 | #define ANOMALY_05000385 (_ANOMALY_BF527(< 2)) |
| 82 | /* bfrom_SysControl() Firmware Routine Not Functional */ | 93 | /* bfrom_SysControl() Firmware Routine Not Functional */ |
| 83 | #define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 94 | #define ANOMALY_05000386 (_ANOMALY_BF527(< 2)) |
| 84 | /* Programmable Preboot Settings Not Functional */ | 95 | /* Programmable Preboot Settings Not Functional */ |
| 85 | #define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 96 | #define ANOMALY_05000387 (_ANOMALY_BF527(< 2)) |
| 86 | /* CRC32 Checksum Support Not Functional */ | 97 | /* CRC32 Checksum Support Not Functional */ |
| 87 | #define ANOMALY_05000388 (__SILICON_REVISION__ < 2) | 98 | #define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 88 | /* Reset Vector Must Not Be in SDRAM Memory Space */ | 99 | /* Reset Vector Must Not Be in SDRAM Memory Space */ |
| 89 | #define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 100 | #define ANOMALY_05000389 (_ANOMALY_BF527(< 2)) |
| 90 | /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ | 101 | /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ |
| 91 | #define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 102 | #define ANOMALY_05000392 (_ANOMALY_BF527(< 2)) |
| 92 | /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ | 103 | /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ |
| 93 | #define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 104 | #define ANOMALY_05000393 (_ANOMALY_BF527(< 2)) |
| 94 | /* Log Buffer Not Functional */ | 105 | /* Log Buffer Not Functional */ |
| 95 | #define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 106 | #define ANOMALY_05000394 (_ANOMALY_BF527(< 2)) |
| 96 | /* Hook Routine Not Functional */ | 107 | /* Hook Routine Not Functional */ |
| 97 | #define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 108 | #define ANOMALY_05000395 (_ANOMALY_BF527(< 2)) |
| 98 | /* Header Indirect Bit Not Functional */ | 109 | /* Header Indirect Bit Not Functional */ |
| 99 | #define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 110 | #define ANOMALY_05000396 (_ANOMALY_BF527(< 2)) |
| 100 | /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ | 111 | /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ |
| 101 | #define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 112 | #define ANOMALY_05000397 (_ANOMALY_BF527(< 2)) |
| 102 | /* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */ | 113 | /* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */ |
| 103 | #define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 114 | #define ANOMALY_05000398 (_ANOMALY_BF527(< 2)) |
| 104 | /* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */ | 115 | /* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */ |
| 105 | #define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 116 | #define ANOMALY_05000399 (_ANOMALY_BF527(< 2)) |
| 106 | /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ | 117 | /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ |
| 107 | #define ANOMALY_05000401 (__SILICON_REVISION__ < 2) | 118 | #define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 108 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ | 119 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
| 109 | #define ANOMALY_05000403 (__SILICON_REVISION__ < 2) | 120 | #define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 110 | /* Lockbox SESR Disallows Certain User Interrupts */ | 121 | /* Lockbox SESR Disallows Certain User Interrupts */ |
| 111 | #define ANOMALY_05000404 (__SILICON_REVISION__ < 2) | 122 | #define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 112 | /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ | 123 | /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ |
| 113 | #define ANOMALY_05000405 (1) | 124 | #define ANOMALY_05000405 (1) |
| 114 | /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ | 125 | /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ |
| 115 | #define ANOMALY_05000407 (__SILICON_REVISION__ < 2) | 126 | #define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 116 | /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ | 127 | /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ |
| 117 | #define ANOMALY_05000408 (1) | 128 | #define ANOMALY_05000408 (1) |
| 118 | /* Lockbox firmware leaves MDMA0 channel enabled */ | 129 | /* Lockbox firmware leaves MDMA0 channel enabled */ |
| 119 | #define ANOMALY_05000409 (__SILICON_REVISION__ < 2) | 130 | #define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 120 | /* Incorrect Default Internal Voltage Regulator Setting */ | 131 | /* Incorrect Default Internal Voltage Regulator Setting */ |
| 121 | #define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 132 | #define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) |
| 122 | /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ | 133 | /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ |
| 123 | #define ANOMALY_05000411 (__SILICON_REVISION__ < 2) | 134 | #define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 124 | /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ | 135 | /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ |
| 125 | #define ANOMALY_05000414 (__SILICON_REVISION__ < 2) | 136 | #define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 126 | /* DEB2_URGENT Bit Not Functional */ | 137 | /* DEB2_URGENT Bit Not Functional */ |
| 127 | #define ANOMALY_05000415 (__SILICON_REVISION__ < 2) | 138 | #define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 128 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | 139 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ |
| 129 | #define ANOMALY_05000416 (1) | 140 | #define ANOMALY_05000416 (1) |
| 130 | /* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ | 141 | /* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ |
| 131 | #define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 142 | #define ANOMALY_05000417 (_ANOMALY_BF527(< 2)) |
| 132 | /* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ | 143 | /* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ |
| 133 | #define ANOMALY_05000418 (__SILICON_REVISION__ < 2) | 144 | #define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 134 | /* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ | 145 | /* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ |
| 135 | #define ANOMALY_05000420 (__SILICON_REVISION__ < 2) | 146 | #define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 136 | /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ | 147 | /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ |
| 137 | #define ANOMALY_05000421 (1) | 148 | #define ANOMALY_05000421 (1) |
| 138 | /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ | 149 | /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ |
| 139 | #define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) | 150 | #define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1)) |
| 140 | /* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */ | 151 | /* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */ |
| 141 | #define ANOMALY_05000423 (__SILICON_REVISION__ < 2) | 152 | #define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 142 | /* Internal Voltage Regulator Not Trimmed */ | 153 | /* Internal Voltage Regulator Not Trimmed */ |
| 143 | #define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) | 154 | #define ANOMALY_05000424 (_ANOMALY_BF527(< 2)) |
| 144 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ | 155 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ |
| 145 | #define ANOMALY_05000425 (__SILICON_REVISION__ < 2) | 156 | #define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 146 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */ | 157 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ |
| 147 | #define ANOMALY_05000426 (1) | 158 | #define ANOMALY_05000426 (1) |
| 148 | /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ | 159 | /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ |
| 149 | #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) | 160 | #define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2)) |
| 150 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ | 161 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ |
| 151 | #define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) | 162 | #define ANOMALY_05000430 (_ANOMALY_BF527(> 1)) |
| 163 | /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ | ||
| 164 | #define ANOMALY_05000431 (1) | ||
| 152 | /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ | 165 | /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ |
| 153 | #define ANOMALY_05000432 (ANOMALY_BF526) | 166 | #define ANOMALY_05000432 (_ANOMALY_BF526(< 1)) |
| 154 | /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ | 167 | /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ |
| 155 | #define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527) | 168 | #define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0)) |
| 169 | /* Preboot Cannot be Used to Alter the PLL_DIV Register */ | ||
| 170 | #define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0)) | ||
| 171 | /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ | ||
| 172 | #define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0)) | ||
| 173 | /* OTP Write Accesses Not Supported */ | ||
| 174 | #define ANOMALY_05000442 (_ANOMALY_BF527(< 1)) | ||
| 156 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | 175 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 157 | #define ANOMALY_05000443 (1) | 176 | #define ANOMALY_05000443 (1) |
| 177 | /* The WURESET Bit in the SYSCR Register is not Functional */ | ||
| 178 | #define ANOMALY_05000445 (1) | ||
| 179 | /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ | ||
| 180 | #define ANOMALY_05000451 (1) | ||
| 181 | /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ | ||
| 182 | #define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) | ||
| 183 | /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ | ||
| 184 | #define ANOMALY_05000456 (1) | ||
| 185 | /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ | ||
| 186 | #define ANOMALY_05000457 (1) | ||
| 187 | /* False Hardware Error when RETI points to invalid memory */ | ||
| 188 | #define ANOMALY_05000461 (1) | ||
| 158 | 189 | ||
| 159 | /* Anomalies that don't exist on this proc */ | 190 | /* Anomalies that don't exist on this proc */ |
| 191 | #define ANOMALY_05000099 (0) | ||
| 192 | #define ANOMALY_05000120 (0) | ||
| 160 | #define ANOMALY_05000125 (0) | 193 | #define ANOMALY_05000125 (0) |
| 194 | #define ANOMALY_05000149 (0) | ||
| 161 | #define ANOMALY_05000158 (0) | 195 | #define ANOMALY_05000158 (0) |
| 196 | #define ANOMALY_05000171 (0) | ||
| 197 | #define ANOMALY_05000179 (0) | ||
| 162 | #define ANOMALY_05000183 (0) | 198 | #define ANOMALY_05000183 (0) |
| 163 | #define ANOMALY_05000198 (0) | 199 | #define ANOMALY_05000198 (0) |
| 200 | #define ANOMALY_05000215 (0) | ||
| 201 | #define ANOMALY_05000220 (0) | ||
| 202 | #define ANOMALY_05000227 (0) | ||
| 164 | #define ANOMALY_05000230 (0) | 203 | #define ANOMALY_05000230 (0) |
| 204 | #define ANOMALY_05000231 (0) | ||
| 205 | #define ANOMALY_05000233 (0) | ||
| 206 | #define ANOMALY_05000242 (0) | ||
| 165 | #define ANOMALY_05000244 (0) | 207 | #define ANOMALY_05000244 (0) |
| 208 | #define ANOMALY_05000248 (0) | ||
| 209 | #define ANOMALY_05000250 (0) | ||
| 166 | #define ANOMALY_05000261 (0) | 210 | #define ANOMALY_05000261 (0) |
| 167 | #define ANOMALY_05000263 (0) | 211 | #define ANOMALY_05000263 (0) |
| 168 | #define ANOMALY_05000266 (0) | 212 | #define ANOMALY_05000266 (0) |
| 169 | #define ANOMALY_05000273 (0) | 213 | #define ANOMALY_05000273 (0) |
| 214 | #define ANOMALY_05000274 (0) | ||
| 170 | #define ANOMALY_05000278 (0) | 215 | #define ANOMALY_05000278 (0) |
| 171 | #define ANOMALY_05000285 (0) | 216 | #define ANOMALY_05000285 (0) |
| 217 | #define ANOMALY_05000287 (0) | ||
| 218 | #define ANOMALY_05000301 (0) | ||
| 172 | #define ANOMALY_05000305 (0) | 219 | #define ANOMALY_05000305 (0) |
| 173 | #define ANOMALY_05000307 (0) | 220 | #define ANOMALY_05000307 (0) |
| 174 | #define ANOMALY_05000311 (0) | 221 | #define ANOMALY_05000311 (0) |
| 175 | #define ANOMALY_05000312 (0) | 222 | #define ANOMALY_05000312 (0) |
| 176 | #define ANOMALY_05000323 (0) | 223 | #define ANOMALY_05000323 (0) |
| 224 | #define ANOMALY_05000362 (1) | ||
| 177 | #define ANOMALY_05000363 (0) | 225 | #define ANOMALY_05000363 (0) |
| 226 | #define ANOMALY_05000400 (0) | ||
| 178 | #define ANOMALY_05000412 (0) | 227 | #define ANOMALY_05000412 (0) |
| 179 | #define ANOMALY_05000447 (0) | 228 | #define ANOMALY_05000447 (0) |
| 180 | #define ANOMALY_05000448 (0) | 229 | #define ANOMALY_05000448 (0) |
| 230 | #define ANOMALY_05000450 (0) | ||
| 181 | 231 | ||
| 182 | #endif | 232 | #endif |
diff --git a/arch/blackfin/mach-bf533/Kconfig b/arch/blackfin/mach-bf533/Kconfig index 14427de7d77f..4c572443147e 100644 --- a/arch/blackfin/mach-bf533/Kconfig +++ b/arch/blackfin/mach-bf533/Kconfig | |||
| @@ -59,6 +59,7 @@ config DMA7_UARTTX | |||
| 59 | default 10 | 59 | default 10 |
| 60 | config TIMER0 | 60 | config TIMER0 |
| 61 | int "TIMER0" | 61 | int "TIMER0" |
| 62 | default 7 if TICKSOURCE_GPTMR0 | ||
| 62 | default 8 | 63 | default 8 |
| 63 | config TIMER1 | 64 | config TIMER1 |
| 64 | int "TIMER1" | 65 | int "TIMER1" |
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c index 0c66bf44cfab..38cf8ffd6d74 100644 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ b/arch/blackfin/mach-bf533/boards/H8606.c | |||
| @@ -173,7 +173,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 173 | }; | 173 | }; |
| 174 | #endif | 174 | #endif |
| 175 | 175 | ||
| 176 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 176 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 177 | /* SPI ADC chip */ | 177 | /* SPI ADC chip */ |
| 178 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | 178 | static struct bfin5xx_spi_chip spi_adc_chip_info = { |
| 179 | .ctl_reg = 0x1000, | 179 | .ctl_reg = 0x1000, |
| @@ -216,7 +216,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 216 | }, | 216 | }, |
| 217 | #endif | 217 | #endif |
| 218 | 218 | ||
| 219 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 219 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 220 | { | 220 | { |
| 221 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | 221 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ |
| 222 | .max_speed_hz = 4, /* actual baudrate is SCLK/(2xspeed_hz) */ | 222 | .max_speed_hz = 4, /* actual baudrate is SCLK/(2xspeed_hz) */ |
| @@ -266,6 +266,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 266 | [1] = { | 266 | [1] = { |
| 267 | .start = CH_SPI, | 267 | .start = CH_SPI, |
| 268 | .end = CH_SPI, | 268 | .end = CH_SPI, |
| 269 | .flags = IORESOURCE_DMA, | ||
| 270 | }, | ||
| 271 | [2] = { | ||
| 272 | .start = IRQ_SPI, | ||
| 273 | .end = IRQ_SPI, | ||
| 269 | .flags = IORESOURCE_IRQ, | 274 | .flags = IORESOURCE_IRQ, |
| 270 | } | 275 | } |
| 271 | }; | 276 | }; |
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c index 0765872a8ada..9ecdc361fa6d 100644 --- a/arch/blackfin/mach-bf533/boards/blackstamp.c +++ b/arch/blackfin/mach-bf533/boards/blackstamp.c | |||
| @@ -162,6 +162,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 162 | [1] = { | 162 | [1] = { |
| 163 | .start = CH_SPI, | 163 | .start = CH_SPI, |
| 164 | .end = CH_SPI, | 164 | .end = CH_SPI, |
| 165 | .flags = IORESOURCE_DMA, | ||
| 166 | }, | ||
| 167 | [2] = { | ||
| 168 | .start = IRQ_SPI, | ||
| 169 | .end = IRQ_SPI, | ||
| 165 | .flags = IORESOURCE_IRQ, | 170 | .flags = IORESOURCE_IRQ, |
| 166 | } | 171 | } |
| 167 | }; | 172 | }; |
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c index e8974878d8c2..1443e92d8b62 100644 --- a/arch/blackfin/mach-bf533/boards/cm_bf533.c +++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c | |||
| @@ -82,7 +82,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 82 | #endif | 82 | #endif |
| 83 | 83 | ||
| 84 | /* SPI ADC chip */ | 84 | /* SPI ADC chip */ |
| 85 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 85 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 86 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | 86 | static struct bfin5xx_spi_chip spi_adc_chip_info = { |
| 87 | .enable_dma = 1, /* use dma transfer with this chip*/ | 87 | .enable_dma = 1, /* use dma transfer with this chip*/ |
| 88 | .bits_per_word = 16, | 88 | .bits_per_word = 16, |
| @@ -117,7 +117,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 117 | }, | 117 | }, |
| 118 | #endif | 118 | #endif |
| 119 | 119 | ||
| 120 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 120 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 121 | { | 121 | { |
| 122 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | 122 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ |
| 123 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | 123 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ |
| @@ -160,6 +160,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 160 | [1] = { | 160 | [1] = { |
| 161 | .start = CH_SPI, | 161 | .start = CH_SPI, |
| 162 | .end = CH_SPI, | 162 | .end = CH_SPI, |
| 163 | .flags = IORESOURCE_DMA, | ||
| 164 | }, | ||
| 165 | [2] = { | ||
| 166 | .start = IRQ_SPI, | ||
| 167 | .end = IRQ_SPI, | ||
| 163 | .flags = IORESOURCE_IRQ, | 168 | .flags = IORESOURCE_IRQ, |
| 164 | } | 169 | } |
| 165 | }; | 170 | }; |
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index 08cd0969de47..89a5ec4ca048 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c | |||
| @@ -118,7 +118,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 118 | }; | 118 | }; |
| 119 | #endif | 119 | #endif |
| 120 | 120 | ||
| 121 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 121 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 122 | /* SPI ADC chip */ | 122 | /* SPI ADC chip */ |
| 123 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | 123 | static struct bfin5xx_spi_chip spi_adc_chip_info = { |
| 124 | .enable_dma = 1, /* use dma transfer with this chip*/ | 124 | .enable_dma = 1, /* use dma transfer with this chip*/ |
| @@ -154,7 +154,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 154 | }, | 154 | }, |
| 155 | #endif | 155 | #endif |
| 156 | 156 | ||
| 157 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 157 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 158 | { | 158 | { |
| 159 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | 159 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ |
| 160 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | 160 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ |
| @@ -196,6 +196,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 196 | [1] = { | 196 | [1] = { |
| 197 | .start = CH_SPI, | 197 | .start = CH_SPI, |
| 198 | .end = CH_SPI, | 198 | .end = CH_SPI, |
| 199 | .flags = IORESOURCE_DMA, | ||
| 200 | }, | ||
| 201 | [2] = { | ||
| 202 | .start = IRQ_SPI, | ||
| 203 | .end = IRQ_SPI, | ||
| 199 | .flags = IORESOURCE_IRQ, | 204 | .flags = IORESOURCE_IRQ, |
| 200 | } | 205 | } |
| 201 | }; | 206 | }; |
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index db96f33f72e2..a68ade8a3ca2 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c | |||
| @@ -192,7 +192,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 192 | }; | 192 | }; |
| 193 | #endif | 193 | #endif |
| 194 | 194 | ||
| 195 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 195 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 196 | /* SPI ADC chip */ | 196 | /* SPI ADC chip */ |
| 197 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | 197 | static struct bfin5xx_spi_chip spi_adc_chip_info = { |
| 198 | .enable_dma = 1, /* use dma transfer with this chip*/ | 198 | .enable_dma = 1, /* use dma transfer with this chip*/ |
| @@ -237,7 +237,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 237 | }, | 237 | }, |
| 238 | #endif | 238 | #endif |
| 239 | 239 | ||
| 240 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 240 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 241 | { | 241 | { |
| 242 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | 242 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ |
| 243 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | 243 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ |
| @@ -299,6 +299,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 299 | [1] = { | 299 | [1] = { |
| 300 | .start = CH_SPI, | 300 | .start = CH_SPI, |
| 301 | .end = CH_SPI, | 301 | .end = CH_SPI, |
| 302 | .flags = IORESOURCE_DMA, | ||
| 303 | }, | ||
| 304 | [2] = { | ||
| 305 | .start = IRQ_SPI, | ||
| 306 | .end = IRQ_SPI, | ||
| 302 | .flags = IORESOURCE_IRQ, | 307 | .flags = IORESOURCE_IRQ, |
| 303 | } | 308 | } |
| 304 | }; | 309 | }; |
| @@ -448,7 +453,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | |||
| 448 | .irq = 39, | 453 | .irq = 39, |
| 449 | }, | 454 | }, |
| 450 | #endif | 455 | #endif |
| 451 | #if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) | 456 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) |
| 452 | { | 457 | { |
| 453 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 458 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
| 454 | }, | 459 | }, |
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h index 1cf893e2e55b..31145b509e20 100644 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file shoule be up to date with: | 9 | /* This file should be up to date with: |
| 10 | * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List | 10 | * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| @@ -34,12 +34,12 @@ | |||
| 34 | # define ANOMALY_BF533 0 | 34 | # define ANOMALY_BF533 0 |
| 35 | #endif | 35 | #endif |
| 36 | 36 | ||
| 37 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ | 37 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ |
| 38 | #define ANOMALY_05000074 (1) | 38 | #define ANOMALY_05000074 (1) |
| 39 | /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ | 39 | /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ |
| 40 | #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) | 40 | #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) |
| 41 | /* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */ | 41 | /* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */ |
| 42 | #define ANOMALY_05000105 (1) | 42 | #define ANOMALY_05000105 (__SILICON_REVISION__ > 2) |
| 43 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | 43 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
| 44 | #define ANOMALY_05000119 (1) | 44 | #define ANOMALY_05000119 (1) |
| 45 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 45 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| @@ -48,7 +48,7 @@ | |||
| 48 | #define ANOMALY_05000158 (__SILICON_REVISION__ < 5) | 48 | #define ANOMALY_05000158 (__SILICON_REVISION__ < 5) |
| 49 | /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ | 49 | /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ |
| 50 | #define ANOMALY_05000166 (1) | 50 | #define ANOMALY_05000166 (1) |
| 51 | /* Turning Serial Ports on with External Frame Syncs */ | 51 | /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ |
| 52 | #define ANOMALY_05000167 (1) | 52 | #define ANOMALY_05000167 (1) |
| 53 | /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ | 53 | /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ |
| 54 | #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) | 54 | #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) |
| @@ -67,9 +67,9 @@ | |||
| 67 | /* Current DMA Address Shows Wrong Value During Carry Fix */ | 67 | /* Current DMA Address Shows Wrong Value During Carry Fix */ |
| 68 | #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) | 68 | #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) |
| 69 | /* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ | 69 | /* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ |
| 70 | #define ANOMALY_05000200 (__SILICON_REVISION__ < 5) | 70 | #define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4) |
| 71 | /* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */ | 71 | /* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */ |
| 72 | #define ANOMALY_05000201 (__SILICON_REVISION__ < 4) | 72 | #define ANOMALY_05000201 (__SILICON_REVISION__ == 3) |
| 73 | /* Possible Infinite Stall with Specific Dual-DAG Situation */ | 73 | /* Possible Infinite Stall with Specific Dual-DAG Situation */ |
| 74 | #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) | 74 | #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) |
| 75 | /* Specific Sequence That Can Cause DMA Error or DMA Stopping */ | 75 | /* Specific Sequence That Can Cause DMA Error or DMA Stopping */ |
| @@ -104,7 +104,7 @@ | |||
| 104 | #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) | 104 | #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) |
| 105 | /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ | 105 | /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ |
| 106 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) | 106 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) |
| 107 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | 107 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
| 108 | #define ANOMALY_05000245 (1) | 108 | #define ANOMALY_05000245 (1) |
| 109 | /* Data CPLBs Should Prevent Spurious Hardware Errors */ | 109 | /* Data CPLBs Should Prevent Spurious Hardware Errors */ |
| 110 | #define ANOMALY_05000246 (__SILICON_REVISION__ < 5) | 110 | #define ANOMALY_05000246 (__SILICON_REVISION__ < 5) |
| @@ -137,7 +137,7 @@ | |||
| 137 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ | 137 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ |
| 138 | #define ANOMALY_05000270 (__SILICON_REVISION__ < 5) | 138 | #define ANOMALY_05000270 (__SILICON_REVISION__ < 5) |
| 139 | /* Spontaneous Reset of Internal Voltage Regulator */ | 139 | /* Spontaneous Reset of Internal Voltage Regulator */ |
| 140 | #define ANOMALY_05000271 (__SILICON_REVISION__ < 4) | 140 | #define ANOMALY_05000271 (__SILICON_REVISION__ == 3) |
| 141 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | 141 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ |
| 142 | #define ANOMALY_05000272 (1) | 142 | #define ANOMALY_05000272 (1) |
| 143 | /* Writes to Synchronous SDRAM Memory May Be Lost */ | 143 | /* Writes to Synchronous SDRAM Memory May Be Lost */ |
| @@ -165,14 +165,14 @@ | |||
| 165 | /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ | 165 | /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ |
| 166 | #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) | 166 | #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) |
| 167 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ | 167 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ |
| 168 | #define ANOMALY_05000307 (1) | 168 | #define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ |
| 169 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | 169 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 170 | #define ANOMALY_05000310 (1) | 170 | #define ANOMALY_05000310 (1) |
| 171 | /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ | 171 | /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ |
| 172 | #define ANOMALY_05000311 (__SILICON_REVISION__ < 6) | 172 | #define ANOMALY_05000311 (__SILICON_REVISION__ < 6) |
| 173 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | 173 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
| 174 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 6) | 174 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 6) |
| 175 | /* PPI Is Level-Sensitive on First Transfer */ | 175 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
| 176 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 6) | 176 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 6) |
| 177 | /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ | 177 | /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ |
| 178 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 6) | 178 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 6) |
| @@ -200,17 +200,63 @@ | |||
| 200 | #define ANOMALY_05000426 (1) | 200 | #define ANOMALY_05000426 (1) |
| 201 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | 201 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 202 | #define ANOMALY_05000443 (1) | 202 | #define ANOMALY_05000443 (1) |
| 203 | /* False Hardware Error when RETI points to invalid memory */ | ||
| 204 | #define ANOMALY_05000461 (1) | ||
| 203 | 205 | ||
| 204 | /* These anomalies have been "phased" out of analog.com anomaly sheets and are | 206 | /* These anomalies have been "phased" out of analog.com anomaly sheets and are |
| 205 | * here to show running on older silicon just isn't feasible. | 207 | * here to show running on older silicon just isn't feasible. |
| 206 | */ | 208 | */ |
| 207 | 209 | ||
| 210 | /* Internal voltage regulator can't be modified via register writes */ | ||
| 211 | #define ANOMALY_05000066 (__SILICON_REVISION__ < 2) | ||
| 208 | /* Watchpoints (Hardware Breakpoints) are not supported */ | 212 | /* Watchpoints (Hardware Breakpoints) are not supported */ |
| 209 | #define ANOMALY_05000067 (__SILICON_REVISION__ < 3) | 213 | #define ANOMALY_05000067 (__SILICON_REVISION__ < 3) |
| 214 | /* SDRAM PSSE bit cannot be set again after SDRAM Powerup */ | ||
| 215 | #define ANOMALY_05000070 (__SILICON_REVISION__ < 2) | ||
| 216 | /* Writing FIO_DIR can corrupt a programmable flag's data */ | ||
| 217 | #define ANOMALY_05000079 (__SILICON_REVISION__ < 2) | ||
| 218 | /* Timer Auto-Baud Mode requires the UART clock to be enabled */ | ||
| 219 | #define ANOMALY_05000086 (__SILICON_REVISION__ < 2) | ||
| 220 | /* Internal Clocking Modes on SPORT0 not supported */ | ||
| 221 | #define ANOMALY_05000088 (__SILICON_REVISION__ < 2) | ||
| 222 | /* Internal voltage regulator does not wake up from an RTC wakeup */ | ||
| 223 | #define ANOMALY_05000092 (__SILICON_REVISION__ < 2) | ||
| 224 | /* The IFLUSH instruction must be preceded by a CSYNC instruction */ | ||
| 225 | #define ANOMALY_05000093 (__SILICON_REVISION__ < 2) | ||
| 226 | /* Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior */ | ||
| 227 | #define ANOMALY_05000095 (__SILICON_REVISION__ < 2) | ||
| 228 | /* PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC */ | ||
| 229 | #define ANOMALY_05000096 (__SILICON_REVISION__ < 2) | ||
| 230 | /* Performance Monitor 0 and 1 are swapped when monitoring memory events */ | ||
| 231 | #define ANOMALY_05000097 (__SILICON_REVISION__ < 2) | ||
| 232 | /* 32-bit SPORT DMA will be word reversed */ | ||
| 233 | #define ANOMALY_05000098 (__SILICON_REVISION__ < 2) | ||
| 234 | /* Incorrect status in the UART_IIR register */ | ||
| 235 | #define ANOMALY_05000100 (__SILICON_REVISION__ < 2) | ||
| 236 | /* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ | ||
| 237 | #define ANOMALY_05000101 (__SILICON_REVISION__ < 2) | ||
| 238 | /* Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ | ||
| 239 | #define ANOMALY_05000102 (__SILICON_REVISION__ < 2) | ||
| 240 | /* Incorrect value written to the cycle counters */ | ||
| 241 | #define ANOMALY_05000103 (__SILICON_REVISION__ < 2) | ||
| 242 | /* Stores to L1 Data memory incorrect when a specific sequence is followed */ | ||
| 243 | #define ANOMALY_05000104 (__SILICON_REVISION__ < 2) | ||
| 244 | /* Programmable Flag (PF3) functionality not supported in all PPI modes */ | ||
| 245 | #define ANOMALY_05000106 (__SILICON_REVISION__ < 2) | ||
| 246 | /* Data store can be lost when targeting a cache line fill */ | ||
| 247 | #define ANOMALY_05000107 (__SILICON_REVISION__ < 2) | ||
| 210 | /* Reserved bits in SYSCFG register not set at power on */ | 248 | /* Reserved bits in SYSCFG register not set at power on */ |
| 211 | #define ANOMALY_05000109 (__SILICON_REVISION__ < 3) | 249 | #define ANOMALY_05000109 (__SILICON_REVISION__ < 3) |
| 250 | /* Infinite Core Stall */ | ||
| 251 | #define ANOMALY_05000114 (__SILICON_REVISION__ < 2) | ||
| 252 | /* PPI_FSx may glitch when generated by the on chip Timers */ | ||
| 253 | #define ANOMALY_05000115 (__SILICON_REVISION__ < 2) | ||
| 212 | /* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ | 254 | /* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ |
| 213 | #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) | 255 | #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) |
| 256 | /* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ | ||
| 257 | #define ANOMALY_05000117 (__SILICON_REVISION__ < 2) | ||
| 258 | /* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ | ||
| 259 | #define ANOMALY_05000118 (__SILICON_REVISION__ < 2) | ||
| 214 | /* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ | 260 | /* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ |
| 215 | #define ANOMALY_05000123 (__SILICON_REVISION__ < 3) | 261 | #define ANOMALY_05000123 (__SILICON_REVISION__ < 3) |
| 216 | /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ | 262 | /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ |
| @@ -222,7 +268,9 @@ | |||
| 222 | /* DMEM_CONTROL is not set on Reset */ | 268 | /* DMEM_CONTROL is not set on Reset */ |
| 223 | #define ANOMALY_05000137 (__SILICON_REVISION__ < 3) | 269 | #define ANOMALY_05000137 (__SILICON_REVISION__ < 3) |
| 224 | /* SPI boot will not complete if there is a zero fill block in the loader file */ | 270 | /* SPI boot will not complete if there is a zero fill block in the loader file */ |
| 225 | #define ANOMALY_05000138 (__SILICON_REVISION__ < 3) | 271 | #define ANOMALY_05000138 (__SILICON_REVISION__ == 2) |
| 272 | /* Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs */ | ||
| 273 | #define ANOMALY_05000139 (__SILICON_REVISION__ < 2) | ||
| 226 | /* Allowing the SPORT RX FIFO to fill will cause an overflow */ | 274 | /* Allowing the SPORT RX FIFO to fill will cause an overflow */ |
| 227 | #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) | 275 | #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) |
| 228 | /* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ | 276 | /* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ |
| @@ -237,17 +285,17 @@ | |||
| 237 | #define ANOMALY_05000145 (__SILICON_REVISION__ < 3) | 285 | #define ANOMALY_05000145 (__SILICON_REVISION__ < 3) |
| 238 | /* MDMA may lose the first few words of a descriptor chain */ | 286 | /* MDMA may lose the first few words of a descriptor chain */ |
| 239 | #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) | 287 | #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) |
| 240 | /* The source MDMA descriptor may stop with a DMA Error */ | 288 | /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ |
| 241 | #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) | 289 | #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) |
| 242 | /* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ | 290 | /* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ |
| 243 | #define ANOMALY_05000148 (__SILICON_REVISION__ < 3) | 291 | #define ANOMALY_05000148 (__SILICON_REVISION__ < 3) |
| 244 | /* Frame Delay in SPORT Multichannel Mode */ | 292 | /* Frame Delay in SPORT Multichannel Mode */ |
| 245 | #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) | 293 | #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) |
| 246 | /* SPORT TFS signal is active in Multi-channel mode outside of valid channels */ | 294 | /* SPORT TFS signal stays active in multichannel mode outside of valid channels */ |
| 247 | #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) | 295 | #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) |
| 248 | /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ | 296 | /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ |
| 249 | #define ANOMALY_05000155 (__SILICON_REVISION__ < 3) | 297 | #define ANOMALY_05000155 (__SILICON_REVISION__ < 3) |
| 250 | /* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */ | 298 | /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ |
| 251 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) | 299 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) |
| 252 | /* SPORT transmit data is not gated by external frame sync in certain conditions */ | 300 | /* SPORT transmit data is not gated by external frame sync in certain conditions */ |
| 253 | #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) | 301 | #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) |
| @@ -275,15 +323,27 @@ | |||
| 275 | #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) | 323 | #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) |
| 276 | 324 | ||
| 277 | /* Anomalies that don't exist on this proc */ | 325 | /* Anomalies that don't exist on this proc */ |
| 326 | #define ANOMALY_05000120 (0) | ||
| 327 | #define ANOMALY_05000149 (0) | ||
| 328 | #define ANOMALY_05000171 (0) | ||
| 329 | #define ANOMALY_05000220 (0) | ||
| 330 | #define ANOMALY_05000248 (0) | ||
| 278 | #define ANOMALY_05000266 (0) | 331 | #define ANOMALY_05000266 (0) |
| 332 | #define ANOMALY_05000274 (0) | ||
| 333 | #define ANOMALY_05000287 (0) | ||
| 279 | #define ANOMALY_05000323 (0) | 334 | #define ANOMALY_05000323 (0) |
| 280 | #define ANOMALY_05000353 (1) | 335 | #define ANOMALY_05000353 (1) |
| 336 | #define ANOMALY_05000362 (1) | ||
| 281 | #define ANOMALY_05000380 (0) | 337 | #define ANOMALY_05000380 (0) |
| 282 | #define ANOMALY_05000386 (1) | 338 | #define ANOMALY_05000386 (1) |
| 339 | #define ANOMALY_05000389 (0) | ||
| 283 | #define ANOMALY_05000412 (0) | 340 | #define ANOMALY_05000412 (0) |
| 341 | #define ANOMALY_05000430 (0) | ||
| 284 | #define ANOMALY_05000432 (0) | 342 | #define ANOMALY_05000432 (0) |
| 285 | #define ANOMALY_05000435 (0) | 343 | #define ANOMALY_05000435 (0) |
| 286 | #define ANOMALY_05000447 (0) | 344 | #define ANOMALY_05000447 (0) |
| 287 | #define ANOMALY_05000448 (0) | 345 | #define ANOMALY_05000448 (0) |
| 346 | #define ANOMALY_05000456 (0) | ||
| 347 | #define ANOMALY_05000450 (0) | ||
| 288 | 348 | ||
| 289 | #endif | 349 | #endif |
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig index bbc08fd4f122..d81224f9d723 100644 --- a/arch/blackfin/mach-bf537/Kconfig +++ b/arch/blackfin/mach-bf537/Kconfig | |||
| @@ -66,6 +66,7 @@ config IRQ_MAC_TX | |||
| 66 | default 11 | 66 | default 11 |
| 67 | config IRQ_TIMER0 | 67 | config IRQ_TIMER0 |
| 68 | int "IRQ_TIMER0" | 68 | int "IRQ_TIMER0" |
| 69 | default 7 if TICKSOURCE_GPTMR0 | ||
| 69 | default 8 | 70 | default 8 |
| 70 | config IRQ_TIMER1 | 71 | config IRQ_TIMER1 |
| 71 | int "IRQ_TIMER1" | 72 | int "IRQ_TIMER1" |
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c index 41c75b9bfac0..2a87d1cfcd06 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c | |||
| @@ -86,7 +86,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 86 | }; | 86 | }; |
| 87 | #endif | 87 | #endif |
| 88 | 88 | ||
| 89 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 89 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 90 | /* SPI ADC chip */ | 90 | /* SPI ADC chip */ |
| 91 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | 91 | static struct bfin5xx_spi_chip spi_adc_chip_info = { |
| 92 | .enable_dma = 1, /* use dma transfer with this chip*/ | 92 | .enable_dma = 1, /* use dma transfer with this chip*/ |
| @@ -129,7 +129,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 129 | }, | 129 | }, |
| 130 | #endif | 130 | #endif |
| 131 | 131 | ||
| 132 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 132 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 133 | { | 133 | { |
| 134 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | 134 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ |
| 135 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | 135 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ |
| @@ -182,8 +182,13 @@ static struct resource bfin_spi0_resource[] = { | |||
| 182 | [1] = { | 182 | [1] = { |
| 183 | .start = CH_SPI, | 183 | .start = CH_SPI, |
| 184 | .end = CH_SPI, | 184 | .end = CH_SPI, |
| 185 | .flags = IORESOURCE_DMA, | ||
| 186 | }, | ||
| 187 | [2] = { | ||
| 188 | .start = IRQ_SPI, | ||
| 189 | .end = IRQ_SPI, | ||
| 185 | .flags = IORESOURCE_IRQ, | 190 | .flags = IORESOURCE_IRQ, |
| 186 | } | 191 | }, |
| 187 | }; | 192 | }; |
| 188 | 193 | ||
| 189 | /* SPI controller data */ | 194 | /* SPI controller data */ |
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c index 3c159819e555..399f81da7b93 100644 --- a/arch/blackfin/mach-bf537/boards/minotaur.c +++ b/arch/blackfin/mach-bf537/boards/minotaur.c | |||
| @@ -184,6 +184,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 184 | [1] = { | 184 | [1] = { |
| 185 | .start = CH_SPI, | 185 | .start = CH_SPI, |
| 186 | .end = CH_SPI, | 186 | .end = CH_SPI, |
| 187 | .flags = IORESOURCE_DMA, | ||
| 188 | }, | ||
| 189 | [2] = { | ||
| 190 | .start = IRQ_SPI, | ||
| 191 | .end = IRQ_SPI, | ||
| 187 | .flags = IORESOURCE_IRQ, | 192 | .flags = IORESOURCE_IRQ, |
| 188 | }, | 193 | }, |
| 189 | }; | 194 | }; |
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index 4e1de1e53f89..838240f151f5 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c | |||
| @@ -265,8 +265,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 265 | }; | 265 | }; |
| 266 | #endif | 266 | #endif |
| 267 | 267 | ||
| 268 | #if defined(CONFIG_SPI_ADC_BF533) \ | 268 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
| 269 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | 269 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 270 | /* SPI ADC chip */ | 270 | /* SPI ADC chip */ |
| 271 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | 271 | static struct bfin5xx_spi_chip spi_adc_chip_info = { |
| 272 | .enable_dma = 1, /* use dma transfer with this chip*/ | 272 | .enable_dma = 1, /* use dma transfer with this chip*/ |
| @@ -333,8 +333,8 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 333 | }, | 333 | }, |
| 334 | #endif | 334 | #endif |
| 335 | 335 | ||
| 336 | #if defined(CONFIG_SPI_ADC_BF533) \ | 336 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
| 337 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | 337 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 338 | { | 338 | { |
| 339 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | 339 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ |
| 340 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | 340 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ |
| @@ -398,8 +398,13 @@ static struct resource bfin_spi0_resource[] = { | |||
| 398 | [1] = { | 398 | [1] = { |
| 399 | .start = CH_SPI, | 399 | .start = CH_SPI, |
| 400 | .end = CH_SPI, | 400 | .end = CH_SPI, |
| 401 | .flags = IORESOURCE_DMA, | ||
| 402 | }, | ||
| 403 | [2] = { | ||
| 404 | .start = IRQ_SPI, | ||
| 405 | .end = IRQ_SPI, | ||
| 401 | .flags = IORESOURCE_IRQ, | 406 | .flags = IORESOURCE_IRQ, |
| 402 | } | 407 | }, |
| 403 | }; | 408 | }; |
| 404 | 409 | ||
| 405 | /* SPI controller data */ | 410 | /* SPI controller data */ |
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 0572926da23f..ff7228caa7da 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c | |||
| @@ -508,8 +508,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 508 | }; | 508 | }; |
| 509 | #endif | 509 | #endif |
| 510 | 510 | ||
| 511 | #if defined(CONFIG_SPI_ADC_BF533) \ | 511 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
| 512 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | 512 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 513 | /* SPI ADC chip */ | 513 | /* SPI ADC chip */ |
| 514 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | 514 | static struct bfin5xx_spi_chip spi_adc_chip_info = { |
| 515 | .enable_dma = 1, /* use dma transfer with this chip*/ | 515 | .enable_dma = 1, /* use dma transfer with this chip*/ |
| @@ -607,6 +607,43 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = { | |||
| 607 | }; | 607 | }; |
| 608 | #endif | 608 | #endif |
| 609 | 609 | ||
| 610 | #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE) | ||
| 611 | #include <linux/input.h> | ||
| 612 | #include <linux/spi/adxl34x.h> | ||
| 613 | static const struct adxl34x_platform_data adxl34x_info = { | ||
| 614 | .x_axis_offset = 0, | ||
| 615 | .y_axis_offset = 0, | ||
| 616 | .z_axis_offset = 0, | ||
| 617 | .tap_threshold = 0x31, | ||
| 618 | .tap_duration = 0x10, | ||
| 619 | .tap_latency = 0x60, | ||
| 620 | .tap_window = 0xF0, | ||
| 621 | .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, | ||
| 622 | .act_axis_control = 0xFF, | ||
| 623 | .activity_threshold = 5, | ||
| 624 | .inactivity_threshold = 3, | ||
| 625 | .inactivity_time = 4, | ||
| 626 | .free_fall_threshold = 0x7, | ||
| 627 | .free_fall_time = 0x20, | ||
| 628 | .data_rate = 0x8, | ||
| 629 | .data_range = ADXL_FULL_RES, | ||
| 630 | |||
| 631 | .ev_type = EV_ABS, | ||
| 632 | .ev_code_x = ABS_X, /* EV_REL */ | ||
| 633 | .ev_code_y = ABS_Y, /* EV_REL */ | ||
| 634 | .ev_code_z = ABS_Z, /* EV_REL */ | ||
| 635 | |||
| 636 | .ev_code_tap_x = BTN_TOUCH, /* EV_KEY */ | ||
| 637 | .ev_code_tap_y = BTN_TOUCH, /* EV_KEY */ | ||
| 638 | .ev_code_tap_z = BTN_TOUCH, /* EV_KEY */ | ||
| 639 | |||
| 640 | /* .ev_code_ff = KEY_F,*/ /* EV_KEY */ | ||
| 641 | /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ | ||
| 642 | .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, | ||
| 643 | .fifo_mode = ADXL_FIFO_STREAM, | ||
| 644 | }; | ||
| 645 | #endif | ||
| 646 | |||
| 610 | #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) | 647 | #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) |
| 611 | static struct bfin5xx_spi_chip spi_ad7879_chip_info = { | 648 | static struct bfin5xx_spi_chip spi_ad7879_chip_info = { |
| 612 | .enable_dma = 0, | 649 | .enable_dma = 0, |
| @@ -695,8 +732,8 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 695 | .mode = SPI_MODE_3, | 732 | .mode = SPI_MODE_3, |
| 696 | }, | 733 | }, |
| 697 | #endif | 734 | #endif |
| 698 | #if defined(CONFIG_SPI_ADC_BF533) \ | 735 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
| 699 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | 736 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 700 | { | 737 | { |
| 701 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | 738 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ |
| 702 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | 739 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ |
| @@ -1280,7 +1317,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | |||
| 1280 | .irq = IRQ_PF5, | 1317 | .irq = IRQ_PF5, |
| 1281 | }, | 1318 | }, |
| 1282 | #endif | 1319 | #endif |
| 1283 | #if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) | 1320 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) |
| 1284 | { | 1321 | { |
| 1285 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 1322 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
| 1286 | }, | 1323 | }, |
| @@ -1308,10 +1345,17 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | |||
| 1308 | #if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE) | 1345 | #if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE) |
| 1309 | { | 1346 | { |
| 1310 | I2C_BOARD_INFO("pmic-adp5520", 0x32), | 1347 | I2C_BOARD_INFO("pmic-adp5520", 0x32), |
| 1311 | .irq = IRQ_PF7, | 1348 | .irq = IRQ_PG0, |
| 1312 | .platform_data = (void *)&adp5520_pdev_data, | 1349 | .platform_data = (void *)&adp5520_pdev_data, |
| 1313 | }, | 1350 | }, |
| 1314 | #endif | 1351 | #endif |
| 1352 | #if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE) | ||
| 1353 | { | ||
| 1354 | I2C_BOARD_INFO("adxl34x", 0x53), | ||
| 1355 | .irq = IRQ_PG3, | ||
| 1356 | .platform_data = (void *)&adxl34x_info, | ||
| 1357 | }, | ||
| 1358 | #endif | ||
| 1315 | }; | 1359 | }; |
| 1316 | 1360 | ||
| 1317 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | 1361 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
| @@ -1358,16 +1402,18 @@ static struct resource bfin_pata_resources[] = { | |||
| 1358 | static struct pata_platform_info bfin_pata_platform_data = { | 1402 | static struct pata_platform_info bfin_pata_platform_data = { |
| 1359 | .ioport_shift = 0, | 1403 | .ioport_shift = 0, |
| 1360 | }; | 1404 | }; |
| 1361 | 1405 | /* CompactFlash Storage Card Memory Mapped Adressing | |
| 1406 | * /REG = A11 = 1 | ||
| 1407 | */ | ||
| 1362 | static struct resource bfin_pata_resources[] = { | 1408 | static struct resource bfin_pata_resources[] = { |
| 1363 | { | 1409 | { |
| 1364 | .start = 0x20211820, | 1410 | .start = 0x20211800, |
| 1365 | .end = 0x2021183F, | 1411 | .end = 0x20211807, |
| 1366 | .flags = IORESOURCE_MEM, | 1412 | .flags = IORESOURCE_MEM, |
| 1367 | }, | 1413 | }, |
| 1368 | { | 1414 | { |
| 1369 | .start = 0x2021181C, | 1415 | .start = 0x2021180E, /* Device Ctl */ |
| 1370 | .end = 0x2021181F, | 1416 | .end = 0x2021180E, |
| 1371 | .flags = IORESOURCE_MEM, | 1417 | .flags = IORESOURCE_MEM, |
| 1372 | }, | 1418 | }, |
| 1373 | }; | 1419 | }; |
| @@ -1527,7 +1573,8 @@ static int __init stamp_init(void) | |||
| 1527 | platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); | 1573 | platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); |
| 1528 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | 1574 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); |
| 1529 | 1575 | ||
| 1530 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) | 1576 | #if (defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)) \ |
| 1577 | && defined(PATA_INT) | ||
| 1531 | irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; | 1578 | irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; |
| 1532 | #endif | 1579 | #endif |
| 1533 | 1580 | ||
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c index 53ad10f3cd76..e523e6e610d0 100644 --- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c | |||
| @@ -86,7 +86,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 86 | }; | 86 | }; |
| 87 | #endif | 87 | #endif |
| 88 | 88 | ||
| 89 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 89 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 90 | /* SPI ADC chip */ | 90 | /* SPI ADC chip */ |
| 91 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | 91 | static struct bfin5xx_spi_chip spi_adc_chip_info = { |
| 92 | .enable_dma = 1, /* use dma transfer with this chip*/ | 92 | .enable_dma = 1, /* use dma transfer with this chip*/ |
| @@ -129,7 +129,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 129 | }, | 129 | }, |
| 130 | #endif | 130 | #endif |
| 131 | 131 | ||
| 132 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 132 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 133 | { | 133 | { |
| 134 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | 134 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ |
| 135 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | 135 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ |
| @@ -182,6 +182,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 182 | [1] = { | 182 | [1] = { |
| 183 | .start = CH_SPI, | 183 | .start = CH_SPI, |
| 184 | .end = CH_SPI, | 184 | .end = CH_SPI, |
| 185 | .flags = IORESOURCE_DMA, | ||
| 186 | }, | ||
| 187 | [2] = { | ||
| 188 | .start = IRQ_SPI, | ||
| 189 | .end = IRQ_SPI, | ||
| 185 | .flags = IORESOURCE_IRQ, | 190 | .flags = IORESOURCE_IRQ, |
| 186 | } | 191 | } |
| 187 | }; | 192 | }; |
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h index 1bfd80c26c90..fc9663425465 100644 --- a/arch/blackfin/mach-bf537/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file shoule be up to date with: | 9 | /* This file should be up to date with: |
| 10 | * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List | 10 | * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| @@ -36,77 +36,75 @@ | |||
| 36 | 36 | ||
| 37 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ | 37 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ |
| 38 | #define ANOMALY_05000074 (1) | 38 | #define ANOMALY_05000074 (1) |
| 39 | /* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */ | 39 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
| 40 | #define ANOMALY_05000119 (1) | 40 | #define ANOMALY_05000119 (1) |
| 41 | /* Rx.H cannot be used to access 16-bit System MMR registers */ | 41 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 42 | #define ANOMALY_05000122 (1) | 42 | #define ANOMALY_05000122 (1) |
| 43 | /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ | 43 | /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ |
| 44 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 2) | 44 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 2) |
| 45 | /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ | 45 | /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ |
| 46 | #define ANOMALY_05000167 (1) | ||
| 47 | /* PPI_DELAY not functional in PPI modes with 0 frame syncs */ | ||
| 48 | #define ANOMALY_05000180 (1) | 46 | #define ANOMALY_05000180 (1) |
| 49 | /* Instruction Cache Is Not Functional */ | 47 | /* Instruction Cache Is Not Functional */ |
| 50 | #define ANOMALY_05000237 (__SILICON_REVISION__ < 2) | 48 | #define ANOMALY_05000237 (__SILICON_REVISION__ < 2) |
| 51 | /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */ | 49 | /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ |
| 52 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) | 50 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) |
| 53 | /* Spurious Hardware Error from an access in the shadow of a conditional branch */ | 51 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
| 54 | #define ANOMALY_05000245 (1) | 52 | #define ANOMALY_05000245 (1) |
| 55 | /* CLKIN Buffer Output Enable Reset Behavior Is Changed */ | 53 | /* CLKIN Buffer Output Enable Reset Behavior Is Changed */ |
| 56 | #define ANOMALY_05000247 (1) | 54 | #define ANOMALY_05000247 (1) |
| 57 | /* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */ | 55 | /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ |
| 58 | #define ANOMALY_05000250 (__SILICON_REVISION__ < 3) | 56 | #define ANOMALY_05000250 (__SILICON_REVISION__ < 3) |
| 59 | /* EMAC Tx DMA error after an early frame abort */ | 57 | /* EMAC Tx DMA error after an early frame abort */ |
| 60 | #define ANOMALY_05000252 (__SILICON_REVISION__ < 3) | 58 | #define ANOMALY_05000252 (__SILICON_REVISION__ < 3) |
| 61 | /* Maximum external clock speed for Timers */ | 59 | /* Maximum External Clock Speed for Timers */ |
| 62 | #define ANOMALY_05000253 (__SILICON_REVISION__ < 3) | 60 | #define ANOMALY_05000253 (__SILICON_REVISION__ < 3) |
| 63 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */ | 61 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ |
| 64 | #define ANOMALY_05000254 (__SILICON_REVISION__ > 2) | 62 | #define ANOMALY_05000254 (__SILICON_REVISION__ > 2) |
| 65 | /* Entering Hibernate Mode with RTC Seconds event interrupt not functional */ | 63 | /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ |
| 66 | #define ANOMALY_05000255 (__SILICON_REVISION__ < 3) | 64 | #define ANOMALY_05000255 (__SILICON_REVISION__ < 3) |
| 67 | /* EMAC MDIO input latched on wrong MDC edge */ | 65 | /* EMAC MDIO input latched on wrong MDC edge */ |
| 68 | #define ANOMALY_05000256 (__SILICON_REVISION__ < 3) | 66 | #define ANOMALY_05000256 (__SILICON_REVISION__ < 3) |
| 69 | /* Interrupt/Exception during short hardware loop may cause bad instruction fetches */ | 67 | /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ |
| 70 | #define ANOMALY_05000257 (__SILICON_REVISION__ < 3) | 68 | #define ANOMALY_05000257 (__SILICON_REVISION__ < 3) |
| 71 | /* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */ | 69 | /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ |
| 72 | #define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2) | 70 | #define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2) |
| 73 | /* ICPLB_STATUS MMR register may be corrupted */ | 71 | /* ICPLB_STATUS MMR Register May Be Corrupted */ |
| 74 | #define ANOMALY_05000260 (__SILICON_REVISION__ == 2) | 72 | #define ANOMALY_05000260 (__SILICON_REVISION__ == 2) |
| 75 | /* DCPLB_FAULT_ADDR MMR register may be corrupted */ | 73 | /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ |
| 76 | #define ANOMALY_05000261 (__SILICON_REVISION__ < 3) | 74 | #define ANOMALY_05000261 (__SILICON_REVISION__ < 3) |
| 77 | /* Stores to data cache may be lost */ | 75 | /* Stores To Data Cache May Be Lost */ |
| 78 | #define ANOMALY_05000262 (__SILICON_REVISION__ < 3) | 76 | #define ANOMALY_05000262 (__SILICON_REVISION__ < 3) |
| 79 | /* Hardware loop corrupted when taking an ICPLB exception */ | 77 | /* Hardware Loop Corrupted When Taking an ICPLB Exception */ |
| 80 | #define ANOMALY_05000263 (__SILICON_REVISION__ == 2) | 78 | #define ANOMALY_05000263 (__SILICON_REVISION__ == 2) |
| 81 | /* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */ | 79 | /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ |
| 82 | #define ANOMALY_05000264 (__SILICON_REVISION__ < 3) | 80 | #define ANOMALY_05000264 (__SILICON_REVISION__ < 3) |
| 83 | /* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */ | 81 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
| 84 | #define ANOMALY_05000265 (1) | 82 | #define ANOMALY_05000265 (1) |
| 85 | /* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ | 83 | /* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ |
| 86 | #define ANOMALY_05000268 (__SILICON_REVISION__ < 3) | 84 | #define ANOMALY_05000268 (__SILICON_REVISION__ < 3) |
| 87 | /* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */ | 85 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ |
| 88 | #define ANOMALY_05000270 (__SILICON_REVISION__ < 3) | 86 | #define ANOMALY_05000270 (__SILICON_REVISION__ < 3) |
| 89 | /* Certain data cache write through modes fail for VDDint <=0.9V */ | 87 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ |
| 90 | #define ANOMALY_05000272 (1) | 88 | #define ANOMALY_05000272 (1) |
| 91 | /* Writes to Synchronous SDRAM memory may be lost */ | 89 | /* Writes to Synchronous SDRAM Memory May Be Lost */ |
| 92 | #define ANOMALY_05000273 (__SILICON_REVISION__ < 3) | 90 | #define ANOMALY_05000273 (__SILICON_REVISION__ < 3) |
| 93 | /* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ | 91 | /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ |
| 94 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) | 92 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) |
| 95 | /* Disabling Peripherals with DMA running may cause DMA system instability */ | 93 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ |
| 96 | #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) | 94 | #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) |
| 97 | /* SPI Master boot mode does not work well with Atmel Data flash devices */ | 95 | /* SPI Master boot mode does not work well with Atmel Data flash devices */ |
| 98 | #define ANOMALY_05000280 (1) | 96 | #define ANOMALY_05000280 (1) |
| 99 | /* False Hardware Error Exception when ISR context is not restored */ | 97 | /* False Hardware Error Exception When ISR Context Is Not Restored */ |
| 100 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 3) | 98 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 3) |
| 101 | /* Memory DMA corruption with 32-bit data and traffic control */ | 99 | /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ |
| 102 | #define ANOMALY_05000282 (__SILICON_REVISION__ < 3) | 100 | #define ANOMALY_05000282 (__SILICON_REVISION__ < 3) |
| 103 | /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ | 101 | /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ |
| 104 | #define ANOMALY_05000283 (__SILICON_REVISION__ < 3) | 102 | #define ANOMALY_05000283 (__SILICON_REVISION__ < 3) |
| 105 | /* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ | 103 | /* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ |
| 106 | #define ANOMALY_05000285 (__SILICON_REVISION__ < 3) | 104 | #define ANOMALY_05000285 (__SILICON_REVISION__ < 3) |
| 107 | /* SPORTs may receive bad data if FIFOs fill up */ | 105 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ |
| 108 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 3) | 106 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 3) |
| 109 | /* Memory to memory DMA source/destination descriptors must be in same memory space */ | 107 | /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ |
| 110 | #define ANOMALY_05000301 (1) | 108 | #define ANOMALY_05000301 (1) |
| 111 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ | 109 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ |
| 112 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 3) | 110 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 3) |
| @@ -116,11 +114,11 @@ | |||
| 116 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 3) | 114 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 3) |
| 117 | /* Writing UART_THR while UART clock is disabled sends erroneous start bit */ | 115 | /* Writing UART_THR while UART clock is disabled sends erroneous start bit */ |
| 118 | #define ANOMALY_05000309 (__SILICON_REVISION__ < 3) | 116 | #define ANOMALY_05000309 (__SILICON_REVISION__ < 3) |
| 119 | /* False hardware errors caused by fetches at the boundary of reserved memory */ | 117 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 120 | #define ANOMALY_05000310 (1) | 118 | #define ANOMALY_05000310 (1) |
| 121 | /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */ | 119 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
| 122 | #define ANOMALY_05000312 (1) | 120 | #define ANOMALY_05000312 (1) |
| 123 | /* PPI is level sensitive on first transfer */ | 121 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
| 124 | #define ANOMALY_05000313 (1) | 122 | #define ANOMALY_05000313 (1) |
| 125 | /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ | 123 | /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ |
| 126 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 3) | 124 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 3) |
| @@ -156,24 +154,46 @@ | |||
| 156 | #define ANOMALY_05000426 (1) | 154 | #define ANOMALY_05000426 (1) |
| 157 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | 155 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 158 | #define ANOMALY_05000443 (1) | 156 | #define ANOMALY_05000443 (1) |
| 157 | /* False Hardware Error when RETI points to invalid memory */ | ||
| 158 | #define ANOMALY_05000461 (1) | ||
| 159 | 159 | ||
| 160 | /* Anomalies that don't exist on this proc */ | 160 | /* Anomalies that don't exist on this proc */ |
| 161 | #define ANOMALY_05000099 (0) | ||
| 162 | #define ANOMALY_05000120 (0) | ||
| 161 | #define ANOMALY_05000125 (0) | 163 | #define ANOMALY_05000125 (0) |
| 164 | #define ANOMALY_05000149 (0) | ||
| 162 | #define ANOMALY_05000158 (0) | 165 | #define ANOMALY_05000158 (0) |
| 166 | #define ANOMALY_05000171 (0) | ||
| 167 | #define ANOMALY_05000179 (0) | ||
| 163 | #define ANOMALY_05000183 (0) | 168 | #define ANOMALY_05000183 (0) |
| 164 | #define ANOMALY_05000198 (0) | 169 | #define ANOMALY_05000198 (0) |
| 170 | #define ANOMALY_05000215 (0) | ||
| 171 | #define ANOMALY_05000220 (0) | ||
| 172 | #define ANOMALY_05000227 (0) | ||
| 165 | #define ANOMALY_05000230 (0) | 173 | #define ANOMALY_05000230 (0) |
| 174 | #define ANOMALY_05000231 (0) | ||
| 175 | #define ANOMALY_05000233 (0) | ||
| 176 | #define ANOMALY_05000242 (0) | ||
| 177 | #define ANOMALY_05000248 (0) | ||
| 166 | #define ANOMALY_05000266 (0) | 178 | #define ANOMALY_05000266 (0) |
| 179 | #define ANOMALY_05000274 (0) | ||
| 180 | #define ANOMALY_05000287 (0) | ||
| 167 | #define ANOMALY_05000311 (0) | 181 | #define ANOMALY_05000311 (0) |
| 168 | #define ANOMALY_05000323 (0) | 182 | #define ANOMALY_05000323 (0) |
| 169 | #define ANOMALY_05000353 (1) | 183 | #define ANOMALY_05000353 (1) |
| 184 | #define ANOMALY_05000362 (1) | ||
| 170 | #define ANOMALY_05000363 (0) | 185 | #define ANOMALY_05000363 (0) |
| 171 | #define ANOMALY_05000380 (0) | 186 | #define ANOMALY_05000380 (0) |
| 172 | #define ANOMALY_05000386 (1) | 187 | #define ANOMALY_05000386 (1) |
| 188 | #define ANOMALY_05000389 (0) | ||
| 189 | #define ANOMALY_05000400 (0) | ||
| 173 | #define ANOMALY_05000412 (0) | 190 | #define ANOMALY_05000412 (0) |
| 191 | #define ANOMALY_05000430 (0) | ||
| 174 | #define ANOMALY_05000432 (0) | 192 | #define ANOMALY_05000432 (0) |
| 175 | #define ANOMALY_05000435 (0) | 193 | #define ANOMALY_05000435 (0) |
| 176 | #define ANOMALY_05000447 (0) | 194 | #define ANOMALY_05000447 (0) |
| 177 | #define ANOMALY_05000448 (0) | 195 | #define ANOMALY_05000448 (0) |
| 196 | #define ANOMALY_05000456 (0) | ||
| 197 | #define ANOMALY_05000450 (0) | ||
| 178 | 198 | ||
| 179 | #endif | 199 | #endif |
diff --git a/arch/blackfin/mach-bf538/Kconfig b/arch/blackfin/mach-bf538/Kconfig index f068c3523cdc..2d280f504ab0 100644 --- a/arch/blackfin/mach-bf538/Kconfig +++ b/arch/blackfin/mach-bf538/Kconfig | |||
| @@ -57,6 +57,7 @@ config IRQ_UART0_TX | |||
| 57 | default 10 | 57 | default 10 |
| 58 | config IRQ_TIMER0 | 58 | config IRQ_TIMER0 |
| 59 | int "IRQ_TIMER0" | 59 | int "IRQ_TIMER0" |
| 60 | default 7 if TICKSOURCE_GPTMR0 | ||
| 60 | default 8 | 61 | default 8 |
| 61 | config IRQ_TIMER1 | 62 | config IRQ_TIMER1 |
| 62 | int "IRQ_TIMER1" | 63 | int "IRQ_TIMER1" |
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c index e37cb9378884..57695b4c3c09 100644 --- a/arch/blackfin/mach-bf538/boards/ezkit.c +++ b/arch/blackfin/mach-bf538/boards/ezkit.c | |||
| @@ -352,6 +352,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 352 | [1] = { | 352 | [1] = { |
| 353 | .start = CH_SPI0, | 353 | .start = CH_SPI0, |
| 354 | .end = CH_SPI0, | 354 | .end = CH_SPI0, |
| 355 | .flags = IORESOURCE_DMA, | ||
| 356 | }, | ||
| 357 | [2] = { | ||
| 358 | .start = IRQ_SPI0, | ||
| 359 | .end = IRQ_SPI0, | ||
| 355 | .flags = IORESOURCE_IRQ, | 360 | .flags = IORESOURCE_IRQ, |
| 356 | } | 361 | } |
| 357 | }; | 362 | }; |
| @@ -366,6 +371,11 @@ static struct resource bfin_spi1_resource[] = { | |||
| 366 | [1] = { | 371 | [1] = { |
| 367 | .start = CH_SPI1, | 372 | .start = CH_SPI1, |
| 368 | .end = CH_SPI1, | 373 | .end = CH_SPI1, |
| 374 | .flags = IORESOURCE_DMA, | ||
| 375 | }, | ||
| 376 | [2] = { | ||
| 377 | .start = IRQ_SPI1, | ||
| 378 | .end = IRQ_SPI1, | ||
| 369 | .flags = IORESOURCE_IRQ, | 379 | .flags = IORESOURCE_IRQ, |
| 370 | } | 380 | } |
| 371 | }; | 381 | }; |
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h index 3a5699827363..175ca9ef7232 100644 --- a/arch/blackfin/mach-bf538/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file shoule be up to date with: | 9 | /* This file should be up to date with: |
| 10 | * - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List | 10 | * - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List |
| 11 | * - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List | 11 | * - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List |
| 12 | */ | 12 | */ |
| @@ -14,17 +14,29 @@ | |||
| 14 | #ifndef _MACH_ANOMALY_H_ | 14 | #ifndef _MACH_ANOMALY_H_ |
| 15 | #define _MACH_ANOMALY_H_ | 15 | #define _MACH_ANOMALY_H_ |
| 16 | 16 | ||
| 17 | /* We do not support old silicon - sorry */ | ||
| 17 | #if __SILICON_REVISION__ < 4 | 18 | #if __SILICON_REVISION__ < 4 |
| 18 | # error will not work on BF538 silicon version 0.0, 0.1, 0.2, or 0.3 | 19 | # error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3 |
| 19 | #endif | 20 | #endif |
| 20 | 21 | ||
| 21 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | 22 | #if defined(__ADSPBF538__) |
| 23 | # define ANOMALY_BF538 1 | ||
| 24 | #else | ||
| 25 | # define ANOMALY_BF538 0 | ||
| 26 | #endif | ||
| 27 | #if defined(__ADSPBF539__) | ||
| 28 | # define ANOMALY_BF539 1 | ||
| 29 | #else | ||
| 30 | # define ANOMALY_BF539 0 | ||
| 31 | #endif | ||
| 32 | |||
| 33 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ | ||
| 22 | #define ANOMALY_05000074 (1) | 34 | #define ANOMALY_05000074 (1) |
| 23 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | 35 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
| 24 | #define ANOMALY_05000119 (1) | 36 | #define ANOMALY_05000119 (1) |
| 25 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 37 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 26 | #define ANOMALY_05000122 (1) | 38 | #define ANOMALY_05000122 (1) |
| 27 | /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ | 39 | /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ |
| 28 | #define ANOMALY_05000166 (1) | 40 | #define ANOMALY_05000166 (1) |
| 29 | /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ | 41 | /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ |
| 30 | #define ANOMALY_05000179 (1) | 42 | #define ANOMALY_05000179 (1) |
| @@ -40,13 +52,13 @@ | |||
| 40 | #define ANOMALY_05000229 (1) | 52 | #define ANOMALY_05000229 (1) |
| 41 | /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ | 53 | /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ |
| 42 | #define ANOMALY_05000233 (1) | 54 | #define ANOMALY_05000233 (1) |
| 43 | /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */ | 55 | /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ |
| 44 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) | 56 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) |
| 45 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | 57 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
| 46 | #define ANOMALY_05000245 (1) | 58 | #define ANOMALY_05000245 (1) |
| 47 | /* Maximum External Clock Speed for Timers */ | 59 | /* Maximum External Clock Speed for Timers */ |
| 48 | #define ANOMALY_05000253 (1) | 60 | #define ANOMALY_05000253 (1) |
| 49 | /* DCPLB_FAULT_ADDR MMR register may be corrupted */ | 61 | /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ |
| 50 | #define ANOMALY_05000261 (__SILICON_REVISION__ < 3) | 62 | #define ANOMALY_05000261 (__SILICON_REVISION__ < 3) |
| 51 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ | 63 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ |
| 52 | #define ANOMALY_05000270 (__SILICON_REVISION__ < 4) | 64 | #define ANOMALY_05000270 (__SILICON_REVISION__ < 4) |
| @@ -58,11 +70,11 @@ | |||
| 58 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 4) | 70 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 4) |
| 59 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ | 71 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ |
| 60 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 4) | 72 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 4) |
| 61 | /* False Hardware Error Exception when ISR Context Is Not Restored */ | 73 | /* False Hardware Error Exception When ISR Context Is Not Restored */ |
| 62 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 4) | 74 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 4) |
| 63 | /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ | 75 | /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ |
| 64 | #define ANOMALY_05000282 (__SILICON_REVISION__ < 4) | 76 | #define ANOMALY_05000282 (__SILICON_REVISION__ < 4) |
| 65 | /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ | 77 | /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ |
| 66 | #define ANOMALY_05000283 (__SILICON_REVISION__ < 4) | 78 | #define ANOMALY_05000283 (__SILICON_REVISION__ < 4) |
| 67 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ | 79 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ |
| 68 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 4) | 80 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 4) |
| @@ -80,14 +92,14 @@ | |||
| 80 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 4) | 92 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 4) |
| 81 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | 93 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 82 | #define ANOMALY_05000310 (1) | 94 | #define ANOMALY_05000310 (1) |
| 83 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | 95 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
| 84 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 5) | 96 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 5) |
| 85 | /* PPI Is Level-Sensitive on First Transfer */ | 97 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
| 86 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 4) | 98 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 4) |
| 87 | /* Killed System MMR Write Completes Erroneously on Next System MMR Access */ | 99 | /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ |
| 88 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 4) | 100 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 4) |
| 89 | /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ | 101 | /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ |
| 90 | #define ANOMALY_05000318 (__SILICON_REVISION__ < 4) | 102 | #define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) |
| 91 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ | 103 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ |
| 92 | #define ANOMALY_05000355 (__SILICON_REVISION__ < 5) | 104 | #define ANOMALY_05000355 (__SILICON_REVISION__ < 5) |
| 93 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ | 105 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ |
| @@ -114,23 +126,45 @@ | |||
| 114 | #define ANOMALY_05000436 (__SILICON_REVISION__ > 3) | 126 | #define ANOMALY_05000436 (__SILICON_REVISION__ > 3) |
| 115 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | 127 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 116 | #define ANOMALY_05000443 (1) | 128 | #define ANOMALY_05000443 (1) |
| 129 | /* False Hardware Error when RETI points to invalid memory */ | ||
| 130 | #define ANOMALY_05000461 (1) | ||
| 117 | 131 | ||
| 118 | /* Anomalies that don't exist on this proc */ | 132 | /* Anomalies that don't exist on this proc */ |
| 133 | #define ANOMALY_05000099 (0) | ||
| 134 | #define ANOMALY_05000120 (0) | ||
| 135 | #define ANOMALY_05000149 (0) | ||
| 119 | #define ANOMALY_05000158 (0) | 136 | #define ANOMALY_05000158 (0) |
| 137 | #define ANOMALY_05000171 (0) | ||
| 120 | #define ANOMALY_05000198 (0) | 138 | #define ANOMALY_05000198 (0) |
| 139 | #define ANOMALY_05000215 (0) | ||
| 140 | #define ANOMALY_05000220 (0) | ||
| 141 | #define ANOMALY_05000227 (0) | ||
| 121 | #define ANOMALY_05000230 (0) | 142 | #define ANOMALY_05000230 (0) |
| 143 | #define ANOMALY_05000231 (0) | ||
| 144 | #define ANOMALY_05000242 (0) | ||
| 145 | #define ANOMALY_05000248 (0) | ||
| 146 | #define ANOMALY_05000250 (0) | ||
| 147 | #define ANOMALY_05000254 (0) | ||
| 122 | #define ANOMALY_05000263 (0) | 148 | #define ANOMALY_05000263 (0) |
| 149 | #define ANOMALY_05000274 (0) | ||
| 150 | #define ANOMALY_05000287 (0) | ||
| 123 | #define ANOMALY_05000305 (0) | 151 | #define ANOMALY_05000305 (0) |
| 124 | #define ANOMALY_05000311 (0) | 152 | #define ANOMALY_05000311 (0) |
| 125 | #define ANOMALY_05000323 (0) | 153 | #define ANOMALY_05000323 (0) |
| 126 | #define ANOMALY_05000353 (1) | 154 | #define ANOMALY_05000353 (1) |
| 155 | #define ANOMALY_05000362 (1) | ||
| 127 | #define ANOMALY_05000363 (0) | 156 | #define ANOMALY_05000363 (0) |
| 128 | #define ANOMALY_05000380 (0) | 157 | #define ANOMALY_05000380 (0) |
| 129 | #define ANOMALY_05000386 (1) | 158 | #define ANOMALY_05000386 (1) |
| 159 | #define ANOMALY_05000389 (0) | ||
| 160 | #define ANOMALY_05000400 (0) | ||
| 130 | #define ANOMALY_05000412 (0) | 161 | #define ANOMALY_05000412 (0) |
| 162 | #define ANOMALY_05000430 (0) | ||
| 131 | #define ANOMALY_05000432 (0) | 163 | #define ANOMALY_05000432 (0) |
| 132 | #define ANOMALY_05000435 (0) | 164 | #define ANOMALY_05000435 (0) |
| 133 | #define ANOMALY_05000447 (0) | 165 | #define ANOMALY_05000447 (0) |
| 134 | #define ANOMALY_05000448 (0) | 166 | #define ANOMALY_05000448 (0) |
| 167 | #define ANOMALY_05000456 (0) | ||
| 168 | #define ANOMALY_05000450 (0) | ||
| 135 | 169 | ||
| 136 | #endif | 170 | #endif |
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h index ea25371a922b..6f628353dde3 100644 --- a/arch/blackfin/mach-bf538/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h | |||
| @@ -68,25 +68,6 @@ | |||
| 68 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | 68 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ |
| 69 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | 69 | #define OFFSET_GCTL 0x24 /* Global Control Register */ |
| 70 | 70 | ||
| 71 | |||
| 72 | #define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_D0_IRQ_STATUS | ||
| 73 | #define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_D0_START_ADDR | ||
| 74 | #define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_S0_START_ADDR | ||
| 75 | #define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_D0_X_COUNT | ||
| 76 | #define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_S0_X_COUNT | ||
| 77 | #define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_D0_Y_COUNT | ||
| 78 | #define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_S0_Y_COUNT | ||
| 79 | #define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_D0_X_MODIFY | ||
| 80 | #define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_S0_X_MODIFY | ||
| 81 | #define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_D0_Y_MODIFY | ||
| 82 | #define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_S0_Y_MODIFY | ||
| 83 | #define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_S0_CONFIG | ||
| 84 | #define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_D0_CONFIG | ||
| 85 | #define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_S0_CONFIG | ||
| 86 | #define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_D0_IRQ_STATUS | ||
| 87 | #define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_S0_IRQ_STATUS | ||
| 88 | |||
| 89 | |||
| 90 | /* DPMC*/ | 71 | /* DPMC*/ |
| 91 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | 72 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() |
| 92 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) | 73 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) |
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h index 241725bc6988..99ca3f4305e2 100644 --- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h +++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h | |||
| @@ -67,14 +67,14 @@ | |||
| 67 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) | 67 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) |
| 68 | #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) | 68 | #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) |
| 69 | #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) | 69 | #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) |
| 70 | #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0)) | 70 | #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0)) |
| 71 | #define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val) | 71 | #define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val) |
| 72 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) | 72 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) |
| 73 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) | 73 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) |
| 74 | #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) | 74 | #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) |
| 75 | #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) | 75 | #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) |
| 76 | #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0)) | 76 | #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0)) |
| 77 | #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val) | 77 | #define bfin_write_SIC_IWR(x, val) bfin_write32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val) |
| 78 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) | 78 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) |
| 79 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) | 79 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) |
| 80 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) | 80 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) |
| @@ -1247,6 +1247,65 @@ | |||
| 1247 | #define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val) | 1247 | #define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val) |
| 1248 | #define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) | 1248 | #define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) |
| 1249 | #define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val) | 1249 | #define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val) |
| 1250 | |||
| 1251 | #define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA0_S0_CONFIG() | ||
| 1252 | #define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA0_S0_CONFIG(val) | ||
| 1253 | #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA0_S0_IRQ_STATUS() | ||
| 1254 | #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA0_S0_IRQ_STATUS(val) | ||
| 1255 | #define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA0_S0_X_MODIFY() | ||
| 1256 | #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA0_S0_X_MODIFY(val) | ||
| 1257 | #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA0_S0_Y_MODIFY() | ||
| 1258 | #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA0_S0_Y_MODIFY(val) | ||
| 1259 | #define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA0_S0_X_COUNT() | ||
| 1260 | #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA0_S0_X_COUNT(val) | ||
| 1261 | #define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA0_S0_Y_COUNT() | ||
| 1262 | #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA0_S0_Y_COUNT(val) | ||
| 1263 | #define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA0_S0_START_ADDR() | ||
| 1264 | #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA0_S0_START_ADDR(val) | ||
| 1265 | #define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA0_D0_CONFIG() | ||
| 1266 | #define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA0_D0_CONFIG(val) | ||
| 1267 | #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA0_D0_IRQ_STATUS() | ||
| 1268 | #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA0_D0_IRQ_STATUS(val) | ||
| 1269 | #define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA0_D0_X_MODIFY() | ||
| 1270 | #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA0_D0_X_MODIFY(val) | ||
| 1271 | #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA0_D0_Y_MODIFY() | ||
| 1272 | #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA0_D0_Y_MODIFY(val) | ||
| 1273 | #define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA0_D0_X_COUNT() | ||
| 1274 | #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA0_D0_X_COUNT(val) | ||
| 1275 | #define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA0_D0_Y_COUNT() | ||
| 1276 | #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA0_D0_Y_COUNT(val) | ||
| 1277 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA0_D0_START_ADDR() | ||
| 1278 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA0_D0_START_ADDR(val) | ||
| 1279 | |||
| 1280 | #define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA0_S1_CONFIG() | ||
| 1281 | #define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA0_S1_CONFIG(val) | ||
| 1282 | #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA0_S1_IRQ_STATUS() | ||
| 1283 | #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA0_S1_IRQ_STATUS(val) | ||
| 1284 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA0_S1_X_MODIFY() | ||
| 1285 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA0_S1_X_MODIFY(val) | ||
| 1286 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA0_S1_Y_MODIFY() | ||
| 1287 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA0_S1_Y_MODIFY(val) | ||
| 1288 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA0_S1_X_COUNT() | ||
| 1289 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA0_S1_X_COUNT(val) | ||
| 1290 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA0_S1_Y_COUNT() | ||
| 1291 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA0_S1_Y_COUNT(val) | ||
| 1292 | #define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA0_S1_START_ADDR() | ||
| 1293 | #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA0_S1_START_ADDR(val) | ||
| 1294 | #define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA0_D1_CONFIG() | ||
| 1295 | #define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA0_D1_CONFIG(val) | ||
| 1296 | #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA0_D1_IRQ_STATUS() | ||
| 1297 | #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA0_D1_IRQ_STATUS(val) | ||
| 1298 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA0_D1_X_MODIFY() | ||
| 1299 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA0_D1_X_MODIFY(val) | ||
| 1300 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA0_D1_Y_MODIFY() | ||
| 1301 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA0_D1_Y_MODIFY(val) | ||
| 1302 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA0_D1_X_COUNT() | ||
| 1303 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA0_D1_X_COUNT(val) | ||
| 1304 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA0_D1_Y_COUNT() | ||
| 1305 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA0_D1_Y_COUNT(val) | ||
| 1306 | #define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA0_D1_START_ADDR() | ||
| 1307 | #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA0_D1_START_ADDR(val) | ||
| 1308 | |||
| 1250 | #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) | 1309 | #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) |
| 1251 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) | 1310 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) |
| 1252 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) | 1311 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) |
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h index 6adbfcc65a35..bdc330cd0e1c 100644 --- a/arch/blackfin/mach-bf538/include/mach/defBF539.h +++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h | |||
| @@ -412,6 +412,62 @@ | |||
| 412 | #define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */ | 412 | #define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */ |
| 413 | #define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */ | 413 | #define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */ |
| 414 | 414 | ||
| 415 | #define MDMA_D0_NEXT_DESC_PTR MDMA0_D0_NEXT_DESC_PTR | ||
| 416 | #define MDMA_D0_START_ADDR MDMA0_D0_START_ADDR | ||
| 417 | #define MDMA_D0_CONFIG MDMA0_D0_CONFIG | ||
| 418 | #define MDMA_D0_X_COUNT MDMA0_D0_X_COUNT | ||
| 419 | #define MDMA_D0_X_MODIFY MDMA0_D0_X_MODIFY | ||
| 420 | #define MDMA_D0_Y_COUNT MDMA0_D0_Y_COUNT | ||
| 421 | #define MDMA_D0_Y_MODIFY MDMA0_D0_Y_MODIFY | ||
| 422 | #define MDMA_D0_CURR_DESC_PTR MDMA0_D0_CURR_DESC_PTR | ||
| 423 | #define MDMA_D0_CURR_ADDR MDMA0_D0_CURR_ADDR | ||
| 424 | #define MDMA_D0_IRQ_STATUS MDMA0_D0_IRQ_STATUS | ||
| 425 | #define MDMA_D0_PERIPHERAL_MAP MDMA0_D0_PERIPHERAL_MAP | ||
| 426 | #define MDMA_D0_CURR_X_COUNT MDMA0_D0_CURR_X_COUNT | ||
| 427 | #define MDMA_D0_CURR_Y_COUNT MDMA0_D0_CURR_Y_COUNT | ||
| 428 | |||
| 429 | #define MDMA_S0_NEXT_DESC_PTR MDMA0_S0_NEXT_DESC_PTR | ||
| 430 | #define MDMA_S0_START_ADDR MDMA0_S0_START_ADDR | ||
| 431 | #define MDMA_S0_CONFIG MDMA0_S0_CONFIG | ||
| 432 | #define MDMA_S0_X_COUNT MDMA0_S0_X_COUNT | ||
| 433 | #define MDMA_S0_X_MODIFY MDMA0_S0_X_MODIFY | ||
| 434 | #define MDMA_S0_Y_COUNT MDMA0_S0_Y_COUNT | ||
| 435 | #define MDMA_S0_Y_MODIFY MDMA0_S0_Y_MODIFY | ||
| 436 | #define MDMA_S0_CURR_DESC_PTR MDMA0_S0_CURR_DESC_PTR | ||
| 437 | #define MDMA_S0_CURR_ADDR MDMA0_S0_CURR_ADDR | ||
| 438 | #define MDMA_S0_IRQ_STATUS MDMA0_S0_IRQ_STATUS | ||
| 439 | #define MDMA_S0_PERIPHERAL_MAP MDMA0_S0_PERIPHERAL_MAP | ||
| 440 | #define MDMA_S0_CURR_X_COUNT MDMA0_S0_CURR_X_COUNT | ||
| 441 | #define MDMA_S0_CURR_Y_COUNT MDMA0_S0_CURR_Y_COUNT | ||
| 442 | |||
| 443 | #define MDMA_D1_NEXT_DESC_PTR MDMA0_D1_NEXT_DESC_PTR | ||
| 444 | #define MDMA_D1_START_ADDR MDMA0_D1_START_ADDR | ||
| 445 | #define MDMA_D1_CONFIG MDMA0_D1_CONFIG | ||
| 446 | #define MDMA_D1_X_COUNT MDMA0_D1_X_COUNT | ||
| 447 | #define MDMA_D1_X_MODIFY MDMA0_D1_X_MODIFY | ||
| 448 | #define MDMA_D1_Y_COUNT MDMA0_D1_Y_COUNT | ||
| 449 | #define MDMA_D1_Y_MODIFY MDMA0_D1_Y_MODIFY | ||
| 450 | #define MDMA_D1_CURR_DESC_PTR MDMA0_D1_CURR_DESC_PTR | ||
| 451 | #define MDMA_D1_CURR_ADDR MDMA0_D1_CURR_ADDR | ||
| 452 | #define MDMA_D1_IRQ_STATUS MDMA0_D1_IRQ_STATUS | ||
| 453 | #define MDMA_D1_PERIPHERAL_MAP MDMA0_D1_PERIPHERAL_MAP | ||
| 454 | #define MDMA_D1_CURR_X_COUNT MDMA0_D1_CURR_X_COUNT | ||
| 455 | #define MDMA_D1_CURR_Y_COUNT MDMA0_D1_CURR_Y_COUNT | ||
| 456 | |||
| 457 | #define MDMA_S1_NEXT_DESC_PTR MDMA0_S1_NEXT_DESC_PTR | ||
| 458 | #define MDMA_S1_START_ADDR MDMA0_S1_START_ADDR | ||
| 459 | #define MDMA_S1_CONFIG MDMA0_S1_CONFIG | ||
| 460 | #define MDMA_S1_X_COUNT MDMA0_S1_X_COUNT | ||
| 461 | #define MDMA_S1_X_MODIFY MDMA0_S1_X_MODIFY | ||
| 462 | #define MDMA_S1_Y_COUNT MDMA0_S1_Y_COUNT | ||
| 463 | #define MDMA_S1_Y_MODIFY MDMA0_S1_Y_MODIFY | ||
| 464 | #define MDMA_S1_CURR_DESC_PTR MDMA0_S1_CURR_DESC_PTR | ||
| 465 | #define MDMA_S1_CURR_ADDR MDMA0_S1_CURR_ADDR | ||
| 466 | #define MDMA_S1_IRQ_STATUS MDMA0_S1_IRQ_STATUS | ||
| 467 | #define MDMA_S1_PERIPHERAL_MAP MDMA0_S1_PERIPHERAL_MAP | ||
| 468 | #define MDMA_S1_CURR_X_COUNT MDMA0_S1_CURR_X_COUNT | ||
| 469 | #define MDMA_S1_CURR_Y_COUNT MDMA0_S1_CURR_Y_COUNT | ||
| 470 | |||
| 415 | 471 | ||
| 416 | /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ | 472 | /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ |
| 417 | #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ | 473 | #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ |
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig index dcf657159051..a09623dfd550 100644 --- a/arch/blackfin/mach-bf548/Kconfig +++ b/arch/blackfin/mach-bf548/Kconfig | |||
| @@ -11,6 +11,13 @@ config DEB_DMA_URGENT | |||
| 11 | help | 11 | help |
| 12 | Treat any DEB1, DEB2 and DEB3 request as Urgent | 12 | Treat any DEB1, DEB2 and DEB3 request as Urgent |
| 13 | 13 | ||
| 14 | config BF548_ATAPI_ALTERNATIVE_PORT | ||
| 15 | bool "BF548 ATAPI alternative port via GPIO" | ||
| 16 | help | ||
| 17 | BF548 ATAPI data and address PINs can be routed through | ||
| 18 | async address or GPIO port F and G. Select y to route it | ||
| 19 | to GPIO. | ||
| 20 | |||
| 14 | comment "Interrupt Priority Assignment" | 21 | comment "Interrupt Priority Assignment" |
| 15 | menu "Priority" | 22 | menu "Priority" |
| 16 | 23 | ||
| @@ -250,6 +257,7 @@ config IRQ_OTPSEC | |||
| 250 | default 11 | 257 | default 11 |
| 251 | config IRQ_TIMER0 | 258 | config IRQ_TIMER0 |
| 252 | int "IRQ_TIMER0" | 259 | int "IRQ_TIMER0" |
| 260 | default 7 if TICKSOURCE_GPTMR0 | ||
| 253 | default 8 | 261 | default 8 |
| 254 | config IRQ_TIMER1 | 262 | config IRQ_TIMER1 |
| 255 | int "IRQ_TIMER1" | 263 | int "IRQ_TIMER1" |
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c index f53ad682530b..f5a3c30a41bd 100644 --- a/arch/blackfin/mach-bf548/boards/cm_bf548.c +++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c | |||
| @@ -612,6 +612,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 612 | [1] = { | 612 | [1] = { |
| 613 | .start = CH_SPI0, | 613 | .start = CH_SPI0, |
| 614 | .end = CH_SPI0, | 614 | .end = CH_SPI0, |
| 615 | .flags = IORESOURCE_DMA, | ||
| 616 | }, | ||
| 617 | [2] = { | ||
| 618 | .start = IRQ_SPI0, | ||
| 619 | .end = IRQ_SPI0, | ||
| 615 | .flags = IORESOURCE_IRQ, | 620 | .flags = IORESOURCE_IRQ, |
| 616 | } | 621 | } |
| 617 | }; | 622 | }; |
| @@ -626,6 +631,11 @@ static struct resource bfin_spi1_resource[] = { | |||
| 626 | [1] = { | 631 | [1] = { |
| 627 | .start = CH_SPI1, | 632 | .start = CH_SPI1, |
| 628 | .end = CH_SPI1, | 633 | .end = CH_SPI1, |
| 634 | .flags = IORESOURCE_DMA, | ||
| 635 | }, | ||
| 636 | [2] = { | ||
| 637 | .start = IRQ_SPI1, | ||
| 638 | .end = IRQ_SPI1, | ||
| 629 | .flags = IORESOURCE_IRQ, | 639 | .flags = IORESOURCE_IRQ, |
| 630 | } | 640 | } |
| 631 | }; | 641 | }; |
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 096e661700a7..805a57b5e650 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c | |||
| @@ -208,6 +208,43 @@ static struct platform_device bfin_rotary_device = { | |||
| 208 | }; | 208 | }; |
| 209 | #endif | 209 | #endif |
| 210 | 210 | ||
| 211 | #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE) | ||
| 212 | #include <linux/input.h> | ||
| 213 | #include <linux/spi/adxl34x.h> | ||
| 214 | static const struct adxl34x_platform_data adxl34x_info = { | ||
| 215 | .x_axis_offset = 0, | ||
| 216 | .y_axis_offset = 0, | ||
| 217 | .z_axis_offset = 0, | ||
| 218 | .tap_threshold = 0x31, | ||
| 219 | .tap_duration = 0x10, | ||
| 220 | .tap_latency = 0x60, | ||
| 221 | .tap_window = 0xF0, | ||
| 222 | .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, | ||
| 223 | .act_axis_control = 0xFF, | ||
| 224 | .activity_threshold = 5, | ||
| 225 | .inactivity_threshold = 3, | ||
| 226 | .inactivity_time = 4, | ||
| 227 | .free_fall_threshold = 0x7, | ||
| 228 | .free_fall_time = 0x20, | ||
| 229 | .data_rate = 0x8, | ||
| 230 | .data_range = ADXL_FULL_RES, | ||
| 231 | |||
| 232 | .ev_type = EV_ABS, | ||
| 233 | .ev_code_x = ABS_X, /* EV_REL */ | ||
| 234 | .ev_code_y = ABS_Y, /* EV_REL */ | ||
| 235 | .ev_code_z = ABS_Z, /* EV_REL */ | ||
| 236 | |||
| 237 | .ev_code_tap_x = BTN_TOUCH, /* EV_KEY */ | ||
| 238 | .ev_code_tap_y = BTN_TOUCH, /* EV_KEY */ | ||
| 239 | .ev_code_tap_z = BTN_TOUCH, /* EV_KEY */ | ||
| 240 | |||
| 241 | /* .ev_code_ff = KEY_F,*/ /* EV_KEY */ | ||
| 242 | /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ | ||
| 243 | .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, | ||
| 244 | .fifo_mode = ADXL_FIFO_STREAM, | ||
| 245 | }; | ||
| 246 | #endif | ||
| 247 | |||
| 211 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | 248 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) |
| 212 | static struct platform_device rtc_device = { | 249 | static struct platform_device rtc_device = { |
| 213 | .name = "rtc-bfin", | 250 | .name = "rtc-bfin", |
| @@ -359,6 +396,8 @@ static struct platform_device bfin_sir3_device = { | |||
| 359 | #endif | 396 | #endif |
| 360 | 397 | ||
| 361 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | 398 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) |
| 399 | #include <linux/smsc911x.h> | ||
| 400 | |||
| 362 | static struct resource smsc911x_resources[] = { | 401 | static struct resource smsc911x_resources[] = { |
| 363 | { | 402 | { |
| 364 | .name = "smsc911x-memory", | 403 | .name = "smsc911x-memory", |
| @@ -372,11 +411,22 @@ static struct resource smsc911x_resources[] = { | |||
| 372 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | 411 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, |
| 373 | }, | 412 | }, |
| 374 | }; | 413 | }; |
| 414 | |||
| 415 | static struct smsc911x_platform_config smsc911x_config = { | ||
| 416 | .flags = SMSC911X_USE_32BIT, | ||
| 417 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | ||
| 418 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, | ||
| 419 | .phy_interface = PHY_INTERFACE_MODE_MII, | ||
| 420 | }; | ||
| 421 | |||
| 375 | static struct platform_device smsc911x_device = { | 422 | static struct platform_device smsc911x_device = { |
| 376 | .name = "smsc911x", | 423 | .name = "smsc911x", |
| 377 | .id = 0, | 424 | .id = 0, |
| 378 | .num_resources = ARRAY_SIZE(smsc911x_resources), | 425 | .num_resources = ARRAY_SIZE(smsc911x_resources), |
| 379 | .resource = smsc911x_resources, | 426 | .resource = smsc911x_resources, |
| 427 | .dev = { | ||
| 428 | .platform_data = &smsc911x_config, | ||
| 429 | }, | ||
| 380 | }; | 430 | }; |
| 381 | #endif | 431 | #endif |
| 382 | 432 | ||
| @@ -628,6 +678,14 @@ static struct bfin5xx_spi_chip spidev_chip_info = { | |||
| 628 | }; | 678 | }; |
| 629 | #endif | 679 | #endif |
| 630 | 680 | ||
| 681 | #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) | ||
| 682 | static struct bfin5xx_spi_chip spi_adxl34x_chip_info = { | ||
| 683 | .enable_dma = 0, /* use dma transfer with this chip*/ | ||
| 684 | .bits_per_word = 8, | ||
| 685 | .cs_change_per_word = 0, | ||
| 686 | }; | ||
| 687 | #endif | ||
| 688 | |||
| 631 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | 689 | static struct spi_board_info bfin_spi_board_info[] __initdata = { |
| 632 | #if defined(CONFIG_MTD_M25P80) \ | 690 | #if defined(CONFIG_MTD_M25P80) \ |
| 633 | || defined(CONFIG_MTD_M25P80_MODULE) | 691 | || defined(CONFIG_MTD_M25P80_MODULE) |
| @@ -653,15 +711,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 653 | }, | 711 | }, |
| 654 | #endif | 712 | #endif |
| 655 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | 713 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
| 656 | { | 714 | { |
| 657 | .modalias = "ad7877", | 715 | .modalias = "ad7877", |
| 658 | .platform_data = &bfin_ad7877_ts_info, | 716 | .platform_data = &bfin_ad7877_ts_info, |
| 659 | .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */ | 717 | .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */ |
| 660 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | 718 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ |
| 661 | .bus_num = 0, | 719 | .bus_num = 0, |
| 662 | .chip_select = 2, | 720 | .chip_select = 2, |
| 663 | .controller_data = &spi_ad7877_chip_info, | 721 | .controller_data = &spi_ad7877_chip_info, |
| 664 | }, | 722 | }, |
| 665 | #endif | 723 | #endif |
| 666 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | 724 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) |
| 667 | { | 725 | { |
| @@ -672,8 +730,19 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 672 | .controller_data = &spidev_chip_info, | 730 | .controller_data = &spidev_chip_info, |
| 673 | }, | 731 | }, |
| 674 | #endif | 732 | #endif |
| 733 | #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) | ||
| 734 | { | ||
| 735 | .modalias = "adxl34x", | ||
| 736 | .platform_data = &adxl34x_info, | ||
| 737 | .irq = IRQ_PC5, | ||
| 738 | .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ | ||
| 739 | .bus_num = 1, | ||
| 740 | .chip_select = 2, | ||
| 741 | .controller_data = &spi_adxl34x_chip_info, | ||
| 742 | .mode = SPI_MODE_3, | ||
| 743 | }, | ||
| 744 | #endif | ||
| 675 | }; | 745 | }; |
| 676 | |||
| 677 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | 746 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
| 678 | /* SPI (0) */ | 747 | /* SPI (0) */ |
| 679 | static struct resource bfin_spi0_resource[] = { | 748 | static struct resource bfin_spi0_resource[] = { |
| @@ -685,6 +754,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 685 | [1] = { | 754 | [1] = { |
| 686 | .start = CH_SPI0, | 755 | .start = CH_SPI0, |
| 687 | .end = CH_SPI0, | 756 | .end = CH_SPI0, |
| 757 | .flags = IORESOURCE_DMA, | ||
| 758 | }, | ||
| 759 | [2] = { | ||
| 760 | .start = IRQ_SPI0, | ||
| 761 | .end = IRQ_SPI0, | ||
| 688 | .flags = IORESOURCE_IRQ, | 762 | .flags = IORESOURCE_IRQ, |
| 689 | } | 763 | } |
| 690 | }; | 764 | }; |
| @@ -699,6 +773,11 @@ static struct resource bfin_spi1_resource[] = { | |||
| 699 | [1] = { | 773 | [1] = { |
| 700 | .start = CH_SPI1, | 774 | .start = CH_SPI1, |
| 701 | .end = CH_SPI1, | 775 | .end = CH_SPI1, |
| 776 | .flags = IORESOURCE_DMA, | ||
| 777 | }, | ||
| 778 | [2] = { | ||
| 779 | .start = IRQ_SPI1, | ||
| 780 | .end = IRQ_SPI1, | ||
| 702 | .flags = IORESOURCE_IRQ, | 781 | .flags = IORESOURCE_IRQ, |
| 703 | } | 782 | } |
| 704 | }; | 783 | }; |
| @@ -786,7 +865,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info0[] = { | |||
| 786 | 865 | ||
| 787 | #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ | 866 | #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ |
| 788 | static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { | 867 | static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { |
| 789 | #if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) | 868 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) |
| 790 | { | 869 | { |
| 791 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 870 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
| 792 | }, | 871 | }, |
| @@ -797,6 +876,13 @@ static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { | |||
| 797 | .irq = 212, | 876 | .irq = 212, |
| 798 | }, | 877 | }, |
| 799 | #endif | 878 | #endif |
| 879 | #if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE) | ||
| 880 | { | ||
| 881 | I2C_BOARD_INFO("adxl34x", 0x53), | ||
| 882 | .irq = IRQ_PC5, | ||
| 883 | .platform_data = (void *)&adxl34x_info, | ||
| 884 | }, | ||
| 885 | #endif | ||
| 800 | }; | 886 | }; |
| 801 | #endif | 887 | #endif |
| 802 | 888 | ||
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index 882e40ccf0d1..c510ae688e28 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h | |||
| @@ -6,26 +6,31 @@ | |||
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file shoule be up to date with: | 9 | /* This file should be up to date with: |
| 10 | * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List | 10 | * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #ifndef _MACH_ANOMALY_H_ | 13 | #ifndef _MACH_ANOMALY_H_ |
| 14 | #define _MACH_ANOMALY_H_ | 14 | #define _MACH_ANOMALY_H_ |
| 15 | 15 | ||
| 16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | 16 | /* We do not support 0.0 or 0.1 silicon - sorry */ |
| 17 | #if __SILICON_REVISION__ < 2 | ||
| 18 | # error will not work on BF548 silicon version 0.0, or 0.1 | ||
| 19 | #endif | ||
| 20 | |||
| 21 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ | ||
| 17 | #define ANOMALY_05000074 (1) | 22 | #define ANOMALY_05000074 (1) |
| 18 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | 23 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
| 19 | #define ANOMALY_05000119 (1) | 24 | #define ANOMALY_05000119 (1) |
| 20 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 25 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 21 | #define ANOMALY_05000122 (1) | 26 | #define ANOMALY_05000122 (1) |
| 22 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | 27 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
| 23 | #define ANOMALY_05000245 (1) | 28 | #define ANOMALY_05000245 (1) |
| 24 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | 29 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
| 25 | #define ANOMALY_05000265 (1) | 30 | #define ANOMALY_05000265 (1) |
| 26 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | 31 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ |
| 27 | #define ANOMALY_05000272 (1) | 32 | #define ANOMALY_05000272 (1) |
| 28 | /* False Hardware Error Exception when ISR context is not restored */ | 33 | /* False Hardware Error Exception When ISR Context Is Not Restored */ |
| 29 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) | 34 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) |
| 30 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ | 35 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ |
| 31 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) | 36 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) |
| @@ -59,7 +64,7 @@ | |||
| 59 | #define ANOMALY_05000340 (__SILICON_REVISION__ < 1) | 64 | #define ANOMALY_05000340 (__SILICON_REVISION__ < 1) |
| 60 | /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ | 65 | /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ |
| 61 | #define ANOMALY_05000344 (__SILICON_REVISION__ < 1) | 66 | #define ANOMALY_05000344 (__SILICON_REVISION__ < 1) |
| 62 | /* USB Calibration Value Is Not Intialized */ | 67 | /* USB Calibration Value Is Not Initialized */ |
| 63 | #define ANOMALY_05000346 (__SILICON_REVISION__ < 1) | 68 | #define ANOMALY_05000346 (__SILICON_REVISION__ < 1) |
| 64 | /* USB Calibration Value to use */ | 69 | /* USB Calibration Value to use */ |
| 65 | #define ANOMALY_05000346_value 0x5411 | 70 | #define ANOMALY_05000346_value 0x5411 |
| @@ -147,11 +152,11 @@ | |||
| 147 | #define ANOMALY_05000416 (1) | 152 | #define ANOMALY_05000416 (1) |
| 148 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ | 153 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ |
| 149 | #define ANOMALY_05000425 (1) | 154 | #define ANOMALY_05000425 (1) |
| 150 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */ | 155 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ |
| 151 | #define ANOMALY_05000426 (1) | 156 | #define ANOMALY_05000426 (1) |
| 152 | /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ | 157 | /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ |
| 153 | #define ANOMALY_05000427 (__SILICON_REVISION__ < 2) | 158 | #define ANOMALY_05000427 (__SILICON_REVISION__ < 2) |
| 154 | /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */ | 159 | /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ |
| 155 | #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) | 160 | #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) |
| 156 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ | 161 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ |
| 157 | #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) | 162 | #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) |
| @@ -170,26 +175,49 @@ | |||
| 170 | /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ | 175 | /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ |
| 171 | #define ANOMALY_05000449 (__SILICON_REVISION__ == 1) | 176 | #define ANOMALY_05000449 (__SILICON_REVISION__ == 1) |
| 172 | /* USB DMA Mode 1 Short Packet Data Corruption */ | 177 | /* USB DMA Mode 1 Short Packet Data Corruption */ |
| 173 | #define ANOMALY_05000450 (1 | 178 | #define ANOMALY_05000450 (1) |
| 179 | /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ | ||
| 180 | #define ANOMALY_05000456 (__SILICON_REVISION__ < 3) | ||
| 181 | /* False Hardware Error when RETI points to invalid memory */ | ||
| 182 | #define ANOMALY_05000461 (1) | ||
| 174 | 183 | ||
| 175 | /* Anomalies that don't exist on this proc */ | 184 | /* Anomalies that don't exist on this proc */ |
| 185 | #define ANOMALY_05000099 (0) | ||
| 186 | #define ANOMALY_05000120 (0) | ||
| 176 | #define ANOMALY_05000125 (0) | 187 | #define ANOMALY_05000125 (0) |
| 188 | #define ANOMALY_05000149 (0) | ||
| 177 | #define ANOMALY_05000158 (0) | 189 | #define ANOMALY_05000158 (0) |
| 190 | #define ANOMALY_05000171 (0) | ||
| 191 | #define ANOMALY_05000179 (0) | ||
| 178 | #define ANOMALY_05000183 (0) | 192 | #define ANOMALY_05000183 (0) |
| 179 | #define ANOMALY_05000198 (0) | 193 | #define ANOMALY_05000198 (0) |
| 194 | #define ANOMALY_05000215 (0) | ||
| 195 | #define ANOMALY_05000220 (0) | ||
| 196 | #define ANOMALY_05000227 (0) | ||
| 180 | #define ANOMALY_05000230 (0) | 197 | #define ANOMALY_05000230 (0) |
| 198 | #define ANOMALY_05000231 (0) | ||
| 199 | #define ANOMALY_05000233 (0) | ||
| 200 | #define ANOMALY_05000242 (0) | ||
| 181 | #define ANOMALY_05000244 (0) | 201 | #define ANOMALY_05000244 (0) |
| 202 | #define ANOMALY_05000248 (0) | ||
| 203 | #define ANOMALY_05000250 (0) | ||
| 204 | #define ANOMALY_05000254 (0) | ||
| 182 | #define ANOMALY_05000261 (0) | 205 | #define ANOMALY_05000261 (0) |
| 183 | #define ANOMALY_05000263 (0) | 206 | #define ANOMALY_05000263 (0) |
| 184 | #define ANOMALY_05000266 (0) | 207 | #define ANOMALY_05000266 (0) |
| 185 | #define ANOMALY_05000273 (0) | 208 | #define ANOMALY_05000273 (0) |
| 209 | #define ANOMALY_05000274 (0) | ||
| 186 | #define ANOMALY_05000278 (0) | 210 | #define ANOMALY_05000278 (0) |
| 211 | #define ANOMALY_05000287 (0) | ||
| 212 | #define ANOMALY_05000301 (0) | ||
| 187 | #define ANOMALY_05000305 (0) | 213 | #define ANOMALY_05000305 (0) |
| 188 | #define ANOMALY_05000307 (0) | 214 | #define ANOMALY_05000307 (0) |
| 189 | #define ANOMALY_05000311 (0) | 215 | #define ANOMALY_05000311 (0) |
| 190 | #define ANOMALY_05000323 (0) | 216 | #define ANOMALY_05000323 (0) |
| 217 | #define ANOMALY_05000362 (1) | ||
| 191 | #define ANOMALY_05000363 (0) | 218 | #define ANOMALY_05000363 (0) |
| 192 | #define ANOMALY_05000380 (0) | 219 | #define ANOMALY_05000380 (0) |
| 220 | #define ANOMALY_05000400 (0) | ||
| 193 | #define ANOMALY_05000412 (0) | 221 | #define ANOMALY_05000412 (0) |
| 194 | #define ANOMALY_05000432 (0) | 222 | #define ANOMALY_05000432 (0) |
| 195 | #define ANOMALY_05000435 (0) | 223 | #define ANOMALY_05000435 (0) |
diff --git a/arch/blackfin/mach-bf548/include/mach/portmux.h b/arch/blackfin/mach-bf548/include/mach/portmux.h index ffb1d0a44b4d..ce372ba0f046 100644 --- a/arch/blackfin/mach-bf548/include/mach/portmux.h +++ b/arch/blackfin/mach-bf548/include/mach/portmux.h | |||
| @@ -167,22 +167,42 @@ | |||
| 167 | #define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) | 167 | #define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) |
| 168 | #define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) | 168 | #define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) |
| 169 | #define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) | 169 | #define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) |
| 170 | #define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) | 170 | |
| 171 | #define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) | 171 | #ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT |
| 172 | #define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) | 172 | # define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) |
| 173 | #define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) | 173 | # define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) |
| 174 | #define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) | 174 | # define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) |
| 175 | #define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) | 175 | # define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) |
| 176 | #define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) | 176 | # define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) |
| 177 | #define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) | 177 | # define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) |
| 178 | #define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) | 178 | # define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) |
| 179 | #define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) | 179 | # define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) |
| 180 | #define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) | 180 | # define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) |
| 181 | #define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) | 181 | # define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) |
| 182 | #define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) | 182 | # define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) |
| 183 | #define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) | 183 | # define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) |
| 184 | #define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) | 184 | # define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) |
| 185 | #define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) | 185 | # define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) |
| 186 | # define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) | ||
| 187 | # define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) | ||
| 188 | #else | ||
| 189 | # define P_ATAPI_D0A (P_DONTCARE) | ||
| 190 | # define P_ATAPI_D1A (P_DONTCARE) | ||
| 191 | # define P_ATAPI_D2A (P_DONTCARE) | ||
| 192 | # define P_ATAPI_D3A (P_DONTCARE) | ||
| 193 | # define P_ATAPI_D4A (P_DONTCARE) | ||
| 194 | # define P_ATAPI_D5A (P_DONTCARE) | ||
| 195 | # define P_ATAPI_D6A (P_DONTCARE) | ||
| 196 | # define P_ATAPI_D7A (P_DONTCARE) | ||
| 197 | # define P_ATAPI_D8A (P_DONTCARE) | ||
| 198 | # define P_ATAPI_D9A (P_DONTCARE) | ||
| 199 | # define P_ATAPI_D10A (P_DONTCARE) | ||
| 200 | # define P_ATAPI_D11A (P_DONTCARE) | ||
| 201 | # define P_ATAPI_D12A (P_DONTCARE) | ||
| 202 | # define P_ATAPI_D13A (P_DONTCARE) | ||
| 203 | # define P_ATAPI_D14A (P_DONTCARE) | ||
| 204 | # define P_ATAPI_D15A (P_DONTCARE) | ||
| 205 | #endif | ||
| 186 | 206 | ||
| 187 | #define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) | 207 | #define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) |
| 188 | #define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) | 208 | #define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) |
| @@ -200,9 +220,15 @@ | |||
| 200 | #define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) | 220 | #define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) |
| 201 | #define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) | 221 | #define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) |
| 202 | #define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) | 222 | #define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) |
| 203 | #define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1)) | 223 | #ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT |
| 204 | #define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) | 224 | # define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1)) |
| 205 | #define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) | 225 | # define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) |
| 226 | # define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) | ||
| 227 | #else | ||
| 228 | # define P_ATAPI_A0A (P_DONTCARE) | ||
| 229 | # define P_ATAPI_A1A (P_DONTCARE) | ||
| 230 | # define P_ATAPI_A2A (P_DONTCARE) | ||
| 231 | #endif | ||
| 206 | #define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) | 232 | #define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) |
| 207 | #define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) | 233 | #define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) |
| 208 | #define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) | 234 | #define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) |
diff --git a/arch/blackfin/mach-bf561/Kconfig b/arch/blackfin/mach-bf561/Kconfig index 638ec38ca470..cb9743641511 100644 --- a/arch/blackfin/mach-bf561/Kconfig +++ b/arch/blackfin/mach-bf561/Kconfig | |||
| @@ -9,22 +9,9 @@ if (!SMP) | |||
| 9 | comment "Core B Support" | 9 | comment "Core B Support" |
| 10 | 10 | ||
| 11 | config BF561_COREB | 11 | config BF561_COREB |
| 12 | bool "Enable Core B support" | 12 | bool "Enable Core B loader" |
| 13 | default y | 13 | default y |
| 14 | 14 | ||
| 15 | config BF561_COREB_RESET | ||
| 16 | bool "Enable Core B reset support" | ||
| 17 | default n | ||
| 18 | help | ||
| 19 | This requires code in the application that is loaded | ||
| 20 | into Core B. In order to reset, the application needs | ||
| 21 | to install an interrupt handler for Supplemental | ||
| 22 | Interrupt 0, that sets RETI to 0xff600000 and writes | ||
| 23 | bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. | ||
| 24 | This causes Core B to stall when Supplemental Interrupt | ||
| 25 | 0 is set, and will reset PC to 0xff600000 when | ||
| 26 | COREB_SRAM_INIT is cleared. | ||
| 27 | |||
| 28 | endif | 15 | endif |
| 29 | 16 | ||
| 30 | comment "Interrupt Priority Assignment" | 17 | comment "Interrupt Priority Assignment" |
| @@ -138,6 +125,7 @@ config IRQ_DMA2_11 | |||
| 138 | default 9 | 125 | default 9 |
| 139 | config IRQ_TIMER0 | 126 | config IRQ_TIMER0 |
| 140 | int "TIMER 0 Interrupt" | 127 | int "TIMER 0 Interrupt" |
| 128 | default 7 if TICKSOURCE_GPTMR0 | ||
| 141 | default 8 | 129 | default 8 |
| 142 | config IRQ_TIMER1 | 130 | config IRQ_TIMER1 |
| 143 | int "TIMER 1 Interrupt" | 131 | int "TIMER 1 Interrupt" |
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index f623c6b0719f..0c9d72c5f5ba 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c | |||
| @@ -83,7 +83,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 83 | }; | 83 | }; |
| 84 | #endif | 84 | #endif |
| 85 | 85 | ||
| 86 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 86 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 87 | /* SPI ADC chip */ | 87 | /* SPI ADC chip */ |
| 88 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | 88 | static struct bfin5xx_spi_chip spi_adc_chip_info = { |
| 89 | .enable_dma = 1, /* use dma transfer with this chip*/ | 89 | .enable_dma = 1, /* use dma transfer with this chip*/ |
| @@ -126,7 +126,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 126 | }, | 126 | }, |
| 127 | #endif | 127 | #endif |
| 128 | 128 | ||
| 129 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | 129 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
| 130 | { | 130 | { |
| 131 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | 131 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ |
| 132 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | 132 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ |
| @@ -177,8 +177,13 @@ static struct resource bfin_spi0_resource[] = { | |||
| 177 | [1] = { | 177 | [1] = { |
| 178 | .start = CH_SPI, | 178 | .start = CH_SPI, |
| 179 | .end = CH_SPI, | 179 | .end = CH_SPI, |
| 180 | .flags = IORESOURCE_DMA, | ||
| 181 | }, | ||
| 182 | [2] = { | ||
| 183 | .start = IRQ_SPI, | ||
| 184 | .end = IRQ_SPI, | ||
| 180 | .flags = IORESOURCE_IRQ, | 185 | .flags = IORESOURCE_IRQ, |
| 181 | } | 186 | }, |
| 182 | }; | 187 | }; |
| 183 | 188 | ||
| 184 | /* SPI controller data */ | 189 | /* SPI controller data */ |
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 0e2178a1aec5..b5ef7ff7b7bd 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c | |||
| @@ -304,6 +304,11 @@ static struct resource bfin_spi0_resource[] = { | |||
| 304 | [1] = { | 304 | [1] = { |
| 305 | .start = CH_SPI, | 305 | .start = CH_SPI, |
| 306 | .end = CH_SPI, | 306 | .end = CH_SPI, |
| 307 | .flags = IORESOURCE_DMA, | ||
| 308 | }, | ||
| 309 | [2] = { | ||
| 310 | .start = IRQ_SPI, | ||
| 311 | .end = IRQ_SPI, | ||
| 307 | .flags = IORESOURCE_IRQ, | 312 | .flags = IORESOURCE_IRQ, |
| 308 | } | 313 | } |
| 309 | }; | 314 | }; |
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c index 8598098c0840..93635a766f9c 100644 --- a/arch/blackfin/mach-bf561/coreb.c +++ b/arch/blackfin/mach-bf561/coreb.c | |||
| @@ -1,406 +1,74 @@ | |||
| 1 | /* | 1 | /* Load firmware into Core B on a BF561 |
| 2 | * File: arch/blackfin/mach-bf561/coreb.c | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | 2 | * |
| 6 | * Created: | 3 | * Copyright 2004-2009 Analog Devices Inc. |
| 7 | * Description: Handle CoreB on a BF561 | 4 | * Licensed under the GPL-2 or later. |
| 8 | * | 5 | */ |
| 9 | * Modified: | 6 | |
| 10 | * Copyright 2004-2006 Analog Devices Inc. | 7 | /* The Core B reset func requires code in the application that is loaded into |
| 11 | * | 8 | * Core B. In order to reset, the application needs to install an interrupt |
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 9 | * handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and |
| 13 | * | 10 | * writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core |
| 14 | * This program is free software; you can redistribute it and/or modify | 11 | * B to stall when Supplemental Interrupt 0 is set, and will reset PC to |
| 15 | * it under the terms of the GNU General Public License as published by | 12 | * 0xff600000 when COREB_SRAM_INIT is cleared. |
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | 13 | */ |
| 29 | 14 | ||
| 30 | #include <linux/mm.h> | ||
| 31 | #include <linux/miscdevice.h> | ||
| 32 | #include <linux/device.h> | 15 | #include <linux/device.h> |
| 33 | #include <linux/ioport.h> | ||
| 34 | #include <linux/module.h> | ||
| 35 | #include <linux/uaccess.h> | ||
| 36 | #include <linux/fs.h> | 16 | #include <linux/fs.h> |
| 37 | #include <asm/dma.h> | 17 | #include <linux/kernel.h> |
| 38 | #include <asm/cacheflush.h> | 18 | #include <linux/miscdevice.h> |
| 39 | 19 | #include <linux/module.h> | |
| 40 | #define MODULE_VER "v0.1" | ||
| 41 | |||
| 42 | static spinlock_t coreb_lock; | ||
| 43 | static wait_queue_head_t coreb_dma_wait; | ||
| 44 | |||
| 45 | #define COREB_IS_OPEN 0x00000001 | ||
| 46 | #define COREB_IS_RUNNING 0x00000010 | ||
| 47 | 20 | ||
| 48 | #define CMD_COREB_INDEX 1 | ||
| 49 | #define CMD_COREB_START 2 | 21 | #define CMD_COREB_START 2 |
| 50 | #define CMD_COREB_STOP 3 | 22 | #define CMD_COREB_STOP 3 |
| 51 | #define CMD_COREB_RESET 4 | 23 | #define CMD_COREB_RESET 4 |
| 52 | 24 | ||
| 53 | #define COREB_MINOR 229 | 25 | static int |
| 54 | 26 | coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) | |
| 55 | static unsigned long coreb_status = 0; | ||
| 56 | static unsigned long coreb_base = 0xff600000; | ||
| 57 | static unsigned long coreb_size = 0x4000; | ||
| 58 | int coreb_dma_done; | ||
| 59 | |||
| 60 | static loff_t coreb_lseek(struct file *file, loff_t offset, int origin); | ||
| 61 | static ssize_t coreb_read(struct file *file, char *buf, size_t count, | ||
| 62 | loff_t * ppos); | ||
| 63 | static ssize_t coreb_write(struct file *file, const char *buf, size_t count, | ||
| 64 | loff_t * ppos); | ||
| 65 | static int coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | ||
| 66 | unsigned long arg); | ||
| 67 | static int coreb_open(struct inode *inode, struct file *file); | ||
| 68 | static int coreb_release(struct inode *inode, struct file *file); | ||
| 69 | |||
| 70 | static irqreturn_t coreb_dma_interrupt(int irq, void *dev_id) | ||
| 71 | { | ||
| 72 | clear_dma_irqstat(CH_MEM_STREAM2_DEST); | ||
| 73 | coreb_dma_done = 1; | ||
| 74 | wake_up_interruptible(&coreb_dma_wait); | ||
| 75 | return IRQ_HANDLED; | ||
| 76 | } | ||
| 77 | |||
| 78 | static ssize_t coreb_write(struct file *file, const char *buf, size_t count, | ||
| 79 | loff_t * ppos) | ||
| 80 | { | ||
| 81 | unsigned long p = *ppos; | ||
| 82 | ssize_t wrote = 0; | ||
| 83 | |||
| 84 | if (p + count > coreb_size) | ||
| 85 | return -EFAULT; | ||
| 86 | |||
| 87 | while (count > 0) { | ||
| 88 | int len = count; | ||
| 89 | |||
| 90 | if (len > PAGE_SIZE) | ||
| 91 | len = PAGE_SIZE; | ||
| 92 | |||
| 93 | coreb_dma_done = 0; | ||
| 94 | |||
| 95 | flush_dcache_range((unsigned long)buf, (unsigned long)(buf+len)); | ||
| 96 | /* Source Channel */ | ||
| 97 | set_dma_start_addr(CH_MEM_STREAM2_SRC, (unsigned long)buf); | ||
| 98 | set_dma_x_count(CH_MEM_STREAM2_SRC, len); | ||
| 99 | set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char)); | ||
| 100 | set_dma_config(CH_MEM_STREAM2_SRC, 0); | ||
| 101 | /* Destination Channel */ | ||
| 102 | set_dma_start_addr(CH_MEM_STREAM2_DEST, coreb_base + p); | ||
| 103 | set_dma_x_count(CH_MEM_STREAM2_DEST, len); | ||
| 104 | set_dma_x_modify(CH_MEM_STREAM2_DEST, sizeof(char)); | ||
| 105 | set_dma_config(CH_MEM_STREAM2_DEST, WNR | RESTART | DI_EN); | ||
| 106 | |||
| 107 | enable_dma(CH_MEM_STREAM2_SRC); | ||
| 108 | enable_dma(CH_MEM_STREAM2_DEST); | ||
| 109 | |||
| 110 | wait_event_interruptible(coreb_dma_wait, coreb_dma_done); | ||
| 111 | |||
| 112 | disable_dma(CH_MEM_STREAM2_SRC); | ||
| 113 | disable_dma(CH_MEM_STREAM2_DEST); | ||
| 114 | |||
| 115 | count -= len; | ||
| 116 | wrote += len; | ||
| 117 | buf += len; | ||
| 118 | p += len; | ||
| 119 | } | ||
| 120 | *ppos = p; | ||
| 121 | return wrote; | ||
| 122 | } | ||
| 123 | |||
| 124 | static ssize_t coreb_read(struct file *file, char *buf, size_t count, | ||
| 125 | loff_t * ppos) | ||
| 126 | { | ||
| 127 | unsigned long p = *ppos; | ||
| 128 | ssize_t read = 0; | ||
| 129 | |||
| 130 | if ((p + count) > coreb_size) | ||
| 131 | return -EFAULT; | ||
| 132 | |||
| 133 | while (count > 0) { | ||
| 134 | int len = count; | ||
| 135 | |||
| 136 | if (len > PAGE_SIZE) | ||
| 137 | len = PAGE_SIZE; | ||
| 138 | |||
| 139 | coreb_dma_done = 0; | ||
| 140 | |||
| 141 | invalidate_dcache_range((unsigned long)buf, (unsigned long)(buf+len)); | ||
| 142 | /* Source Channel */ | ||
| 143 | set_dma_start_addr(CH_MEM_STREAM2_SRC, coreb_base + p); | ||
| 144 | set_dma_x_count(CH_MEM_STREAM2_SRC, len); | ||
| 145 | set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char)); | ||
| 146 | set_dma_config(CH_MEM_STREAM2_SRC, 0); | ||
| 147 | /* Destination Channel */ | ||
| 148 | set_dma_start_addr(CH_MEM_STREAM2_DEST, (unsigned long)buf); | ||
| 149 | set_dma_x_count(CH_MEM_STREAM2_DEST, len); | ||
| 150 | set_dma_x_modify(CH_MEM_STREAM2_DEST, sizeof(char)); | ||
| 151 | set_dma_config(CH_MEM_STREAM2_DEST, WNR | RESTART | DI_EN); | ||
| 152 | |||
| 153 | enable_dma(CH_MEM_STREAM2_SRC); | ||
| 154 | enable_dma(CH_MEM_STREAM2_DEST); | ||
| 155 | |||
| 156 | wait_event_interruptible(coreb_dma_wait, coreb_dma_done); | ||
| 157 | |||
| 158 | disable_dma(CH_MEM_STREAM2_SRC); | ||
| 159 | disable_dma(CH_MEM_STREAM2_DEST); | ||
| 160 | |||
| 161 | count -= len; | ||
| 162 | read += len; | ||
| 163 | buf += len; | ||
| 164 | p += len; | ||
| 165 | } | ||
| 166 | |||
| 167 | return read; | ||
| 168 | } | ||
| 169 | |||
| 170 | static loff_t coreb_lseek(struct file *file, loff_t offset, int origin) | ||
| 171 | { | 27 | { |
| 172 | loff_t ret; | 28 | int ret = 0; |
| 173 | |||
| 174 | mutex_lock(&file->f_dentry->d_inode->i_mutex); | ||
| 175 | |||
| 176 | switch (origin) { | ||
| 177 | case 0 /* SEEK_SET */ : | ||
| 178 | if (offset < coreb_size) { | ||
| 179 | file->f_pos = offset; | ||
| 180 | ret = file->f_pos; | ||
| 181 | } else | ||
| 182 | ret = -EINVAL; | ||
| 183 | break; | ||
| 184 | case 1 /* SEEK_CUR */ : | ||
| 185 | if ((offset + file->f_pos) < coreb_size) { | ||
| 186 | file->f_pos += offset; | ||
| 187 | ret = file->f_pos; | ||
| 188 | } else | ||
| 189 | ret = -EINVAL; | ||
| 190 | default: | ||
| 191 | ret = -EINVAL; | ||
| 192 | } | ||
| 193 | mutex_unlock(&file->f_dentry->d_inode->i_mutex); | ||
| 194 | return ret; | ||
| 195 | } | ||
| 196 | |||
| 197 | /* No BKL needed here */ | ||
| 198 | static int coreb_open(struct inode *inode, struct file *file) | ||
| 199 | { | ||
| 200 | spin_lock_irq(&coreb_lock); | ||
| 201 | |||
| 202 | if (coreb_status & COREB_IS_OPEN) | ||
| 203 | goto out_busy; | ||
| 204 | |||
| 205 | coreb_status |= COREB_IS_OPEN; | ||
| 206 | |||
| 207 | spin_unlock_irq(&coreb_lock); | ||
| 208 | return 0; | ||
| 209 | |||
| 210 | out_busy: | ||
| 211 | spin_unlock_irq(&coreb_lock); | ||
| 212 | return -EBUSY; | ||
| 213 | } | ||
| 214 | |||
| 215 | static int coreb_release(struct inode *inode, struct file *file) | ||
| 216 | { | ||
| 217 | spin_lock_irq(&coreb_lock); | ||
| 218 | coreb_status &= ~COREB_IS_OPEN; | ||
| 219 | spin_unlock_irq(&coreb_lock); | ||
| 220 | return 0; | ||
| 221 | } | ||
| 222 | |||
| 223 | static int coreb_ioctl(struct inode *inode, struct file *file, | ||
| 224 | unsigned int cmd, unsigned long arg) | ||
| 225 | { | ||
| 226 | int retval = 0; | ||
| 227 | int coreb_index = 0; | ||
| 228 | 29 | ||
| 229 | switch (cmd) { | 30 | switch (cmd) { |
| 230 | case CMD_COREB_INDEX: | ||
| 231 | if (copy_from_user(&coreb_index, (int *)arg, sizeof(int))) { | ||
| 232 | retval = -EFAULT; | ||
| 233 | break; | ||
| 234 | } | ||
| 235 | |||
| 236 | spin_lock_irq(&coreb_lock); | ||
| 237 | switch (coreb_index) { | ||
| 238 | case 0: | ||
| 239 | coreb_base = 0xff600000; | ||
| 240 | coreb_size = 0x4000; | ||
| 241 | break; | ||
| 242 | case 1: | ||
| 243 | coreb_base = 0xff610000; | ||
| 244 | coreb_size = 0x4000; | ||
| 245 | break; | ||
| 246 | case 2: | ||
| 247 | coreb_base = 0xff500000; | ||
| 248 | coreb_size = 0x8000; | ||
| 249 | break; | ||
| 250 | case 3: | ||
| 251 | coreb_base = 0xff400000; | ||
| 252 | coreb_size = 0x8000; | ||
| 253 | break; | ||
| 254 | default: | ||
| 255 | retval = -EINVAL; | ||
| 256 | break; | ||
| 257 | } | ||
| 258 | spin_unlock_irq(&coreb_lock); | ||
| 259 | |||
| 260 | mutex_lock(&file->f_dentry->d_inode->i_mutex); | ||
| 261 | file->f_pos = 0; | ||
| 262 | mutex_unlock(&file->f_dentry->d_inode->i_mutex); | ||
| 263 | break; | ||
| 264 | case CMD_COREB_START: | 31 | case CMD_COREB_START: |
| 265 | spin_lock_irq(&coreb_lock); | ||
| 266 | if (coreb_status & COREB_IS_RUNNING) { | ||
| 267 | retval = -EBUSY; | ||
| 268 | break; | ||
| 269 | } | ||
| 270 | printk(KERN_INFO "Starting Core B\n"); | ||
| 271 | coreb_status |= COREB_IS_RUNNING; | ||
| 272 | bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020); | 32 | bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020); |
| 273 | SSYNC(); | ||
| 274 | spin_unlock_irq(&coreb_lock); | ||
| 275 | break; | 33 | break; |
| 276 | #if defined(CONFIG_BF561_COREB_RESET) | ||
| 277 | case CMD_COREB_STOP: | 34 | case CMD_COREB_STOP: |
| 278 | spin_lock_irq(&coreb_lock); | ||
| 279 | printk(KERN_INFO "Stopping Core B\n"); | ||
| 280 | bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020); | 35 | bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020); |
| 281 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); | 36 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); |
| 282 | coreb_status &= ~COREB_IS_RUNNING; | ||
| 283 | spin_unlock_irq(&coreb_lock); | ||
| 284 | break; | 37 | break; |
| 285 | case CMD_COREB_RESET: | 38 | case CMD_COREB_RESET: |
| 286 | printk(KERN_INFO "Resetting Core B\n"); | ||
| 287 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); | 39 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); |
| 288 | break; | 40 | break; |
| 289 | #endif | 41 | default: |
| 42 | ret = -EINVAL; | ||
| 43 | break; | ||
| 290 | } | 44 | } |
| 291 | 45 | ||
| 292 | return retval; | 46 | CSYNC(); |
| 47 | |||
| 48 | return ret; | ||
| 293 | } | 49 | } |
| 294 | 50 | ||
| 295 | static struct file_operations coreb_fops = { | 51 | static struct file_operations coreb_fops = { |
| 296 | .owner = THIS_MODULE, | 52 | .owner = THIS_MODULE, |
| 297 | .llseek = coreb_lseek, | 53 | .ioctl = coreb_ioctl, |
| 298 | .read = coreb_read, | ||
| 299 | .write = coreb_write, | ||
| 300 | .ioctl = coreb_ioctl, | ||
| 301 | .open = coreb_open, | ||
| 302 | .release = coreb_release | ||
| 303 | }; | 54 | }; |
| 304 | 55 | ||
| 305 | static struct miscdevice coreb_dev = { | 56 | static struct miscdevice coreb_dev = { |
| 306 | COREB_MINOR, | 57 | .minor = MISC_DYNAMIC_MINOR, |
| 307 | "coreb", | 58 | .name = "coreb", |
| 308 | &coreb_fops | 59 | .fops = &coreb_fops, |
| 309 | }; | 60 | }; |
| 310 | 61 | ||
| 311 | static ssize_t coreb_show_status(struct device *dev, struct device_attribute *attr, char *buf) | 62 | static int __init bf561_coreb_init(void) |
| 312 | { | 63 | { |
| 313 | return sprintf(buf, | 64 | return misc_register(&coreb_dev); |
| 314 | "Base Address:\t0x%08lx\n" | ||
| 315 | "Core B is %s\n" | ||
| 316 | "SICA_SYSCR:\t%04x\n" | ||
| 317 | "SICB_SYSCR:\t%04x\n" | ||
| 318 | "\n" | ||
| 319 | "IRQ Status:\tCore A\t\tCore B\n" | ||
| 320 | "ISR0:\t\t%08x\t\t%08x\n" | ||
| 321 | "ISR1:\t\t%08x\t\t%08x\n" | ||
| 322 | "IMASK0:\t\t%08x\t\t%08x\n" | ||
| 323 | "IMASK1:\t\t%08x\t\t%08x\n", | ||
| 324 | coreb_base, | ||
| 325 | coreb_status & COREB_IS_RUNNING ? "running" : "stalled", | ||
| 326 | bfin_read_SICA_SYSCR(), bfin_read_SICB_SYSCR(), | ||
| 327 | bfin_read_SICA_ISR0(), bfin_read_SICB_ISR0(), | ||
| 328 | bfin_read_SICA_ISR1(), bfin_read_SICB_ISR0(), | ||
| 329 | bfin_read_SICA_IMASK0(), bfin_read_SICB_IMASK0(), | ||
| 330 | bfin_read_SICA_IMASK1(), bfin_read_SICB_IMASK1()); | ||
| 331 | } | ||
| 332 | |||
| 333 | static DEVICE_ATTR(coreb_status, S_IRUGO, coreb_show_status, NULL); | ||
| 334 | |||
| 335 | int __init bf561_coreb_init(void) | ||
| 336 | { | ||
| 337 | init_waitqueue_head(&coreb_dma_wait); | ||
| 338 | |||
| 339 | spin_lock_init(&coreb_lock); | ||
| 340 | /* Request the core memory regions for Core B */ | ||
| 341 | if (request_mem_region(0xff600000, 0x4000, | ||
| 342 | "Core B - Instruction SRAM") == NULL) | ||
| 343 | goto exit; | ||
| 344 | |||
| 345 | if (request_mem_region(0xFF610000, 0x4000, | ||
| 346 | "Core B - Instruction SRAM") == NULL) | ||
| 347 | goto release_instruction_a_sram; | ||
| 348 | |||
| 349 | if (request_mem_region(0xFF500000, 0x8000, | ||
| 350 | "Core B - Data Bank B SRAM") == NULL) | ||
| 351 | goto release_instruction_b_sram; | ||
| 352 | |||
| 353 | if (request_mem_region(0xff400000, 0x8000, | ||
| 354 | "Core B - Data Bank A SRAM") == NULL) | ||
| 355 | goto release_data_b_sram; | ||
| 356 | |||
| 357 | if (request_dma(CH_MEM_STREAM2_DEST, "Core B - DMA Destination") < 0) | ||
| 358 | goto release_data_a_sram; | ||
| 359 | |||
| 360 | if (request_dma(CH_MEM_STREAM2_SRC, "Core B - DMA Source") < 0) | ||
| 361 | goto release_dma_dest; | ||
| 362 | |||
| 363 | set_dma_callback(CH_MEM_STREAM2_DEST, coreb_dma_interrupt, NULL); | ||
| 364 | |||
| 365 | misc_register(&coreb_dev); | ||
| 366 | |||
| 367 | if (device_create_file(coreb_dev.this_device, &dev_attr_coreb_status)) | ||
| 368 | goto release_dma_src; | ||
| 369 | |||
| 370 | printk(KERN_INFO "BF561 Core B driver %s initialized.\n", MODULE_VER); | ||
| 371 | return 0; | ||
| 372 | |||
| 373 | release_dma_src: | ||
| 374 | free_dma(CH_MEM_STREAM2_SRC); | ||
| 375 | release_dma_dest: | ||
| 376 | free_dma(CH_MEM_STREAM2_DEST); | ||
| 377 | release_data_a_sram: | ||
| 378 | release_mem_region(0xff400000, 0x8000); | ||
| 379 | release_data_b_sram: | ||
| 380 | release_mem_region(0xff500000, 0x8000); | ||
| 381 | release_instruction_b_sram: | ||
| 382 | release_mem_region(0xff610000, 0x4000); | ||
| 383 | release_instruction_a_sram: | ||
| 384 | release_mem_region(0xff600000, 0x4000); | ||
| 385 | exit: | ||
| 386 | return -ENOMEM; | ||
| 387 | } | 65 | } |
| 66 | module_init(bf561_coreb_init); | ||
| 388 | 67 | ||
| 389 | void __exit bf561_coreb_exit(void) | 68 | static void __exit bf561_coreb_exit(void) |
| 390 | { | 69 | { |
| 391 | device_remove_file(coreb_dev.this_device, &dev_attr_coreb_status); | ||
| 392 | misc_deregister(&coreb_dev); | 70 | misc_deregister(&coreb_dev); |
| 393 | |||
| 394 | release_mem_region(0xff610000, 0x4000); | ||
| 395 | release_mem_region(0xff600000, 0x4000); | ||
| 396 | release_mem_region(0xff500000, 0x8000); | ||
| 397 | release_mem_region(0xff400000, 0x8000); | ||
| 398 | |||
| 399 | free_dma(CH_MEM_STREAM2_DEST); | ||
| 400 | free_dma(CH_MEM_STREAM2_SRC); | ||
| 401 | } | 71 | } |
| 402 | |||
| 403 | module_init(bf561_coreb_init); | ||
| 404 | module_exit(bf561_coreb_exit); | 72 | module_exit(bf561_coreb_exit); |
| 405 | 73 | ||
| 406 | MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>"); | 74 | MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>"); |
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index d0b0b3506440..dccd396cd931 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file shoule be up to date with: | 9 | /* This file should be up to date with: |
| 10 | * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List | 10 | * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| @@ -18,11 +18,11 @@ | |||
| 18 | # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 | 18 | # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 |
| 19 | #endif | 19 | #endif |
| 20 | 20 | ||
| 21 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ | 21 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ |
| 22 | #define ANOMALY_05000074 (1) | 22 | #define ANOMALY_05000074 (1) |
| 23 | /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ | 23 | /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ |
| 24 | #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) | 24 | #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) |
| 25 | /* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */ | 25 | /* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ |
| 26 | #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) | 26 | #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) |
| 27 | /* Testset instructions restricted to 32-bit aligned memory locations */ | 27 | /* Testset instructions restricted to 32-bit aligned memory locations */ |
| 28 | #define ANOMALY_05000120 (1) | 28 | #define ANOMALY_05000120 (1) |
| @@ -40,7 +40,7 @@ | |||
| 40 | #define ANOMALY_05000136 (__SILICON_REVISION__ < 3) | 40 | #define ANOMALY_05000136 (__SILICON_REVISION__ < 3) |
| 41 | /* Allowing the SPORT RX FIFO to fill will cause an overflow */ | 41 | /* Allowing the SPORT RX FIFO to fill will cause an overflow */ |
| 42 | #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) | 42 | #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) |
| 43 | /* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ | 43 | /* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ |
| 44 | #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) | 44 | #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) |
| 45 | /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ | 45 | /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ |
| 46 | #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) | 46 | #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) |
| @@ -80,7 +80,7 @@ | |||
| 80 | #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) | 80 | #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) |
| 81 | /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ | 81 | /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ |
| 82 | #define ANOMALY_05000166 (1) | 82 | #define ANOMALY_05000166 (1) |
| 83 | /* Turning Serial Ports on with External Frame Syncs */ | 83 | /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ |
| 84 | #define ANOMALY_05000167 (1) | 84 | #define ANOMALY_05000167 (1) |
| 85 | /* SDRAM auto-refresh and subsequent Power Ups */ | 85 | /* SDRAM auto-refresh and subsequent Power Ups */ |
| 86 | #define ANOMALY_05000168 (__SILICON_REVISION__ < 5) | 86 | #define ANOMALY_05000168 (__SILICON_REVISION__ < 5) |
| @@ -164,7 +164,7 @@ | |||
| 164 | #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) | 164 | #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) |
| 165 | /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ | 165 | /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ |
| 166 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) | 166 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) |
| 167 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | 167 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
| 168 | #define ANOMALY_05000245 (__SILICON_REVISION__ < 5) | 168 | #define ANOMALY_05000245 (__SILICON_REVISION__ < 5) |
| 169 | /* TESTSET operation forces stall on the other core */ | 169 | /* TESTSET operation forces stall on the other core */ |
| 170 | #define ANOMALY_05000248 (__SILICON_REVISION__ < 5) | 170 | #define ANOMALY_05000248 (__SILICON_REVISION__ < 5) |
| @@ -208,7 +208,7 @@ | |||
| 208 | #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) | 208 | #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) |
| 209 | /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ | 209 | /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ |
| 210 | #define ANOMALY_05000276 (__SILICON_REVISION__ < 5) | 210 | #define ANOMALY_05000276 (__SILICON_REVISION__ < 5) |
| 211 | /* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ | 211 | /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ |
| 212 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) | 212 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) |
| 213 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ | 213 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ |
| 214 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) | 214 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) |
| @@ -232,7 +232,7 @@ | |||
| 232 | #define ANOMALY_05000310 (1) | 232 | #define ANOMALY_05000310 (1) |
| 233 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | 233 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
| 234 | #define ANOMALY_05000312 (1) | 234 | #define ANOMALY_05000312 (1) |
| 235 | /* PPI Is Level-Sensitive on First Transfer */ | 235 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
| 236 | #define ANOMALY_05000313 (1) | 236 | #define ANOMALY_05000313 (1) |
| 237 | /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ | 237 | /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ |
| 238 | #define ANOMALY_05000315 (1) | 238 | #define ANOMALY_05000315 (1) |
| @@ -276,18 +276,27 @@ | |||
| 276 | #define ANOMALY_05000428 (__SILICON_REVISION__ > 3) | 276 | #define ANOMALY_05000428 (__SILICON_REVISION__ > 3) |
| 277 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | 277 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 278 | #define ANOMALY_05000443 (1) | 278 | #define ANOMALY_05000443 (1) |
| 279 | /* False Hardware Error when RETI points to invalid memory */ | ||
| 280 | #define ANOMALY_05000461 (1) | ||
| 279 | 281 | ||
| 280 | /* Anomalies that don't exist on this proc */ | 282 | /* Anomalies that don't exist on this proc */ |
| 283 | #define ANOMALY_05000119 (0) | ||
| 281 | #define ANOMALY_05000158 (0) | 284 | #define ANOMALY_05000158 (0) |
| 282 | #define ANOMALY_05000183 (0) | 285 | #define ANOMALY_05000183 (0) |
| 286 | #define ANOMALY_05000233 (0) | ||
| 283 | #define ANOMALY_05000273 (0) | 287 | #define ANOMALY_05000273 (0) |
| 284 | #define ANOMALY_05000311 (0) | 288 | #define ANOMALY_05000311 (0) |
| 285 | #define ANOMALY_05000353 (1) | 289 | #define ANOMALY_05000353 (1) |
| 286 | #define ANOMALY_05000380 (0) | 290 | #define ANOMALY_05000380 (0) |
| 287 | #define ANOMALY_05000386 (1) | 291 | #define ANOMALY_05000386 (1) |
| 292 | #define ANOMALY_05000389 (0) | ||
| 293 | #define ANOMALY_05000400 (0) | ||
| 294 | #define ANOMALY_05000430 (0) | ||
| 288 | #define ANOMALY_05000432 (0) | 295 | #define ANOMALY_05000432 (0) |
| 289 | #define ANOMALY_05000435 (0) | 296 | #define ANOMALY_05000435 (0) |
| 290 | #define ANOMALY_05000447 (0) | 297 | #define ANOMALY_05000447 (0) |
| 291 | #define ANOMALY_05000448 (0) | 298 | #define ANOMALY_05000448 (0) |
| 299 | #define ANOMALY_05000456 (0) | ||
| 300 | #define ANOMALY_05000450 (0) | ||
| 292 | 301 | ||
| 293 | #endif | 302 | #endif |
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h index 95d609f11c97..9d9858c2be68 100644 --- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h | |||
| @@ -1526,6 +1526,35 @@ | |||
| 1526 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR() | 1526 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR() |
| 1527 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val) | 1527 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val) |
| 1528 | 1528 | ||
| 1529 | #define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA1_S1_CONFIG() | ||
| 1530 | #define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA1_S1_CONFIG(val) | ||
| 1531 | #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA1_S1_IRQ_STATUS() | ||
| 1532 | #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA1_S1_IRQ_STATUS(val) | ||
| 1533 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA1_S1_X_MODIFY() | ||
| 1534 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA1_S1_X_MODIFY(val) | ||
| 1535 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA1_S1_Y_MODIFY() | ||
| 1536 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA1_S1_Y_MODIFY(val) | ||
| 1537 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA1_S1_X_COUNT() | ||
| 1538 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA1_S1_X_COUNT(val) | ||
| 1539 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA1_S1_Y_COUNT() | ||
| 1540 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA1_S1_Y_COUNT(val) | ||
| 1541 | #define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA1_S1_START_ADDR() | ||
| 1542 | #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA1_S1_START_ADDR(val) | ||
| 1543 | #define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA1_D1_CONFIG() | ||
| 1544 | #define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA1_D1_CONFIG(val) | ||
| 1545 | #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA1_D1_IRQ_STATUS() | ||
| 1546 | #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA1_D1_IRQ_STATUS(val) | ||
| 1547 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA1_D1_X_MODIFY() | ||
| 1548 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA1_D1_X_MODIFY(val) | ||
| 1549 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA1_D1_Y_MODIFY() | ||
| 1550 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA1_D1_Y_MODIFY(val) | ||
| 1551 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA1_D1_X_COUNT() | ||
| 1552 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA1_D1_X_COUNT(val) | ||
| 1553 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA1_D1_Y_COUNT() | ||
| 1554 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA1_D1_Y_COUNT(val) | ||
| 1555 | #define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA1_D1_START_ADDR() | ||
| 1556 | #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA1_D1_START_ADDR(val) | ||
| 1557 | |||
| 1529 | /* These need to be last due to the cdef/linux inter-dependencies */ | 1558 | /* These need to be last due to the cdef/linux inter-dependencies */ |
| 1530 | #include <asm/irq.h> | 1559 | #include <asm/irq.h> |
| 1531 | 1560 | ||
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index cf922295f4ce..5fc0f05026e0 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h | |||
| @@ -796,6 +796,62 @@ | |||
| 796 | #define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ | 796 | #define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ |
| 797 | #define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ | 797 | #define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ |
| 798 | 798 | ||
| 799 | #define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR | ||
| 800 | #define MDMA_D0_START_ADDR MDMA1_D0_START_ADDR | ||
| 801 | #define MDMA_D0_CONFIG MDMA1_D0_CONFIG | ||
| 802 | #define MDMA_D0_X_COUNT MDMA1_D0_X_COUNT | ||
| 803 | #define MDMA_D0_X_MODIFY MDMA1_D0_X_MODIFY | ||
| 804 | #define MDMA_D0_Y_COUNT MDMA1_D0_Y_COUNT | ||
| 805 | #define MDMA_D0_Y_MODIFY MDMA1_D0_Y_MODIFY | ||
| 806 | #define MDMA_D0_CURR_DESC_PTR MDMA1_D0_CURR_DESC_PTR | ||
| 807 | #define MDMA_D0_CURR_ADDR MDMA1_D0_CURR_ADDR | ||
| 808 | #define MDMA_D0_IRQ_STATUS MDMA1_D0_IRQ_STATUS | ||
| 809 | #define MDMA_D0_PERIPHERAL_MAP MDMA1_D0_PERIPHERAL_MAP | ||
| 810 | #define MDMA_D0_CURR_X_COUNT MDMA1_D0_CURR_X_COUNT | ||
| 811 | #define MDMA_D0_CURR_Y_COUNT MDMA1_D0_CURR_Y_COUNT | ||
| 812 | |||
| 813 | #define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR | ||
| 814 | #define MDMA_S0_START_ADDR MDMA1_S0_START_ADDR | ||
| 815 | #define MDMA_S0_CONFIG MDMA1_S0_CONFIG | ||
| 816 | #define MDMA_S0_X_COUNT MDMA1_S0_X_COUNT | ||
| 817 | #define MDMA_S0_X_MODIFY MDMA1_S0_X_MODIFY | ||
| 818 | #define MDMA_S0_Y_COUNT MDMA1_S0_Y_COUNT | ||
| 819 | #define MDMA_S0_Y_MODIFY MDMA1_S0_Y_MODIFY | ||
| 820 | #define MDMA_S0_CURR_DESC_PTR MDMA1_S0_CURR_DESC_PTR | ||
| 821 | #define MDMA_S0_CURR_ADDR MDMA1_S0_CURR_ADDR | ||
| 822 | #define MDMA_S0_IRQ_STATUS MDMA1_S0_IRQ_STATUS | ||
| 823 | #define MDMA_S0_PERIPHERAL_MAP MDMA1_S0_PERIPHERAL_MAP | ||
| 824 | #define MDMA_S0_CURR_X_COUNT MDMA1_S0_CURR_X_COUNT | ||
| 825 | #define MDMA_S0_CURR_Y_COUNT MDMA1_S0_CURR_Y_COUNT | ||
| 826 | |||
| 827 | #define MDMA_D1_NEXT_DESC_PTR MDMA1_D1_NEXT_DESC_PTR | ||
| 828 | #define MDMA_D1_START_ADDR MDMA1_D1_START_ADDR | ||
| 829 | #define MDMA_D1_CONFIG MDMA1_D1_CONFIG | ||
| 830 | #define MDMA_D1_X_COUNT MDMA1_D1_X_COUNT | ||
| 831 | #define MDMA_D1_X_MODIFY MDMA1_D1_X_MODIFY | ||
| 832 | #define MDMA_D1_Y_COUNT MDMA1_D1_Y_COUNT | ||
| 833 | #define MDMA_D1_Y_MODIFY MDMA1_D1_Y_MODIFY | ||
| 834 | #define MDMA_D1_CURR_DESC_PTR MDMA1_D1_CURR_DESC_PTR | ||
| 835 | #define MDMA_D1_CURR_ADDR MDMA1_D1_CURR_ADDR | ||
| 836 | #define MDMA_D1_IRQ_STATUS MDMA1_D1_IRQ_STATUS | ||
| 837 | #define MDMA_D1_PERIPHERAL_MAP MDMA1_D1_PERIPHERAL_MAP | ||
| 838 | #define MDMA_D1_CURR_X_COUNT MDMA1_D1_CURR_X_COUNT | ||
| 839 | #define MDMA_D1_CURR_Y_COUNT MDMA1_D1_CURR_Y_COUNT | ||
| 840 | |||
| 841 | #define MDMA_S1_NEXT_DESC_PTR MDMA1_S1_NEXT_DESC_PTR | ||
| 842 | #define MDMA_S1_START_ADDR MDMA1_S1_START_ADDR | ||
| 843 | #define MDMA_S1_CONFIG MDMA1_S1_CONFIG | ||
| 844 | #define MDMA_S1_X_COUNT MDMA1_S1_X_COUNT | ||
| 845 | #define MDMA_S1_X_MODIFY MDMA1_S1_X_MODIFY | ||
| 846 | #define MDMA_S1_Y_COUNT MDMA1_S1_Y_COUNT | ||
| 847 | #define MDMA_S1_Y_MODIFY MDMA1_S1_Y_MODIFY | ||
| 848 | #define MDMA_S1_CURR_DESC_PTR MDMA1_S1_CURR_DESC_PTR | ||
| 849 | #define MDMA_S1_CURR_ADDR MDMA1_S1_CURR_ADDR | ||
| 850 | #define MDMA_S1_IRQ_STATUS MDMA1_S1_IRQ_STATUS | ||
| 851 | #define MDMA_S1_PERIPHERAL_MAP MDMA1_S1_PERIPHERAL_MAP | ||
| 852 | #define MDMA_S1_CURR_X_COUNT MDMA1_S1_CURR_X_COUNT | ||
| 853 | #define MDMA_S1_CURR_Y_COUNT MDMA1_S1_CURR_Y_COUNT | ||
| 854 | |||
| 799 | /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ | 855 | /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ |
| 800 | #define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ | 856 | #define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ |
| 801 | #define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */ | 857 | #define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */ |
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c index 9b27e698c0b2..8c10701c251f 100644 --- a/arch/blackfin/mach-bf561/smp.c +++ b/arch/blackfin/mach-bf561/smp.c | |||
| @@ -133,9 +133,9 @@ void __init platform_request_ipi(irq_handler_t handler) | |||
| 133 | int ret; | 133 | int ret; |
| 134 | 134 | ||
| 135 | ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED, | 135 | ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED, |
| 136 | "SMP interrupt", handler); | 136 | "Supplemental Interrupt0", handler); |
| 137 | if (ret) | 137 | if (ret) |
| 138 | panic("Cannot request supplemental interrupt 0 for IPI service\n"); | 138 | panic("Cannot request supplemental interrupt 0 for IPI service"); |
| 139 | } | 139 | } |
| 140 | 140 | ||
| 141 | void platform_send_ipi(cpumask_t callmap) | 141 | void platform_send_ipi(cpumask_t callmap) |
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile index 1f3228ed713f..dd8b2dc97f56 100644 --- a/arch/blackfin/mach-common/Makefile +++ b/arch/blackfin/mach-common/Makefile | |||
| @@ -4,7 +4,7 @@ | |||
| 4 | 4 | ||
| 5 | obj-y := \ | 5 | obj-y := \ |
| 6 | cache.o cache-c.o entry.o head.o \ | 6 | cache.o cache-c.o entry.o head.o \ |
| 7 | interrupt.o irqpanic.o arch_checks.o ints-priority.o | 7 | interrupt.o arch_checks.o ints-priority.o |
| 8 | 8 | ||
| 9 | obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o | 9 | obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o |
| 10 | obj-$(CONFIG_PM) += pm.o dpmc_modes.o | 10 | obj-$(CONFIG_PM) += pm.o dpmc_modes.o |
| @@ -12,3 +12,4 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq.o | |||
| 12 | obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o | 12 | obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o |
| 13 | obj-$(CONFIG_SMP) += smp.o | 13 | obj-$(CONFIG_SMP) += smp.o |
| 14 | obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o | 14 | obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o |
| 15 | obj-$(CONFIG_DEBUG_ICACHE_CHECK) += irqpanic.o | ||
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c index 80d39b2f9db2..da93d9207165 100644 --- a/arch/blackfin/mach-common/arch_checks.c +++ b/arch/blackfin/mach-common/arch_checks.c | |||
| @@ -71,3 +71,10 @@ | |||
| 71 | #if ANOMALY_05000448 | 71 | #if ANOMALY_05000448 |
| 72 | # error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes. | 72 | # error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes. |
| 73 | #endif | 73 | #endif |
| 74 | |||
| 75 | /* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ | ||
| 76 | #if ANOMALY_05000220 && \ | ||
| 77 | ((defined(CONFIG_BFIN_WB) && defined(CONFIG_BFIN_L2_NOT_CACHED)) || \ | ||
| 78 | (!defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_L2_WB))) | ||
| 79 | # error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB. | ||
| 80 | #endif | ||
diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c index e6ab1f815123..b59ce3cb3807 100644 --- a/arch/blackfin/mach-common/cache-c.c +++ b/arch/blackfin/mach-common/cache-c.c | |||
| @@ -16,9 +16,21 @@ | |||
| 16 | void blackfin_invalidate_entire_dcache(void) | 16 | void blackfin_invalidate_entire_dcache(void) |
| 17 | { | 17 | { |
| 18 | u32 dmem = bfin_read_DMEM_CONTROL(); | 18 | u32 dmem = bfin_read_DMEM_CONTROL(); |
| 19 | SSYNC(); | ||
| 20 | bfin_write_DMEM_CONTROL(dmem & ~0xc); | 19 | bfin_write_DMEM_CONTROL(dmem & ~0xc); |
| 21 | SSYNC(); | 20 | SSYNC(); |
| 22 | bfin_write_DMEM_CONTROL(dmem); | 21 | bfin_write_DMEM_CONTROL(dmem); |
| 23 | SSYNC(); | 22 | SSYNC(); |
| 24 | } | 23 | } |
| 24 | |||
| 25 | /* Invalidate the Entire Instruction cache by | ||
| 26 | * clearing IMC bit | ||
| 27 | */ | ||
| 28 | void blackfin_invalidate_entire_icache(void) | ||
| 29 | { | ||
| 30 | u32 imem = bfin_read_IMEM_CONTROL(); | ||
| 31 | bfin_write_IMEM_CONTROL(imem & ~0x4); | ||
| 32 | SSYNC(); | ||
| 33 | bfin_write_IMEM_CONTROL(imem); | ||
| 34 | SSYNC(); | ||
| 35 | } | ||
| 36 | |||
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index aa0648c6a9fe..d9666fe6c3d6 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S | |||
| @@ -15,6 +15,13 @@ | |||
| 15 | 15 | ||
| 16 | .text | 16 | .text |
| 17 | 17 | ||
| 18 | /* 05000443 - IFLUSH cannot be last instruction in hardware loop */ | ||
| 19 | #if ANOMALY_05000443 | ||
| 20 | # define BROK_FLUSH_INST "IFLUSH" | ||
| 21 | #else | ||
| 22 | # define BROK_FLUSH_INST "no anomaly! yeah!" | ||
| 23 | #endif | ||
| 24 | |||
| 18 | /* Since all L1 caches work the same way, we use the same method for flushing | 25 | /* Since all L1 caches work the same way, we use the same method for flushing |
| 19 | * them. Only the actual flush instruction differs. We write this in asm as | 26 | * them. Only the actual flush instruction differs. We write this in asm as |
| 20 | * GCC can be hard to coax into writing nice hardware loops. | 27 | * GCC can be hard to coax into writing nice hardware loops. |
| @@ -23,7 +30,7 @@ | |||
| 23 | * R0 = start address | 30 | * R0 = start address |
| 24 | * R1 = end address | 31 | * R1 = end address |
| 25 | */ | 32 | */ |
| 26 | .macro do_flush flushins:req optflushins optnopins label | 33 | .macro do_flush flushins:req label |
| 27 | 34 | ||
| 28 | R2 = -L1_CACHE_BYTES; | 35 | R2 = -L1_CACHE_BYTES; |
| 29 | 36 | ||
| @@ -44,22 +51,15 @@ | |||
| 44 | \label : | 51 | \label : |
| 45 | .endif | 52 | .endif |
| 46 | P0 = R0; | 53 | P0 = R0; |
| 54 | |||
| 47 | LSETUP (1f, 2f) LC1 = P1; | 55 | LSETUP (1f, 2f) LC1 = P1; |
| 48 | 1: | 56 | 1: |
| 49 | .ifnb \optflushins | 57 | .ifeqs "\flushins", BROK_FLUSH_INST |
| 50 | \optflushins [P0]; | ||
| 51 | .endif | ||
| 52 | #if ANOMALY_05000443 | ||
| 53 | .ifb \optnopins | ||
| 54 | 2: | ||
| 55 | .endif | ||
| 56 | \flushins [P0++]; | 58 | \flushins [P0++]; |
| 57 | .ifnb \optnopins | 59 | 2: nop; |
| 58 | 2: \optnopins; | 60 | .else |
| 59 | .endif | ||
| 60 | #else | ||
| 61 | 2: \flushins [P0++]; | 61 | 2: \flushins [P0++]; |
| 62 | #endif | 62 | .endif |
| 63 | 63 | ||
| 64 | RTS; | 64 | RTS; |
| 65 | .endm | 65 | .endm |
| @@ -77,25 +77,9 @@ ENTRY(_blackfin_icache_flush_range) | |||
| 77 | */ | 77 | */ |
| 78 | P0 = R0; | 78 | P0 = R0; |
| 79 | IFLUSH[P0]; | 79 | IFLUSH[P0]; |
| 80 | do_flush IFLUSH, , nop | 80 | do_flush IFLUSH |
| 81 | ENDPROC(_blackfin_icache_flush_range) | 81 | ENDPROC(_blackfin_icache_flush_range) |
| 82 | 82 | ||
| 83 | /* Flush all cache lines assocoiated with this area of memory. */ | ||
| 84 | ENTRY(_blackfin_icache_dcache_flush_range) | ||
| 85 | /* | ||
| 86 | * Walkaround to avoid loading wrong instruction after invalidating icache | ||
| 87 | * and following sequence is met. | ||
| 88 | * | ||
| 89 | * 1) One instruction address is cached in the instruction cache. | ||
| 90 | * 2) This instruction in SDRAM is changed. | ||
| 91 | * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range(). | ||
| 92 | * 4) This instruction is executed again, but the old one is loaded. | ||
| 93 | */ | ||
| 94 | P0 = R0; | ||
| 95 | IFLUSH[P0]; | ||
| 96 | do_flush FLUSH, IFLUSH | ||
| 97 | ENDPROC(_blackfin_icache_dcache_flush_range) | ||
| 98 | |||
| 99 | /* Throw away all D-cached data in specified region without any obligation to | 83 | /* Throw away all D-cached data in specified region without any obligation to |
| 100 | * write them back. Since the Blackfin ISA does not have an "invalidate" | 84 | * write them back. Since the Blackfin ISA does not have an "invalidate" |
| 101 | * instruction, we use flush/invalidate. Perhaps as a speed optimization we | 85 | * instruction, we use flush/invalidate. Perhaps as a speed optimization we |
| @@ -107,7 +91,7 @@ ENDPROC(_blackfin_dcache_invalidate_range) | |||
| 107 | 91 | ||
| 108 | /* Flush all data cache lines assocoiated with this memory area */ | 92 | /* Flush all data cache lines assocoiated with this memory area */ |
| 109 | ENTRY(_blackfin_dcache_flush_range) | 93 | ENTRY(_blackfin_dcache_flush_range) |
| 110 | do_flush FLUSH, , , .Ldfr | 94 | do_flush FLUSH, .Ldfr |
| 111 | ENDPROC(_blackfin_dcache_flush_range) | 95 | ENDPROC(_blackfin_dcache_flush_range) |
| 112 | 96 | ||
| 113 | /* Our headers convert the page structure to an address, so just need to flush | 97 | /* Our headers convert the page structure to an address, so just need to flush |
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c index 35393651359b..ef6870e9eea6 100644 --- a/arch/blackfin/mach-common/clocks-init.c +++ b/arch/blackfin/mach-common/clocks-init.c | |||
| @@ -72,6 +72,7 @@ void init_clocks(void) | |||
| 72 | #endif | 72 | #endif |
| 73 | bfin_write_PLL_LOCKCNT(0x300); | 73 | bfin_write_PLL_LOCKCNT(0x300); |
| 74 | do_sync(); | 74 | do_sync(); |
| 75 | /* We always write PLL_CTL thus avoiding Anomaly 05000242 */ | ||
| 75 | bfin_write16(PLL_CTL, PLL_CTL_VAL); | 76 | bfin_write16(PLL_CTL, PLL_CTL_VAL); |
| 76 | __asm__ __volatile__("IDLE;"); | 77 | __asm__ __volatile__("IDLE;"); |
| 77 | bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); | 78 | bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); |
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c index 72e16605ca09..70e3411f558c 100644 --- a/arch/blackfin/mach-common/cpufreq.c +++ b/arch/blackfin/mach-common/cpufreq.c | |||
| @@ -140,7 +140,8 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy) | |||
| 140 | cclk = get_cclk() / 1000; | 140 | cclk = get_cclk() / 1000; |
| 141 | sclk = get_sclk() / 1000; | 141 | sclk = get_sclk() / 1000; |
| 142 | 142 | ||
| 143 | #if ANOMALY_05000273 || (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE)) | 143 | #if ANOMALY_05000273 || ANOMALY_05000274 || \ |
| 144 | (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE)) | ||
| 144 | min_cclk = sclk * 2; | 145 | min_cclk = sclk * 2; |
| 145 | #else | 146 | #else |
| 146 | min_cclk = sclk; | 147 | min_cclk = sclk; |
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 21e65a339a22..31fa313e81cf 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S | |||
| @@ -36,13 +36,13 @@ | |||
| 36 | #include <linux/init.h> | 36 | #include <linux/init.h> |
| 37 | #include <linux/linkage.h> | 37 | #include <linux/linkage.h> |
| 38 | #include <linux/unistd.h> | 38 | #include <linux/unistd.h> |
| 39 | #include <linux/threads.h> | ||
| 40 | #include <asm/blackfin.h> | 39 | #include <asm/blackfin.h> |
| 41 | #include <asm/errno.h> | 40 | #include <asm/errno.h> |
| 42 | #include <asm/fixed_code.h> | 41 | #include <asm/fixed_code.h> |
| 43 | #include <asm/thread_info.h> /* TIF_NEED_RESCHED */ | 42 | #include <asm/thread_info.h> /* TIF_NEED_RESCHED */ |
| 44 | #include <asm/asm-offsets.h> | 43 | #include <asm/asm-offsets.h> |
| 45 | #include <asm/trace.h> | 44 | #include <asm/trace.h> |
| 45 | #include <asm/traps.h> | ||
| 46 | 46 | ||
| 47 | #include <asm/context.S> | 47 | #include <asm/context.S> |
| 48 | 48 | ||
| @@ -85,13 +85,15 @@ ENTRY(_ex_workaround_261) | |||
| 85 | if !cc jump _bfin_return_from_exception; | 85 | if !cc jump _bfin_return_from_exception; |
| 86 | /* fall through */ | 86 | /* fall through */ |
| 87 | R7 = P4; | 87 | R7 = P4; |
| 88 | R6 = 0x26; /* Data CPLB Miss */ | 88 | R6 = VEC_CPLB_M; /* Data CPLB Miss */ |
| 89 | cc = R6 == R7; | 89 | cc = R6 == R7; |
| 90 | if cc jump _ex_dcplb_miss (BP); | 90 | if cc jump _ex_dcplb_miss (BP); |
| 91 | R6 = 0x23; /* Data CPLB Miss */ | 91 | #ifdef CONFIG_MPU |
| 92 | R6 = VEC_CPLB_VL; /* Data CPLB Violation */ | ||
| 92 | cc = R6 == R7; | 93 | cc = R6 == R7; |
| 93 | if cc jump _ex_dcplb_viol (BP); | 94 | if cc jump _ex_dcplb_viol (BP); |
| 94 | /* Handle 0x23 Data CPLB Protection Violation | 95 | #endif |
| 96 | /* Handle Data CPLB Protection Violation | ||
| 95 | * and Data CPLB Multiple Hits - Linux Trap Zero | 97 | * and Data CPLB Multiple Hits - Linux Trap Zero |
| 96 | */ | 98 | */ |
| 97 | jump _ex_trap_c; | 99 | jump _ex_trap_c; |
| @@ -201,7 +203,18 @@ ENTRY(_ex_single_step) | |||
| 201 | cc = r7 == 0; | 203 | cc = r7 == 0; |
| 202 | if !cc jump 1f; | 204 | if !cc jump 1f; |
| 203 | #endif | 205 | #endif |
| 204 | 206 | #ifdef CONFIG_EXACT_HWERR | |
| 207 | /* Read the ILAT, and to check to see if the process we are | ||
| 208 | * single stepping caused a previous hardware error | ||
| 209 | * If so, do not single step, (which lowers to IRQ5, and makes | ||
| 210 | * us miss the error). | ||
| 211 | */ | ||
| 212 | p5.l = lo(ILAT); | ||
| 213 | p5.h = hi(ILAT); | ||
| 214 | r7 = [p5]; | ||
| 215 | cc = bittst(r7, EVT_IVHW_P); | ||
| 216 | if cc jump 1f; | ||
| 217 | #endif | ||
| 205 | /* Single stepping only a single instruction, so clear the trace | 218 | /* Single stepping only a single instruction, so clear the trace |
| 206 | * bit here. */ | 219 | * bit here. */ |
| 207 | r7 = syscfg; | 220 | r7 = syscfg; |
| @@ -260,16 +273,7 @@ ENTRY(_bfin_return_from_exception) | |||
| 260 | r6.l = lo(SEQSTAT_EXCAUSE); | 273 | r6.l = lo(SEQSTAT_EXCAUSE); |
| 261 | r6.h = hi(SEQSTAT_EXCAUSE); | 274 | r6.h = hi(SEQSTAT_EXCAUSE); |
| 262 | r7 = r7 & r6; | 275 | r7 = r7 & r6; |
| 263 | r6 = 0x25; | 276 | r6 = VEC_UNCOV; |
| 264 | CC = R7 == R6; | ||
| 265 | if CC JUMP _double_fault; | ||
| 266 | |||
| 267 | /* Did we cause a HW error? */ | ||
| 268 | p5.l = lo(ILAT); | ||
| 269 | p5.h = hi(ILAT); | ||
| 270 | r6 = [p5]; | ||
| 271 | r7 = 0x20; /* Did I just cause anther HW error? */ | ||
| 272 | r6 = r7 & r6; | ||
| 273 | CC = R7 == R6; | 277 | CC = R7 == R6; |
| 274 | if CC JUMP _double_fault; | 278 | if CC JUMP _double_fault; |
| 275 | #endif | 279 | #endif |
| @@ -473,6 +477,16 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/ | |||
| 473 | [--sp] = ASTAT; | 477 | [--sp] = ASTAT; |
| 474 | [--sp] = (R7:6,P5:4); | 478 | [--sp] = (R7:6,P5:4); |
| 475 | 479 | ||
| 480 | #ifdef CONFIG_EXACT_HWERR | ||
| 481 | /* Make sure all pending read/writes complete. This will ensure any | ||
| 482 | * accesses which could cause hardware errors completes, and signal | ||
| 483 | * the the hardware before we do something silly, like crash the | ||
| 484 | * kernel. We don't need to work around anomaly 05000312, since | ||
| 485 | * we are already atomic | ||
| 486 | */ | ||
| 487 | ssync; | ||
| 488 | #endif | ||
| 489 | |||
| 476 | #if ANOMALY_05000283 || ANOMALY_05000315 | 490 | #if ANOMALY_05000283 || ANOMALY_05000315 |
| 477 | cc = r7 == r7; | 491 | cc = r7 == r7; |
| 478 | p5.h = HI(CHIPID); | 492 | p5.h = HI(CHIPID); |
| @@ -855,7 +869,7 @@ ENTRY(_ret_from_exception) | |||
| 855 | p1.h = _schedule_and_signal; | 869 | p1.h = _schedule_and_signal; |
| 856 | [p0] = p1; | 870 | [p0] = p1; |
| 857 | csync; | 871 | csync; |
| 858 | raise 15; /* raise evt14 to do signal or reschedule */ | 872 | raise 15; /* raise evt15 to do signal or reschedule */ |
| 859 | 4: | 873 | 4: |
| 860 | r0 = syscfg; | 874 | r0 = syscfg; |
| 861 | bitclr(r0, 0); | 875 | bitclr(r0, 0); |
| @@ -916,7 +930,7 @@ ENTRY(_return_from_int) | |||
| 916 | p1.h = _schedule_and_signal_from_int; | 930 | p1.h = _schedule_and_signal_from_int; |
| 917 | [p0] = p1; | 931 | [p0] = p1; |
| 918 | csync; | 932 | csync; |
| 919 | #if ANOMALY_05000281 | 933 | #if ANOMALY_05000281 || ANOMALY_05000461 |
| 920 | r0.l = lo(SAFE_USER_INSTRUCTION); | 934 | r0.l = lo(SAFE_USER_INSTRUCTION); |
| 921 | r0.h = hi(SAFE_USER_INSTRUCTION); | 935 | r0.h = hi(SAFE_USER_INSTRUCTION); |
| 922 | reti = r0; | 936 | reti = r0; |
| @@ -930,18 +944,27 @@ ENTRY(_return_from_int) | |||
| 930 | ENDPROC(_return_from_int) | 944 | ENDPROC(_return_from_int) |
| 931 | 945 | ||
| 932 | ENTRY(_lower_to_irq14) | 946 | ENTRY(_lower_to_irq14) |
| 933 | #if ANOMALY_05000281 | 947 | #if ANOMALY_05000281 || ANOMALY_05000461 |
| 934 | r0.l = lo(SAFE_USER_INSTRUCTION); | 948 | r0.l = lo(SAFE_USER_INSTRUCTION); |
| 935 | r0.h = hi(SAFE_USER_INSTRUCTION); | 949 | r0.h = hi(SAFE_USER_INSTRUCTION); |
| 936 | reti = r0; | 950 | reti = r0; |
| 937 | #endif | 951 | #endif |
| 938 | r0 = 0x401f; | 952 | |
| 953 | #ifdef CONFIG_DEBUG_HWERR | ||
| 954 | /* enable irq14 & hwerr interrupt, until we transition to _evt14_softirq */ | ||
| 955 | r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); | ||
| 956 | #else | ||
| 957 | /* Only enable irq14 interrupt, until we transition to _evt14_softirq */ | ||
| 958 | r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); | ||
| 959 | #endif | ||
| 939 | sti r0; | 960 | sti r0; |
| 940 | raise 14; | 961 | raise 14; |
| 941 | rti; | 962 | rti; |
| 963 | ENDPROC(_lower_to_irq14) | ||
| 964 | |||
| 942 | ENTRY(_evt14_softirq) | 965 | ENTRY(_evt14_softirq) |
| 943 | #ifdef CONFIG_DEBUG_HWERR | 966 | #ifdef CONFIG_DEBUG_HWERR |
| 944 | r0 = 0x3f; | 967 | r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); |
| 945 | sti r0; | 968 | sti r0; |
| 946 | #else | 969 | #else |
| 947 | cli r0; | 970 | cli r0; |
| @@ -949,8 +972,9 @@ ENTRY(_evt14_softirq) | |||
| 949 | [--sp] = RETI; | 972 | [--sp] = RETI; |
| 950 | SP += 4; | 973 | SP += 4; |
| 951 | rts; | 974 | rts; |
| 975 | ENDPROC(_evt14_softirq) | ||
| 952 | 976 | ||
| 953 | _schedule_and_signal_from_int: | 977 | ENTRY(_schedule_and_signal_from_int) |
| 954 | /* To end up here, vector 15 was changed - so we have to change it | 978 | /* To end up here, vector 15 was changed - so we have to change it |
| 955 | * back. | 979 | * back. |
| 956 | */ | 980 | */ |
| @@ -983,8 +1007,9 @@ _schedule_and_signal_from_int: | |||
| 983 | call _finish_atomic_sections; | 1007 | call _finish_atomic_sections; |
| 984 | sp += 12; | 1008 | sp += 12; |
| 985 | jump.s .Lresume_userspace; | 1009 | jump.s .Lresume_userspace; |
| 1010 | ENDPROC(_schedule_and_signal_from_int) | ||
| 986 | 1011 | ||
| 987 | _schedule_and_signal: | 1012 | ENTRY(_schedule_and_signal) |
| 988 | SAVE_CONTEXT_SYSCALL | 1013 | SAVE_CONTEXT_SYSCALL |
| 989 | /* To end up here, vector 15 was changed - so we have to change it | 1014 | /* To end up here, vector 15 was changed - so we have to change it |
| 990 | * back. | 1015 | * back. |
| @@ -1002,7 +1027,7 @@ _schedule_and_signal: | |||
| 1002 | 1: | 1027 | 1: |
| 1003 | RESTORE_CONTEXT | 1028 | RESTORE_CONTEXT |
| 1004 | rti; | 1029 | rti; |
| 1005 | ENDPROC(_lower_to_irq14) | 1030 | ENDPROC(_schedule_and_signal) |
| 1006 | 1031 | ||
| 1007 | /* We handle this 100% in exception space - to reduce overhead | 1032 | /* We handle this 100% in exception space - to reduce overhead |
| 1008 | * Only potiential problem is if the software buffer gets swapped out of the | 1033 | * Only potiential problem is if the software buffer gets swapped out of the |
| @@ -1581,24 +1606,11 @@ ENTRY(_sys_call_table) | |||
| 1581 | .long _sys_dup3 | 1606 | .long _sys_dup3 |
| 1582 | .long _sys_pipe2 | 1607 | .long _sys_pipe2 |
| 1583 | .long _sys_inotify_init1 /* 365 */ | 1608 | .long _sys_inotify_init1 /* 365 */ |
| 1609 | .long _sys_preadv | ||
| 1610 | .long _sys_pwritev | ||
| 1611 | .long _sys_rt_tgsigqueueinfo | ||
| 1584 | 1612 | ||
| 1585 | .rept NR_syscalls-(.-_sys_call_table)/4 | 1613 | .rept NR_syscalls-(.-_sys_call_table)/4 |
| 1586 | .long _sys_ni_syscall | 1614 | .long _sys_ni_syscall |
| 1587 | .endr | 1615 | .endr |
| 1588 | END(_sys_call_table) | 1616 | END(_sys_call_table) |
| 1589 | |||
| 1590 | #ifdef CONFIG_EXCEPTION_L1_SCRATCH | ||
| 1591 | /* .section .l1.bss.scratch */ | ||
| 1592 | .set _exception_stack_top, L1_SCRATCH_START + L1_SCRATCH_LENGTH | ||
| 1593 | #else | ||
| 1594 | #ifdef CONFIG_SYSCALL_TAB_L1 | ||
| 1595 | .section .l1.bss | ||
| 1596 | #else | ||
| 1597 | .bss | ||
| 1598 | #endif | ||
| 1599 | ENTRY(_exception_stack) | ||
| 1600 | .rept 1024 * NR_CPUS | ||
| 1601 | .long 0 | ||
| 1602 | .endr | ||
| 1603 | _exception_stack_top: | ||
| 1604 | #endif | ||
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S index 698d4c05947e..f826f6b9f917 100644 --- a/arch/blackfin/mach-common/head.S +++ b/arch/blackfin/mach-common/head.S | |||
| @@ -30,8 +30,6 @@ ENTRY(__init_clear_bss) | |||
| 30 | rts; | 30 | rts; |
| 31 | ENDPROC(__init_clear_bss) | 31 | ENDPROC(__init_clear_bss) |
| 32 | 32 | ||
| 33 | #define INITIAL_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) | ||
| 34 | |||
| 35 | ENTRY(__start) | 33 | ENTRY(__start) |
| 36 | /* R0: argument of command line string, passed from uboot, save it */ | 34 | /* R0: argument of command line string, passed from uboot, save it */ |
| 37 | R7 = R0; | 35 | R7 = R0; |
| @@ -126,30 +124,30 @@ ENTRY(__start) | |||
| 126 | * below | 124 | * below |
| 127 | */ | 125 | */ |
| 128 | GET_PDA(p0, r0); | 126 | GET_PDA(p0, r0); |
| 129 | r7 = [p0 + PDA_RETX]; | 127 | r6 = [p0 + PDA_RETX]; |
| 130 | p1.l = _init_saved_retx; | 128 | p1.l = _init_saved_retx; |
| 131 | p1.h = _init_saved_retx; | 129 | p1.h = _init_saved_retx; |
| 132 | [p1] = r7; | 130 | [p1] = r6; |
| 133 | 131 | ||
| 134 | r7 = [p0 + PDA_DCPLB]; | 132 | r6 = [p0 + PDA_DCPLB]; |
| 135 | p1.l = _init_saved_dcplb_fault_addr; | 133 | p1.l = _init_saved_dcplb_fault_addr; |
| 136 | p1.h = _init_saved_dcplb_fault_addr; | 134 | p1.h = _init_saved_dcplb_fault_addr; |
| 137 | [p1] = r7; | 135 | [p1] = r6; |
| 138 | 136 | ||
| 139 | r7 = [p0 + PDA_ICPLB]; | 137 | r6 = [p0 + PDA_ICPLB]; |
| 140 | p1.l = _init_saved_icplb_fault_addr; | 138 | p1.l = _init_saved_icplb_fault_addr; |
| 141 | p1.h = _init_saved_icplb_fault_addr; | 139 | p1.h = _init_saved_icplb_fault_addr; |
| 142 | [p1] = r7; | 140 | [p1] = r6; |
| 143 | 141 | ||
| 144 | r7 = [p0 + PDA_SEQSTAT]; | 142 | r6 = [p0 + PDA_SEQSTAT]; |
| 145 | p1.l = _init_saved_seqstat; | 143 | p1.l = _init_saved_seqstat; |
| 146 | p1.h = _init_saved_seqstat; | 144 | p1.h = _init_saved_seqstat; |
| 147 | [p1] = r7; | 145 | [p1] = r6; |
| 148 | #endif | 146 | #endif |
| 149 | 147 | ||
| 150 | /* Initialize stack pointer */ | 148 | /* Initialize stack pointer */ |
| 151 | sp.l = lo(INITIAL_STACK); | 149 | sp.l = _init_thread_union; |
| 152 | sp.h = hi(INITIAL_STACK); | 150 | sp.h = _init_thread_union; |
| 153 | fp = sp; | 151 | fp = sp; |
| 154 | usp = sp; | 152 | usp = sp; |
| 155 | 153 | ||
| @@ -189,7 +187,15 @@ ENTRY(__start) | |||
| 189 | /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ | 187 | /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ |
| 190 | call _bfin_relocate_l1_mem; | 188 | call _bfin_relocate_l1_mem; |
| 191 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | 189 | #ifdef CONFIG_BFIN_KERNEL_CLOCK |
| 190 | /* Only use on-chip scratch space for stack when absolutely required | ||
| 191 | * to avoid Anomaly 05000227 ... we know the init_clocks() func only | ||
| 192 | * uses L1 text and stack space and no other memory region. | ||
| 193 | */ | ||
| 194 | # define KERNEL_CLOCK_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) | ||
| 195 | sp.l = lo(KERNEL_CLOCK_STACK); | ||
| 196 | sp.h = hi(KERNEL_CLOCK_STACK); | ||
| 192 | call _init_clocks; | 197 | call _init_clocks; |
| 198 | sp = usp; /* usp hasnt been touched, so restore from there */ | ||
| 193 | #endif | 199 | #endif |
| 194 | 200 | ||
| 195 | /* This section keeps the processor in supervisor mode | 201 | /* This section keeps the processor in supervisor mode |
| @@ -243,9 +249,7 @@ ENTRY(_real_start) | |||
| 243 | call _cmdline_init; | 249 | call _cmdline_init; |
| 244 | 250 | ||
| 245 | /* Load the current thread pointer and stack */ | 251 | /* Load the current thread pointer and stack */ |
| 246 | sp.l = _init_thread_union; | 252 | p1 = THREAD_SIZE + 4 (z); /* +4 is for reti loading */ |
| 247 | sp.h = _init_thread_union; | ||
| 248 | p1 = THREAD_SIZE (z); | ||
| 249 | sp = sp + p1; | 253 | sp = sp + p1; |
| 250 | usp = sp; | 254 | usp = sp; |
| 251 | fp = sp; | 255 | fp = sp; |
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S index 0069c2dd4625..9c46680186e4 100644 --- a/arch/blackfin/mach-common/interrupt.S +++ b/arch/blackfin/mach-common/interrupt.S | |||
| @@ -145,6 +145,14 @@ __common_int_entry: | |||
| 145 | 145 | ||
| 146 | /* interrupt routine for ivhw - 5 */ | 146 | /* interrupt routine for ivhw - 5 */ |
| 147 | ENTRY(_evt_ivhw) | 147 | ENTRY(_evt_ivhw) |
| 148 | /* In case a single action kicks off multiple memory transactions, (like | ||
| 149 | * a cache line fetch, - this can cause multiple hardware errors, let's | ||
| 150 | * catch them all. First - make sure all the actions are complete, and | ||
| 151 | * the core sees the hardware errors. | ||
| 152 | */ | ||
| 153 | SSYNC; | ||
| 154 | SSYNC; | ||
| 155 | |||
| 148 | SAVE_ALL_SYS | 156 | SAVE_ALL_SYS |
| 149 | #ifdef CONFIG_FRAME_POINTER | 157 | #ifdef CONFIG_FRAME_POINTER |
| 150 | fp = 0; | 158 | fp = 0; |
| @@ -159,6 +167,25 @@ ENTRY(_evt_ivhw) | |||
| 159 | 1: | 167 | 1: |
| 160 | #endif | 168 | #endif |
| 161 | 169 | ||
| 170 | /* Handle all stacked hardware errors | ||
| 171 | * To make sure we don't hang forever, only do it 10 times | ||
| 172 | */ | ||
| 173 | R0 = 0; | ||
| 174 | R2 = 10; | ||
| 175 | 1: | ||
| 176 | P0.L = LO(ILAT); | ||
| 177 | P0.H = HI(ILAT); | ||
| 178 | R1 = [P0]; | ||
| 179 | CC = BITTST(R1, EVT_IVHW_P); | ||
| 180 | IF ! CC JUMP 2f; | ||
| 181 | /* OK a hardware error is pending - clear it */ | ||
| 182 | R1 = EVT_IVHW_P; | ||
| 183 | [P0] = R1; | ||
| 184 | R0 += 1; | ||
| 185 | CC = R1 == R2; | ||
| 186 | if CC JUMP 2f; | ||
| 187 | JUMP 1b; | ||
| 188 | 2: | ||
| 162 | # We are going to dump something out, so make sure we print IPEND properly | 189 | # We are going to dump something out, so make sure we print IPEND properly |
| 163 | p2.l = lo(IPEND); | 190 | p2.l = lo(IPEND); |
| 164 | p2.h = hi(IPEND); | 191 | p2.h = hi(IPEND); |
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index a7d7b2dd4059..af70f09acd55 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c | |||
| @@ -472,7 +472,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) | |||
| 472 | 472 | ||
| 473 | if (type == IRQ_TYPE_PROBE) { | 473 | if (type == IRQ_TYPE_PROBE) { |
| 474 | /* only probe unenabled GPIO interrupt lines */ | 474 | /* only probe unenabled GPIO interrupt lines */ |
| 475 | if (__test_bit(gpionr, gpio_enabled)) | 475 | if (test_bit(gpionr, gpio_enabled)) |
| 476 | return 0; | 476 | return 0; |
| 477 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | 477 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 478 | } | 478 | } |
| @@ -782,7 +782,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) | |||
| 782 | 782 | ||
| 783 | if (type == IRQ_TYPE_PROBE) { | 783 | if (type == IRQ_TYPE_PROBE) { |
| 784 | /* only probe unenabled GPIO interrupt lines */ | 784 | /* only probe unenabled GPIO interrupt lines */ |
| 785 | if (__test_bit(gpionr, gpio_enabled)) | 785 | if (test_bit(gpionr, gpio_enabled)) |
| 786 | return 0; | 786 | return 0; |
| 787 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | 787 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 788 | } | 788 | } |
| @@ -1052,7 +1052,7 @@ int __init init_arch_irq(void) | |||
| 1052 | set_irq_chained_handler(irq, bfin_demux_error_irq); | 1052 | set_irq_chained_handler(irq, bfin_demux_error_irq); |
| 1053 | break; | 1053 | break; |
| 1054 | #endif | 1054 | #endif |
| 1055 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) | 1055 | #if defined(CONFIG_TICKSOURCE_GPTMR0) |
| 1056 | case IRQ_TIMER0: | 1056 | case IRQ_TIMER0: |
| 1057 | set_irq_handler(irq, handle_percpu_irq); | 1057 | set_irq_handler(irq, handle_percpu_irq); |
| 1058 | break; | 1058 | break; |
| @@ -1116,6 +1116,9 @@ int __init init_arch_irq(void) | |||
| 1116 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | | 1116 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
| 1117 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; | 1117 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
| 1118 | 1118 | ||
| 1119 | /* This implicitly covers ANOMALY_05000171 | ||
| 1120 | * Boot-ROM code modifies SICA_IWRx wakeup registers | ||
| 1121 | */ | ||
| 1119 | #ifdef SIC_IWR0 | 1122 | #ifdef SIC_IWR0 |
| 1120 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); | 1123 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
| 1121 | # ifdef SIC_IWR1 | 1124 | # ifdef SIC_IWR1 |
| @@ -1136,13 +1139,6 @@ int __init init_arch_irq(void) | |||
| 1136 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); | 1139 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
| 1137 | #endif | 1140 | #endif |
| 1138 | 1141 | ||
| 1139 | #ifdef CONFIG_IPIPE | ||
| 1140 | for (irq = 0; irq < NR_IRQS; irq++) { | ||
| 1141 | struct irq_desc *desc = irq_to_desc(irq); | ||
| 1142 | desc->ic_prio = __ipipe_get_irq_priority(irq); | ||
| 1143 | } | ||
| 1144 | #endif /* CONFIG_IPIPE */ | ||
| 1145 | |||
| 1146 | return 0; | 1142 | return 0; |
| 1147 | } | 1143 | } |
| 1148 | 1144 | ||
| @@ -1156,23 +1152,22 @@ void do_irq(int vec, struct pt_regs *fp) | |||
| 1156 | } else { | 1152 | } else { |
| 1157 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; | 1153 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; |
| 1158 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; | 1154 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; |
| 1159 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ | 1155 | #if defined(SIC_ISR0) || defined(SICA_ISR0) |
| 1160 | || defined(BF538_FAMILY) || defined(CONFIG_BF51x) | ||
| 1161 | unsigned long sic_status[3]; | 1156 | unsigned long sic_status[3]; |
| 1162 | 1157 | ||
| 1163 | if (smp_processor_id()) { | 1158 | if (smp_processor_id()) { |
| 1164 | #ifdef CONFIG_SMP | 1159 | # ifdef SICB_ISR0 |
| 1165 | /* This will be optimized out in UP mode. */ | 1160 | /* This will be optimized out in UP mode. */ |
| 1166 | sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0(); | 1161 | sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0(); |
| 1167 | sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1(); | 1162 | sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1(); |
| 1168 | #endif | 1163 | # endif |
| 1169 | } else { | 1164 | } else { |
| 1170 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); | 1165 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); |
| 1171 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); | 1166 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); |
| 1172 | } | 1167 | } |
| 1173 | #ifdef CONFIG_BF54x | 1168 | # ifdef SIC_ISR2 |
| 1174 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); | 1169 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); |
| 1175 | #endif | 1170 | # endif |
| 1176 | for (;; ivg++) { | 1171 | for (;; ivg++) { |
| 1177 | if (ivg >= ivg_stop) { | 1172 | if (ivg >= ivg_stop) { |
| 1178 | atomic_inc(&num_spurious); | 1173 | atomic_inc(&num_spurious); |
| @@ -1236,20 +1231,16 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | |||
| 1236 | 1231 | ||
| 1237 | if (likely(vec == EVT_IVTMR_P)) { | 1232 | if (likely(vec == EVT_IVTMR_P)) { |
| 1238 | irq = IRQ_CORETMR; | 1233 | irq = IRQ_CORETMR; |
| 1239 | goto core_tick; | ||
| 1240 | } | ||
| 1241 | 1234 | ||
| 1242 | SSYNC(); | 1235 | } else { |
| 1243 | 1236 | #if defined(SIC_ISR0) || defined(SICA_ISR0) | |
| 1244 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) | ||
| 1245 | { | ||
| 1246 | unsigned long sic_status[3]; | 1237 | unsigned long sic_status[3]; |
| 1247 | 1238 | ||
| 1248 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); | 1239 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); |
| 1249 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); | 1240 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); |
| 1250 | #ifdef CONFIG_BF54x | 1241 | # ifdef SIC_ISR2 |
| 1251 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); | 1242 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); |
| 1252 | #endif | 1243 | # endif |
| 1253 | for (;; ivg++) { | 1244 | for (;; ivg++) { |
| 1254 | if (ivg >= ivg_stop) { | 1245 | if (ivg >= ivg_stop) { |
| 1255 | atomic_inc(&num_spurious); | 1246 | atomic_inc(&num_spurious); |
| @@ -1258,9 +1249,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | |||
| 1258 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) | 1249 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) |
| 1259 | break; | 1250 | break; |
| 1260 | } | 1251 | } |
| 1261 | } | ||
| 1262 | #else | 1252 | #else |
| 1263 | { | ||
| 1264 | unsigned long sic_status; | 1253 | unsigned long sic_status; |
| 1265 | 1254 | ||
| 1266 | sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); | 1255 | sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); |
| @@ -1272,15 +1261,13 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | |||
| 1272 | } else if (sic_status & ivg->isrflag) | 1261 | } else if (sic_status & ivg->isrflag) |
| 1273 | break; | 1262 | break; |
| 1274 | } | 1263 | } |
| 1275 | } | ||
| 1276 | #endif | 1264 | #endif |
| 1277 | 1265 | ||
| 1278 | irq = ivg->irqno; | 1266 | irq = ivg->irqno; |
| 1267 | } | ||
| 1279 | 1268 | ||
| 1280 | if (irq == IRQ_SYSTMR) { | 1269 | if (irq == IRQ_SYSTMR) { |
| 1281 | #ifdef CONFIG_GENERIC_CLOCKEVENTS | 1270 | #ifndef CONFIG_GENERIC_CLOCKEVENTS |
| 1282 | core_tick: | ||
| 1283 | #else | ||
| 1284 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ | 1271 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ |
| 1285 | #endif | 1272 | #endif |
| 1286 | /* This is basically what we need from the register frame. */ | 1273 | /* This is basically what we need from the register frame. */ |
| @@ -1292,9 +1279,6 @@ core_tick: | |||
| 1292 | __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; | 1279 | __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; |
| 1293 | } | 1280 | } |
| 1294 | 1281 | ||
| 1295 | #ifndef CONFIG_GENERIC_CLOCKEVENTS | ||
| 1296 | core_tick: | ||
| 1297 | #endif | ||
| 1298 | if (this_domain == ipipe_root_domain) { | 1282 | if (this_domain == ipipe_root_domain) { |
| 1299 | s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); | 1283 | s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); |
| 1300 | barrier(); | 1284 | barrier(); |
| @@ -1312,7 +1296,7 @@ core_tick: | |||
| 1312 | } | 1296 | } |
| 1313 | } | 1297 | } |
| 1314 | 1298 | ||
| 1315 | return 0; | 1299 | return 0; |
| 1316 | } | 1300 | } |
| 1317 | 1301 | ||
| 1318 | #endif /* CONFIG_IPIPE */ | 1302 | #endif /* CONFIG_IPIPE */ |
diff --git a/arch/blackfin/mach-common/irqpanic.c b/arch/blackfin/mach-common/irqpanic.c index 05004df0f78b..883e3241b17e 100644 --- a/arch/blackfin/mach-common/irqpanic.c +++ b/arch/blackfin/mach-common/irqpanic.c | |||
| @@ -30,21 +30,17 @@ | |||
| 30 | #include <linux/module.h> | 30 | #include <linux/module.h> |
| 31 | #include <linux/kernel_stat.h> | 31 | #include <linux/kernel_stat.h> |
| 32 | #include <linux/sched.h> | 32 | #include <linux/sched.h> |
| 33 | #include <asm/traps.h> | ||
| 34 | #include <asm/blackfin.h> | 33 | #include <asm/blackfin.h> |
| 35 | 34 | ||
| 36 | #ifdef CONFIG_DEBUG_ICACHE_CHECK | ||
| 37 | #define L1_ICACHE_START 0xffa10000 | 35 | #define L1_ICACHE_START 0xffa10000 |
| 38 | #define L1_ICACHE_END 0xffa13fff | 36 | #define L1_ICACHE_END 0xffa13fff |
| 39 | void irq_panic(int reason, struct pt_regs *regs) __attribute__ ((l1_text)); | ||
| 40 | #endif | ||
| 41 | 37 | ||
| 42 | /* | 38 | /* |
| 43 | * irq_panic - calls panic with string setup | 39 | * irq_panic - calls panic with string setup |
| 44 | */ | 40 | */ |
| 41 | __attribute__ ((l1_text)) | ||
| 45 | asmlinkage void irq_panic(int reason, struct pt_regs *regs) | 42 | asmlinkage void irq_panic(int reason, struct pt_regs *regs) |
| 46 | { | 43 | { |
| 47 | #ifdef CONFIG_DEBUG_ICACHE_CHECK | ||
| 48 | unsigned int cmd, tag, ca, cache_hi, cache_lo, *pa; | 44 | unsigned int cmd, tag, ca, cache_hi, cache_lo, *pa; |
| 49 | unsigned short i, j, die; | 45 | unsigned short i, j, die; |
| 50 | unsigned int bad[10][6]; | 46 | unsigned int bad[10][6]; |
| @@ -126,9 +122,6 @@ asmlinkage void irq_panic(int reason, struct pt_regs *regs) | |||
| 126 | bad[j][3], bad[j][4], bad[j][5]); | 122 | bad[j][3], bad[j][4], bad[j][5]); |
| 127 | } | 123 | } |
| 128 | panic("icache coherency error"); | 124 | panic("icache coherency error"); |
| 129 | } else { | 125 | } else |
| 130 | printk(KERN_EMERG "icache checked, and OK\n"); | 126 | printk(KERN_EMERG "icache checked, and OK\n"); |
| 131 | } | ||
| 132 | #endif | ||
| 133 | |||
| 134 | } | 127 | } |
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c index 93eab6146079..61840059dfac 100644 --- a/arch/blackfin/mach-common/smp.c +++ b/arch/blackfin/mach-common/smp.c | |||
| @@ -43,8 +43,13 @@ | |||
| 43 | #include <asm/processor.h> | 43 | #include <asm/processor.h> |
| 44 | #include <asm/ptrace.h> | 44 | #include <asm/ptrace.h> |
| 45 | #include <asm/cpu.h> | 45 | #include <asm/cpu.h> |
| 46 | #include <asm/time.h> | ||
| 46 | #include <linux/err.h> | 47 | #include <linux/err.h> |
| 47 | 48 | ||
| 49 | /* | ||
| 50 | * Anomaly notes: | ||
| 51 | * 05000120 - we always define corelock as 32-bit integer in L2 | ||
| 52 | */ | ||
| 48 | struct corelock_slot corelock __attribute__ ((__section__(".l2.bss"))); | 53 | struct corelock_slot corelock __attribute__ ((__section__(".l2.bss"))); |
| 49 | 54 | ||
| 50 | void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb, | 55 | void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb, |
| @@ -139,7 +144,7 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg) | |||
| 139 | 144 | ||
| 140 | static irqreturn_t ipi_handler(int irq, void *dev_instance) | 145 | static irqreturn_t ipi_handler(int irq, void *dev_instance) |
| 141 | { | 146 | { |
| 142 | struct ipi_message *msg, *mg; | 147 | struct ipi_message *msg; |
| 143 | struct ipi_message_queue *msg_queue; | 148 | struct ipi_message_queue *msg_queue; |
| 144 | unsigned int cpu = smp_processor_id(); | 149 | unsigned int cpu = smp_processor_id(); |
| 145 | 150 | ||
| @@ -149,7 +154,8 @@ static irqreturn_t ipi_handler(int irq, void *dev_instance) | |||
| 149 | msg_queue->count++; | 154 | msg_queue->count++; |
| 150 | 155 | ||
| 151 | spin_lock(&msg_queue->lock); | 156 | spin_lock(&msg_queue->lock); |
| 152 | list_for_each_entry_safe(msg, mg, &msg_queue->head, list) { | 157 | while (!list_empty(&msg_queue->head)) { |
| 158 | msg = list_entry(msg_queue->head.next, typeof(*msg), list); | ||
| 153 | list_del(&msg->list); | 159 | list_del(&msg->list); |
| 154 | switch (msg->type) { | 160 | switch (msg->type) { |
| 155 | case BFIN_IPI_RESCHEDULE: | 161 | case BFIN_IPI_RESCHEDULE: |
| @@ -216,7 +222,7 @@ int smp_call_function(void (*func)(void *info), void *info, int wait) | |||
| 216 | for_each_cpu_mask(cpu, callmap) { | 222 | for_each_cpu_mask(cpu, callmap) { |
| 217 | msg_queue = &per_cpu(ipi_msg_queue, cpu); | 223 | msg_queue = &per_cpu(ipi_msg_queue, cpu); |
| 218 | spin_lock_irqsave(&msg_queue->lock, flags); | 224 | spin_lock_irqsave(&msg_queue->lock, flags); |
| 219 | list_add(&msg->list, &msg_queue->head); | 225 | list_add_tail(&msg->list, &msg_queue->head); |
| 220 | spin_unlock_irqrestore(&msg_queue->lock, flags); | 226 | spin_unlock_irqrestore(&msg_queue->lock, flags); |
| 221 | platform_send_ipi_cpu(cpu); | 227 | platform_send_ipi_cpu(cpu); |
| 222 | } | 228 | } |
| @@ -256,7 +262,7 @@ int smp_call_function_single(int cpuid, void (*func) (void *info), void *info, | |||
| 256 | 262 | ||
| 257 | msg_queue = &per_cpu(ipi_msg_queue, cpu); | 263 | msg_queue = &per_cpu(ipi_msg_queue, cpu); |
| 258 | spin_lock_irqsave(&msg_queue->lock, flags); | 264 | spin_lock_irqsave(&msg_queue->lock, flags); |
| 259 | list_add(&msg->list, &msg_queue->head); | 265 | list_add_tail(&msg->list, &msg_queue->head); |
| 260 | spin_unlock_irqrestore(&msg_queue->lock, flags); | 266 | spin_unlock_irqrestore(&msg_queue->lock, flags); |
| 261 | platform_send_ipi_cpu(cpu); | 267 | platform_send_ipi_cpu(cpu); |
| 262 | 268 | ||
| @@ -287,7 +293,7 @@ void smp_send_reschedule(int cpu) | |||
| 287 | 293 | ||
| 288 | msg_queue = &per_cpu(ipi_msg_queue, cpu); | 294 | msg_queue = &per_cpu(ipi_msg_queue, cpu); |
| 289 | spin_lock_irqsave(&msg_queue->lock, flags); | 295 | spin_lock_irqsave(&msg_queue->lock, flags); |
| 290 | list_add(&msg->list, &msg_queue->head); | 296 | list_add_tail(&msg->list, &msg_queue->head); |
| 291 | spin_unlock_irqrestore(&msg_queue->lock, flags); | 297 | spin_unlock_irqrestore(&msg_queue->lock, flags); |
| 292 | platform_send_ipi_cpu(cpu); | 298 | platform_send_ipi_cpu(cpu); |
| 293 | 299 | ||
| @@ -315,7 +321,7 @@ void smp_send_stop(void) | |||
| 315 | for_each_cpu_mask(cpu, callmap) { | 321 | for_each_cpu_mask(cpu, callmap) { |
| 316 | msg_queue = &per_cpu(ipi_msg_queue, cpu); | 322 | msg_queue = &per_cpu(ipi_msg_queue, cpu); |
| 317 | spin_lock_irqsave(&msg_queue->lock, flags); | 323 | spin_lock_irqsave(&msg_queue->lock, flags); |
| 318 | list_add(&msg->list, &msg_queue->head); | 324 | list_add_tail(&msg->list, &msg_queue->head); |
| 319 | spin_unlock_irqrestore(&msg_queue->lock, flags); | 325 | spin_unlock_irqrestore(&msg_queue->lock, flags); |
| 320 | platform_send_ipi_cpu(cpu); | 326 | platform_send_ipi_cpu(cpu); |
| 321 | } | 327 | } |
| @@ -352,7 +358,7 @@ int __cpuinit __cpu_up(unsigned int cpu) | |||
| 352 | 358 | ||
| 353 | static void __cpuinit setup_secondary(unsigned int cpu) | 359 | static void __cpuinit setup_secondary(unsigned int cpu) |
| 354 | { | 360 | { |
| 355 | #if !(defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)) | 361 | #if !defined(CONFIG_TICKSOURCE_GPTMR0) |
| 356 | struct irq_desc *timer_desc; | 362 | struct irq_desc *timer_desc; |
| 357 | #endif | 363 | #endif |
| 358 | unsigned long ilat; | 364 | unsigned long ilat; |
| @@ -364,16 +370,13 @@ static void __cpuinit setup_secondary(unsigned int cpu) | |||
| 364 | bfin_write_ILAT(ilat); | 370 | bfin_write_ILAT(ilat); |
| 365 | CSYNC(); | 371 | CSYNC(); |
| 366 | 372 | ||
| 367 | /* Reserve the PDA space for the secondary CPU. */ | ||
| 368 | reserve_pda(); | ||
| 369 | |||
| 370 | /* Enable interrupt levels IVG7-15. IARs have been already | 373 | /* Enable interrupt levels IVG7-15. IARs have been already |
| 371 | * programmed by the boot CPU. */ | 374 | * programmed by the boot CPU. */ |
| 372 | bfin_irq_flags |= IMASK_IVG15 | | 375 | bfin_irq_flags |= IMASK_IVG15 | |
| 373 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | | 376 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
| 374 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; | 377 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
| 375 | 378 | ||
| 376 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) | 379 | #if defined(CONFIG_TICKSOURCE_GPTMR0) |
| 377 | /* Power down the core timer, just to play safe. */ | 380 | /* Power down the core timer, just to play safe. */ |
| 378 | bfin_write_TCNTL(0); | 381 | bfin_write_TCNTL(0); |
| 379 | 382 | ||
| @@ -466,6 +469,17 @@ void smp_icache_flush_range_others(unsigned long start, unsigned long end) | |||
| 466 | } | 469 | } |
| 467 | EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); | 470 | EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); |
| 468 | 471 | ||
| 472 | #ifdef __ARCH_SYNC_CORE_ICACHE | ||
| 473 | void resync_core_icache(void) | ||
| 474 | { | ||
| 475 | unsigned int cpu = get_cpu(); | ||
| 476 | blackfin_invalidate_entire_icache(); | ||
| 477 | ++per_cpu(cpu_data, cpu).icache_invld_count; | ||
| 478 | put_cpu(); | ||
| 479 | } | ||
| 480 | EXPORT_SYMBOL(resync_core_icache); | ||
| 481 | #endif | ||
| 482 | |||
| 469 | #ifdef __ARCH_SYNC_CORE_DCACHE | 483 | #ifdef __ARCH_SYNC_CORE_DCACHE |
| 470 | unsigned long barrier_mask __attribute__ ((__section__(".l2.bss"))); | 484 | unsigned long barrier_mask __attribute__ ((__section__(".l2.bss"))); |
| 471 | 485 | ||
diff --git a/arch/blackfin/mm/blackfin_sram.h b/arch/blackfin/mm/blackfin_sram.h index 8cb0945563f9..bc0062884fde 100644 --- a/arch/blackfin/mm/blackfin_sram.h +++ b/arch/blackfin/mm/blackfin_sram.h | |||
| @@ -30,7 +30,6 @@ | |||
| 30 | #ifndef __BLACKFIN_SRAM_H__ | 30 | #ifndef __BLACKFIN_SRAM_H__ |
| 31 | #define __BLACKFIN_SRAM_H__ | 31 | #define __BLACKFIN_SRAM_H__ |
| 32 | 32 | ||
| 33 | extern void bfin_sram_init(void); | ||
| 34 | extern void *l1sram_alloc(size_t); | 33 | extern void *l1sram_alloc(size_t); |
| 35 | 34 | ||
| 36 | #endif | 35 | #endif |
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index 9c3629b9a689..014a55abd09a 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c | |||
| @@ -52,9 +52,14 @@ static unsigned long empty_bad_page_table; | |||
| 52 | 52 | ||
| 53 | static unsigned long empty_bad_page; | 53 | static unsigned long empty_bad_page; |
| 54 | 54 | ||
| 55 | unsigned long empty_zero_page; | 55 | static unsigned long empty_zero_page; |
| 56 | 56 | ||
| 57 | extern unsigned long exception_stack[NR_CPUS][1024]; | 57 | #ifndef CONFIG_EXCEPTION_L1_SCRATCH |
| 58 | #if defined CONFIG_SYSCALL_TAB_L1 | ||
| 59 | __attribute__((l1_data)) | ||
| 60 | #endif | ||
| 61 | static unsigned long exception_stack[NR_CPUS][1024]; | ||
| 62 | #endif | ||
| 58 | 63 | ||
| 59 | struct blackfin_pda cpu_pda[NR_CPUS]; | 64 | struct blackfin_pda cpu_pda[NR_CPUS]; |
| 60 | EXPORT_SYMBOL(cpu_pda); | 65 | EXPORT_SYMBOL(cpu_pda); |
| @@ -117,19 +122,18 @@ asmlinkage void __init init_pda(void) | |||
| 117 | cpu_pda[0].next = &cpu_pda[1]; | 122 | cpu_pda[0].next = &cpu_pda[1]; |
| 118 | cpu_pda[1].next = &cpu_pda[0]; | 123 | cpu_pda[1].next = &cpu_pda[0]; |
| 119 | 124 | ||
| 125 | #ifdef CONFIG_EXCEPTION_L1_SCRATCH | ||
| 126 | cpu_pda[cpu].ex_stack = (unsigned long *)(L1_SCRATCH_START + \ | ||
| 127 | L1_SCRATCH_LENGTH); | ||
| 128 | #else | ||
| 120 | cpu_pda[cpu].ex_stack = exception_stack[cpu + 1]; | 129 | cpu_pda[cpu].ex_stack = exception_stack[cpu + 1]; |
| 130 | #endif | ||
| 121 | 131 | ||
| 122 | #ifdef CONFIG_SMP | 132 | #ifdef CONFIG_SMP |
| 123 | cpu_pda[cpu].imask = 0x1f; | 133 | cpu_pda[cpu].imask = 0x1f; |
| 124 | #endif | 134 | #endif |
| 125 | } | 135 | } |
| 126 | 136 | ||
| 127 | void __cpuinit reserve_pda(void) | ||
| 128 | { | ||
| 129 | printk(KERN_INFO "PDA for CPU%u reserved at %p\n", smp_processor_id(), | ||
| 130 | &cpu_pda[smp_processor_id()]); | ||
| 131 | } | ||
| 132 | |||
| 133 | void __init mem_init(void) | 137 | void __init mem_init(void) |
| 134 | { | 138 | { |
| 135 | unsigned int codek = 0, datak = 0, initk = 0; | 139 | unsigned int codek = 0, datak = 0, initk = 0; |
| @@ -171,19 +175,6 @@ void __init mem_init(void) | |||
| 171 | initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10))); | 175 | initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10))); |
| 172 | } | 176 | } |
| 173 | 177 | ||
| 174 | static int __init sram_init(void) | ||
| 175 | { | ||
| 176 | /* Initialize the blackfin L1 Memory. */ | ||
| 177 | bfin_sram_init(); | ||
| 178 | |||
| 179 | /* Reserve the PDA space for the boot CPU right after we | ||
| 180 | * initialized the scratch memory allocator. | ||
| 181 | */ | ||
| 182 | reserve_pda(); | ||
| 183 | return 0; | ||
| 184 | } | ||
| 185 | pure_initcall(sram_init); | ||
| 186 | |||
| 187 | static void __init free_init_pages(const char *what, unsigned long begin, unsigned long end) | 178 | static void __init free_init_pages(const char *what, unsigned long begin, unsigned long end) |
| 188 | { | 179 | { |
| 189 | unsigned long addr; | 180 | unsigned long addr; |
diff --git a/arch/blackfin/mm/isram-driver.c b/arch/blackfin/mm/isram-driver.c index 22913e7a1818..c080e70f98b0 100644 --- a/arch/blackfin/mm/isram-driver.c +++ b/arch/blackfin/mm/isram-driver.c | |||
| @@ -125,7 +125,7 @@ static bool isram_check_addr(const void *addr, size_t n) | |||
| 125 | { | 125 | { |
| 126 | if ((addr >= (void *)L1_CODE_START) && | 126 | if ((addr >= (void *)L1_CODE_START) && |
| 127 | (addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) { | 127 | (addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) { |
| 128 | if ((addr + n) >= (void *)(L1_CODE_START + L1_CODE_LENGTH)) { | 128 | if ((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH)) { |
| 129 | show_stack(NULL, NULL); | 129 | show_stack(NULL, NULL); |
| 130 | printk(KERN_ERR "isram_memcpy: copy involving %p length " | 130 | printk(KERN_ERR "isram_memcpy: copy involving %p length " |
| 131 | "(%zu) too long\n", addr, n); | 131 | "(%zu) too long\n", addr, n); |
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c index 530d1393a232..0bc3c4ef0aad 100644 --- a/arch/blackfin/mm/sram-alloc.c +++ b/arch/blackfin/mm/sram-alloc.c | |||
| @@ -83,6 +83,14 @@ static struct kmem_cache *sram_piece_cache; | |||
| 83 | static void __init l1sram_init(void) | 83 | static void __init l1sram_init(void) |
| 84 | { | 84 | { |
| 85 | unsigned int cpu; | 85 | unsigned int cpu; |
| 86 | unsigned long reserve; | ||
| 87 | |||
| 88 | #ifdef CONFIG_SMP | ||
| 89 | reserve = 0; | ||
| 90 | #else | ||
| 91 | reserve = sizeof(struct l1_scratch_task_info); | ||
| 92 | #endif | ||
| 93 | |||
| 86 | for (cpu = 0; cpu < num_possible_cpus(); ++cpu) { | 94 | for (cpu = 0; cpu < num_possible_cpus(); ++cpu) { |
| 87 | per_cpu(free_l1_ssram_head, cpu).next = | 95 | per_cpu(free_l1_ssram_head, cpu).next = |
| 88 | kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); | 96 | kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); |
| @@ -91,8 +99,8 @@ static void __init l1sram_init(void) | |||
| 91 | return; | 99 | return; |
| 92 | } | 100 | } |
| 93 | 101 | ||
| 94 | per_cpu(free_l1_ssram_head, cpu).next->paddr = (void *)get_l1_scratch_start_cpu(cpu); | 102 | per_cpu(free_l1_ssram_head, cpu).next->paddr = (void *)get_l1_scratch_start_cpu(cpu) + reserve; |
| 95 | per_cpu(free_l1_ssram_head, cpu).next->size = L1_SCRATCH_LENGTH; | 103 | per_cpu(free_l1_ssram_head, cpu).next->size = L1_SCRATCH_LENGTH - reserve; |
| 96 | per_cpu(free_l1_ssram_head, cpu).next->pid = 0; | 104 | per_cpu(free_l1_ssram_head, cpu).next->pid = 0; |
| 97 | per_cpu(free_l1_ssram_head, cpu).next->next = NULL; | 105 | per_cpu(free_l1_ssram_head, cpu).next->next = NULL; |
| 98 | 106 | ||
| @@ -223,7 +231,7 @@ static void __init l2_sram_init(void) | |||
| 223 | spin_lock_init(&l2_sram_lock); | 231 | spin_lock_init(&l2_sram_lock); |
| 224 | } | 232 | } |
| 225 | 233 | ||
| 226 | void __init bfin_sram_init(void) | 234 | static int __init bfin_sram_init(void) |
| 227 | { | 235 | { |
| 228 | sram_piece_cache = kmem_cache_create("sram_piece_cache", | 236 | sram_piece_cache = kmem_cache_create("sram_piece_cache", |
| 229 | sizeof(struct sram_piece), | 237 | sizeof(struct sram_piece), |
| @@ -233,7 +241,10 @@ void __init bfin_sram_init(void) | |||
| 233 | l1_data_sram_init(); | 241 | l1_data_sram_init(); |
| 234 | l1_inst_sram_init(); | 242 | l1_inst_sram_init(); |
| 235 | l2_sram_init(); | 243 | l2_sram_init(); |
| 244 | |||
| 245 | return 0; | ||
| 236 | } | 246 | } |
| 247 | pure_initcall(bfin_sram_init); | ||
| 237 | 248 | ||
| 238 | /* SRAM allocate function */ | 249 | /* SRAM allocate function */ |
| 239 | static void *_sram_alloc(size_t size, struct sram_piece *pfree_head, | 250 | static void *_sram_alloc(size_t size, struct sram_piece *pfree_head, |
| @@ -732,6 +743,10 @@ found: | |||
| 732 | } | 743 | } |
| 733 | EXPORT_SYMBOL(sram_free_with_lsl); | 744 | EXPORT_SYMBOL(sram_free_with_lsl); |
| 734 | 745 | ||
| 746 | /* Allocate memory and keep in L1 SRAM List (lsl) so that the resources are | ||
| 747 | * tracked. These are designed for userspace so that when a process exits, | ||
| 748 | * we can safely reap their resources. | ||
| 749 | */ | ||
| 735 | void *sram_alloc_with_lsl(size_t size, unsigned long flags) | 750 | void *sram_alloc_with_lsl(size_t size, unsigned long flags) |
| 736 | { | 751 | { |
| 737 | void *addr = NULL; | 752 | void *addr = NULL; |