diff options
Diffstat (limited to 'arch/blackfin')
93 files changed, 2772 insertions, 1776 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 7faa2f554ab1..9a01d445eca8 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig | |||
@@ -342,8 +342,9 @@ config MEM_MT48LC64M4A2FB_7E | |||
342 | config MEM_MT48LC16M16A2TG_75 | 342 | config MEM_MT48LC16M16A2TG_75 |
343 | bool | 343 | bool |
344 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | 344 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ |
345 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ | 345 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
346 | || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM) | 346 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ |
347 | || BFIN527_BLUETECHNIX_CM) | ||
347 | default y | 348 | default y |
348 | 349 | ||
349 | config MEM_MT48LC32M8A2_75 | 350 | config MEM_MT48LC32M8A2_75 |
@@ -459,7 +460,7 @@ config VCO_MULT | |||
459 | default "45" if BFIN533_STAMP | 460 | default "45" if BFIN533_STAMP |
460 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) | 461 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
461 | default "22" if BFIN533_BLUETECHNIX_CM | 462 | default "22" if BFIN533_BLUETECHNIX_CM |
462 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) | 463 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
463 | default "20" if BFIN561_EZKIT | 464 | default "20" if BFIN561_EZKIT |
464 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) | 465 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
465 | help | 466 | help |
@@ -574,8 +575,8 @@ config MAX_VCO_HZ | |||
574 | default 400000000 if BF514 | 575 | default 400000000 if BF514 |
575 | default 400000000 if BF516 | 576 | default 400000000 if BF516 |
576 | default 400000000 if BF518 | 577 | default 400000000 if BF518 |
577 | default 600000000 if BF522 | 578 | default 400000000 if BF522 |
578 | default 400000000 if BF523 | 579 | default 600000000 if BF523 |
579 | default 400000000 if BF524 | 580 | default 400000000 if BF524 |
580 | default 600000000 if BF525 | 581 | default 600000000 if BF525 |
581 | default 400000000 if BF526 | 582 | default 400000000 if BF526 |
@@ -647,7 +648,7 @@ config CYCLES_CLOCKSOURCE | |||
647 | writing the registers will most likely crash the kernel. | 648 | writing the registers will most likely crash the kernel. |
648 | 649 | ||
649 | config GPTMR0_CLOCKSOURCE | 650 | config GPTMR0_CLOCKSOURCE |
650 | bool "Use GPTimer0 as a clocksource (higher rating)" | 651 | bool "Use GPTimer0 as a clocksource" |
651 | select BFIN_GPTIMERS | 652 | select BFIN_GPTIMERS |
652 | depends on GENERIC_CLOCKEVENTS | 653 | depends on GENERIC_CLOCKEVENTS |
653 | depends on !TICKSOURCE_GPTMR0 | 654 | depends on !TICKSOURCE_GPTMR0 |
@@ -917,10 +918,6 @@ comment "Cache Support" | |||
917 | config BFIN_ICACHE | 918 | config BFIN_ICACHE |
918 | bool "Enable ICACHE" | 919 | bool "Enable ICACHE" |
919 | default y | 920 | default y |
920 | config BFIN_ICACHE_LOCK | ||
921 | bool "Enable Instruction Cache Locking" | ||
922 | depends on BFIN_ICACHE | ||
923 | default n | ||
924 | config BFIN_EXTMEM_ICACHEABLE | 921 | config BFIN_EXTMEM_ICACHEABLE |
925 | bool "Enable ICACHE for external memory" | 922 | bool "Enable ICACHE for external memory" |
926 | depends on BFIN_ICACHE | 923 | depends on BFIN_ICACHE |
@@ -987,7 +984,7 @@ endchoice | |||
987 | config BFIN_L2_DCACHEABLE | 984 | config BFIN_L2_DCACHEABLE |
988 | bool "Enable DCACHE for L2 SRAM" | 985 | bool "Enable DCACHE for L2 SRAM" |
989 | depends on BFIN_DCACHE | 986 | depends on BFIN_DCACHE |
990 | depends on BF54x || BF561 | 987 | depends on (BF54x || BF561) && !SMP |
991 | default n | 988 | default n |
992 | choice | 989 | choice |
993 | prompt "L2 SRAM DCACHE policy" | 990 | prompt "L2 SRAM DCACHE policy" |
@@ -995,11 +992,9 @@ choice | |||
995 | default BFIN_L2_WRITEBACK | 992 | default BFIN_L2_WRITEBACK |
996 | config BFIN_L2_WRITEBACK | 993 | config BFIN_L2_WRITEBACK |
997 | bool "Write back" | 994 | bool "Write back" |
998 | depends on !SMP | ||
999 | 995 | ||
1000 | config BFIN_L2_WRITETHROUGH | 996 | config BFIN_L2_WRITETHROUGH |
1001 | bool "Write through" | 997 | bool "Write through" |
1002 | depends on !SMP | ||
1003 | endchoice | 998 | endchoice |
1004 | 999 | ||
1005 | 1000 | ||
@@ -1154,11 +1149,12 @@ source "fs/Kconfig.binfmt" | |||
1154 | endmenu | 1149 | endmenu |
1155 | 1150 | ||
1156 | menu "Power management options" | 1151 | menu "Power management options" |
1152 | depends on !SMP | ||
1153 | |||
1157 | source "kernel/power/Kconfig" | 1154 | source "kernel/power/Kconfig" |
1158 | 1155 | ||
1159 | config ARCH_SUSPEND_POSSIBLE | 1156 | config ARCH_SUSPEND_POSSIBLE |
1160 | def_bool y | 1157 | def_bool y |
1161 | depends on !SMP | ||
1162 | 1158 | ||
1163 | choice | 1159 | choice |
1164 | prompt "Standby Power Saving Mode" | 1160 | prompt "Standby Power Saving Mode" |
@@ -1246,6 +1242,7 @@ config PM_BFIN_WAKE_GP | |||
1246 | endmenu | 1242 | endmenu |
1247 | 1243 | ||
1248 | menu "CPU Frequency scaling" | 1244 | menu "CPU Frequency scaling" |
1245 | depends on !SMP | ||
1249 | 1246 | ||
1250 | source "drivers/cpufreq/Kconfig" | 1247 | source "drivers/cpufreq/Kconfig" |
1251 | 1248 | ||
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug index 1fc4981d486f..87f195ee2e06 100644 --- a/arch/blackfin/Kconfig.debug +++ b/arch/blackfin/Kconfig.debug | |||
@@ -252,4 +252,10 @@ config ACCESS_CHECK | |||
252 | 252 | ||
253 | Say N here to disable that check to improve the performance. | 253 | Say N here to disable that check to improve the performance. |
254 | 254 | ||
255 | config BFIN_ISRAM_SELF_TEST | ||
256 | bool "isram boot self tests" | ||
257 | default n | ||
258 | help | ||
259 | Run some self tests of the isram driver code at boot. | ||
260 | |||
255 | endmenu | 261 | endmenu |
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig index dcfb4889559a..9905b26009e5 100644 --- a/arch/blackfin/configs/BF518F-EZBRD_defconfig +++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig | |||
@@ -358,9 +358,9 @@ CONFIG_C_AMBEN_ALL=y | |||
358 | # EBIU_AMBCTL Control | 358 | # EBIU_AMBCTL Control |
359 | # | 359 | # |
360 | CONFIG_BANK_0=0x7BB0 | 360 | CONFIG_BANK_0=0x7BB0 |
361 | CONFIG_BANK_1=0x5554 | 361 | CONFIG_BANK_1=0x7BB0 |
362 | CONFIG_BANK_2=0x7BB0 | 362 | CONFIG_BANK_2=0x7BB0 |
363 | CONFIG_BANK_3=0xFFC0 | 363 | CONFIG_BANK_3=0x99B2 |
364 | 364 | ||
365 | # | 365 | # |
366 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | 366 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) |
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig index 48a3a7a9099c..9dc682088023 100644 --- a/arch/blackfin/configs/BF526-EZBRD_defconfig +++ b/arch/blackfin/configs/BF526-EZBRD_defconfig | |||
@@ -359,9 +359,9 @@ CONFIG_C_AMBEN_ALL=y | |||
359 | # EBIU_AMBCTL Control | 359 | # EBIU_AMBCTL Control |
360 | # | 360 | # |
361 | CONFIG_BANK_0=0x7BB0 | 361 | CONFIG_BANK_0=0x7BB0 |
362 | CONFIG_BANK_1=0x5554 | 362 | CONFIG_BANK_1=0x7BB0 |
363 | CONFIG_BANK_2=0x7BB0 | 363 | CONFIG_BANK_2=0x7BB0 |
364 | CONFIG_BANK_3=0xFFC0 | 364 | CONFIG_BANK_3=0x99B2 |
365 | 365 | ||
366 | # | 366 | # |
367 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | 367 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) |
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig index dd8352791daf..77e35d4baf53 100644 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT_defconfig | |||
@@ -363,9 +363,9 @@ CONFIG_C_AMBEN_ALL=y | |||
363 | # EBIU_AMBCTL Control | 363 | # EBIU_AMBCTL Control |
364 | # | 364 | # |
365 | CONFIG_BANK_0=0x7BB0 | 365 | CONFIG_BANK_0=0x7BB0 |
366 | CONFIG_BANK_1=0x5554 | 366 | CONFIG_BANK_1=0x7BB0 |
367 | CONFIG_BANK_2=0x7BB0 | 367 | CONFIG_BANK_2=0x7BB0 |
368 | CONFIG_BANK_3=0xFFC0 | 368 | CONFIG_BANK_3=0x99B2 |
369 | 369 | ||
370 | # | 370 | # |
371 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | 371 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) |
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index b3d3cab81cfe..f773ad1155d4 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig | |||
@@ -400,7 +400,7 @@ CONFIG_C_AMBEN_ALL=y | |||
400 | # EBIU_AMBCTL Control | 400 | # EBIU_AMBCTL Control |
401 | # | 401 | # |
402 | CONFIG_BANK_0=0x7BB0 | 402 | CONFIG_BANK_0=0x7BB0 |
403 | CONFIG_BANK_1=0x5554 | 403 | CONFIG_BANK_1=0x7BB0 |
404 | CONFIG_BANK_2=0x7BB0 | 404 | CONFIG_BANK_2=0x7BB0 |
405 | CONFIG_BANK_3=0x99B2 | 405 | CONFIG_BANK_3=0x99B2 |
406 | CONFIG_EBIU_MBSCTLVAL=0x0 | 406 | CONFIG_EBIU_MBSCTLVAL=0x0 |
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h index e39277ea43e8..aef0594e7865 100644 --- a/arch/blackfin/include/asm/bfin-global.h +++ b/arch/blackfin/include/asm/bfin-global.h | |||
@@ -66,7 +66,6 @@ extern void program_IAR(void); | |||
66 | 66 | ||
67 | extern asmlinkage void lower_to_irq14(void); | 67 | extern asmlinkage void lower_to_irq14(void); |
68 | extern asmlinkage void bfin_return_from_exception(void); | 68 | extern asmlinkage void bfin_return_from_exception(void); |
69 | extern asmlinkage void evt14_softirq(void); | ||
70 | extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); | 69 | extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); |
71 | extern int bfin_internal_set_wake(unsigned int irq, unsigned int state); | 70 | extern int bfin_internal_set_wake(unsigned int irq, unsigned int state); |
72 | 71 | ||
@@ -100,11 +99,6 @@ extern unsigned long bfin_sic_iwr[]; | |||
100 | extern unsigned vr_wakeup; | 99 | extern unsigned vr_wakeup; |
101 | extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ | 100 | extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ |
102 | 101 | ||
103 | #ifdef CONFIG_BFIN_ICACHE_LOCK | ||
104 | extern void cache_grab_lock(int way); | ||
105 | extern void bfin_cache_lock(int way); | ||
106 | #endif | ||
107 | |||
108 | #endif | 102 | #endif |
109 | 103 | ||
110 | #endif /* _BLACKFIN_H_ */ | 104 | #endif /* _BLACKFIN_H_ */ |
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h index aaeb4df10d57..c281c6328276 100644 --- a/arch/blackfin/include/asm/bfin5xx_spi.h +++ b/arch/blackfin/include/asm/bfin5xx_spi.h | |||
@@ -127,6 +127,7 @@ struct bfin5xx_spi_chip { | |||
127 | u32 cs_gpio; | 127 | u32 cs_gpio; |
128 | /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */ | 128 | /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */ |
129 | u16 idle_tx_val; | 129 | u16 idle_tx_val; |
130 | u8 pio_interrupt; /* Enable spi data irq */ | ||
130 | }; | 131 | }; |
131 | 132 | ||
132 | #endif /* _SPI_CHANNEL_H_ */ | 133 | #endif /* _SPI_CHANNEL_H_ */ |
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index c5dacf8f8cf9..d18d16837a6d 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h | |||
@@ -125,4 +125,48 @@ | |||
125 | #define FAULT_USERSUPV (1 << 17) | 125 | #define FAULT_USERSUPV (1 << 17) |
126 | #define FAULT_CPLBBITS 0x0000ffff | 126 | #define FAULT_CPLBBITS 0x0000ffff |
127 | 127 | ||
128 | #endif /* _CPLB_H */ | 128 | #ifndef __ASSEMBLY__ |
129 | |||
130 | static inline void _disable_cplb(u32 mmr, u32 mask) | ||
131 | { | ||
132 | u32 ctrl = bfin_read32(mmr) & ~mask; | ||
133 | /* CSYNC to ensure load store ordering */ | ||
134 | __builtin_bfin_csync(); | ||
135 | bfin_write32(mmr, ctrl); | ||
136 | __builtin_bfin_ssync(); | ||
137 | } | ||
138 | static inline void disable_cplb(u32 mmr, u32 mask) | ||
139 | { | ||
140 | u32 ctrl = bfin_read32(mmr) & ~mask; | ||
141 | CSYNC(); | ||
142 | bfin_write32(mmr, ctrl); | ||
143 | SSYNC(); | ||
144 | } | ||
145 | #define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB) | ||
146 | #define disable_dcplb() disable_cplb(DMEM_CONTROL, ENDCPLB) | ||
147 | #define _disable_icplb() _disable_cplb(IMEM_CONTROL, ENICPLB) | ||
148 | #define disable_icplb() disable_cplb(IMEM_CONTROL, ENICPLB) | ||
149 | |||
150 | static inline void _enable_cplb(u32 mmr, u32 mask) | ||
151 | { | ||
152 | u32 ctrl = bfin_read32(mmr) | mask; | ||
153 | /* CSYNC to ensure load store ordering */ | ||
154 | __builtin_bfin_csync(); | ||
155 | bfin_write32(mmr, ctrl); | ||
156 | __builtin_bfin_ssync(); | ||
157 | } | ||
158 | static inline void enable_cplb(u32 mmr, u32 mask) | ||
159 | { | ||
160 | u32 ctrl = bfin_read32(mmr) | mask; | ||
161 | CSYNC(); | ||
162 | bfin_write32(mmr, ctrl); | ||
163 | SSYNC(); | ||
164 | } | ||
165 | #define _enable_dcplb() _enable_cplb(DMEM_CONTROL, ENDCPLB) | ||
166 | #define enable_dcplb() enable_cplb(DMEM_CONTROL, ENDCPLB) | ||
167 | #define _enable_icplb() _enable_cplb(IMEM_CONTROL, ENICPLB) | ||
168 | #define enable_icplb() enable_cplb(IMEM_CONTROL, ENICPLB) | ||
169 | |||
170 | #endif /* __ASSEMBLY__ */ | ||
171 | |||
172 | #endif /* _CPLB_H */ | ||
diff --git a/arch/blackfin/include/asm/early_printk.h b/arch/blackfin/include/asm/early_printk.h index 110f1c1f845c..53a762b6fcd2 100644 --- a/arch/blackfin/include/asm/early_printk.h +++ b/arch/blackfin/include/asm/early_printk.h | |||
@@ -21,8 +21,32 @@ | |||
21 | * GNU General Public License for more details. | 21 | * GNU General Public License for more details. |
22 | */ | 22 | */ |
23 | 23 | ||
24 | |||
25 | #ifndef __ASM_EARLY_PRINTK_H__ | ||
26 | #define __ASM_EARLY_PRINTK_H__ | ||
27 | |||
24 | #ifdef CONFIG_EARLY_PRINTK | 28 | #ifdef CONFIG_EARLY_PRINTK |
29 | /* For those that don't include it already */ | ||
30 | #include <linux/console.h> | ||
31 | |||
25 | extern int setup_early_printk(char *); | 32 | extern int setup_early_printk(char *); |
33 | extern void enable_shadow_console(void); | ||
34 | extern int shadow_console_enabled(void); | ||
35 | extern void mark_shadow_error(void); | ||
36 | extern void early_shadow_reg(unsigned long reg, unsigned int n); | ||
37 | extern void early_shadow_write(struct console *con, const char *s, | ||
38 | unsigned int n) __attribute__((nonnull(2))); | ||
39 | #define early_shadow_puts(str) early_shadow_write(NULL, str, strlen(str)) | ||
40 | #define early_shadow_stamp() \ | ||
41 | do { \ | ||
42 | early_shadow_puts(__FILE__ " : " __stringify(__LINE__) " ["); \ | ||
43 | early_shadow_puts(__func__); \ | ||
44 | early_shadow_puts("]\n"); \ | ||
45 | } while (0) | ||
26 | #else | 46 | #else |
27 | #define setup_early_printk(fmt) do { } while (0) | 47 | #define setup_early_printk(fmt) do { } while (0) |
48 | #define enable_shadow_console(fmt) do { } while (0) | ||
49 | #define early_shadow_stamp() do { } while (0) | ||
28 | #endif /* CONFIG_EARLY_PRINTK */ | 50 | #endif /* CONFIG_EARLY_PRINTK */ |
51 | |||
52 | #endif /* __ASM_EARLY_PRINTK_H__ */ | ||
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h index 5a87baf0659d..c823e8ebbfa1 100644 --- a/arch/blackfin/include/asm/elf.h +++ b/arch/blackfin/include/asm/elf.h | |||
@@ -23,7 +23,7 @@ typedef unsigned long elf_greg_t; | |||
23 | #define ELF_NGREG 40 /* (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) */ | 23 | #define ELF_NGREG 40 /* (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) */ |
24 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | 24 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; |
25 | 25 | ||
26 | typedef struct user_bfinfp_struct elf_fpregset_t; | 26 | typedef struct { } elf_fpregset_t; |
27 | /* | 27 | /* |
28 | * This is used to ensure we don't load something for the wrong architecture. | 28 | * This is used to ensure we don't load something for the wrong architecture. |
29 | */ | 29 | */ |
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h index ec58efc130e6..55b808fced71 100644 --- a/arch/blackfin/include/asm/entry.h +++ b/arch/blackfin/include/asm/entry.h | |||
@@ -36,6 +36,21 @@ | |||
36 | # define LOAD_IPIPE_IPEND | 36 | # define LOAD_IPIPE_IPEND |
37 | #endif | 37 | #endif |
38 | 38 | ||
39 | /* | ||
40 | * Workaround for anomalies 05000283 and 05000315 | ||
41 | */ | ||
42 | #if ANOMALY_05000283 || ANOMALY_05000315 | ||
43 | # define ANOMALY_283_315_WORKAROUND(preg, dreg) \ | ||
44 | cc = dreg == dreg; \ | ||
45 | preg.h = HI(CHIPID); \ | ||
46 | preg.l = LO(CHIPID); \ | ||
47 | if cc jump 1f; \ | ||
48 | dreg.l = W[preg]; \ | ||
49 | 1: | ||
50 | #else | ||
51 | # define ANOMALY_283_315_WORKAROUND(preg, dreg) | ||
52 | #endif /* ANOMALY_05000283 || ANOMALY_05000315 */ | ||
53 | |||
39 | #ifndef CONFIG_EXACT_HWERR | 54 | #ifndef CONFIG_EXACT_HWERR |
40 | /* As a debugging aid - we save IPEND when DEBUG_KERNEL is on, | 55 | /* As a debugging aid - we save IPEND when DEBUG_KERNEL is on, |
41 | * otherwise it is a waste of cycles. | 56 | * otherwise it is a waste of cycles. |
@@ -88,17 +103,22 @@ | |||
88 | * As you can see by the code - we actually need to do two SSYNCS - one to | 103 | * As you can see by the code - we actually need to do two SSYNCS - one to |
89 | * make sure the read/writes complete, and another to make sure the hardware | 104 | * make sure the read/writes complete, and another to make sure the hardware |
90 | * error is recognized by the core. | 105 | * error is recognized by the core. |
106 | * | ||
107 | * The extra nop before the SSYNC is to make sure we work around 05000244, | ||
108 | * since the 283/315 workaround includes a branch to the end | ||
91 | */ | 109 | */ |
92 | #define INTERRUPT_ENTRY(N) \ | 110 | #define INTERRUPT_ENTRY(N) \ |
93 | SSYNC; \ | ||
94 | SSYNC; \ | ||
95 | [--sp] = SYSCFG; \ | 111 | [--sp] = SYSCFG; \ |
96 | [--sp] = P0; /*orig_p0*/ \ | 112 | [--sp] = P0; /*orig_p0*/ \ |
97 | [--sp] = R0; /*orig_r0*/ \ | 113 | [--sp] = R0; /*orig_r0*/ \ |
98 | [--sp] = (R7:0,P5:0); \ | 114 | [--sp] = (R7:0,P5:0); \ |
99 | R1 = ASTAT; \ | 115 | R1 = ASTAT; \ |
116 | ANOMALY_283_315_WORKAROUND(p0, r0) \ | ||
100 | P0.L = LO(ILAT); \ | 117 | P0.L = LO(ILAT); \ |
101 | P0.H = HI(ILAT); \ | 118 | P0.H = HI(ILAT); \ |
119 | NOP; \ | ||
120 | SSYNC; \ | ||
121 | SSYNC; \ | ||
102 | R0 = [P0]; \ | 122 | R0 = [P0]; \ |
103 | CC = BITTST(R0, EVT_IVHW_P); \ | 123 | CC = BITTST(R0, EVT_IVHW_P); \ |
104 | IF CC JUMP 1f; \ | 124 | IF CC JUMP 1f; \ |
@@ -118,15 +138,17 @@ | |||
118 | RTI; | 138 | RTI; |
119 | 139 | ||
120 | #define TIMER_INTERRUPT_ENTRY(N) \ | 140 | #define TIMER_INTERRUPT_ENTRY(N) \ |
121 | SSYNC; \ | ||
122 | SSYNC; \ | ||
123 | [--sp] = SYSCFG; \ | 141 | [--sp] = SYSCFG; \ |
124 | [--sp] = P0; /*orig_p0*/ \ | 142 | [--sp] = P0; /*orig_p0*/ \ |
125 | [--sp] = R0; /*orig_r0*/ \ | 143 | [--sp] = R0; /*orig_r0*/ \ |
126 | [--sp] = (R7:0,P5:0); \ | 144 | [--sp] = (R7:0,P5:0); \ |
127 | R1 = ASTAT; \ | 145 | R1 = ASTAT; \ |
146 | ANOMALY_283_315_WORKAROUND(p0, r0) \ | ||
128 | P0.L = LO(ILAT); \ | 147 | P0.L = LO(ILAT); \ |
129 | P0.H = HI(ILAT); \ | 148 | P0.H = HI(ILAT); \ |
149 | NOP; \ | ||
150 | SSYNC; \ | ||
151 | SSYNC; \ | ||
130 | R0 = [P0]; \ | 152 | R0 = [P0]; \ |
131 | CC = BITTST(R0, EVT_IVHW_P); \ | 153 | CC = BITTST(R0, EVT_IVHW_P); \ |
132 | IF CC JUMP 1f; \ | 154 | IF CC JUMP 1f; \ |
diff --git a/arch/blackfin/include/asm/ftrace.h b/arch/blackfin/include/asm/ftrace.h index 8643680f0f78..90c9b400ba6d 100644 --- a/arch/blackfin/include/asm/ftrace.h +++ b/arch/blackfin/include/asm/ftrace.h | |||
@@ -8,6 +8,6 @@ | |||
8 | #ifndef __ASM_BFIN_FTRACE_H__ | 8 | #ifndef __ASM_BFIN_FTRACE_H__ |
9 | #define __ASM_BFIN_FTRACE_H__ | 9 | #define __ASM_BFIN_FTRACE_H__ |
10 | 10 | ||
11 | #define MCOUNT_INSN_SIZE 8 /* sizeof mcount call: LINK + CALL */ | 11 | #define MCOUNT_INSN_SIZE 6 /* sizeof "[++sp] = rets; call __mcount;" */ |
12 | 12 | ||
13 | #endif | 13 | #endif |
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h index 87ba9ad399cb..4617ba66278f 100644 --- a/arch/blackfin/include/asm/ipipe.h +++ b/arch/blackfin/include/asm/ipipe.h | |||
@@ -145,10 +145,6 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); | |||
145 | 145 | ||
146 | int __ipipe_get_irq_priority(unsigned irq); | 146 | int __ipipe_get_irq_priority(unsigned irq); |
147 | 147 | ||
148 | void __ipipe_stall_root_raw(void); | ||
149 | |||
150 | void __ipipe_unstall_root_raw(void); | ||
151 | |||
152 | void __ipipe_serial_debug(const char *fmt, ...); | 148 | void __ipipe_serial_debug(const char *fmt, ...); |
153 | 149 | ||
154 | asmlinkage void __ipipe_call_irqtail(unsigned long addr); | 150 | asmlinkage void __ipipe_call_irqtail(unsigned long addr); |
@@ -234,9 +230,6 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); | |||
234 | #define task_hijacked(p) 0 | 230 | #define task_hijacked(p) 0 |
235 | #define ipipe_trap_notify(t, r) 0 | 231 | #define ipipe_trap_notify(t, r) 0 |
236 | 232 | ||
237 | #define __ipipe_stall_root_raw() do { } while (0) | ||
238 | #define __ipipe_unstall_root_raw() do { } while (0) | ||
239 | |||
240 | #define ipipe_init_irq_threads() do { } while (0) | 233 | #define ipipe_init_irq_threads() do { } while (0) |
241 | #define ipipe_start_irq_thread(irq, desc) 0 | 234 | #define ipipe_start_irq_thread(irq, desc) 0 |
242 | 235 | ||
diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h index 139b5208f9d8..7d9e2d3bbede 100644 --- a/arch/blackfin/include/asm/irq_handler.h +++ b/arch/blackfin/include/asm/irq_handler.h | |||
@@ -17,6 +17,7 @@ asmlinkage void evt_evt10(void); | |||
17 | asmlinkage void evt_evt11(void); | 17 | asmlinkage void evt_evt11(void); |
18 | asmlinkage void evt_evt12(void); | 18 | asmlinkage void evt_evt12(void); |
19 | asmlinkage void evt_evt13(void); | 19 | asmlinkage void evt_evt13(void); |
20 | asmlinkage void evt_evt14(void); | ||
20 | asmlinkage void evt_soft_int1(void); | 21 | asmlinkage void evt_soft_int1(void); |
21 | asmlinkage void evt_system_call(void); | 22 | asmlinkage void evt_system_call(void); |
22 | asmlinkage void init_exception_buff(void); | 23 | asmlinkage void init_exception_buff(void); |
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h index 944e29faae48..040410bb07e1 100644 --- a/arch/blackfin/include/asm/mmu_context.h +++ b/arch/blackfin/include/asm/mmu_context.h | |||
@@ -127,17 +127,17 @@ static inline void protect_page(struct mm_struct *mm, unsigned long addr, | |||
127 | unsigned long idx = page >> 5; | 127 | unsigned long idx = page >> 5; |
128 | unsigned long bit = 1 << (page & 31); | 128 | unsigned long bit = 1 << (page & 31); |
129 | 129 | ||
130 | if (flags & VM_MAYREAD) | 130 | if (flags & VM_READ) |
131 | mask[idx] |= bit; | 131 | mask[idx] |= bit; |
132 | else | 132 | else |
133 | mask[idx] &= ~bit; | 133 | mask[idx] &= ~bit; |
134 | mask += page_mask_nelts; | 134 | mask += page_mask_nelts; |
135 | if (flags & VM_MAYWRITE) | 135 | if (flags & VM_WRITE) |
136 | mask[idx] |= bit; | 136 | mask[idx] |= bit; |
137 | else | 137 | else |
138 | mask[idx] &= ~bit; | 138 | mask[idx] &= ~bit; |
139 | mask += page_mask_nelts; | 139 | mask += page_mask_nelts; |
140 | if (flags & VM_MAYEXEC) | 140 | if (flags & VM_EXEC) |
141 | mask[idx] |= bit; | 141 | mask[idx] |= bit; |
142 | else | 142 | else |
143 | mask[idx] &= ~bit; | 143 | mask[idx] &= ~bit; |
diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h index b42555c1431c..a6f95695731d 100644 --- a/arch/blackfin/include/asm/pda.h +++ b/arch/blackfin/include/asm/pda.h | |||
@@ -50,6 +50,7 @@ struct blackfin_pda { /* Per-processor Data Area */ | |||
50 | unsigned long ex_optr; | 50 | unsigned long ex_optr; |
51 | unsigned long ex_buf[4]; | 51 | unsigned long ex_buf[4]; |
52 | unsigned long ex_imask; /* Saved imask from exception */ | 52 | unsigned long ex_imask; /* Saved imask from exception */ |
53 | unsigned long ex_ipend; /* Saved IPEND from exception */ | ||
53 | unsigned long *ex_stack; /* Exception stack space */ | 54 | unsigned long *ex_stack; /* Exception stack space */ |
54 | 55 | ||
55 | #ifdef ANOMALY_05000261 | 56 | #ifdef ANOMALY_05000261 |
@@ -60,6 +61,12 @@ struct blackfin_pda { /* Per-processor Data Area */ | |||
60 | unsigned long retx; | 61 | unsigned long retx; |
61 | unsigned long seqstat; | 62 | unsigned long seqstat; |
62 | unsigned int __nmi_count; /* number of times NMI asserted on this CPU */ | 63 | unsigned int __nmi_count; /* number of times NMI asserted on this CPU */ |
64 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | ||
65 | unsigned long dcplb_doublefault_addr; | ||
66 | unsigned long icplb_doublefault_addr; | ||
67 | unsigned long retx_doublefault; | ||
68 | unsigned long seqstat_doublefault; | ||
69 | #endif | ||
63 | }; | 70 | }; |
64 | 71 | ||
65 | extern struct blackfin_pda cpu_pda[]; | 72 | extern struct blackfin_pda cpu_pda[]; |
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index 141d9281e4b0..a8ddbc8ed5af 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile | |||
@@ -26,6 +26,7 @@ obj-$(CONFIG_MODULES) += module.o | |||
26 | obj-$(CONFIG_KGDB) += kgdb.o | 26 | obj-$(CONFIG_KGDB) += kgdb.o |
27 | obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o | 27 | obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o |
28 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o | 28 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o |
29 | obj-$(CONFIG_EARLY_PRINTK) += shadow_console.o | ||
29 | obj-$(CONFIG_STACKTRACE) += stacktrace.o | 30 | obj-$(CONFIG_STACKTRACE) += stacktrace.o |
30 | 31 | ||
31 | # the kgdb test puts code into L2 and without linker | 32 | # the kgdb test puts code into L2 and without linker |
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c index b5df9459d6d5..f05d1b99b0ef 100644 --- a/arch/blackfin/kernel/asm-offsets.c +++ b/arch/blackfin/kernel/asm-offsets.c | |||
@@ -145,6 +145,7 @@ int main(void) | |||
145 | DEFINE(PDA_EXBUF, offsetof(struct blackfin_pda, ex_buf)); | 145 | DEFINE(PDA_EXBUF, offsetof(struct blackfin_pda, ex_buf)); |
146 | DEFINE(PDA_EXIMASK, offsetof(struct blackfin_pda, ex_imask)); | 146 | DEFINE(PDA_EXIMASK, offsetof(struct blackfin_pda, ex_imask)); |
147 | DEFINE(PDA_EXSTACK, offsetof(struct blackfin_pda, ex_stack)); | 147 | DEFINE(PDA_EXSTACK, offsetof(struct blackfin_pda, ex_stack)); |
148 | DEFINE(PDA_EXIPEND, offsetof(struct blackfin_pda, ex_ipend)); | ||
148 | #ifdef ANOMALY_05000261 | 149 | #ifdef ANOMALY_05000261 |
149 | DEFINE(PDA_LFRETX, offsetof(struct blackfin_pda, last_cplb_fault_retx)); | 150 | DEFINE(PDA_LFRETX, offsetof(struct blackfin_pda, last_cplb_fault_retx)); |
150 | #endif | 151 | #endif |
@@ -152,6 +153,12 @@ int main(void) | |||
152 | DEFINE(PDA_ICPLB, offsetof(struct blackfin_pda, icplb_fault_addr)); | 153 | DEFINE(PDA_ICPLB, offsetof(struct blackfin_pda, icplb_fault_addr)); |
153 | DEFINE(PDA_RETX, offsetof(struct blackfin_pda, retx)); | 154 | DEFINE(PDA_RETX, offsetof(struct blackfin_pda, retx)); |
154 | DEFINE(PDA_SEQSTAT, offsetof(struct blackfin_pda, seqstat)); | 155 | DEFINE(PDA_SEQSTAT, offsetof(struct blackfin_pda, seqstat)); |
156 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | ||
157 | DEFINE(PDA_DF_DCPLB, offsetof(struct blackfin_pda, dcplb_doublefault_addr)); | ||
158 | DEFINE(PDA_DF_ICPLB, offsetof(struct blackfin_pda, icplb_doublefault_addr)); | ||
159 | DEFINE(PDA_DF_SEQSTAT, offsetof(struct blackfin_pda, seqstat_doublefault)); | ||
160 | DEFINE(PDA_DF_RETX, offsetof(struct blackfin_pda, retx_doublefault)); | ||
161 | #endif | ||
155 | #ifdef CONFIG_SMP | 162 | #ifdef CONFIG_SMP |
156 | /* Inter-core lock (in L2 SRAM) */ | 163 | /* Inter-core lock (in L2 SRAM) */ |
157 | DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot)); | 164 | DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot)); |
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c index 9f9b82816652..384868dedac3 100644 --- a/arch/blackfin/kernel/bfin_dma_5xx.c +++ b/arch/blackfin/kernel/bfin_dma_5xx.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <asm/cacheflush.h> | 19 | #include <asm/cacheflush.h> |
20 | #include <asm/dma.h> | 20 | #include <asm/dma.h> |
21 | #include <asm/uaccess.h> | 21 | #include <asm/uaccess.h> |
22 | #include <asm/early_printk.h> | ||
22 | 23 | ||
23 | /* | 24 | /* |
24 | * To make sure we work around 05000119 - we always check DMA_DONE bit, | 25 | * To make sure we work around 05000119 - we always check DMA_DONE bit, |
@@ -146,8 +147,8 @@ EXPORT_SYMBOL(request_dma); | |||
146 | 147 | ||
147 | int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data) | 148 | int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data) |
148 | { | 149 | { |
149 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | 150 | BUG_ON(channel >= MAX_DMA_CHANNELS || |
150 | && channel < MAX_DMA_CHANNELS)); | 151 | dma_ch[channel].chan_status == DMA_CHANNEL_FREE); |
151 | 152 | ||
152 | if (callback != NULL) { | 153 | if (callback != NULL) { |
153 | int ret; | 154 | int ret; |
@@ -181,8 +182,8 @@ static void clear_dma_buffer(unsigned int channel) | |||
181 | void free_dma(unsigned int channel) | 182 | void free_dma(unsigned int channel) |
182 | { | 183 | { |
183 | pr_debug("freedma() : BEGIN \n"); | 184 | pr_debug("freedma() : BEGIN \n"); |
184 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | 185 | BUG_ON(channel >= MAX_DMA_CHANNELS || |
185 | && channel < MAX_DMA_CHANNELS)); | 186 | dma_ch[channel].chan_status == DMA_CHANNEL_FREE); |
186 | 187 | ||
187 | /* Halt the DMA */ | 188 | /* Halt the DMA */ |
188 | disable_dma(channel); | 189 | disable_dma(channel); |
@@ -236,6 +237,7 @@ void blackfin_dma_resume(void) | |||
236 | */ | 237 | */ |
237 | void __init blackfin_dma_early_init(void) | 238 | void __init blackfin_dma_early_init(void) |
238 | { | 239 | { |
240 | early_shadow_stamp(); | ||
239 | bfin_write_MDMA_S0_CONFIG(0); | 241 | bfin_write_MDMA_S0_CONFIG(0); |
240 | bfin_write_MDMA_S1_CONFIG(0); | 242 | bfin_write_MDMA_S1_CONFIG(0); |
241 | } | 243 | } |
@@ -246,6 +248,8 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size) | |||
246 | unsigned long src = (unsigned long)psrc; | 248 | unsigned long src = (unsigned long)psrc; |
247 | struct dma_register *dst_ch, *src_ch; | 249 | struct dma_register *dst_ch, *src_ch; |
248 | 250 | ||
251 | early_shadow_stamp(); | ||
252 | |||
249 | /* We assume that everything is 4 byte aligned, so include | 253 | /* We assume that everything is 4 byte aligned, so include |
250 | * a basic sanity check | 254 | * a basic sanity check |
251 | */ | 255 | */ |
@@ -300,6 +304,8 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size) | |||
300 | 304 | ||
301 | void __init early_dma_memcpy_done(void) | 305 | void __init early_dma_memcpy_done(void) |
302 | { | 306 | { |
307 | early_shadow_stamp(); | ||
308 | |||
303 | while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) || | 309 | while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) || |
304 | (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE))) | 310 | (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE))) |
305 | continue; | 311 | continue; |
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index 6b9446271371..fc4681c0170e 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c | |||
@@ -722,7 +722,6 @@ void bfin_gpio_pm_hibernate_suspend(void) | |||
722 | gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer; | 722 | gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer; |
723 | gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux; | 723 | gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux; |
724 | gpio_bank_saved[bank].data = gpio_array[bank]->data; | 724 | gpio_bank_saved[bank].data = gpio_array[bank]->data; |
725 | gpio_bank_saved[bank].data = gpio_array[bank]->data; | ||
726 | gpio_bank_saved[bank].inen = gpio_array[bank]->inen; | 725 | gpio_bank_saved[bank].inen = gpio_array[bank]->inen; |
727 | gpio_bank_saved[bank].dir = gpio_array[bank]->dir_set; | 726 | gpio_bank_saved[bank].dir = gpio_array[bank]->dir_set; |
728 | } | 727 | } |
diff --git a/arch/blackfin/kernel/cplb-mpu/Makefile b/arch/blackfin/kernel/cplb-mpu/Makefile index 7d70d3bf3212..394d0b1b28fe 100644 --- a/arch/blackfin/kernel/cplb-mpu/Makefile +++ b/arch/blackfin/kernel/cplb-mpu/Makefile | |||
@@ -2,7 +2,7 @@ | |||
2 | # arch/blackfin/kernel/cplb-nompu/Makefile | 2 | # arch/blackfin/kernel/cplb-nompu/Makefile |
3 | # | 3 | # |
4 | 4 | ||
5 | obj-y := cplbinit.o cacheinit.o cplbmgr.o | 5 | obj-y := cplbinit.o cplbmgr.o |
6 | 6 | ||
7 | CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \ | 7 | CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \ |
8 | -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \ | 8 | -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \ |
diff --git a/arch/blackfin/kernel/cplb-mpu/cacheinit.c b/arch/blackfin/kernel/cplb-mpu/cacheinit.c deleted file mode 100644 index d5a86c3017f7..000000000000 --- a/arch/blackfin/kernel/cplb-mpu/cacheinit.c +++ /dev/null | |||
@@ -1,69 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2004-2007 Analog Devices Inc. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, see the file COPYING, or write | ||
16 | * to the Free Software Foundation, Inc., | ||
17 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
18 | */ | ||
19 | |||
20 | #include <linux/cpu.h> | ||
21 | |||
22 | #include <asm/cacheflush.h> | ||
23 | #include <asm/blackfin.h> | ||
24 | #include <asm/cplb.h> | ||
25 | #include <asm/cplbinit.h> | ||
26 | |||
27 | #if defined(CONFIG_BFIN_ICACHE) | ||
28 | void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl) | ||
29 | { | ||
30 | unsigned long ctrl; | ||
31 | int i; | ||
32 | |||
33 | SSYNC(); | ||
34 | for (i = 0; i < MAX_CPLBS; i++) { | ||
35 | bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr); | ||
36 | bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data); | ||
37 | } | ||
38 | ctrl = bfin_read_IMEM_CONTROL(); | ||
39 | ctrl |= IMC | ENICPLB; | ||
40 | bfin_write_IMEM_CONTROL(ctrl); | ||
41 | SSYNC(); | ||
42 | } | ||
43 | #endif | ||
44 | |||
45 | #if defined(CONFIG_BFIN_DCACHE) | ||
46 | void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) | ||
47 | { | ||
48 | unsigned long ctrl; | ||
49 | int i; | ||
50 | |||
51 | SSYNC(); | ||
52 | for (i = 0; i < MAX_CPLBS; i++) { | ||
53 | bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr); | ||
54 | bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data); | ||
55 | } | ||
56 | |||
57 | ctrl = bfin_read_DMEM_CONTROL(); | ||
58 | |||
59 | /* | ||
60 | * Anomaly notes: | ||
61 | * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL | ||
62 | * register, so that the port preferences for DAG0 and DAG1 are set | ||
63 | * to port B | ||
64 | */ | ||
65 | ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0); | ||
66 | bfin_write_DMEM_CONTROL(ctrl); | ||
67 | SSYNC(); | ||
68 | } | ||
69 | #endif | ||
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index bcdfe9b0b71f..8e1e9e9e9632 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c | |||
@@ -22,6 +22,7 @@ | |||
22 | 22 | ||
23 | #include <asm/blackfin.h> | 23 | #include <asm/blackfin.h> |
24 | #include <asm/cacheflush.h> | 24 | #include <asm/cacheflush.h> |
25 | #include <asm/cplb.h> | ||
25 | #include <asm/cplbinit.h> | 26 | #include <asm/cplbinit.h> |
26 | #include <asm/mmu_context.h> | 27 | #include <asm/mmu_context.h> |
27 | 28 | ||
@@ -41,46 +42,6 @@ int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS]; | |||
41 | int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS]; | 42 | int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS]; |
42 | int nr_cplb_flush[NR_CPUS]; | 43 | int nr_cplb_flush[NR_CPUS]; |
43 | 44 | ||
44 | static inline void disable_dcplb(void) | ||
45 | { | ||
46 | unsigned long ctrl; | ||
47 | SSYNC(); | ||
48 | ctrl = bfin_read_DMEM_CONTROL(); | ||
49 | ctrl &= ~ENDCPLB; | ||
50 | bfin_write_DMEM_CONTROL(ctrl); | ||
51 | SSYNC(); | ||
52 | } | ||
53 | |||
54 | static inline void enable_dcplb(void) | ||
55 | { | ||
56 | unsigned long ctrl; | ||
57 | SSYNC(); | ||
58 | ctrl = bfin_read_DMEM_CONTROL(); | ||
59 | ctrl |= ENDCPLB; | ||
60 | bfin_write_DMEM_CONTROL(ctrl); | ||
61 | SSYNC(); | ||
62 | } | ||
63 | |||
64 | static inline void disable_icplb(void) | ||
65 | { | ||
66 | unsigned long ctrl; | ||
67 | SSYNC(); | ||
68 | ctrl = bfin_read_IMEM_CONTROL(); | ||
69 | ctrl &= ~ENICPLB; | ||
70 | bfin_write_IMEM_CONTROL(ctrl); | ||
71 | SSYNC(); | ||
72 | } | ||
73 | |||
74 | static inline void enable_icplb(void) | ||
75 | { | ||
76 | unsigned long ctrl; | ||
77 | SSYNC(); | ||
78 | ctrl = bfin_read_IMEM_CONTROL(); | ||
79 | ctrl |= ENICPLB; | ||
80 | bfin_write_IMEM_CONTROL(ctrl); | ||
81 | SSYNC(); | ||
82 | } | ||
83 | |||
84 | /* | 45 | /* |
85 | * Given the contents of the status register, return the index of the | 46 | * Given the contents of the status register, return the index of the |
86 | * CPLB that caused the fault. | 47 | * CPLB that caused the fault. |
@@ -198,10 +159,10 @@ static noinline int dcplb_miss(unsigned int cpu) | |||
198 | dcplb_tbl[cpu][idx].addr = addr; | 159 | dcplb_tbl[cpu][idx].addr = addr; |
199 | dcplb_tbl[cpu][idx].data = d_data; | 160 | dcplb_tbl[cpu][idx].data = d_data; |
200 | 161 | ||
201 | disable_dcplb(); | 162 | _disable_dcplb(); |
202 | bfin_write32(DCPLB_DATA0 + idx * 4, d_data); | 163 | bfin_write32(DCPLB_DATA0 + idx * 4, d_data); |
203 | bfin_write32(DCPLB_ADDR0 + idx * 4, addr); | 164 | bfin_write32(DCPLB_ADDR0 + idx * 4, addr); |
204 | enable_dcplb(); | 165 | _enable_dcplb(); |
205 | 166 | ||
206 | return 0; | 167 | return 0; |
207 | } | 168 | } |
@@ -288,10 +249,10 @@ static noinline int icplb_miss(unsigned int cpu) | |||
288 | icplb_tbl[cpu][idx].addr = addr; | 249 | icplb_tbl[cpu][idx].addr = addr; |
289 | icplb_tbl[cpu][idx].data = i_data; | 250 | icplb_tbl[cpu][idx].data = i_data; |
290 | 251 | ||
291 | disable_icplb(); | 252 | _disable_icplb(); |
292 | bfin_write32(ICPLB_DATA0 + idx * 4, i_data); | 253 | bfin_write32(ICPLB_DATA0 + idx * 4, i_data); |
293 | bfin_write32(ICPLB_ADDR0 + idx * 4, addr); | 254 | bfin_write32(ICPLB_ADDR0 + idx * 4, addr); |
294 | enable_icplb(); | 255 | _enable_icplb(); |
295 | 256 | ||
296 | return 0; | 257 | return 0; |
297 | } | 258 | } |
@@ -319,7 +280,7 @@ static noinline int dcplb_protection_fault(unsigned int cpu) | |||
319 | int cplb_hdr(int seqstat, struct pt_regs *regs) | 280 | int cplb_hdr(int seqstat, struct pt_regs *regs) |
320 | { | 281 | { |
321 | int cause = seqstat & 0x3f; | 282 | int cause = seqstat & 0x3f; |
322 | unsigned int cpu = smp_processor_id(); | 283 | unsigned int cpu = raw_smp_processor_id(); |
323 | switch (cause) { | 284 | switch (cause) { |
324 | case 0x23: | 285 | case 0x23: |
325 | return dcplb_protection_fault(cpu); | 286 | return dcplb_protection_fault(cpu); |
@@ -340,19 +301,19 @@ void flush_switched_cplbs(unsigned int cpu) | |||
340 | nr_cplb_flush[cpu]++; | 301 | nr_cplb_flush[cpu]++; |
341 | 302 | ||
342 | local_irq_save_hw(flags); | 303 | local_irq_save_hw(flags); |
343 | disable_icplb(); | 304 | _disable_icplb(); |
344 | for (i = first_switched_icplb; i < MAX_CPLBS; i++) { | 305 | for (i = first_switched_icplb; i < MAX_CPLBS; i++) { |
345 | icplb_tbl[cpu][i].data = 0; | 306 | icplb_tbl[cpu][i].data = 0; |
346 | bfin_write32(ICPLB_DATA0 + i * 4, 0); | 307 | bfin_write32(ICPLB_DATA0 + i * 4, 0); |
347 | } | 308 | } |
348 | enable_icplb(); | 309 | _enable_icplb(); |
349 | 310 | ||
350 | disable_dcplb(); | 311 | _disable_dcplb(); |
351 | for (i = first_switched_dcplb; i < MAX_CPLBS; i++) { | 312 | for (i = first_switched_dcplb; i < MAX_CPLBS; i++) { |
352 | dcplb_tbl[cpu][i].data = 0; | 313 | dcplb_tbl[cpu][i].data = 0; |
353 | bfin_write32(DCPLB_DATA0 + i * 4, 0); | 314 | bfin_write32(DCPLB_DATA0 + i * 4, 0); |
354 | } | 315 | } |
355 | enable_dcplb(); | 316 | _enable_dcplb(); |
356 | local_irq_restore_hw(flags); | 317 | local_irq_restore_hw(flags); |
357 | 318 | ||
358 | } | 319 | } |
@@ -385,7 +346,7 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu) | |||
385 | #endif | 346 | #endif |
386 | } | 347 | } |
387 | 348 | ||
388 | disable_dcplb(); | 349 | _disable_dcplb(); |
389 | for (i = first_mask_dcplb; i < first_switched_dcplb; i++) { | 350 | for (i = first_mask_dcplb; i < first_switched_dcplb; i++) { |
390 | dcplb_tbl[cpu][i].addr = addr; | 351 | dcplb_tbl[cpu][i].addr = addr; |
391 | dcplb_tbl[cpu][i].data = d_data; | 352 | dcplb_tbl[cpu][i].data = d_data; |
@@ -393,6 +354,6 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu) | |||
393 | bfin_write32(DCPLB_ADDR0 + i * 4, addr); | 354 | bfin_write32(DCPLB_ADDR0 + i * 4, addr); |
394 | addr += PAGE_SIZE; | 355 | addr += PAGE_SIZE; |
395 | } | 356 | } |
396 | enable_dcplb(); | 357 | _enable_dcplb(); |
397 | local_irq_restore_hw(flags); | 358 | local_irq_restore_hw(flags); |
398 | } | 359 | } |
diff --git a/arch/blackfin/kernel/cplb-nompu/Makefile b/arch/blackfin/kernel/cplb-nompu/Makefile index 7d70d3bf3212..394d0b1b28fe 100644 --- a/arch/blackfin/kernel/cplb-nompu/Makefile +++ b/arch/blackfin/kernel/cplb-nompu/Makefile | |||
@@ -2,7 +2,7 @@ | |||
2 | # arch/blackfin/kernel/cplb-nompu/Makefile | 2 | # arch/blackfin/kernel/cplb-nompu/Makefile |
3 | # | 3 | # |
4 | 4 | ||
5 | obj-y := cplbinit.o cacheinit.o cplbmgr.o | 5 | obj-y := cplbinit.o cplbmgr.o |
6 | 6 | ||
7 | CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \ | 7 | CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \ |
8 | -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \ | 8 | -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \ |
diff --git a/arch/blackfin/kernel/cplb-nompu/cacheinit.c b/arch/blackfin/kernel/cplb-nompu/cacheinit.c deleted file mode 100644 index d5a86c3017f7..000000000000 --- a/arch/blackfin/kernel/cplb-nompu/cacheinit.c +++ /dev/null | |||
@@ -1,69 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2004-2007 Analog Devices Inc. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, see the file COPYING, or write | ||
16 | * to the Free Software Foundation, Inc., | ||
17 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
18 | */ | ||
19 | |||
20 | #include <linux/cpu.h> | ||
21 | |||
22 | #include <asm/cacheflush.h> | ||
23 | #include <asm/blackfin.h> | ||
24 | #include <asm/cplb.h> | ||
25 | #include <asm/cplbinit.h> | ||
26 | |||
27 | #if defined(CONFIG_BFIN_ICACHE) | ||
28 | void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl) | ||
29 | { | ||
30 | unsigned long ctrl; | ||
31 | int i; | ||
32 | |||
33 | SSYNC(); | ||
34 | for (i = 0; i < MAX_CPLBS; i++) { | ||
35 | bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr); | ||
36 | bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data); | ||
37 | } | ||
38 | ctrl = bfin_read_IMEM_CONTROL(); | ||
39 | ctrl |= IMC | ENICPLB; | ||
40 | bfin_write_IMEM_CONTROL(ctrl); | ||
41 | SSYNC(); | ||
42 | } | ||
43 | #endif | ||
44 | |||
45 | #if defined(CONFIG_BFIN_DCACHE) | ||
46 | void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) | ||
47 | { | ||
48 | unsigned long ctrl; | ||
49 | int i; | ||
50 | |||
51 | SSYNC(); | ||
52 | for (i = 0; i < MAX_CPLBS; i++) { | ||
53 | bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr); | ||
54 | bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data); | ||
55 | } | ||
56 | |||
57 | ctrl = bfin_read_DMEM_CONTROL(); | ||
58 | |||
59 | /* | ||
60 | * Anomaly notes: | ||
61 | * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL | ||
62 | * register, so that the port preferences for DAG0 and DAG1 are set | ||
63 | * to port B | ||
64 | */ | ||
65 | ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0); | ||
66 | bfin_write_DMEM_CONTROL(ctrl); | ||
67 | SSYNC(); | ||
68 | } | ||
69 | #endif | ||
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 685f160a5a36..5d8ad503f82a 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c | |||
@@ -36,7 +36,7 @@ int first_switched_icplb PDT_ATTR; | |||
36 | int first_switched_dcplb PDT_ATTR; | 36 | int first_switched_dcplb PDT_ATTR; |
37 | 37 | ||
38 | struct cplb_boundary dcplb_bounds[9] PDT_ATTR; | 38 | struct cplb_boundary dcplb_bounds[9] PDT_ATTR; |
39 | struct cplb_boundary icplb_bounds[7] PDT_ATTR; | 39 | struct cplb_boundary icplb_bounds[9] PDT_ATTR; |
40 | 40 | ||
41 | int icplb_nr_bounds PDT_ATTR; | 41 | int icplb_nr_bounds PDT_ATTR; |
42 | int dcplb_nr_bounds PDT_ATTR; | 42 | int dcplb_nr_bounds PDT_ATTR; |
@@ -167,14 +167,21 @@ void __init generate_cplb_tables_all(void) | |||
167 | icplb_bounds[i_i++].data = (reserved_mem_icache_on ? | 167 | icplb_bounds[i_i++].data = (reserved_mem_icache_on ? |
168 | SDRAM_IGENERIC : SDRAM_INON_CHBL); | 168 | SDRAM_IGENERIC : SDRAM_INON_CHBL); |
169 | } | 169 | } |
170 | /* Addressing hole up to the async bank. */ | ||
171 | icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE; | ||
172 | icplb_bounds[i_i++].data = 0; | ||
173 | /* ASYNC banks. */ | ||
174 | icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE; | ||
175 | icplb_bounds[i_i++].data = SDRAM_EBIU; | ||
170 | /* Addressing hole up to BootROM. */ | 176 | /* Addressing hole up to BootROM. */ |
171 | icplb_bounds[i_i].eaddr = BOOT_ROM_START; | 177 | icplb_bounds[i_i].eaddr = BOOT_ROM_START; |
172 | icplb_bounds[i_i++].data = 0; | 178 | icplb_bounds[i_i++].data = 0; |
173 | /* BootROM -- largest one should be less than 1 meg. */ | 179 | /* BootROM -- largest one should be less than 1 meg. */ |
174 | icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024); | 180 | icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024); |
175 | icplb_bounds[i_i++].data = SDRAM_IGENERIC; | 181 | icplb_bounds[i_i++].data = SDRAM_IGENERIC; |
182 | |||
176 | if (L2_LENGTH) { | 183 | if (L2_LENGTH) { |
177 | /* Addressing hole up to L2 SRAM, including the async bank. */ | 184 | /* Addressing hole up to L2 SRAM. */ |
178 | icplb_bounds[i_i].eaddr = L2_START; | 185 | icplb_bounds[i_i].eaddr = L2_START; |
179 | icplb_bounds[i_i++].data = 0; | 186 | icplb_bounds[i_i++].data = 0; |
180 | /* L2 SRAM. */ | 187 | /* L2 SRAM. */ |
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c index 12b030842fdb..d9ea46c6e41a 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c | |||
@@ -48,36 +48,13 @@ int nr_cplb_flush[NR_CPUS], nr_dcplb_prot[NR_CPUS]; | |||
48 | #define MGR_ATTR | 48 | #define MGR_ATTR |
49 | #endif | 49 | #endif |
50 | 50 | ||
51 | /* | ||
52 | * We're in an exception handler. The normal cli nop nop workaround | ||
53 | * isn't going to do very much, as the only thing that can interrupt | ||
54 | * us is an NMI, and the cli isn't going to stop that. | ||
55 | */ | ||
56 | #define NOWA_SSYNC __asm__ __volatile__ ("ssync;") | ||
57 | |||
58 | /* Anomaly handlers provide SSYNCs, so avoid extra if anomaly is present */ | ||
59 | #if ANOMALY_05000125 | ||
60 | |||
61 | #define bfin_write_DMEM_CONTROL_SSYNC(v) bfin_write_DMEM_CONTROL(v) | ||
62 | #define bfin_write_IMEM_CONTROL_SSYNC(v) bfin_write_IMEM_CONTROL(v) | ||
63 | |||
64 | #else | ||
65 | |||
66 | #define bfin_write_DMEM_CONTROL_SSYNC(v) \ | ||
67 | do { NOWA_SSYNC; bfin_write_DMEM_CONTROL(v); NOWA_SSYNC; } while (0) | ||
68 | #define bfin_write_IMEM_CONTROL_SSYNC(v) \ | ||
69 | do { NOWA_SSYNC; bfin_write_IMEM_CONTROL(v); NOWA_SSYNC; } while (0) | ||
70 | |||
71 | #endif | ||
72 | |||
73 | static inline void write_dcplb_data(int cpu, int idx, unsigned long data, | 51 | static inline void write_dcplb_data(int cpu, int idx, unsigned long data, |
74 | unsigned long addr) | 52 | unsigned long addr) |
75 | { | 53 | { |
76 | unsigned long ctrl = bfin_read_DMEM_CONTROL(); | 54 | _disable_dcplb(); |
77 | bfin_write_DMEM_CONTROL_SSYNC(ctrl & ~ENDCPLB); | ||
78 | bfin_write32(DCPLB_DATA0 + idx * 4, data); | 55 | bfin_write32(DCPLB_DATA0 + idx * 4, data); |
79 | bfin_write32(DCPLB_ADDR0 + idx * 4, addr); | 56 | bfin_write32(DCPLB_ADDR0 + idx * 4, addr); |
80 | bfin_write_DMEM_CONTROL_SSYNC(ctrl); | 57 | _enable_dcplb(); |
81 | 58 | ||
82 | #ifdef CONFIG_CPLB_INFO | 59 | #ifdef CONFIG_CPLB_INFO |
83 | dcplb_tbl[cpu][idx].addr = addr; | 60 | dcplb_tbl[cpu][idx].addr = addr; |
@@ -88,12 +65,10 @@ static inline void write_dcplb_data(int cpu, int idx, unsigned long data, | |||
88 | static inline void write_icplb_data(int cpu, int idx, unsigned long data, | 65 | static inline void write_icplb_data(int cpu, int idx, unsigned long data, |
89 | unsigned long addr) | 66 | unsigned long addr) |
90 | { | 67 | { |
91 | unsigned long ctrl = bfin_read_IMEM_CONTROL(); | 68 | _disable_icplb(); |
92 | |||
93 | bfin_write_IMEM_CONTROL_SSYNC(ctrl & ~ENICPLB); | ||
94 | bfin_write32(ICPLB_DATA0 + idx * 4, data); | 69 | bfin_write32(ICPLB_DATA0 + idx * 4, data); |
95 | bfin_write32(ICPLB_ADDR0 + idx * 4, addr); | 70 | bfin_write32(ICPLB_ADDR0 + idx * 4, addr); |
96 | bfin_write_IMEM_CONTROL_SSYNC(ctrl); | 71 | _enable_icplb(); |
97 | 72 | ||
98 | #ifdef CONFIG_CPLB_INFO | 73 | #ifdef CONFIG_CPLB_INFO |
99 | icplb_tbl[cpu][idx].addr = addr; | 74 | icplb_tbl[cpu][idx].addr = addr; |
@@ -227,7 +202,7 @@ MGR_ATTR static int dcplb_miss(int cpu) | |||
227 | MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs) | 202 | MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs) |
228 | { | 203 | { |
229 | int cause = seqstat & 0x3f; | 204 | int cause = seqstat & 0x3f; |
230 | unsigned int cpu = smp_processor_id(); | 205 | unsigned int cpu = raw_smp_processor_id(); |
231 | switch (cause) { | 206 | switch (cause) { |
232 | case VEC_CPLB_I_M: | 207 | case VEC_CPLB_I_M: |
233 | return icplb_miss(cpu); | 208 | return icplb_miss(cpu); |
diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c index 2ab56811841c..931c78b5ea1f 100644 --- a/arch/blackfin/kernel/early_printk.c +++ b/arch/blackfin/kernel/early_printk.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include <linux/serial_core.h> | 27 | #include <linux/serial_core.h> |
28 | #include <linux/console.h> | 28 | #include <linux/console.h> |
29 | #include <linux/string.h> | 29 | #include <linux/string.h> |
30 | #include <linux/reboot.h> | ||
30 | #include <asm/blackfin.h> | 31 | #include <asm/blackfin.h> |
31 | #include <asm/irq_handler.h> | 32 | #include <asm/irq_handler.h> |
32 | #include <asm/early_printk.h> | 33 | #include <asm/early_printk.h> |
@@ -181,6 +182,22 @@ asmlinkage void __init init_early_exception_vectors(void) | |||
181 | u32 evt; | 182 | u32 evt; |
182 | SSYNC(); | 183 | SSYNC(); |
183 | 184 | ||
185 | /* | ||
186 | * This starts up the shadow buffer, incase anything crashes before | ||
187 | * setup arch | ||
188 | */ | ||
189 | mark_shadow_error(); | ||
190 | early_shadow_puts(linux_banner); | ||
191 | early_shadow_stamp(); | ||
192 | |||
193 | if (CPUID != bfin_cpuid()) { | ||
194 | early_shadow_puts("Running on wrong machine type, expected"); | ||
195 | early_shadow_reg(CPUID, 16); | ||
196 | early_shadow_puts(", but running on"); | ||
197 | early_shadow_reg(bfin_cpuid(), 16); | ||
198 | early_shadow_puts("\n"); | ||
199 | } | ||
200 | |||
184 | /* cannot program in software: | 201 | /* cannot program in software: |
185 | * evt0 - emulation (jtag) | 202 | * evt0 - emulation (jtag) |
186 | * evt1 - reset | 203 | * evt1 - reset |
@@ -199,6 +216,7 @@ asmlinkage void __init init_early_exception_vectors(void) | |||
199 | 216 | ||
200 | } | 217 | } |
201 | 218 | ||
219 | __attribute__((__noreturn__)) | ||
202 | asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr) | 220 | asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr) |
203 | { | 221 | { |
204 | /* This can happen before the uart is initialized, so initialize | 222 | /* This can happen before the uart is initialized, so initialize |
@@ -210,10 +228,58 @@ asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr) | |||
210 | if (likely(early_console == NULL) && CPUID == bfin_cpuid()) | 228 | if (likely(early_console == NULL) && CPUID == bfin_cpuid()) |
211 | setup_early_printk(DEFAULT_EARLY_PORT); | 229 | setup_early_printk(DEFAULT_EARLY_PORT); |
212 | 230 | ||
213 | printk(KERN_EMERG "Early panic\n"); | 231 | if (!shadow_console_enabled()) { |
214 | dump_bfin_mem(fp); | 232 | /* crap - we crashed before setup_arch() */ |
215 | show_regs(fp); | 233 | early_shadow_puts("panic before setup_arch\n"); |
216 | dump_bfin_trace_buffer(); | 234 | early_shadow_puts("IPEND:"); |
235 | early_shadow_reg(fp->ipend, 16); | ||
236 | if (fp->seqstat & SEQSTAT_EXCAUSE) { | ||
237 | early_shadow_puts("\nEXCAUSE:"); | ||
238 | early_shadow_reg(fp->seqstat & SEQSTAT_EXCAUSE, 8); | ||
239 | } | ||
240 | if (fp->seqstat & SEQSTAT_HWERRCAUSE) { | ||
241 | early_shadow_puts("\nHWERRCAUSE:"); | ||
242 | early_shadow_reg( | ||
243 | (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14, 8); | ||
244 | } | ||
245 | early_shadow_puts("\nErr @"); | ||
246 | if (fp->ipend & EVT_EVX) | ||
247 | early_shadow_reg(fp->retx, 32); | ||
248 | else | ||
249 | early_shadow_reg(fp->pc, 32); | ||
250 | #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON | ||
251 | early_shadow_puts("\nTrace:"); | ||
252 | if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) { | ||
253 | while (bfin_read_TBUFSTAT() & TBUFCNT) { | ||
254 | early_shadow_puts("\nT :"); | ||
255 | early_shadow_reg(bfin_read_TBUF(), 32); | ||
256 | early_shadow_puts("\n S :"); | ||
257 | early_shadow_reg(bfin_read_TBUF(), 32); | ||
258 | } | ||
259 | } | ||
260 | #endif | ||
261 | early_shadow_puts("\nUse bfin-elf-addr2line to determine " | ||
262 | "function names\n"); | ||
263 | /* | ||
264 | * We should panic(), but we can't - since panic calls printk, | ||
265 | * and printk uses memcpy. | ||
266 | * we want to reboot, but if the machine type is different, | ||
267 | * can't due to machine specific reboot sequences | ||
268 | */ | ||
269 | if (CPUID == bfin_cpuid()) { | ||
270 | early_shadow_puts("Trying to restart\n"); | ||
271 | machine_restart(""); | ||
272 | } | ||
273 | |||
274 | early_shadow_puts("Halting, since it is not safe to restart\n"); | ||
275 | while (1) | ||
276 | asm volatile ("EMUEXCPT; IDLE;\n"); | ||
277 | |||
278 | } else { | ||
279 | printk(KERN_EMERG "Early panic\n"); | ||
280 | show_regs(fp); | ||
281 | dump_bfin_trace_buffer(); | ||
282 | } | ||
217 | 283 | ||
218 | panic("Died early"); | 284 | panic("Died early"); |
219 | } | 285 | } |
diff --git a/arch/blackfin/kernel/entry.S b/arch/blackfin/kernel/entry.S index a9cfba9946b5..3f8769b7db54 100644 --- a/arch/blackfin/kernel/entry.S +++ b/arch/blackfin/kernel/entry.S | |||
@@ -43,8 +43,28 @@ | |||
43 | 43 | ||
44 | ENTRY(_ret_from_fork) | 44 | ENTRY(_ret_from_fork) |
45 | #ifdef CONFIG_IPIPE | 45 | #ifdef CONFIG_IPIPE |
46 | [--sp] = reti; /* IRQs on. */ | 46 | /* |
47 | SP += 4; | 47 | * Hw IRQs are off on entry, and we don't want the scheduling tail |
48 | * code to starve high priority domains from interrupts while it | ||
49 | * runs. Therefore we first stall the root stage to have the | ||
50 | * virtual interrupt state reflect IMASK. | ||
51 | */ | ||
52 | p0.l = ___ipipe_root_status; | ||
53 | p0.h = ___ipipe_root_status; | ||
54 | r4 = [p0]; | ||
55 | bitset(r4, 0); | ||
56 | [p0] = r4; | ||
57 | /* | ||
58 | * Then we may enable hw IRQs, allowing preemption from high | ||
59 | * priority domains. schedule_tail() will do local_irq_enable() | ||
60 | * since Blackfin does not define __ARCH_WANT_UNLOCKED_CTXSW, so | ||
61 | * there is no need to unstall the root domain by ourselves | ||
62 | * afterwards. | ||
63 | */ | ||
64 | p0.l = _bfin_irq_flags; | ||
65 | p0.h = _bfin_irq_flags; | ||
66 | r4 = [p0]; | ||
67 | sti r4; | ||
48 | #endif /* CONFIG_IPIPE */ | 68 | #endif /* CONFIG_IPIPE */ |
49 | SP += -12; | 69 | SP += -12; |
50 | call _schedule_tail; | 70 | call _schedule_tail; |
diff --git a/arch/blackfin/kernel/ftrace-entry.S b/arch/blackfin/kernel/ftrace-entry.S index 6980b7a0615d..76dd4fbcd17a 100644 --- a/arch/blackfin/kernel/ftrace-entry.S +++ b/arch/blackfin/kernel/ftrace-entry.S | |||
@@ -17,8 +17,8 @@ | |||
17 | * only one we can blow away. With pointer registers, we have P0-P2. | 17 | * only one we can blow away. With pointer registers, we have P0-P2. |
18 | * | 18 | * |
19 | * Upon entry, the RETS will point to the top of the current profiled | 19 | * Upon entry, the RETS will point to the top of the current profiled |
20 | * function. And since GCC setup the frame for us, the previous function | 20 | * function. And since GCC pushed the previous RETS for us, the previous |
21 | * will be waiting there. mmmm pie. | 21 | * function will be waiting there. mmmm pie. |
22 | */ | 22 | */ |
23 | ENTRY(__mcount) | 23 | ENTRY(__mcount) |
24 | /* save third function arg early so we can do testing below */ | 24 | /* save third function arg early so we can do testing below */ |
@@ -70,14 +70,14 @@ ENTRY(__mcount) | |||
70 | /* setup the tracer function */ | 70 | /* setup the tracer function */ |
71 | p0 = r3; | 71 | p0 = r3; |
72 | 72 | ||
73 | /* tracer(ulong frompc, ulong selfpc): | 73 | /* function_trace_call(unsigned long ip, unsigned long parent_ip): |
74 | * frompc: the pc that did the call to ... | 74 | * ip: this point was called by ... |
75 | * selfpc: ... this location | 75 | * parent_ip: ... this function |
76 | * the selfpc itself will need adjusting for the mcount call | 76 | * the ip itself will need adjusting for the mcount call |
77 | */ | 77 | */ |
78 | r1 = rets; | 78 | r0 = rets; |
79 | r0 = [fp + 4]; | 79 | r1 = [sp + 16]; /* skip the 4 local regs on stack */ |
80 | r1 += -MCOUNT_INSN_SIZE; | 80 | r0 += -MCOUNT_INSN_SIZE; |
81 | 81 | ||
82 | /* call the tracer */ | 82 | /* call the tracer */ |
83 | call (p0); | 83 | call (p0); |
@@ -106,9 +106,10 @@ ENTRY(_ftrace_graph_caller) | |||
106 | [--sp] = r1; | 106 | [--sp] = r1; |
107 | [--sp] = rets; | 107 | [--sp] = rets; |
108 | 108 | ||
109 | r0 = fp; | 109 | /* prepare_ftrace_return(unsigned long *parent, unsigned long self_addr) */ |
110 | r0 = sp; | ||
110 | r1 = rets; | 111 | r1 = rets; |
111 | r0 += 4; | 112 | r0 += 16; /* skip the 4 local regs on stack */ |
112 | r1 += -MCOUNT_INSN_SIZE; | 113 | r1 += -MCOUNT_INSN_SIZE; |
113 | call _prepare_ftrace_return; | 114 | call _prepare_ftrace_return; |
114 | 115 | ||
diff --git a/arch/blackfin/kernel/ftrace.c b/arch/blackfin/kernel/ftrace.c index 905bfc40a00b..f2c85ac6f2da 100644 --- a/arch/blackfin/kernel/ftrace.c +++ b/arch/blackfin/kernel/ftrace.c | |||
@@ -24,7 +24,7 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr) | |||
24 | if (unlikely(atomic_read(¤t->tracing_graph_pause))) | 24 | if (unlikely(atomic_read(¤t->tracing_graph_pause))) |
25 | return; | 25 | return; |
26 | 26 | ||
27 | if (ftrace_push_return_trace(*parent, self_addr, &trace.depth) == -EBUSY) | 27 | if (ftrace_push_return_trace(*parent, self_addr, &trace.depth, 0) == -EBUSY) |
28 | return; | 28 | return; |
29 | 29 | ||
30 | trace.func = self_addr; | 30 | trace.func = self_addr; |
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c index b8d22034b9a6..5d7382396dc0 100644 --- a/arch/blackfin/kernel/ipipe.c +++ b/arch/blackfin/kernel/ipipe.c | |||
@@ -30,10 +30,10 @@ | |||
30 | #include <linux/slab.h> | 30 | #include <linux/slab.h> |
31 | #include <linux/errno.h> | 31 | #include <linux/errno.h> |
32 | #include <linux/kthread.h> | 32 | #include <linux/kthread.h> |
33 | #include <asm/unistd.h> | 33 | #include <linux/unistd.h> |
34 | #include <linux/io.h> | ||
34 | #include <asm/system.h> | 35 | #include <asm/system.h> |
35 | #include <asm/atomic.h> | 36 | #include <asm/atomic.h> |
36 | #include <asm/io.h> | ||
37 | 37 | ||
38 | DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs); | 38 | DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs); |
39 | 39 | ||
@@ -90,6 +90,7 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) | |||
90 | struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); | 90 | struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); |
91 | struct ipipe_domain *this_domain, *next_domain; | 91 | struct ipipe_domain *this_domain, *next_domain; |
92 | struct list_head *head, *pos; | 92 | struct list_head *head, *pos; |
93 | struct ipipe_irqdesc *idesc; | ||
93 | int m_ack, s = -1; | 94 | int m_ack, s = -1; |
94 | 95 | ||
95 | /* | 96 | /* |
@@ -100,17 +101,20 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) | |||
100 | */ | 101 | */ |
101 | m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR); | 102 | m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR); |
102 | this_domain = __ipipe_current_domain; | 103 | this_domain = __ipipe_current_domain; |
104 | idesc = &this_domain->irqs[irq]; | ||
103 | 105 | ||
104 | if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))) | 106 | if (unlikely(test_bit(IPIPE_STICKY_FLAG, &idesc->control))) |
105 | head = &this_domain->p_link; | 107 | head = &this_domain->p_link; |
106 | else { | 108 | else { |
107 | head = __ipipe_pipeline.next; | 109 | head = __ipipe_pipeline.next; |
108 | next_domain = list_entry(head, struct ipipe_domain, p_link); | 110 | next_domain = list_entry(head, struct ipipe_domain, p_link); |
109 | if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) { | 111 | idesc = &next_domain->irqs[irq]; |
110 | if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) | 112 | if (likely(test_bit(IPIPE_WIRED_FLAG, &idesc->control))) { |
111 | next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq)); | 113 | if (!m_ack && idesc->acknowledge != NULL) |
114 | idesc->acknowledge(irq, irq_to_desc(irq)); | ||
112 | if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status)) | 115 | if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status)) |
113 | s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status); | 116 | s = __test_and_set_bit(IPIPE_STALL_FLAG, |
117 | &p->status); | ||
114 | __ipipe_dispatch_wired(next_domain, irq); | 118 | __ipipe_dispatch_wired(next_domain, irq); |
115 | goto out; | 119 | goto out; |
116 | } | 120 | } |
@@ -121,14 +125,15 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) | |||
121 | pos = head; | 125 | pos = head; |
122 | while (pos != &__ipipe_pipeline) { | 126 | while (pos != &__ipipe_pipeline) { |
123 | next_domain = list_entry(pos, struct ipipe_domain, p_link); | 127 | next_domain = list_entry(pos, struct ipipe_domain, p_link); |
124 | if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) { | 128 | idesc = &next_domain->irqs[irq]; |
129 | if (test_bit(IPIPE_HANDLE_FLAG, &idesc->control)) { | ||
125 | __ipipe_set_irq_pending(next_domain, irq); | 130 | __ipipe_set_irq_pending(next_domain, irq); |
126 | if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) { | 131 | if (!m_ack && idesc->acknowledge != NULL) { |
127 | next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq)); | 132 | idesc->acknowledge(irq, irq_to_desc(irq)); |
128 | m_ack = 1; | 133 | m_ack = 1; |
129 | } | 134 | } |
130 | } | 135 | } |
131 | if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control)) | 136 | if (!test_bit(IPIPE_PASS_FLAG, &idesc->control)) |
132 | break; | 137 | break; |
133 | pos = next_domain->p_link.next; | 138 | pos = next_domain->p_link.next; |
134 | } | 139 | } |
@@ -159,11 +164,6 @@ out: | |||
159 | __clear_bit(IPIPE_STALL_FLAG, &p->status); | 164 | __clear_bit(IPIPE_STALL_FLAG, &p->status); |
160 | } | 165 | } |
161 | 166 | ||
162 | int __ipipe_check_root(void) | ||
163 | { | ||
164 | return ipipe_root_domain_p; | ||
165 | } | ||
166 | |||
167 | void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq) | 167 | void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq) |
168 | { | 168 | { |
169 | struct irq_desc *desc = irq_to_desc(irq); | 169 | struct irq_desc *desc = irq_to_desc(irq); |
@@ -186,30 +186,6 @@ void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq) | |||
186 | } | 186 | } |
187 | EXPORT_SYMBOL(__ipipe_disable_irqdesc); | 187 | EXPORT_SYMBOL(__ipipe_disable_irqdesc); |
188 | 188 | ||
189 | void __ipipe_stall_root_raw(void) | ||
190 | { | ||
191 | /* | ||
192 | * This code is called by the ins{bwl} routines (see | ||
193 | * arch/blackfin/lib/ins.S), which are heavily used by the | ||
194 | * network stack. It masks all interrupts but those handled by | ||
195 | * non-root domains, so that we keep decent network transfer | ||
196 | * rates for Linux without inducing pathological jitter for | ||
197 | * the real-time domain. | ||
198 | */ | ||
199 | __asm__ __volatile__ ("sti %0;" : : "d"(__ipipe_irq_lvmask)); | ||
200 | |||
201 | __set_bit(IPIPE_STALL_FLAG, | ||
202 | &ipipe_root_cpudom_var(status)); | ||
203 | } | ||
204 | |||
205 | void __ipipe_unstall_root_raw(void) | ||
206 | { | ||
207 | __clear_bit(IPIPE_STALL_FLAG, | ||
208 | &ipipe_root_cpudom_var(status)); | ||
209 | |||
210 | __asm__ __volatile__ ("sti %0;" : : "d"(bfin_irq_flags)); | ||
211 | } | ||
212 | |||
213 | int __ipipe_syscall_root(struct pt_regs *regs) | 189 | int __ipipe_syscall_root(struct pt_regs *regs) |
214 | { | 190 | { |
215 | struct ipipe_percpu_domain_data *p; | 191 | struct ipipe_percpu_domain_data *p; |
@@ -333,12 +309,29 @@ asmlinkage void __ipipe_sync_root(void) | |||
333 | 309 | ||
334 | void ___ipipe_sync_pipeline(unsigned long syncmask) | 310 | void ___ipipe_sync_pipeline(unsigned long syncmask) |
335 | { | 311 | { |
336 | if (__ipipe_root_domain_p) { | 312 | if (__ipipe_root_domain_p && |
337 | if (test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status))) | 313 | test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status))) |
338 | return; | 314 | return; |
339 | } | ||
340 | 315 | ||
341 | __ipipe_sync_stage(syncmask); | 316 | __ipipe_sync_stage(syncmask); |
342 | } | 317 | } |
343 | 318 | ||
344 | EXPORT_SYMBOL(show_stack); | 319 | void __ipipe_disable_root_irqs_hw(void) |
320 | { | ||
321 | /* | ||
322 | * This code is called by the ins{bwl} routines (see | ||
323 | * arch/blackfin/lib/ins.S), which are heavily used by the | ||
324 | * network stack. It masks all interrupts but those handled by | ||
325 | * non-root domains, so that we keep decent network transfer | ||
326 | * rates for Linux without inducing pathological jitter for | ||
327 | * the real-time domain. | ||
328 | */ | ||
329 | bfin_sti(__ipipe_irq_lvmask); | ||
330 | __set_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); | ||
331 | } | ||
332 | |||
333 | void __ipipe_enable_root_irqs_hw(void) | ||
334 | { | ||
335 | __clear_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); | ||
336 | bfin_sti(bfin_irq_flags); | ||
337 | } | ||
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c index dbcf3e45cb0b..59fc42dc5d6a 100644 --- a/arch/blackfin/kernel/kgdb_test.c +++ b/arch/blackfin/kernel/kgdb_test.c | |||
@@ -54,7 +54,7 @@ void kgdb_l2_test(void) | |||
54 | 54 | ||
55 | int kgdb_test(char *name, int len, int count, int z) | 55 | int kgdb_test(char *name, int len, int count, int z) |
56 | { | 56 | { |
57 | printk(KERN_DEBUG "kgdb name(%d): %s, %d, %d\n", len, name, count, z); | 57 | printk(KERN_ALERT "kgdb name(%d): %s, %d, %d\n", len, name, count, z); |
58 | count = z; | 58 | count = z; |
59 | return count; | 59 | return count; |
60 | } | 60 | } |
diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c index d5aee3626688..67fc7a56c865 100644 --- a/arch/blackfin/kernel/module.c +++ b/arch/blackfin/kernel/module.c | |||
@@ -27,6 +27,7 @@ | |||
27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
28 | */ | 28 | */ |
29 | 29 | ||
30 | #define pr_fmt(fmt) "module %s: " fmt | ||
30 | 31 | ||
31 | #include <linux/moduleloader.h> | 32 | #include <linux/moduleloader.h> |
32 | #include <linux/elf.h> | 33 | #include <linux/elf.h> |
@@ -36,6 +37,7 @@ | |||
36 | #include <linux/kernel.h> | 37 | #include <linux/kernel.h> |
37 | #include <asm/dma.h> | 38 | #include <asm/dma.h> |
38 | #include <asm/cacheflush.h> | 39 | #include <asm/cacheflush.h> |
40 | #include <asm/uaccess.h> | ||
39 | 41 | ||
40 | void *module_alloc(unsigned long size) | 42 | void *module_alloc(unsigned long size) |
41 | { | 43 | { |
@@ -52,7 +54,7 @@ void module_free(struct module *mod, void *module_region) | |||
52 | 54 | ||
53 | /* Transfer the section to the L1 memory */ | 55 | /* Transfer the section to the L1 memory */ |
54 | int | 56 | int |
55 | module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs, | 57 | module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, |
56 | char *secstrings, struct module *mod) | 58 | char *secstrings, struct module *mod) |
57 | { | 59 | { |
58 | /* | 60 | /* |
@@ -63,126 +65,119 @@ module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs, | |||
63 | * NOTE: this breaks the semantic of mod->arch structure. | 65 | * NOTE: this breaks the semantic of mod->arch structure. |
64 | */ | 66 | */ |
65 | Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum; | 67 | Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum; |
66 | void *dest = NULL; | 68 | void *dest; |
67 | 69 | ||
68 | for (s = sechdrs; s < sechdrs_end; ++s) { | 70 | for (s = sechdrs; s < sechdrs_end; ++s) { |
69 | if ((strcmp(".l1.text", secstrings + s->sh_name) == 0) || | 71 | const char *shname = secstrings + s->sh_name; |
70 | ((strcmp(".text", secstrings + s->sh_name) == 0) && | 72 | |
71 | (hdr->e_flags & EF_BFIN_CODE_IN_L1) && (s->sh_size > 0))) { | 73 | if (s->sh_size == 0) |
74 | continue; | ||
75 | |||
76 | if (!strcmp(".l1.text", shname) || | ||
77 | (!strcmp(".text", shname) && | ||
78 | (hdr->e_flags & EF_BFIN_CODE_IN_L1))) { | ||
79 | |||
72 | dest = l1_inst_sram_alloc(s->sh_size); | 80 | dest = l1_inst_sram_alloc(s->sh_size); |
73 | mod->arch.text_l1 = dest; | 81 | mod->arch.text_l1 = dest; |
74 | if (dest == NULL) { | 82 | if (dest == NULL) { |
75 | printk(KERN_ERR | 83 | pr_err("L1 inst memory allocation failed\n", |
76 | "module %s: L1 instruction memory allocation failed\n", | 84 | mod->name); |
77 | mod->name); | ||
78 | return -1; | 85 | return -1; |
79 | } | 86 | } |
80 | dma_memcpy(dest, (void *)s->sh_addr, s->sh_size); | 87 | dma_memcpy(dest, (void *)s->sh_addr, s->sh_size); |
81 | s->sh_flags &= ~SHF_ALLOC; | 88 | |
82 | s->sh_addr = (unsigned long)dest; | 89 | } else if (!strcmp(".l1.data", shname) || |
83 | } | 90 | (!strcmp(".data", shname) && |
84 | if ((strcmp(".l1.data", secstrings + s->sh_name) == 0) || | 91 | (hdr->e_flags & EF_BFIN_DATA_IN_L1))) { |
85 | ((strcmp(".data", secstrings + s->sh_name) == 0) && | 92 | |
86 | (hdr->e_flags & EF_BFIN_DATA_IN_L1) && (s->sh_size > 0))) { | ||
87 | dest = l1_data_sram_alloc(s->sh_size); | 93 | dest = l1_data_sram_alloc(s->sh_size); |
88 | mod->arch.data_a_l1 = dest; | 94 | mod->arch.data_a_l1 = dest; |
89 | if (dest == NULL) { | 95 | if (dest == NULL) { |
90 | printk(KERN_ERR | 96 | pr_err("L1 data memory allocation failed\n", |
91 | "module %s: L1 data memory allocation failed\n", | ||
92 | mod->name); | 97 | mod->name); |
93 | return -1; | 98 | return -1; |
94 | } | 99 | } |
95 | memcpy(dest, (void *)s->sh_addr, s->sh_size); | 100 | memcpy(dest, (void *)s->sh_addr, s->sh_size); |
96 | s->sh_flags &= ~SHF_ALLOC; | 101 | |
97 | s->sh_addr = (unsigned long)dest; | 102 | } else if (!strcmp(".l1.bss", shname) || |
98 | } | 103 | (!strcmp(".bss", shname) && |
99 | if (strcmp(".l1.bss", secstrings + s->sh_name) == 0 || | 104 | (hdr->e_flags & EF_BFIN_DATA_IN_L1))) { |
100 | ((strcmp(".bss", secstrings + s->sh_name) == 0) && | 105 | |
101 | (hdr->e_flags & EF_BFIN_DATA_IN_L1) && (s->sh_size > 0))) { | 106 | dest = l1_data_sram_zalloc(s->sh_size); |
102 | dest = l1_data_sram_alloc(s->sh_size); | ||
103 | mod->arch.bss_a_l1 = dest; | 107 | mod->arch.bss_a_l1 = dest; |
104 | if (dest == NULL) { | 108 | if (dest == NULL) { |
105 | printk(KERN_ERR | 109 | pr_err("L1 data memory allocation failed\n", |
106 | "module %s: L1 data memory allocation failed\n", | ||
107 | mod->name); | 110 | mod->name); |
108 | return -1; | 111 | return -1; |
109 | } | 112 | } |
110 | memset(dest, 0, s->sh_size); | 113 | |
111 | s->sh_flags &= ~SHF_ALLOC; | 114 | } else if (!strcmp(".l1.data.B", shname)) { |
112 | s->sh_addr = (unsigned long)dest; | 115 | |
113 | } | ||
114 | if (strcmp(".l1.data.B", secstrings + s->sh_name) == 0) { | ||
115 | dest = l1_data_B_sram_alloc(s->sh_size); | 116 | dest = l1_data_B_sram_alloc(s->sh_size); |
116 | mod->arch.data_b_l1 = dest; | 117 | mod->arch.data_b_l1 = dest; |
117 | if (dest == NULL) { | 118 | if (dest == NULL) { |
118 | printk(KERN_ERR | 119 | pr_err("L1 data memory allocation failed\n", |
119 | "module %s: L1 data memory allocation failed\n", | ||
120 | mod->name); | 120 | mod->name); |
121 | return -1; | 121 | return -1; |
122 | } | 122 | } |
123 | memcpy(dest, (void *)s->sh_addr, s->sh_size); | 123 | memcpy(dest, (void *)s->sh_addr, s->sh_size); |
124 | s->sh_flags &= ~SHF_ALLOC; | 124 | |
125 | s->sh_addr = (unsigned long)dest; | 125 | } else if (!strcmp(".l1.bss.B", shname)) { |
126 | } | 126 | |
127 | if (strcmp(".l1.bss.B", secstrings + s->sh_name) == 0) { | ||
128 | dest = l1_data_B_sram_alloc(s->sh_size); | 127 | dest = l1_data_B_sram_alloc(s->sh_size); |
129 | mod->arch.bss_b_l1 = dest; | 128 | mod->arch.bss_b_l1 = dest; |
130 | if (dest == NULL) { | 129 | if (dest == NULL) { |
131 | printk(KERN_ERR | 130 | pr_err("L1 data memory allocation failed\n", |
132 | "module %s: L1 data memory allocation failed\n", | ||
133 | mod->name); | 131 | mod->name); |
134 | return -1; | 132 | return -1; |
135 | } | 133 | } |
136 | memset(dest, 0, s->sh_size); | 134 | memset(dest, 0, s->sh_size); |
137 | s->sh_flags &= ~SHF_ALLOC; | 135 | |
138 | s->sh_addr = (unsigned long)dest; | 136 | } else if (!strcmp(".l2.text", shname) || |
139 | } | 137 | (!strcmp(".text", shname) && |
140 | if ((strcmp(".l2.text", secstrings + s->sh_name) == 0) || | 138 | (hdr->e_flags & EF_BFIN_CODE_IN_L2))) { |
141 | ((strcmp(".text", secstrings + s->sh_name) == 0) && | 139 | |
142 | (hdr->e_flags & EF_BFIN_CODE_IN_L2) && (s->sh_size > 0))) { | ||
143 | dest = l2_sram_alloc(s->sh_size); | 140 | dest = l2_sram_alloc(s->sh_size); |
144 | mod->arch.text_l2 = dest; | 141 | mod->arch.text_l2 = dest; |
145 | if (dest == NULL) { | 142 | if (dest == NULL) { |
146 | printk(KERN_ERR | 143 | pr_err("L2 SRAM allocation failed\n", |
147 | "module %s: L2 SRAM allocation failed\n", | 144 | mod->name); |
148 | mod->name); | ||
149 | return -1; | 145 | return -1; |
150 | } | 146 | } |
151 | memcpy(dest, (void *)s->sh_addr, s->sh_size); | 147 | memcpy(dest, (void *)s->sh_addr, s->sh_size); |
152 | s->sh_flags &= ~SHF_ALLOC; | 148 | |
153 | s->sh_addr = (unsigned long)dest; | 149 | } else if (!strcmp(".l2.data", shname) || |
154 | } | 150 | (!strcmp(".data", shname) && |
155 | if ((strcmp(".l2.data", secstrings + s->sh_name) == 0) || | 151 | (hdr->e_flags & EF_BFIN_DATA_IN_L2))) { |
156 | ((strcmp(".data", secstrings + s->sh_name) == 0) && | 152 | |
157 | (hdr->e_flags & EF_BFIN_DATA_IN_L2) && (s->sh_size > 0))) { | ||
158 | dest = l2_sram_alloc(s->sh_size); | 153 | dest = l2_sram_alloc(s->sh_size); |
159 | mod->arch.data_l2 = dest; | 154 | mod->arch.data_l2 = dest; |
160 | if (dest == NULL) { | 155 | if (dest == NULL) { |
161 | printk(KERN_ERR | 156 | pr_err("L2 SRAM allocation failed\n", |
162 | "module %s: L2 SRAM allocation failed\n", | ||
163 | mod->name); | 157 | mod->name); |
164 | return -1; | 158 | return -1; |
165 | } | 159 | } |
166 | memcpy(dest, (void *)s->sh_addr, s->sh_size); | 160 | memcpy(dest, (void *)s->sh_addr, s->sh_size); |
167 | s->sh_flags &= ~SHF_ALLOC; | 161 | |
168 | s->sh_addr = (unsigned long)dest; | 162 | } else if (!strcmp(".l2.bss", shname) || |
169 | } | 163 | (!strcmp(".bss", shname) && |
170 | if (strcmp(".l2.bss", secstrings + s->sh_name) == 0 || | 164 | (hdr->e_flags & EF_BFIN_DATA_IN_L2))) { |
171 | ((strcmp(".bss", secstrings + s->sh_name) == 0) && | 165 | |
172 | (hdr->e_flags & EF_BFIN_DATA_IN_L2) && (s->sh_size > 0))) { | 166 | dest = l2_sram_zalloc(s->sh_size); |
173 | dest = l2_sram_alloc(s->sh_size); | ||
174 | mod->arch.bss_l2 = dest; | 167 | mod->arch.bss_l2 = dest; |
175 | if (dest == NULL) { | 168 | if (dest == NULL) { |
176 | printk(KERN_ERR | 169 | pr_err("L2 SRAM allocation failed\n", |
177 | "module %s: L2 SRAM allocation failed\n", | ||
178 | mod->name); | 170 | mod->name); |
179 | return -1; | 171 | return -1; |
180 | } | 172 | } |
181 | memset(dest, 0, s->sh_size); | 173 | |
182 | s->sh_flags &= ~SHF_ALLOC; | 174 | } else |
183 | s->sh_addr = (unsigned long)dest; | 175 | continue; |
184 | } | 176 | |
177 | s->sh_flags &= ~SHF_ALLOC; | ||
178 | s->sh_addr = (unsigned long)dest; | ||
185 | } | 179 | } |
180 | |||
186 | return 0; | 181 | return 0; |
187 | } | 182 | } |
188 | 183 | ||
@@ -190,7 +185,7 @@ int | |||
190 | apply_relocate(Elf_Shdr * sechdrs, const char *strtab, | 185 | apply_relocate(Elf_Shdr * sechdrs, const char *strtab, |
191 | unsigned int symindex, unsigned int relsec, struct module *me) | 186 | unsigned int symindex, unsigned int relsec, struct module *me) |
192 | { | 187 | { |
193 | printk(KERN_ERR "module %s: .rel unsupported\n", me->name); | 188 | pr_err(".rel unsupported\n", me->name); |
194 | return -ENOEXEC; | 189 | return -ENOEXEC; |
195 | } | 190 | } |
196 | 191 | ||
@@ -205,109 +200,86 @@ apply_relocate(Elf_Shdr * sechdrs, const char *strtab, | |||
205 | /* gas does not generate it. */ | 200 | /* gas does not generate it. */ |
206 | /*************************************************************************/ | 201 | /*************************************************************************/ |
207 | int | 202 | int |
208 | apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab, | 203 | apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, |
209 | unsigned int symindex, unsigned int relsec, | 204 | unsigned int symindex, unsigned int relsec, |
210 | struct module *mod) | 205 | struct module *mod) |
211 | { | 206 | { |
212 | unsigned int i; | 207 | unsigned int i; |
213 | unsigned short tmp; | ||
214 | Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr; | 208 | Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr; |
215 | Elf32_Sym *sym; | 209 | Elf32_Sym *sym; |
216 | uint32_t *location32; | 210 | unsigned long location, value, size; |
217 | uint16_t *location16; | 211 | |
218 | uint32_t value; | 212 | pr_debug("applying relocate section %u to %u\n", mod->name, |
213 | relsec, sechdrs[relsec].sh_info); | ||
219 | 214 | ||
220 | pr_debug("Applying relocate section %u to %u\n", relsec, | ||
221 | sechdrs[relsec].sh_info); | ||
222 | for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { | 215 | for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { |
223 | /* This is where to make the change */ | 216 | /* This is where to make the change */ |
224 | location16 = | 217 | location = sechdrs[sechdrs[relsec].sh_info].sh_addr + |
225 | (uint16_t *) (sechdrs[sechdrs[relsec].sh_info].sh_addr + | 218 | rel[i].r_offset; |
226 | rel[i].r_offset); | 219 | |
227 | location32 = (uint32_t *) location16; | ||
228 | /* This is the symbol it is referring to. Note that all | 220 | /* This is the symbol it is referring to. Note that all |
229 | undefined symbols have been resolved. */ | 221 | undefined symbols have been resolved. */ |
230 | sym = (Elf32_Sym *) sechdrs[symindex].sh_addr | 222 | sym = (Elf32_Sym *) sechdrs[symindex].sh_addr |
231 | + ELF32_R_SYM(rel[i].r_info); | 223 | + ELF32_R_SYM(rel[i].r_info); |
232 | value = sym->st_value; | 224 | value = sym->st_value; |
233 | value += rel[i].r_addend; | 225 | value += rel[i].r_addend; |
234 | pr_debug("location is %x, value is %x type is %d \n", | 226 | |
235 | (unsigned int) location32, value, | ||
236 | ELF32_R_TYPE(rel[i].r_info)); | ||
237 | #ifdef CONFIG_SMP | 227 | #ifdef CONFIG_SMP |
238 | if ((unsigned long)location16 >= COREB_L1_DATA_A_START) { | 228 | if (location >= COREB_L1_DATA_A_START) { |
239 | printk(KERN_ERR "module %s: cannot relocate in L1: %u (SMP kernel)", | 229 | pr_err("cannot relocate in L1: %u (SMP kernel)", |
240 | mod->name, ELF32_R_TYPE(rel[i].r_info)); | 230 | mod->name, ELF32_R_TYPE(rel[i].r_info)); |
241 | return -ENOEXEC; | 231 | return -ENOEXEC; |
242 | } | 232 | } |
243 | #endif | 233 | #endif |
234 | |||
235 | pr_debug("location is %lx, value is %lx type is %d\n", | ||
236 | mod->name, location, value, ELF32_R_TYPE(rel[i].r_info)); | ||
237 | |||
244 | switch (ELF32_R_TYPE(rel[i].r_info)) { | 238 | switch (ELF32_R_TYPE(rel[i].r_info)) { |
245 | 239 | ||
240 | case R_BFIN_HUIMM16: | ||
241 | value >>= 16; | ||
242 | case R_BFIN_LUIMM16: | ||
243 | case R_BFIN_RIMM16: | ||
244 | size = 2; | ||
245 | break; | ||
246 | case R_BFIN_BYTE4_DATA: | ||
247 | size = 4; | ||
248 | break; | ||
249 | |||
246 | case R_BFIN_PCREL24: | 250 | case R_BFIN_PCREL24: |
247 | case R_BFIN_PCREL24_JUMP_L: | 251 | case R_BFIN_PCREL24_JUMP_L: |
248 | /* Add the value, subtract its postition */ | ||
249 | location16 = | ||
250 | (uint16_t *) (sechdrs[sechdrs[relsec].sh_info]. | ||
251 | sh_addr + rel[i].r_offset - 2); | ||
252 | location32 = (uint32_t *) location16; | ||
253 | value -= (uint32_t) location32; | ||
254 | value >>= 1; | ||
255 | if ((value & 0xFF000000) != 0 && | ||
256 | (value & 0xFF000000) != 0xFF000000) { | ||
257 | printk(KERN_ERR "module %s: relocation overflow\n", | ||
258 | mod->name); | ||
259 | return -ENOEXEC; | ||
260 | } | ||
261 | pr_debug("value is %x, before %x-%x after %x-%x\n", value, | ||
262 | *location16, *(location16 + 1), | ||
263 | (*location16 & 0xff00) | (value >> 16 & 0x00ff), | ||
264 | value & 0xffff); | ||
265 | *location16 = | ||
266 | (*location16 & 0xff00) | (value >> 16 & 0x00ff); | ||
267 | *(location16 + 1) = value & 0xffff; | ||
268 | break; | ||
269 | case R_BFIN_PCREL12_JUMP: | 252 | case R_BFIN_PCREL12_JUMP: |
270 | case R_BFIN_PCREL12_JUMP_S: | 253 | case R_BFIN_PCREL12_JUMP_S: |
271 | value -= (uint32_t) location32; | ||
272 | value >>= 1; | ||
273 | *location16 = (value & 0xfff); | ||
274 | break; | ||
275 | case R_BFIN_PCREL10: | 254 | case R_BFIN_PCREL10: |
276 | value -= (uint32_t) location32; | 255 | pr_err("unsupported relocation: %u (no -mlong-calls?)\n", |
277 | value >>= 1; | 256 | mod->name, ELF32_R_TYPE(rel[i].r_info)); |
278 | *location16 = (value & 0x3ff); | 257 | return -ENOEXEC; |
279 | break; | 258 | |
280 | case R_BFIN_LUIMM16: | 259 | default: |
281 | pr_debug("before %x after %x\n", *location16, | 260 | pr_err("unknown relocation: %u\n", mod->name, |
282 | (value & 0xffff)); | 261 | ELF32_R_TYPE(rel[i].r_info)); |
283 | tmp = (value & 0xffff); | 262 | return -ENOEXEC; |
284 | if ((unsigned long)location16 >= L1_CODE_START) { | 263 | } |
285 | dma_memcpy(location16, &tmp, 2); | 264 | |
286 | } else | 265 | switch (bfin_mem_access_type(location, size)) { |
287 | *location16 = tmp; | 266 | case BFIN_MEM_ACCESS_CORE: |
288 | break; | 267 | case BFIN_MEM_ACCESS_CORE_ONLY: |
289 | case R_BFIN_HUIMM16: | 268 | memcpy((void *)location, &value, size); |
290 | pr_debug("before %x after %x\n", *location16, | ||
291 | ((value >> 16) & 0xffff)); | ||
292 | tmp = ((value >> 16) & 0xffff); | ||
293 | if ((unsigned long)location16 >= L1_CODE_START) { | ||
294 | dma_memcpy(location16, &tmp, 2); | ||
295 | } else | ||
296 | *location16 = tmp; | ||
297 | break; | 269 | break; |
298 | case R_BFIN_RIMM16: | 270 | case BFIN_MEM_ACCESS_DMA: |
299 | *location16 = (value & 0xffff); | 271 | dma_memcpy((void *)location, &value, size); |
300 | break; | 272 | break; |
301 | case R_BFIN_BYTE4_DATA: | 273 | case BFIN_MEM_ACCESS_ITEST: |
302 | pr_debug("before %x after %x\n", *location32, value); | 274 | isram_memcpy((void *)location, &value, size); |
303 | *location32 = value; | ||
304 | break; | 275 | break; |
305 | default: | 276 | default: |
306 | printk(KERN_ERR "module %s: Unknown relocation: %u\n", | 277 | pr_err("invalid relocation for %#lx\n", |
307 | mod->name, ELF32_R_TYPE(rel[i].r_info)); | 278 | mod->name, location); |
308 | return -ENOEXEC; | 279 | return -ENOEXEC; |
309 | } | 280 | } |
310 | } | 281 | } |
282 | |||
311 | return 0; | 283 | return 0; |
312 | } | 284 | } |
313 | 285 | ||
@@ -332,22 +304,28 @@ module_finalize(const Elf_Ehdr * hdr, | |||
332 | for (i = 1; i < hdr->e_shnum; i++) { | 304 | for (i = 1; i < hdr->e_shnum; i++) { |
333 | const char *strtab = (char *)sechdrs[strindex].sh_addr; | 305 | const char *strtab = (char *)sechdrs[strindex].sh_addr; |
334 | unsigned int info = sechdrs[i].sh_info; | 306 | unsigned int info = sechdrs[i].sh_info; |
307 | const char *shname = secstrings + sechdrs[i].sh_name; | ||
335 | 308 | ||
336 | /* Not a valid relocation section? */ | 309 | /* Not a valid relocation section? */ |
337 | if (info >= hdr->e_shnum) | 310 | if (info >= hdr->e_shnum) |
338 | continue; | 311 | continue; |
339 | 312 | ||
340 | if ((sechdrs[i].sh_type == SHT_RELA) && | 313 | /* Only support RELA relocation types */ |
341 | ((strcmp(".rela.l2.text", secstrings + sechdrs[i].sh_name) == 0) || | 314 | if (sechdrs[i].sh_type != SHT_RELA) |
342 | (strcmp(".rela.l1.text", secstrings + sechdrs[i].sh_name) == 0) || | 315 | continue; |
343 | ((strcmp(".rela.text", secstrings + sechdrs[i].sh_name) == 0) && | 316 | |
344 | (hdr->e_flags & (EF_BFIN_CODE_IN_L1|EF_BFIN_CODE_IN_L2))))) { | 317 | if (!strcmp(".rela.l2.text", shname) || |
318 | !strcmp(".rela.l1.text", shname) || | ||
319 | (!strcmp(".rela.text", shname) && | ||
320 | (hdr->e_flags & (EF_BFIN_CODE_IN_L1 | EF_BFIN_CODE_IN_L2)))) { | ||
321 | |||
345 | err = apply_relocate_add((Elf_Shdr *) sechdrs, strtab, | 322 | err = apply_relocate_add((Elf_Shdr *) sechdrs, strtab, |
346 | symindex, i, mod); | 323 | symindex, i, mod); |
347 | if (err < 0) | 324 | if (err < 0) |
348 | return -ENOEXEC; | 325 | return -ENOEXEC; |
349 | } | 326 | } |
350 | } | 327 | } |
328 | |||
351 | return 0; | 329 | return 0; |
352 | } | 330 | } |
353 | 331 | ||
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 9da36bab7ccb..f5b286189647 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c | |||
@@ -282,25 +282,19 @@ void finish_atomic_sections (struct pt_regs *regs) | |||
282 | { | 282 | { |
283 | int __user *up0 = (int __user *)regs->p0; | 283 | int __user *up0 = (int __user *)regs->p0; |
284 | 284 | ||
285 | if (regs->pc < ATOMIC_SEQS_START || regs->pc >= ATOMIC_SEQS_END) | ||
286 | return; | ||
287 | |||
288 | switch (regs->pc) { | 285 | switch (regs->pc) { |
289 | case ATOMIC_XCHG32 + 2: | 286 | case ATOMIC_XCHG32 + 2: |
290 | put_user(regs->r1, up0); | 287 | put_user(regs->r1, up0); |
291 | regs->pc += 2; | 288 | regs->pc = ATOMIC_XCHG32 + 4; |
292 | break; | 289 | break; |
293 | 290 | ||
294 | case ATOMIC_CAS32 + 2: | 291 | case ATOMIC_CAS32 + 2: |
295 | case ATOMIC_CAS32 + 4: | 292 | case ATOMIC_CAS32 + 4: |
296 | if (regs->r0 == regs->r1) | 293 | if (regs->r0 == regs->r1) |
294 | case ATOMIC_CAS32 + 6: | ||
297 | put_user(regs->r2, up0); | 295 | put_user(regs->r2, up0); |
298 | regs->pc = ATOMIC_CAS32 + 8; | 296 | regs->pc = ATOMIC_CAS32 + 8; |
299 | break; | 297 | break; |
300 | case ATOMIC_CAS32 + 6: | ||
301 | put_user(regs->r2, up0); | ||
302 | regs->pc += 2; | ||
303 | break; | ||
304 | 298 | ||
305 | case ATOMIC_ADD32 + 2: | 299 | case ATOMIC_ADD32 + 2: |
306 | regs->r0 = regs->r1 + regs->r0; | 300 | regs->r0 = regs->r1 + regs->r0; |
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c index 6a387eec6b65..30f4828277ad 100644 --- a/arch/blackfin/kernel/ptrace.c +++ b/arch/blackfin/kernel/ptrace.c | |||
@@ -206,6 +206,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) | |||
206 | { | 206 | { |
207 | int ret; | 207 | int ret; |
208 | unsigned long __user *datap = (unsigned long __user *)data; | 208 | unsigned long __user *datap = (unsigned long __user *)data; |
209 | void *paddr = (void *)addr; | ||
209 | 210 | ||
210 | switch (request) { | 211 | switch (request) { |
211 | /* when I and D space are separate, these will need to be fixed. */ | 212 | /* when I and D space are separate, these will need to be fixed. */ |
@@ -215,42 +216,49 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) | |||
215 | case PTRACE_PEEKTEXT: /* read word at location addr. */ | 216 | case PTRACE_PEEKTEXT: /* read word at location addr. */ |
216 | { | 217 | { |
217 | unsigned long tmp = 0; | 218 | unsigned long tmp = 0; |
218 | int copied; | 219 | int copied = 0, to_copy = sizeof(tmp); |
219 | 220 | ||
220 | ret = -EIO; | 221 | ret = -EIO; |
221 | pr_debug("ptrace: PEEKTEXT at addr 0x%08lx + %ld\n", addr, sizeof(data)); | 222 | pr_debug("ptrace: PEEKTEXT at addr 0x%08lx + %i\n", addr, to_copy); |
222 | if (is_user_addr_valid(child, addr, sizeof(tmp)) < 0) | 223 | if (is_user_addr_valid(child, addr, to_copy) < 0) |
223 | break; | 224 | break; |
224 | pr_debug("ptrace: user address is valid\n"); | 225 | pr_debug("ptrace: user address is valid\n"); |
225 | 226 | ||
226 | if (L1_CODE_LENGTH != 0 && addr >= get_l1_code_start() | 227 | switch (bfin_mem_access_type(addr, to_copy)) { |
227 | && addr + sizeof(tmp) <= get_l1_code_start() + L1_CODE_LENGTH) { | 228 | case BFIN_MEM_ACCESS_CORE: |
228 | safe_dma_memcpy (&tmp, (const void *)(addr), sizeof(tmp)); | 229 | case BFIN_MEM_ACCESS_CORE_ONLY: |
229 | copied = sizeof(tmp); | ||
230 | |||
231 | } else if (L1_DATA_A_LENGTH != 0 && addr >= L1_DATA_A_START | ||
232 | && addr + sizeof(tmp) <= L1_DATA_A_START + L1_DATA_A_LENGTH) { | ||
233 | memcpy(&tmp, (const void *)(addr), sizeof(tmp)); | ||
234 | copied = sizeof(tmp); | ||
235 | |||
236 | } else if (L1_DATA_B_LENGTH != 0 && addr >= L1_DATA_B_START | ||
237 | && addr + sizeof(tmp) <= L1_DATA_B_START + L1_DATA_B_LENGTH) { | ||
238 | memcpy(&tmp, (const void *)(addr), sizeof(tmp)); | ||
239 | copied = sizeof(tmp); | ||
240 | |||
241 | } else if (addr >= FIXED_CODE_START | ||
242 | && addr + sizeof(tmp) <= FIXED_CODE_END) { | ||
243 | copy_from_user_page(0, 0, 0, &tmp, (const void *)(addr), sizeof(tmp)); | ||
244 | copied = sizeof(tmp); | ||
245 | |||
246 | } else | ||
247 | copied = access_process_vm(child, addr, &tmp, | 230 | copied = access_process_vm(child, addr, &tmp, |
248 | sizeof(tmp), 0); | 231 | to_copy, 0); |
232 | if (copied) | ||
233 | break; | ||
234 | |||
235 | /* hrm, why didn't that work ... maybe no mapping */ | ||
236 | if (addr >= FIXED_CODE_START && | ||
237 | addr + to_copy <= FIXED_CODE_END) { | ||
238 | copy_from_user_page(0, 0, 0, &tmp, paddr, to_copy); | ||
239 | copied = to_copy; | ||
240 | } else if (addr >= BOOT_ROM_START) { | ||
241 | memcpy(&tmp, paddr, to_copy); | ||
242 | copied = to_copy; | ||
243 | } | ||
249 | 244 | ||
250 | pr_debug("ptrace: copied size %d [0x%08lx]\n", copied, tmp); | ||
251 | if (copied != sizeof(tmp)) | ||
252 | break; | 245 | break; |
253 | ret = put_user(tmp, datap); | 246 | case BFIN_MEM_ACCESS_DMA: |
247 | if (safe_dma_memcpy(&tmp, paddr, to_copy)) | ||
248 | copied = to_copy; | ||
249 | break; | ||
250 | case BFIN_MEM_ACCESS_ITEST: | ||
251 | if (isram_memcpy(&tmp, paddr, to_copy)) | ||
252 | copied = to_copy; | ||
253 | break; | ||
254 | default: | ||
255 | copied = 0; | ||
256 | break; | ||
257 | } | ||
258 | |||
259 | pr_debug("ptrace: copied size %d [0x%08lx]\n", copied, tmp); | ||
260 | if (copied == to_copy) | ||
261 | ret = put_user(tmp, datap); | ||
254 | break; | 262 | break; |
255 | } | 263 | } |
256 | 264 | ||
@@ -277,9 +285,9 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) | |||
277 | tmp = child->mm->start_data; | 285 | tmp = child->mm->start_data; |
278 | #ifdef CONFIG_BINFMT_ELF_FDPIC | 286 | #ifdef CONFIG_BINFMT_ELF_FDPIC |
279 | } else if (addr == (sizeof(struct pt_regs) + 12)) { | 287 | } else if (addr == (sizeof(struct pt_regs) + 12)) { |
280 | tmp = child->mm->context.exec_fdpic_loadmap; | 288 | goto case_PTRACE_GETFDPIC_EXEC; |
281 | } else if (addr == (sizeof(struct pt_regs) + 16)) { | 289 | } else if (addr == (sizeof(struct pt_regs) + 16)) { |
282 | tmp = child->mm->context.interp_fdpic_loadmap; | 290 | goto case_PTRACE_GETFDPIC_INTERP; |
283 | #endif | 291 | #endif |
284 | } else { | 292 | } else { |
285 | tmp = get_reg(child, addr); | 293 | tmp = get_reg(child, addr); |
@@ -288,49 +296,78 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) | |||
288 | break; | 296 | break; |
289 | } | 297 | } |
290 | 298 | ||
299 | #ifdef CONFIG_BINFMT_ELF_FDPIC | ||
300 | case PTRACE_GETFDPIC: { | ||
301 | unsigned long tmp = 0; | ||
302 | |||
303 | switch (addr) { | ||
304 | case_PTRACE_GETFDPIC_EXEC: | ||
305 | case PTRACE_GETFDPIC_EXEC: | ||
306 | tmp = child->mm->context.exec_fdpic_loadmap; | ||
307 | break; | ||
308 | case_PTRACE_GETFDPIC_INTERP: | ||
309 | case PTRACE_GETFDPIC_INTERP: | ||
310 | tmp = child->mm->context.interp_fdpic_loadmap; | ||
311 | break; | ||
312 | default: | ||
313 | break; | ||
314 | } | ||
315 | |||
316 | ret = put_user(tmp, datap); | ||
317 | break; | ||
318 | } | ||
319 | #endif | ||
320 | |||
291 | /* when I and D space are separate, this will have to be fixed. */ | 321 | /* when I and D space are separate, this will have to be fixed. */ |
292 | case PTRACE_POKEDATA: | 322 | case PTRACE_POKEDATA: |
293 | pr_debug("ptrace: PTRACE_PEEKDATA\n"); | 323 | pr_debug("ptrace: PTRACE_PEEKDATA\n"); |
294 | /* fall through */ | 324 | /* fall through */ |
295 | case PTRACE_POKETEXT: /* write the word at location addr. */ | 325 | case PTRACE_POKETEXT: /* write the word at location addr. */ |
296 | { | 326 | { |
297 | int copied; | 327 | int copied = 0, to_copy = sizeof(data); |
298 | 328 | ||
299 | ret = -EIO; | 329 | ret = -EIO; |
300 | pr_debug("ptrace: POKETEXT at addr 0x%08lx + %ld bytes %lx\n", | 330 | pr_debug("ptrace: POKETEXT at addr 0x%08lx + %i bytes %lx\n", |
301 | addr, sizeof(data), data); | 331 | addr, to_copy, data); |
302 | if (is_user_addr_valid(child, addr, sizeof(data)) < 0) | 332 | if (is_user_addr_valid(child, addr, to_copy) < 0) |
303 | break; | 333 | break; |
304 | pr_debug("ptrace: user address is valid\n"); | 334 | pr_debug("ptrace: user address is valid\n"); |
305 | 335 | ||
306 | if (L1_CODE_LENGTH != 0 && addr >= get_l1_code_start() | 336 | switch (bfin_mem_access_type(addr, to_copy)) { |
307 | && addr + sizeof(data) <= get_l1_code_start() + L1_CODE_LENGTH) { | 337 | case BFIN_MEM_ACCESS_CORE: |
308 | safe_dma_memcpy ((void *)(addr), &data, sizeof(data)); | 338 | case BFIN_MEM_ACCESS_CORE_ONLY: |
309 | copied = sizeof(data); | ||
310 | |||
311 | } else if (L1_DATA_A_LENGTH != 0 && addr >= L1_DATA_A_START | ||
312 | && addr + sizeof(data) <= L1_DATA_A_START + L1_DATA_A_LENGTH) { | ||
313 | memcpy((void *)(addr), &data, sizeof(data)); | ||
314 | copied = sizeof(data); | ||
315 | |||
316 | } else if (L1_DATA_B_LENGTH != 0 && addr >= L1_DATA_B_START | ||
317 | && addr + sizeof(data) <= L1_DATA_B_START + L1_DATA_B_LENGTH) { | ||
318 | memcpy((void *)(addr), &data, sizeof(data)); | ||
319 | copied = sizeof(data); | ||
320 | |||
321 | } else if (addr >= FIXED_CODE_START | ||
322 | && addr + sizeof(data) <= FIXED_CODE_END) { | ||
323 | copy_to_user_page(0, 0, 0, (void *)(addr), &data, sizeof(data)); | ||
324 | copied = sizeof(data); | ||
325 | |||
326 | } else | ||
327 | copied = access_process_vm(child, addr, &data, | 339 | copied = access_process_vm(child, addr, &data, |
328 | sizeof(data), 1); | 340 | to_copy, 0); |
341 | if (copied) | ||
342 | break; | ||
343 | |||
344 | /* hrm, why didn't that work ... maybe no mapping */ | ||
345 | if (addr >= FIXED_CODE_START && | ||
346 | addr + to_copy <= FIXED_CODE_END) { | ||
347 | copy_to_user_page(0, 0, 0, paddr, &data, to_copy); | ||
348 | copied = to_copy; | ||
349 | } else if (addr >= BOOT_ROM_START) { | ||
350 | memcpy(paddr, &data, to_copy); | ||
351 | copied = to_copy; | ||
352 | } | ||
329 | 353 | ||
330 | pr_debug("ptrace: copied size %d\n", copied); | ||
331 | if (copied != sizeof(data)) | ||
332 | break; | 354 | break; |
333 | ret = 0; | 355 | case BFIN_MEM_ACCESS_DMA: |
356 | if (safe_dma_memcpy(paddr, &data, to_copy)) | ||
357 | copied = to_copy; | ||
358 | break; | ||
359 | case BFIN_MEM_ACCESS_ITEST: | ||
360 | if (isram_memcpy(paddr, &data, to_copy)) | ||
361 | copied = to_copy; | ||
362 | break; | ||
363 | default: | ||
364 | copied = 0; | ||
365 | break; | ||
366 | } | ||
367 | |||
368 | pr_debug("ptrace: copied size %d\n", copied); | ||
369 | if (copied == to_copy) | ||
370 | ret = 0; | ||
334 | break; | 371 | break; |
335 | } | 372 | } |
336 | 373 | ||
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 6225edae488e..369535b61ed1 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c | |||
@@ -112,7 +112,7 @@ void __cpuinit bfin_setup_caches(unsigned int cpu) | |||
112 | /* | 112 | /* |
113 | * In cache coherence emulation mode, we need to have the | 113 | * In cache coherence emulation mode, we need to have the |
114 | * D-cache enabled before running any atomic operation which | 114 | * D-cache enabled before running any atomic operation which |
115 | * might invove cache invalidation (i.e. spinlock, rwlock). | 115 | * might involve cache invalidation (i.e. spinlock, rwlock). |
116 | * So printk's are deferred until then. | 116 | * So printk's are deferred until then. |
117 | */ | 117 | */ |
118 | #ifdef CONFIG_BFIN_ICACHE | 118 | #ifdef CONFIG_BFIN_ICACHE |
@@ -187,6 +187,8 @@ void __init bfin_relocate_l1_mem(void) | |||
187 | unsigned long l1_data_b_length; | 187 | unsigned long l1_data_b_length; |
188 | unsigned long l2_length; | 188 | unsigned long l2_length; |
189 | 189 | ||
190 | early_shadow_stamp(); | ||
191 | |||
190 | /* | 192 | /* |
191 | * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S | 193 | * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S |
192 | * we know that everything about l1 text/data is nice and aligned, | 194 | * we know that everything about l1 text/data is nice and aligned, |
@@ -511,6 +513,7 @@ static __init void memory_setup(void) | |||
511 | #ifdef CONFIG_MTD_UCLINUX | 513 | #ifdef CONFIG_MTD_UCLINUX |
512 | unsigned long mtd_phys = 0; | 514 | unsigned long mtd_phys = 0; |
513 | #endif | 515 | #endif |
516 | unsigned long max_mem; | ||
514 | 517 | ||
515 | _rambase = (unsigned long)_stext; | 518 | _rambase = (unsigned long)_stext; |
516 | _ramstart = (unsigned long)_end; | 519 | _ramstart = (unsigned long)_end; |
@@ -520,7 +523,22 @@ static __init void memory_setup(void) | |||
520 | panic("DMA region exceeds memory limit: %lu.", | 523 | panic("DMA region exceeds memory limit: %lu.", |
521 | _ramend - _ramstart); | 524 | _ramend - _ramstart); |
522 | } | 525 | } |
523 | memory_end = _ramend - DMA_UNCACHED_REGION; | 526 | max_mem = memory_end = _ramend - DMA_UNCACHED_REGION; |
527 | |||
528 | #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) | ||
529 | /* Due to a Hardware Anomaly we need to limit the size of usable | ||
530 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | ||
531 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | ||
532 | */ | ||
533 | # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO)) | ||
534 | if (max_mem >= 56 * 1024 * 1024) | ||
535 | max_mem = 56 * 1024 * 1024; | ||
536 | # else | ||
537 | if (max_mem >= 60 * 1024 * 1024) | ||
538 | max_mem = 60 * 1024 * 1024; | ||
539 | # endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */ | ||
540 | #endif /* ANOMALY_05000263 */ | ||
541 | |||
524 | 542 | ||
525 | #ifdef CONFIG_MPU | 543 | #ifdef CONFIG_MPU |
526 | /* Round up to multiple of 4MB */ | 544 | /* Round up to multiple of 4MB */ |
@@ -549,22 +567,16 @@ static __init void memory_setup(void) | |||
549 | 567 | ||
550 | # if defined(CONFIG_ROMFS_FS) | 568 | # if defined(CONFIG_ROMFS_FS) |
551 | if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0 | 569 | if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0 |
552 | && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) | 570 | && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) { |
553 | mtd_size = | 571 | mtd_size = |
554 | PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); | 572 | PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); |
555 | # if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) | 573 | |
556 | /* Due to a Hardware Anomaly we need to limit the size of usable | 574 | /* ROM_FS is XIP, so if we found it, we need to limit memory */ |
557 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | 575 | if (memory_end > max_mem) { |
558 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | 576 | pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20); |
559 | */ | 577 | memory_end = max_mem; |
560 | # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO)) | 578 | } |
561 | if (memory_end >= 56 * 1024 * 1024) | 579 | } |
562 | memory_end = 56 * 1024 * 1024; | ||
563 | # else | ||
564 | if (memory_end >= 60 * 1024 * 1024) | ||
565 | memory_end = 60 * 1024 * 1024; | ||
566 | # endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */ | ||
567 | # endif /* ANOMALY_05000263 */ | ||
568 | # endif /* CONFIG_ROMFS_FS */ | 580 | # endif /* CONFIG_ROMFS_FS */ |
569 | 581 | ||
570 | /* Since the default MTD_UCLINUX has no magic number, we just blindly | 582 | /* Since the default MTD_UCLINUX has no magic number, we just blindly |
@@ -586,20 +598,14 @@ static __init void memory_setup(void) | |||
586 | } | 598 | } |
587 | #endif /* CONFIG_MTD_UCLINUX */ | 599 | #endif /* CONFIG_MTD_UCLINUX */ |
588 | 600 | ||
589 | #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) | 601 | /* We need lo limit memory, since everything could have a text section |
590 | /* Due to a Hardware Anomaly we need to limit the size of usable | 602 | * of userspace in it, and expose anomaly 05000263. If the anomaly |
591 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | 603 | * doesn't exist, or we don't need to - then dont. |
592 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | ||
593 | */ | 604 | */ |
594 | #if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO)) | 605 | if (memory_end > max_mem) { |
595 | if (memory_end >= 56 * 1024 * 1024) | 606 | pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20); |
596 | memory_end = 56 * 1024 * 1024; | 607 | memory_end = max_mem; |
597 | #else | 608 | } |
598 | if (memory_end >= 60 * 1024 * 1024) | ||
599 | memory_end = 60 * 1024 * 1024; | ||
600 | #endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */ | ||
601 | printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20); | ||
602 | #endif /* ANOMALY_05000263 */ | ||
603 | 609 | ||
604 | #ifdef CONFIG_MPU | 610 | #ifdef CONFIG_MPU |
605 | page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32; | 611 | page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32; |
@@ -693,7 +699,7 @@ static __init void setup_bootmem_allocator(void) | |||
693 | sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map); | 699 | sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map); |
694 | print_memory_map("boot memmap"); | 700 | print_memory_map("boot memmap"); |
695 | 701 | ||
696 | /* intialize globals in linux/bootmem.h */ | 702 | /* initialize globals in linux/bootmem.h */ |
697 | find_min_max_pfn(); | 703 | find_min_max_pfn(); |
698 | /* pfn of the last usable page frame */ | 704 | /* pfn of the last usable page frame */ |
699 | if (max_pfn > memory_end >> PAGE_SHIFT) | 705 | if (max_pfn > memory_end >> PAGE_SHIFT) |
@@ -806,6 +812,8 @@ void __init setup_arch(char **cmdline_p) | |||
806 | { | 812 | { |
807 | unsigned long sclk, cclk; | 813 | unsigned long sclk, cclk; |
808 | 814 | ||
815 | enable_shadow_console(); | ||
816 | |||
809 | /* Check to make sure we are running on the right processor */ | 817 | /* Check to make sure we are running on the right processor */ |
810 | if (unlikely(CPUID != bfin_cpuid())) | 818 | if (unlikely(CPUID != bfin_cpuid())) |
811 | printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", | 819 | printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", |
@@ -1230,57 +1238,6 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
1230 | #ifdef __ARCH_SYNC_CORE_ICACHE | 1238 | #ifdef __ARCH_SYNC_CORE_ICACHE |
1231 | seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", cpudata->icache_invld_count); | 1239 | seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", cpudata->icache_invld_count); |
1232 | #endif | 1240 | #endif |
1233 | #ifdef CONFIG_BFIN_ICACHE_LOCK | ||
1234 | switch ((cpudata->imemctl >> 3) & WAYALL_L) { | ||
1235 | case WAY0_L: | ||
1236 | seq_printf(m, "Way0 Locked-Down\n"); | ||
1237 | break; | ||
1238 | case WAY1_L: | ||
1239 | seq_printf(m, "Way1 Locked-Down\n"); | ||
1240 | break; | ||
1241 | case WAY01_L: | ||
1242 | seq_printf(m, "Way0,Way1 Locked-Down\n"); | ||
1243 | break; | ||
1244 | case WAY2_L: | ||
1245 | seq_printf(m, "Way2 Locked-Down\n"); | ||
1246 | break; | ||
1247 | case WAY02_L: | ||
1248 | seq_printf(m, "Way0,Way2 Locked-Down\n"); | ||
1249 | break; | ||
1250 | case WAY12_L: | ||
1251 | seq_printf(m, "Way1,Way2 Locked-Down\n"); | ||
1252 | break; | ||
1253 | case WAY012_L: | ||
1254 | seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n"); | ||
1255 | break; | ||
1256 | case WAY3_L: | ||
1257 | seq_printf(m, "Way3 Locked-Down\n"); | ||
1258 | break; | ||
1259 | case WAY03_L: | ||
1260 | seq_printf(m, "Way0,Way3 Locked-Down\n"); | ||
1261 | break; | ||
1262 | case WAY13_L: | ||
1263 | seq_printf(m, "Way1,Way3 Locked-Down\n"); | ||
1264 | break; | ||
1265 | case WAY013_L: | ||
1266 | seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n"); | ||
1267 | break; | ||
1268 | case WAY32_L: | ||
1269 | seq_printf(m, "Way3,Way2 Locked-Down\n"); | ||
1270 | break; | ||
1271 | case WAY320_L: | ||
1272 | seq_printf(m, "Way3,Way2,Way0 Locked-Down\n"); | ||
1273 | break; | ||
1274 | case WAY321_L: | ||
1275 | seq_printf(m, "Way3,Way2,Way1 Locked-Down\n"); | ||
1276 | break; | ||
1277 | case WAYALL_L: | ||
1278 | seq_printf(m, "All Ways are locked\n"); | ||
1279 | break; | ||
1280 | default: | ||
1281 | seq_printf(m, "No Ways are locked\n"); | ||
1282 | } | ||
1283 | #endif | ||
1284 | 1241 | ||
1285 | if (cpu_num != num_possible_cpus() - 1) | 1242 | if (cpu_num != num_possible_cpus() - 1) |
1286 | return 0; | 1243 | return 0; |
@@ -1346,6 +1303,7 @@ const struct seq_operations cpuinfo_op = { | |||
1346 | 1303 | ||
1347 | void __init cmdline_init(const char *r0) | 1304 | void __init cmdline_init(const char *r0) |
1348 | { | 1305 | { |
1306 | early_shadow_stamp(); | ||
1349 | if (r0) | 1307 | if (r0) |
1350 | strncpy(command_line, r0, COMMAND_LINE_SIZE); | 1308 | strncpy(command_line, r0, COMMAND_LINE_SIZE); |
1351 | } | 1309 | } |
diff --git a/arch/blackfin/kernel/shadow_console.c b/arch/blackfin/kernel/shadow_console.c new file mode 100644 index 000000000000..8b8c7107a162 --- /dev/null +++ b/arch/blackfin/kernel/shadow_console.c | |||
@@ -0,0 +1,113 @@ | |||
1 | /* | ||
2 | * manage a small early shadow of the log buffer which we can pass between the | ||
3 | * bootloader so early crash messages are communicated properly and easily | ||
4 | * | ||
5 | * Copyright 2009 Analog Devices Inc. | ||
6 | * | ||
7 | * Enter bugs at http://blackfin.uclinux.org/ | ||
8 | * | ||
9 | * Licensed under the GPL-2 or later. | ||
10 | */ | ||
11 | |||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/init.h> | ||
14 | #include <linux/console.h> | ||
15 | #include <linux/string.h> | ||
16 | #include <asm/blackfin.h> | ||
17 | #include <asm/irq_handler.h> | ||
18 | #include <asm/early_printk.h> | ||
19 | |||
20 | #define SHADOW_CONSOLE_START (0x500) | ||
21 | #define SHADOW_CONSOLE_END (0x1000) | ||
22 | #define SHADOW_CONSOLE_MAGIC_LOC (0x4F0) | ||
23 | #define SHADOW_CONSOLE_MAGIC (0xDEADBEEF) | ||
24 | |||
25 | static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START; | ||
26 | |||
27 | __init void early_shadow_write(struct console *con, const char *s, | ||
28 | unsigned int n) | ||
29 | { | ||
30 | unsigned int i; | ||
31 | /* | ||
32 | * save 2 bytes for the double null at the end | ||
33 | * once we fail on a long line, make sure we don't write a short line afterwards | ||
34 | */ | ||
35 | if ((shadow_console_buffer + n) <= (char *)(SHADOW_CONSOLE_END - 2)) { | ||
36 | /* can't use memcpy - it may not be relocated yet */ | ||
37 | for (i = 0; i <= n; i++) | ||
38 | shadow_console_buffer[i] = s[i]; | ||
39 | shadow_console_buffer += n; | ||
40 | shadow_console_buffer[0] = 0; | ||
41 | shadow_console_buffer[1] = 0; | ||
42 | } else | ||
43 | shadow_console_buffer = (char *)SHADOW_CONSOLE_END; | ||
44 | } | ||
45 | |||
46 | static __initdata struct console early_shadow_console = { | ||
47 | .name = "early_shadow", | ||
48 | .write = early_shadow_write, | ||
49 | .flags = CON_BOOT | CON_PRINTBUFFER, | ||
50 | .index = -1, | ||
51 | .device = 0, | ||
52 | }; | ||
53 | |||
54 | __init int shadow_console_enabled(void) | ||
55 | { | ||
56 | return early_shadow_console.flags & CON_ENABLED; | ||
57 | } | ||
58 | |||
59 | __init void mark_shadow_error(void) | ||
60 | { | ||
61 | int *loc = (int *)SHADOW_CONSOLE_MAGIC_LOC; | ||
62 | loc[0] = SHADOW_CONSOLE_MAGIC; | ||
63 | loc[1] = SHADOW_CONSOLE_START; | ||
64 | } | ||
65 | |||
66 | __init void enable_shadow_console(void) | ||
67 | { | ||
68 | if (!shadow_console_enabled()) { | ||
69 | register_console(&early_shadow_console); | ||
70 | /* for now, assume things are going to fail */ | ||
71 | mark_shadow_error(); | ||
72 | } | ||
73 | } | ||
74 | |||
75 | static __init int disable_shadow_console(void) | ||
76 | { | ||
77 | /* | ||
78 | * by the time pure_initcall runs, the standard console is enabled, | ||
79 | * and the early_console is off, so unset the magic numbers | ||
80 | * unregistering the console is taken care of in common code (See | ||
81 | * ./kernel/printk:disable_boot_consoles() ) | ||
82 | */ | ||
83 | int *loc = (int *)SHADOW_CONSOLE_MAGIC_LOC; | ||
84 | |||
85 | loc[0] = 0; | ||
86 | |||
87 | return 0; | ||
88 | } | ||
89 | pure_initcall(disable_shadow_console); | ||
90 | |||
91 | /* | ||
92 | * since we can't use printk, dump numbers (as hex), n = # bits | ||
93 | */ | ||
94 | __init void early_shadow_reg(unsigned long reg, unsigned int n) | ||
95 | { | ||
96 | /* | ||
97 | * can't use any "normal" kernel features, since thay | ||
98 | * may not be relocated to their execute address yet | ||
99 | */ | ||
100 | int i; | ||
101 | char ascii[11] = " 0x"; | ||
102 | |||
103 | n = n / 4; | ||
104 | reg = reg << ((8 - n) * 4); | ||
105 | n += 3; | ||
106 | |||
107 | for (i = 3; i <= n ; i++) { | ||
108 | ascii[i] = hex_asc_lo(reg >> 28); | ||
109 | reg <<= 4; | ||
110 | } | ||
111 | early_shadow_write(NULL, ascii, n); | ||
112 | |||
113 | } | ||
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c index 0791eba40d9f..f9715764383e 100644 --- a/arch/blackfin/kernel/time-ts.c +++ b/arch/blackfin/kernel/time-ts.c | |||
@@ -66,7 +66,7 @@ static cycle_t bfin_read_cycles(struct clocksource *cs) | |||
66 | 66 | ||
67 | static struct clocksource bfin_cs_cycles = { | 67 | static struct clocksource bfin_cs_cycles = { |
68 | .name = "bfin_cs_cycles", | 68 | .name = "bfin_cs_cycles", |
69 | .rating = 350, | 69 | .rating = 400, |
70 | .read = bfin_read_cycles, | 70 | .read = bfin_read_cycles, |
71 | .mask = CLOCKSOURCE_MASK(64), | 71 | .mask = CLOCKSOURCE_MASK(64), |
72 | .shift = 22, | 72 | .shift = 22, |
@@ -115,7 +115,7 @@ static cycle_t bfin_read_gptimer0(void) | |||
115 | 115 | ||
116 | static struct clocksource bfin_cs_gptimer0 = { | 116 | static struct clocksource bfin_cs_gptimer0 = { |
117 | .name = "bfin_cs_gptimer0", | 117 | .name = "bfin_cs_gptimer0", |
118 | .rating = 400, | 118 | .rating = 350, |
119 | .read = bfin_read_gptimer0, | 119 | .read = bfin_read_gptimer0, |
120 | .mask = CLOCKSOURCE_MASK(32), | 120 | .mask = CLOCKSOURCE_MASK(32), |
121 | .shift = 22, | 121 | .shift = 22, |
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index bf2b2d1f8ae5..56464cb8edf3 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c | |||
@@ -100,7 +100,11 @@ static void decode_address(char *buf, unsigned long address) | |||
100 | char *modname; | 100 | char *modname; |
101 | char *delim = ":"; | 101 | char *delim = ":"; |
102 | char namebuf[128]; | 102 | char namebuf[128]; |
103 | #endif | ||
104 | |||
105 | buf += sprintf(buf, "<0x%08lx> ", address); | ||
103 | 106 | ||
107 | #ifdef CONFIG_KALLSYMS | ||
104 | /* look up the address and see if we are in kernel space */ | 108 | /* look up the address and see if we are in kernel space */ |
105 | symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf); | 109 | symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf); |
106 | 110 | ||
@@ -108,23 +112,33 @@ static void decode_address(char *buf, unsigned long address) | |||
108 | /* yeah! kernel space! */ | 112 | /* yeah! kernel space! */ |
109 | if (!modname) | 113 | if (!modname) |
110 | modname = delim = ""; | 114 | modname = delim = ""; |
111 | sprintf(buf, "<0x%p> { %s%s%s%s + 0x%lx }", | 115 | sprintf(buf, "{ %s%s%s%s + 0x%lx }", |
112 | (void *)address, delim, modname, delim, symname, | 116 | delim, modname, delim, symname, |
113 | (unsigned long)offset); | 117 | (unsigned long)offset); |
114 | return; | 118 | return; |
115 | |||
116 | } | 119 | } |
117 | #endif | 120 | #endif |
118 | 121 | ||
119 | /* Problem in fixed code section? */ | ||
120 | if (address >= FIXED_CODE_START && address < FIXED_CODE_END) { | 122 | if (address >= FIXED_CODE_START && address < FIXED_CODE_END) { |
121 | sprintf(buf, "<0x%p> /* Maybe fixed code section */", (void *)address); | 123 | /* Problem in fixed code section? */ |
124 | strcat(buf, "/* Maybe fixed code section */"); | ||
125 | return; | ||
126 | |||
127 | } else if (address < CONFIG_BOOT_LOAD) { | ||
128 | /* Problem somewhere before the kernel start address */ | ||
129 | strcat(buf, "/* Maybe null pointer? */"); | ||
130 | return; | ||
131 | |||
132 | } else if (address >= COREMMR_BASE) { | ||
133 | strcat(buf, "/* core mmrs */"); | ||
122 | return; | 134 | return; |
123 | } | ||
124 | 135 | ||
125 | /* Problem somewhere before the kernel start address */ | 136 | } else if (address >= SYSMMR_BASE) { |
126 | if (address < CONFIG_BOOT_LOAD) { | 137 | strcat(buf, "/* system mmrs */"); |
127 | sprintf(buf, "<0x%p> /* Maybe null pointer? */", (void *)address); | 138 | return; |
139 | |||
140 | } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) { | ||
141 | strcat(buf, "/* on-chip L1 ROM */"); | ||
128 | return; | 142 | return; |
129 | } | 143 | } |
130 | 144 | ||
@@ -172,18 +186,16 @@ static void decode_address(char *buf, unsigned long address) | |||
172 | offset = (address - vma->vm_start) + | 186 | offset = (address - vma->vm_start) + |
173 | (vma->vm_pgoff << PAGE_SHIFT); | 187 | (vma->vm_pgoff << PAGE_SHIFT); |
174 | 188 | ||
175 | sprintf(buf, "<0x%p> [ %s + 0x%lx ]", | 189 | sprintf(buf, "[ %s + 0x%lx ]", name, offset); |
176 | (void *)address, name, offset); | ||
177 | } else | 190 | } else |
178 | sprintf(buf, "<0x%p> [ %s vma:0x%lx-0x%lx]", | 191 | sprintf(buf, "[ %s vma:0x%lx-0x%lx]", |
179 | (void *)address, name, | 192 | name, vma->vm_start, vma->vm_end); |
180 | vma->vm_start, vma->vm_end); | ||
181 | 193 | ||
182 | if (!in_atomic) | 194 | if (!in_atomic) |
183 | mmput(mm); | 195 | mmput(mm); |
184 | 196 | ||
185 | if (!strlen(buf)) | 197 | if (buf[0] == '\0') |
186 | sprintf(buf, "<0x%p> [ %s ] dynamic memory", (void *)address, name); | 198 | sprintf(buf, "[ %s ] dynamic memory", name); |
187 | 199 | ||
188 | goto done; | 200 | goto done; |
189 | } | 201 | } |
@@ -193,7 +205,7 @@ static void decode_address(char *buf, unsigned long address) | |||
193 | } | 205 | } |
194 | 206 | ||
195 | /* we were unable to find this address anywhere */ | 207 | /* we were unable to find this address anywhere */ |
196 | sprintf(buf, "<0x%p> /* kernel dynamic memory */", (void *)address); | 208 | sprintf(buf, "/* kernel dynamic memory */"); |
197 | 209 | ||
198 | done: | 210 | done: |
199 | write_unlock_irqrestore(&tasklist_lock, flags); | 211 | write_unlock_irqrestore(&tasklist_lock, flags); |
@@ -215,14 +227,14 @@ asmlinkage void double_fault_c(struct pt_regs *fp) | |||
215 | printk(KERN_EMERG "Double Fault\n"); | 227 | printk(KERN_EMERG "Double Fault\n"); |
216 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT | 228 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT |
217 | if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) { | 229 | if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) { |
218 | unsigned int cpu = smp_processor_id(); | 230 | unsigned int cpu = raw_smp_processor_id(); |
219 | char buf[150]; | 231 | char buf[150]; |
220 | decode_address(buf, cpu_pda[cpu].retx); | 232 | decode_address(buf, cpu_pda[cpu].retx_doublefault); |
221 | printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n", | 233 | printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n", |
222 | (unsigned int)cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE, buf); | 234 | (unsigned int)cpu_pda[cpu].seqstat_doublefault & SEQSTAT_EXCAUSE, buf); |
223 | decode_address(buf, cpu_pda[cpu].dcplb_fault_addr); | 235 | decode_address(buf, cpu_pda[cpu].dcplb_doublefault_addr); |
224 | printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf); | 236 | printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf); |
225 | decode_address(buf, cpu_pda[cpu].icplb_fault_addr); | 237 | decode_address(buf, cpu_pda[cpu].icplb_doublefault_addr); |
226 | printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf); | 238 | printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf); |
227 | 239 | ||
228 | decode_address(buf, fp->retx); | 240 | decode_address(buf, fp->retx); |
@@ -245,13 +257,13 @@ static int kernel_mode_regs(struct pt_regs *regs) | |||
245 | return regs->ipend & 0xffc0; | 257 | return regs->ipend & 0xffc0; |
246 | } | 258 | } |
247 | 259 | ||
248 | asmlinkage void trap_c(struct pt_regs *fp) | 260 | asmlinkage notrace void trap_c(struct pt_regs *fp) |
249 | { | 261 | { |
250 | #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON | 262 | #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON |
251 | int j; | 263 | int j; |
252 | #endif | 264 | #endif |
253 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO | 265 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO |
254 | unsigned int cpu = smp_processor_id(); | 266 | unsigned int cpu = raw_smp_processor_id(); |
255 | #endif | 267 | #endif |
256 | const char *strerror = NULL; | 268 | const char *strerror = NULL; |
257 | int sig = 0; | 269 | int sig = 0; |
@@ -267,11 +279,6 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
267 | * double faults if the stack has become corrupt | 279 | * double faults if the stack has become corrupt |
268 | */ | 280 | */ |
269 | 281 | ||
270 | #ifndef CONFIG_KGDB | ||
271 | /* IPEND is skipped if KGDB isn't enabled (see entry code) */ | ||
272 | fp->ipend = bfin_read_IPEND(); | ||
273 | #endif | ||
274 | |||
275 | /* trap_c() will be called for exceptions. During exceptions | 282 | /* trap_c() will be called for exceptions. During exceptions |
276 | * processing, the pc value should be set with retx value. | 283 | * processing, the pc value should be set with retx value. |
277 | * With this change we can cleanup some code in signal.c- TODO | 284 | * With this change we can cleanup some code in signal.c- TODO |
@@ -404,7 +411,7 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
404 | /* 0x23 - Data CPLB protection violation, handled here */ | 411 | /* 0x23 - Data CPLB protection violation, handled here */ |
405 | case VEC_CPLB_VL: | 412 | case VEC_CPLB_VL: |
406 | info.si_code = ILL_CPLB_VI; | 413 | info.si_code = ILL_CPLB_VI; |
407 | sig = SIGBUS; | 414 | sig = SIGSEGV; |
408 | strerror = KERN_NOTICE EXC_0x23(KERN_NOTICE); | 415 | strerror = KERN_NOTICE EXC_0x23(KERN_NOTICE); |
409 | CHK_DEBUGGER_TRAP_MAYBE(); | 416 | CHK_DEBUGGER_TRAP_MAYBE(); |
410 | break; | 417 | break; |
@@ -904,7 +911,7 @@ void show_stack(struct task_struct *task, unsigned long *stack) | |||
904 | frame_no = 0; | 911 | frame_no = 0; |
905 | 912 | ||
906 | for (addr = (unsigned int *)((unsigned int)stack & ~0xF), i = 0; | 913 | for (addr = (unsigned int *)((unsigned int)stack & ~0xF), i = 0; |
907 | addr <= endstack; addr++, i++) { | 914 | addr < endstack; addr++, i++) { |
908 | 915 | ||
909 | ret_addr = 0; | 916 | ret_addr = 0; |
910 | if (!j && i % 8 == 0) | 917 | if (!j && i % 8 == 0) |
@@ -949,6 +956,7 @@ void show_stack(struct task_struct *task, unsigned long *stack) | |||
949 | } | 956 | } |
950 | #endif | 957 | #endif |
951 | } | 958 | } |
959 | EXPORT_SYMBOL(show_stack); | ||
952 | 960 | ||
953 | void dump_stack(void) | 961 | void dump_stack(void) |
954 | { | 962 | { |
@@ -1090,7 +1098,7 @@ void show_regs(struct pt_regs *fp) | |||
1090 | struct irqaction *action; | 1098 | struct irqaction *action; |
1091 | unsigned int i; | 1099 | unsigned int i; |
1092 | unsigned long flags = 0; | 1100 | unsigned long flags = 0; |
1093 | unsigned int cpu = smp_processor_id(); | 1101 | unsigned int cpu = raw_smp_processor_id(); |
1094 | unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic(); | 1102 | unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic(); |
1095 | 1103 | ||
1096 | verbose_printk(KERN_NOTICE "\n"); | 1104 | verbose_printk(KERN_NOTICE "\n"); |
@@ -1116,10 +1124,16 @@ void show_regs(struct pt_regs *fp) | |||
1116 | 1124 | ||
1117 | verbose_printk(KERN_NOTICE "%s", linux_banner); | 1125 | verbose_printk(KERN_NOTICE "%s", linux_banner); |
1118 | 1126 | ||
1119 | verbose_printk(KERN_NOTICE "\nSEQUENCER STATUS:\t\t%s\n", | 1127 | verbose_printk(KERN_NOTICE "\nSEQUENCER STATUS:\t\t%s\n", print_tainted()); |
1120 | print_tainted()); | 1128 | verbose_printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n", |
1121 | verbose_printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", | 1129 | (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg); |
1122 | (long)fp->seqstat, fp->ipend, fp->syscfg); | 1130 | if (fp->ipend & EVT_IRPTEN) |
1131 | verbose_printk(KERN_NOTICE " Global Interrupts Disabled (IPEND[4])\n"); | ||
1132 | if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 | | ||
1133 | EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR))) | ||
1134 | verbose_printk(KERN_NOTICE " Peripheral interrupts masked off\n"); | ||
1135 | if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14))) | ||
1136 | verbose_printk(KERN_NOTICE " Kernel interrupts masked off\n"); | ||
1123 | if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) { | 1137 | if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) { |
1124 | verbose_printk(KERN_NOTICE " HWERRCAUSE: 0x%lx\n", | 1138 | verbose_printk(KERN_NOTICE " HWERRCAUSE: 0x%lx\n", |
1125 | (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14); | 1139 | (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14); |
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S index d7ffe299b979..21ac7c26079e 100644 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ b/arch/blackfin/kernel/vmlinux.lds.S | |||
@@ -221,7 +221,7 @@ SECTIONS | |||
221 | . = ALIGN(4); | 221 | . = ALIGN(4); |
222 | __ebss_l1 = .; | 222 | __ebss_l1 = .; |
223 | } | 223 | } |
224 | ASSERT (SIZEOF(.data_a_l1) <= L1_DATA_A_LENGTH, "L1 data A overflow!") | 224 | ASSERT (SIZEOF(.data_l1) <= L1_DATA_A_LENGTH, "L1 data A overflow!") |
225 | 225 | ||
226 | .data_b_l1 L1_DATA_B_START : AT(LOADADDR(.data_l1) + SIZEOF(.data_l1)) | 226 | .data_b_l1 L1_DATA_B_START : AT(LOADADDR(.data_l1) + SIZEOF(.data_l1)) |
227 | { | 227 | { |
@@ -262,7 +262,7 @@ SECTIONS | |||
262 | . = ALIGN(4); | 262 | . = ALIGN(4); |
263 | __ebss_l2 = .; | 263 | __ebss_l2 = .; |
264 | } | 264 | } |
265 | ASSERT (SIZEOF(.text_data_l1) <= L2_LENGTH, "L2 overflow!") | 265 | ASSERT (SIZEOF(.text_data_l2) <= L2_LENGTH, "L2 overflow!") |
266 | 266 | ||
267 | /* Force trailing alignment of our init section so that when we | 267 | /* Force trailing alignment of our init section so that when we |
268 | * free our init memory, we don't leave behind a partial page. | 268 | * free our init memory, we don't leave behind a partial page. |
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S index 1863a6ba507c..3edbd8db6598 100644 --- a/arch/blackfin/lib/ins.S +++ b/arch/blackfin/lib/ins.S | |||
@@ -16,7 +16,7 @@ | |||
16 | [--sp] = rets; \ | 16 | [--sp] = rets; \ |
17 | [--sp] = (P5:0); \ | 17 | [--sp] = (P5:0); \ |
18 | sp += -12; \ | 18 | sp += -12; \ |
19 | call ___ipipe_stall_root_raw; \ | 19 | call ___ipipe_disable_root_irqs_hw; \ |
20 | sp += 12; \ | 20 | sp += 12; \ |
21 | (P5:0) = [sp++]; | 21 | (P5:0) = [sp++]; |
22 | # define CLI_INNER_NOP | 22 | # define CLI_INNER_NOP |
@@ -28,7 +28,7 @@ | |||
28 | #ifdef CONFIG_IPIPE | 28 | #ifdef CONFIG_IPIPE |
29 | # define DO_STI \ | 29 | # define DO_STI \ |
30 | sp += -12; \ | 30 | sp += -12; \ |
31 | call ___ipipe_unstall_root_raw; \ | 31 | call ___ipipe_enable_root_irqs_hw; \ |
32 | sp += 12; \ | 32 | sp += 12; \ |
33 | 2: rets = [sp++]; | 33 | 2: rets = [sp++]; |
34 | #else | 34 | #else |
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c index 809be268e42d..03e4a9941f01 100644 --- a/arch/blackfin/mach-bf518/boards/ezbrd.c +++ b/arch/blackfin/mach-bf518/boards/ezbrd.c | |||
@@ -199,15 +199,6 @@ static struct bfin5xx_spi_chip mmc_spi_chip_info = { | |||
199 | }; | 199 | }; |
200 | #endif | 200 | #endif |
201 | 201 | ||
202 | #if defined(CONFIG_PBX) | ||
203 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | ||
204 | .ctl_reg = 0x4, /* send zero */ | ||
205 | .enable_dma = 0, | ||
206 | .bits_per_word = 8, | ||
207 | .cs_change_per_word = 1, | ||
208 | }; | ||
209 | #endif | ||
210 | |||
211 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | 202 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
212 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { | 203 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { |
213 | .enable_dma = 0, | 204 | .enable_dma = 0, |
@@ -296,24 +287,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
296 | .mode = SPI_MODE_3, | 287 | .mode = SPI_MODE_3, |
297 | }, | 288 | }, |
298 | #endif | 289 | #endif |
299 | #if defined(CONFIG_PBX) | ||
300 | { | ||
301 | .modalias = "fxs-spi", | ||
302 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
303 | .bus_num = 0, | ||
304 | .chip_select = 8 - CONFIG_J11_JUMPER, | ||
305 | .controller_data = &spi_si3xxx_chip_info, | ||
306 | .mode = SPI_MODE_3, | ||
307 | }, | ||
308 | { | ||
309 | .modalias = "fxo-spi", | ||
310 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
311 | .bus_num = 0, | ||
312 | .chip_select = 8 - CONFIG_J19_JUMPER, | ||
313 | .controller_data = &spi_si3xxx_chip_info, | ||
314 | .mode = SPI_MODE_3, | ||
315 | }, | ||
316 | #endif | ||
317 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | 290 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
318 | { | 291 | { |
319 | .modalias = "ad7877", | 292 | .modalias = "ad7877", |
@@ -539,7 +512,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | |||
539 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 512 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
540 | }, | 513 | }, |
541 | #endif | 514 | #endif |
542 | #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) | 515 | #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE) |
543 | { | 516 | { |
544 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), | 517 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), |
545 | .irq = IRQ_PF8, | 518 | .irq = IRQ_PF8, |
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h index 753ed810e1c6..e9c65390edd1 100644 --- a/arch/blackfin/mach-bf518/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h | |||
@@ -124,6 +124,7 @@ | |||
124 | #define ANOMALY_05000386 (0) | 124 | #define ANOMALY_05000386 (0) |
125 | #define ANOMALY_05000389 (0) | 125 | #define ANOMALY_05000389 (0) |
126 | #define ANOMALY_05000400 (0) | 126 | #define ANOMALY_05000400 (0) |
127 | #define ANOMALY_05000402 (0) | ||
127 | #define ANOMALY_05000412 (0) | 128 | #define ANOMALY_05000412 (0) |
128 | #define ANOMALY_05000432 (0) | 129 | #define ANOMALY_05000432 (0) |
129 | #define ANOMALY_05000447 (0) | 130 | #define ANOMALY_05000447 (0) |
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h index e8e14c2769ed..83421d393148 100644 --- a/arch/blackfin/mach-bf518/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h | |||
@@ -68,11 +68,6 @@ | |||
68 | #endif | 68 | #endif |
69 | #endif | 69 | #endif |
70 | 70 | ||
71 | /* UART_IIR Register */ | ||
72 | #define STATUS(x) ((x << 1) & 0x06) | ||
73 | #define STATUS_P1 0x02 | ||
74 | #define STATUS_P0 0x01 | ||
75 | |||
76 | #define BFIN_UART_NR_PORTS 2 | 71 | #define BFIN_UART_NR_PORTS 2 |
77 | 72 | ||
78 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | 73 | #define OFFSET_THR 0x00 /* Transmit Holding register */ |
@@ -88,11 +83,6 @@ | |||
88 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | 83 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ |
89 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | 84 | #define OFFSET_GCTL 0x24 /* Global Control Register */ |
90 | 85 | ||
91 | /* DPMC*/ | ||
92 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | ||
93 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) | ||
94 | #define STOPCK_OFF STOPCK | ||
95 | |||
96 | /* PLL_DIV Masks */ | 86 | /* PLL_DIV Masks */ |
97 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | 87 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ |
98 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | 88 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ |
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c index b09484f538f4..08a3f01c9886 100644 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c | |||
@@ -151,46 +151,6 @@ static struct platform_device musb_device = { | |||
151 | }; | 151 | }; |
152 | #endif | 152 | #endif |
153 | 153 | ||
154 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
155 | static struct mtd_partition ezkit_partitions[] = { | ||
156 | { | ||
157 | .name = "bootloader(nor)", | ||
158 | .size = 0x40000, | ||
159 | .offset = 0, | ||
160 | }, { | ||
161 | .name = "linux kernel(nor)", | ||
162 | .size = 0x1C0000, | ||
163 | .offset = MTDPART_OFS_APPEND, | ||
164 | }, { | ||
165 | .name = "file system(nor)", | ||
166 | .size = MTDPART_SIZ_FULL, | ||
167 | .offset = MTDPART_OFS_APPEND, | ||
168 | } | ||
169 | }; | ||
170 | |||
171 | static struct physmap_flash_data ezkit_flash_data = { | ||
172 | .width = 2, | ||
173 | .parts = ezkit_partitions, | ||
174 | .nr_parts = ARRAY_SIZE(ezkit_partitions), | ||
175 | }; | ||
176 | |||
177 | static struct resource ezkit_flash_resource = { | ||
178 | .start = 0x20000000, | ||
179 | .end = 0x201fffff, | ||
180 | .flags = IORESOURCE_MEM, | ||
181 | }; | ||
182 | |||
183 | static struct platform_device ezkit_flash_device = { | ||
184 | .name = "physmap-flash", | ||
185 | .id = 0, | ||
186 | .dev = { | ||
187 | .platform_data = &ezkit_flash_data, | ||
188 | }, | ||
189 | .num_resources = 1, | ||
190 | .resource = &ezkit_flash_resource, | ||
191 | }; | ||
192 | #endif | ||
193 | |||
194 | #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) | 154 | #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) |
195 | static struct mtd_partition partition_info[] = { | 155 | static struct mtd_partition partition_info[] = { |
196 | { | 156 | { |
@@ -275,6 +235,14 @@ static struct platform_device rtc_device = { | |||
275 | #endif | 235 | #endif |
276 | 236 | ||
277 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 237 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
238 | #include <linux/smc91x.h> | ||
239 | |||
240 | static struct smc91x_platdata smc91x_info = { | ||
241 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
242 | .leda = RPC_LED_100_10, | ||
243 | .ledb = RPC_LED_TX_RX, | ||
244 | }; | ||
245 | |||
278 | static struct resource smc91x_resources[] = { | 246 | static struct resource smc91x_resources[] = { |
279 | { | 247 | { |
280 | .name = "smc91x-regs", | 248 | .name = "smc91x-regs", |
@@ -293,6 +261,9 @@ static struct platform_device smc91x_device = { | |||
293 | .id = 0, | 261 | .id = 0, |
294 | .num_resources = ARRAY_SIZE(smc91x_resources), | 262 | .num_resources = ARRAY_SIZE(smc91x_resources), |
295 | .resource = smc91x_resources, | 263 | .resource = smc91x_resources, |
264 | .dev = { | ||
265 | .platform_data = &smc91x_info, | ||
266 | }, | ||
296 | }; | 267 | }; |
297 | #endif | 268 | #endif |
298 | 269 | ||
@@ -300,10 +271,15 @@ static struct platform_device smc91x_device = { | |||
300 | static struct resource dm9000_resources[] = { | 271 | static struct resource dm9000_resources[] = { |
301 | [0] = { | 272 | [0] = { |
302 | .start = 0x203FB800, | 273 | .start = 0x203FB800, |
303 | .end = 0x203FB800 + 8, | 274 | .end = 0x203FB800 + 1, |
304 | .flags = IORESOURCE_MEM, | 275 | .flags = IORESOURCE_MEM, |
305 | }, | 276 | }, |
306 | [1] = { | 277 | [1] = { |
278 | .start = 0x203FB804, | ||
279 | .end = 0x203FB804 + 1, | ||
280 | .flags = IORESOURCE_MEM, | ||
281 | }, | ||
282 | [2] = { | ||
307 | .start = IRQ_PF9, | 283 | .start = IRQ_PF9, |
308 | .end = IRQ_PF9, | 284 | .end = IRQ_PF9, |
309 | .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), | 285 | .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), |
@@ -479,13 +455,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |||
479 | }; | 455 | }; |
480 | #endif | 456 | #endif |
481 | 457 | ||
482 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
483 | static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | ||
484 | .enable_dma = 0, | ||
485 | .bits_per_word = 16, | ||
486 | }; | ||
487 | #endif | ||
488 | |||
489 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 458 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
490 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | 459 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
491 | .enable_dma = 0, | 460 | .enable_dma = 0, |
@@ -493,15 +462,6 @@ static struct bfin5xx_spi_chip mmc_spi_chip_info = { | |||
493 | }; | 462 | }; |
494 | #endif | 463 | #endif |
495 | 464 | ||
496 | #if defined(CONFIG_PBX) | ||
497 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | ||
498 | .ctl_reg = 0x4, /* send zero */ | ||
499 | .enable_dma = 0, | ||
500 | .bits_per_word = 8, | ||
501 | .cs_change_per_word = 1, | ||
502 | }; | ||
503 | #endif | ||
504 | |||
505 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | 465 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
506 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { | 466 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { |
507 | .enable_dma = 0, | 467 | .enable_dma = 0, |
@@ -568,22 +528,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
568 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ | 528 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ |
569 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 529 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) |
570 | { | 530 | { |
571 | .modalias = "ad1836-spi", | 531 | .modalias = "ad1836", |
572 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | 532 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
573 | .bus_num = 0, | 533 | .bus_num = 0, |
574 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 534 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
575 | .controller_data = &ad1836_spi_chip_info, | 535 | .controller_data = &ad1836_spi_chip_info, |
576 | }, | 536 | }, |
577 | #endif | 537 | #endif |
578 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
579 | { | ||
580 | .modalias = "ad9960-spi", | ||
581 | .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ | ||
582 | .bus_num = 0, | ||
583 | .chip_select = 1, | ||
584 | .controller_data = &ad9960_spi_chip_info, | ||
585 | }, | ||
586 | #endif | ||
587 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 538 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
588 | { | 539 | { |
589 | .modalias = "mmc_spi", | 540 | .modalias = "mmc_spi", |
@@ -594,24 +545,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
594 | .mode = SPI_MODE_3, | 545 | .mode = SPI_MODE_3, |
595 | }, | 546 | }, |
596 | #endif | 547 | #endif |
597 | #if defined(CONFIG_PBX) | ||
598 | { | ||
599 | .modalias = "fxs-spi", | ||
600 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
601 | .bus_num = 0, | ||
602 | .chip_select = 8 - CONFIG_J11_JUMPER, | ||
603 | .controller_data = &spi_si3xxx_chip_info, | ||
604 | .mode = SPI_MODE_3, | ||
605 | }, | ||
606 | { | ||
607 | .modalias = "fxo-spi", | ||
608 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
609 | .bus_num = 0, | ||
610 | .chip_select = 8 - CONFIG_J19_JUMPER, | ||
611 | .controller_data = &spi_si3xxx_chip_info, | ||
612 | .mode = SPI_MODE_3, | ||
613 | }, | ||
614 | #endif | ||
615 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | 548 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
616 | { | 549 | { |
617 | .modalias = "ad7877", | 550 | .modalias = "ad7877", |
@@ -689,6 +622,55 @@ static struct platform_device bfin_fb_adv7393_device = { | |||
689 | }; | 622 | }; |
690 | #endif | 623 | #endif |
691 | 624 | ||
625 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) | ||
626 | static struct mtd_partition cm_partitions[] = { | ||
627 | { | ||
628 | .name = "bootloader(nor)", | ||
629 | .size = 0x40000, | ||
630 | .offset = 0, | ||
631 | }, { | ||
632 | .name = "linux kernel(nor)", | ||
633 | .size = 0x100000, | ||
634 | .offset = MTDPART_OFS_APPEND, | ||
635 | }, { | ||
636 | .name = "file system(nor)", | ||
637 | .size = MTDPART_SIZ_FULL, | ||
638 | .offset = MTDPART_OFS_APPEND, | ||
639 | } | ||
640 | }; | ||
641 | |||
642 | static struct physmap_flash_data cm_flash_data = { | ||
643 | .width = 2, | ||
644 | .parts = cm_partitions, | ||
645 | .nr_parts = ARRAY_SIZE(cm_partitions), | ||
646 | }; | ||
647 | |||
648 | static unsigned cm_flash_gpios[] = { GPIO_PH9, GPIO_PG11 }; | ||
649 | |||
650 | static struct resource cm_flash_resource[] = { | ||
651 | { | ||
652 | .name = "cfi_probe", | ||
653 | .start = 0x20000000, | ||
654 | .end = 0x201fffff, | ||
655 | .flags = IORESOURCE_MEM, | ||
656 | }, { | ||
657 | .start = (unsigned long)cm_flash_gpios, | ||
658 | .end = ARRAY_SIZE(cm_flash_gpios), | ||
659 | .flags = IORESOURCE_IRQ, | ||
660 | } | ||
661 | }; | ||
662 | |||
663 | static struct platform_device cm_flash_device = { | ||
664 | .name = "gpio-addr-flash", | ||
665 | .id = 0, | ||
666 | .dev = { | ||
667 | .platform_data = &cm_flash_data, | ||
668 | }, | ||
669 | .num_resources = ARRAY_SIZE(cm_flash_resource), | ||
670 | .resource = cm_flash_resource, | ||
671 | }; | ||
672 | #endif | ||
673 | |||
692 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | 674 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) |
693 | static struct resource bfin_uart_resources[] = { | 675 | static struct resource bfin_uart_resources[] = { |
694 | #ifdef CONFIG_SERIAL_BFIN_UART0 | 676 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
@@ -796,13 +778,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | |||
796 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) | 778 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) |
797 | { | 779 | { |
798 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 780 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
799 | .type = "pcf8574_lcd", | ||
800 | }, | 781 | }, |
801 | #endif | 782 | #endif |
802 | #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) | 783 | #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE) |
803 | { | 784 | { |
804 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), | 785 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), |
805 | .type = "pcf8574_keypad", | ||
806 | .irq = IRQ_PF8, | 786 | .irq = IRQ_PF8, |
807 | }, | 787 | }, |
808 | #endif | 788 | #endif |
@@ -876,7 +856,7 @@ static struct platform_device bfin_dpmc = { | |||
876 | }, | 856 | }, |
877 | }; | 857 | }; |
878 | 858 | ||
879 | static struct platform_device *stamp_devices[] __initdata = { | 859 | static struct platform_device *cmbf527_devices[] __initdata = { |
880 | 860 | ||
881 | &bfin_dpmc, | 861 | &bfin_dpmc, |
882 | 862 | ||
@@ -959,8 +939,8 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
959 | &bfin_device_gpiokeys, | 939 | &bfin_device_gpiokeys, |
960 | #endif | 940 | #endif |
961 | 941 | ||
962 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | 942 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) |
963 | &ezkit_flash_device, | 943 | &cm_flash_device, |
964 | #endif | 944 | #endif |
965 | 945 | ||
966 | &bfin_gpios_device, | 946 | &bfin_gpios_device, |
@@ -971,7 +951,7 @@ static int __init cm_init(void) | |||
971 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | 951 | printk(KERN_INFO "%s(): registering device resources\n", __func__); |
972 | i2c_register_board_info(0, bfin_i2c_board_info, | 952 | i2c_register_board_info(0, bfin_i2c_board_info, |
973 | ARRAY_SIZE(bfin_i2c_board_info)); | 953 | ARRAY_SIZE(bfin_i2c_board_info)); |
974 | platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); | 954 | platform_add_devices(cmbf527_devices, ARRAY_SIZE(cmbf527_devices)); |
975 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | 955 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); |
976 | return 0; | 956 | return 0; |
977 | } | 957 | } |
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c index 2ad68cd10ae6..68b4c804364c 100644 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ b/arch/blackfin/mach-bf527/boards/ezbrd.c | |||
@@ -263,15 +263,6 @@ static struct bfin5xx_spi_chip mmc_spi_chip_info = { | |||
263 | }; | 263 | }; |
264 | #endif | 264 | #endif |
265 | 265 | ||
266 | #if defined(CONFIG_PBX) | ||
267 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | ||
268 | .ctl_reg = 0x4, /* send zero */ | ||
269 | .enable_dma = 0, | ||
270 | .bits_per_word = 8, | ||
271 | .cs_change_per_word = 1, | ||
272 | }; | ||
273 | #endif | ||
274 | |||
275 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | 266 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
276 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { | 267 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { |
277 | .enable_dma = 0, | 268 | .enable_dma = 0, |
@@ -376,24 +367,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
376 | .mode = SPI_MODE_3, | 367 | .mode = SPI_MODE_3, |
377 | }, | 368 | }, |
378 | #endif | 369 | #endif |
379 | #if defined(CONFIG_PBX) | ||
380 | { | ||
381 | .modalias = "fxs-spi", | ||
382 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
383 | .bus_num = 0, | ||
384 | .chip_select = 8 - CONFIG_J11_JUMPER, | ||
385 | .controller_data = &spi_si3xxx_chip_info, | ||
386 | .mode = SPI_MODE_3, | ||
387 | }, | ||
388 | { | ||
389 | .modalias = "fxo-spi", | ||
390 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
391 | .bus_num = 0, | ||
392 | .chip_select = 8 - CONFIG_J19_JUMPER, | ||
393 | .controller_data = &spi_si3xxx_chip_info, | ||
394 | .mode = SPI_MODE_3, | ||
395 | }, | ||
396 | #endif | ||
397 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | 370 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
398 | { | 371 | { |
399 | .modalias = "ad7877", | 372 | .modalias = "ad7877", |
@@ -596,7 +569,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | |||
596 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 569 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
597 | }, | 570 | }, |
598 | #endif | 571 | #endif |
599 | #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) | 572 | #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE) |
600 | { | 573 | { |
601 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), | 574 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), |
602 | .irq = IRQ_PF8, | 575 | .irq = IRQ_PF8, |
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index 75e563d3f9d4..2849b09abe99 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c | |||
@@ -292,6 +292,14 @@ static struct platform_device rtc_device = { | |||
292 | #endif | 292 | #endif |
293 | 293 | ||
294 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 294 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
295 | #include <linux/smc91x.h> | ||
296 | |||
297 | static struct smc91x_platdata smc91x_info = { | ||
298 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
299 | .leda = RPC_LED_100_10, | ||
300 | .ledb = RPC_LED_TX_RX, | ||
301 | }; | ||
302 | |||
295 | static struct resource smc91x_resources[] = { | 303 | static struct resource smc91x_resources[] = { |
296 | { | 304 | { |
297 | .name = "smc91x-regs", | 305 | .name = "smc91x-regs", |
@@ -310,6 +318,9 @@ static struct platform_device smc91x_device = { | |||
310 | .id = 0, | 318 | .id = 0, |
311 | .num_resources = ARRAY_SIZE(smc91x_resources), | 319 | .num_resources = ARRAY_SIZE(smc91x_resources), |
312 | .resource = smc91x_resources, | 320 | .resource = smc91x_resources, |
321 | .dev = { | ||
322 | .platform_data = &smc91x_info, | ||
323 | }, | ||
313 | }; | 324 | }; |
314 | #endif | 325 | #endif |
315 | 326 | ||
@@ -501,13 +512,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |||
501 | }; | 512 | }; |
502 | #endif | 513 | #endif |
503 | 514 | ||
504 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
505 | static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | ||
506 | .enable_dma = 0, | ||
507 | .bits_per_word = 16, | ||
508 | }; | ||
509 | #endif | ||
510 | |||
511 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 515 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
512 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | 516 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
513 | .enable_dma = 0, | 517 | .enable_dma = 0, |
@@ -515,15 +519,6 @@ static struct bfin5xx_spi_chip mmc_spi_chip_info = { | |||
515 | }; | 519 | }; |
516 | #endif | 520 | #endif |
517 | 521 | ||
518 | #if defined(CONFIG_PBX) | ||
519 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | ||
520 | .ctl_reg = 0x4, /* send zero */ | ||
521 | .enable_dma = 0, | ||
522 | .bits_per_word = 8, | ||
523 | .cs_change_per_word = 1, | ||
524 | }; | ||
525 | #endif | ||
526 | |||
527 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | 522 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
528 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { | 523 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { |
529 | .enable_dma = 0, | 524 | .enable_dma = 0, |
@@ -614,22 +609,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
614 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ | 609 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ |
615 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 610 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) |
616 | { | 611 | { |
617 | .modalias = "ad1836-spi", | 612 | .modalias = "ad1836", |
618 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | 613 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
619 | .bus_num = 0, | 614 | .bus_num = 0, |
620 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 615 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
621 | .controller_data = &ad1836_spi_chip_info, | 616 | .controller_data = &ad1836_spi_chip_info, |
622 | }, | 617 | }, |
623 | #endif | 618 | #endif |
624 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
625 | { | ||
626 | .modalias = "ad9960-spi", | ||
627 | .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ | ||
628 | .bus_num = 0, | ||
629 | .chip_select = 1, | ||
630 | .controller_data = &ad9960_spi_chip_info, | ||
631 | }, | ||
632 | #endif | ||
633 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 619 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
634 | { | 620 | { |
635 | .modalias = "mmc_spi", | 621 | .modalias = "mmc_spi", |
@@ -641,24 +627,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
641 | }, | 627 | }, |
642 | #endif | 628 | #endif |
643 | 629 | ||
644 | #if defined(CONFIG_PBX) | ||
645 | { | ||
646 | .modalias = "fxs-spi", | ||
647 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
648 | .bus_num = 0, | ||
649 | .chip_select = 8 - CONFIG_J11_JUMPER, | ||
650 | .controller_data = &spi_si3xxx_chip_info, | ||
651 | .mode = SPI_MODE_3, | ||
652 | }, | ||
653 | { | ||
654 | .modalias = "fxo-spi", | ||
655 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
656 | .bus_num = 0, | ||
657 | .chip_select = 8 - CONFIG_J19_JUMPER, | ||
658 | .controller_data = &spi_si3xxx_chip_info, | ||
659 | .mode = SPI_MODE_3, | ||
660 | }, | ||
661 | #endif | ||
662 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | 630 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
663 | { | 631 | { |
664 | .modalias = "ad7877", | 632 | .modalias = "ad7877", |
@@ -863,7 +831,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | |||
863 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 831 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
864 | }, | 832 | }, |
865 | #endif | 833 | #endif |
866 | #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) | 834 | #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE) |
867 | { | 835 | { |
868 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), | 836 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), |
869 | .irq = IRQ_PF8, | 837 | .irq = IRQ_PF8, |
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index c438ca89d8c9..3f9052687fa8 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h | |||
@@ -7,7 +7,7 @@ | |||
7 | */ | 7 | */ |
8 | 8 | ||
9 | /* This file should be up to date with: | 9 | /* This file should be up to date with: |
10 | * - Revision C, 03/13/2009; ADSP-BF526 Blackfin Processor Anomaly List | 10 | * - Revision D, 08/14/2009; ADSP-BF526 Blackfin Processor Anomaly List |
11 | * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List | 11 | * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List |
12 | */ | 12 | */ |
13 | 13 | ||
@@ -176,7 +176,7 @@ | |||
176 | #define ANOMALY_05000443 (1) | 176 | #define ANOMALY_05000443 (1) |
177 | /* The WURESET Bit in the SYSCR Register is not Functional */ | 177 | /* The WURESET Bit in the SYSCR Register is not Functional */ |
178 | #define ANOMALY_05000445 (1) | 178 | #define ANOMALY_05000445 (1) |
179 | /* USB DMA Short Packet Data Corruption */ | 179 | /* USB DMA Mode 1 Short Packet Data Corruption */ |
180 | #define ANOMALY_05000450 (1) | 180 | #define ANOMALY_05000450 (1) |
181 | /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ | 181 | /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ |
182 | #define ANOMALY_05000451 (1) | 182 | #define ANOMALY_05000451 (1) |
@@ -186,12 +186,20 @@ | |||
186 | #define ANOMALY_05000456 (1) | 186 | #define ANOMALY_05000456 (1) |
187 | /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ | 187 | /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ |
188 | #define ANOMALY_05000457 (1) | 188 | #define ANOMALY_05000457 (1) |
189 | /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ | ||
190 | #define ANOMALY_05000460 (1) | ||
189 | /* False Hardware Error when RETI Points to Invalid Memory */ | 191 | /* False Hardware Error when RETI Points to Invalid Memory */ |
190 | #define ANOMALY_05000461 (1) | 192 | #define ANOMALY_05000461 (1) |
193 | /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ | ||
194 | #define ANOMALY_05000462 (1) | ||
191 | /* USB Rx DMA hang */ | 195 | /* USB Rx DMA hang */ |
192 | #define ANOMALY_05000465 (1) | 196 | #define ANOMALY_05000465 (1) |
197 | /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ | ||
198 | #define ANOMALY_05000466 (1) | ||
193 | /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ | 199 | /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ |
194 | #define ANOMALY_05000467 (1) | 200 | #define ANOMALY_05000467 (1) |
201 | /* PLL Latches Incorrect Settings During Reset */ | ||
202 | #define ANOMALY_05000469 (1) | ||
195 | 203 | ||
196 | /* Anomalies that don't exist on this proc */ | 204 | /* Anomalies that don't exist on this proc */ |
197 | #define ANOMALY_05000099 (0) | 205 | #define ANOMALY_05000099 (0) |
@@ -238,6 +246,7 @@ | |||
238 | #define ANOMALY_05000362 (1) | 246 | #define ANOMALY_05000362 (1) |
239 | #define ANOMALY_05000363 (0) | 247 | #define ANOMALY_05000363 (0) |
240 | #define ANOMALY_05000400 (0) | 248 | #define ANOMALY_05000400 (0) |
249 | #define ANOMALY_05000402 (0) | ||
241 | #define ANOMALY_05000412 (0) | 250 | #define ANOMALY_05000412 (0) |
242 | #define ANOMALY_05000447 (0) | 251 | #define ANOMALY_05000447 (0) |
243 | #define ANOMALY_05000448 (0) | 252 | #define ANOMALY_05000448 (0) |
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h index 03665a8e16be..ea9cb0fef8bc 100644 --- a/arch/blackfin/mach-bf527/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h | |||
@@ -56,11 +56,6 @@ | |||
56 | #endif | 56 | #endif |
57 | #endif | 57 | #endif |
58 | 58 | ||
59 | /* UART_IIR Register */ | ||
60 | #define STATUS(x) ((x << 1) & 0x06) | ||
61 | #define STATUS_P1 0x02 | ||
62 | #define STATUS_P0 0x01 | ||
63 | |||
64 | #define BFIN_UART_NR_PORTS 2 | 59 | #define BFIN_UART_NR_PORTS 2 |
65 | 60 | ||
66 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | 61 | #define OFFSET_THR 0x00 /* Transmit Holding register */ |
@@ -76,11 +71,6 @@ | |||
76 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | 71 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ |
77 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | 72 | #define OFFSET_GCTL 0x24 /* Global Control Register */ |
78 | 73 | ||
79 | /* DPMC*/ | ||
80 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | ||
81 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) | ||
82 | #define STOPCK_OFF STOPCK | ||
83 | |||
84 | /* PLL_DIV Masks */ | 74 | /* PLL_DIV Masks */ |
85 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | 75 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ |
86 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | 76 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ |
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c index 38cf8ffd6d74..6c2b47fe4fe4 100644 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ b/arch/blackfin/mach-bf533/boards/H8606.c | |||
@@ -88,6 +88,14 @@ static struct platform_device dm9000_device = { | |||
88 | #endif | 88 | #endif |
89 | 89 | ||
90 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 90 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
91 | #include <linux/smc91x.h> | ||
92 | |||
93 | static struct smc91x_platdata smc91x_info = { | ||
94 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
95 | .leda = RPC_LED_100_10, | ||
96 | .ledb = RPC_LED_TX_RX, | ||
97 | }; | ||
98 | |||
91 | static struct resource smc91x_resources[] = { | 99 | static struct resource smc91x_resources[] = { |
92 | { | 100 | { |
93 | .name = "smc91x-regs", | 101 | .name = "smc91x-regs", |
@@ -110,6 +118,9 @@ static struct platform_device smc91x_device = { | |||
110 | .id = 0, | 118 | .id = 0, |
111 | .num_resources = ARRAY_SIZE(smc91x_resources), | 119 | .num_resources = ARRAY_SIZE(smc91x_resources), |
112 | .resource = smc91x_resources, | 120 | .resource = smc91x_resources, |
121 | .dev = { | ||
122 | .platform_data = &smc91x_info, | ||
123 | }, | ||
113 | }; | 124 | }; |
114 | #endif | 125 | #endif |
115 | 126 | ||
@@ -190,15 +201,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |||
190 | }; | 201 | }; |
191 | #endif | 202 | #endif |
192 | 203 | ||
193 | #if defined(CONFIG_PBX) | ||
194 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | ||
195 | .ctl_reg = 0x1c04, | ||
196 | .enable_dma = 0, | ||
197 | .bits_per_word = 8, | ||
198 | .cs_change_per_word = 1, | ||
199 | }; | ||
200 | #endif | ||
201 | |||
202 | /* Notice: for blackfin, the speed_hz is the value of register | 204 | /* Notice: for blackfin, the speed_hz is the value of register |
203 | * SPI_BAUD, not the real baudrate */ | 205 | * SPI_BAUD, not the real baudrate */ |
204 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | 206 | static struct spi_board_info bfin_spi_board_info[] __initdata = { |
@@ -229,7 +231,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
229 | 231 | ||
230 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 232 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) |
231 | { | 233 | { |
232 | .modalias = "ad1836-spi", | 234 | .modalias = "ad1836", |
233 | .max_speed_hz = 16, | 235 | .max_speed_hz = 16, |
234 | .bus_num = 1, | 236 | .bus_num = 1, |
235 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 237 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
@@ -237,23 +239,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
237 | }, | 239 | }, |
238 | #endif | 240 | #endif |
239 | 241 | ||
240 | #if defined(CONFIG_PBX) | ||
241 | { | ||
242 | .modalias = "fxs-spi", | ||
243 | .max_speed_hz = 4, | ||
244 | .bus_num = 1, | ||
245 | .chip_select = 3, | ||
246 | .controller_data = &spi_si3xxx_chip_info, | ||
247 | }, | ||
248 | |||
249 | { | ||
250 | .modalias = "fxo-spi", | ||
251 | .max_speed_hz = 4, | ||
252 | .bus_num = 1, | ||
253 | .chip_select = 2, | ||
254 | .controller_data = &spi_si3xxx_chip_info, | ||
255 | }, | ||
256 | #endif | ||
257 | }; | 242 | }; |
258 | 243 | ||
259 | /* SPI (0) */ | 244 | /* SPI (0) */ |
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c index 9ecdc361fa6d..8208d67e2c97 100644 --- a/arch/blackfin/mach-bf533/boards/blackstamp.c +++ b/arch/blackfin/mach-bf533/boards/blackstamp.c | |||
@@ -48,6 +48,14 @@ static struct platform_device rtc_device = { | |||
48 | * Driver needs to know address, irq and flag pin. | 48 | * Driver needs to know address, irq and flag pin. |
49 | */ | 49 | */ |
50 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 50 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
51 | #include <linux/smc91x.h> | ||
52 | |||
53 | static struct smc91x_platdata smc91x_info = { | ||
54 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
55 | .leda = RPC_LED_100_10, | ||
56 | .ledb = RPC_LED_TX_RX, | ||
57 | }; | ||
58 | |||
51 | static struct resource smc91x_resources[] = { | 59 | static struct resource smc91x_resources[] = { |
52 | { | 60 | { |
53 | .name = "smc91x-regs", | 61 | .name = "smc91x-regs", |
@@ -66,6 +74,9 @@ static struct platform_device smc91x_device = { | |||
66 | .id = 0, | 74 | .id = 0, |
67 | .num_resources = ARRAY_SIZE(smc91x_resources), | 75 | .num_resources = ARRAY_SIZE(smc91x_resources), |
68 | .resource = smc91x_resources, | 76 | .resource = smc91x_resources, |
77 | .dev = { | ||
78 | .platform_data = &smc91x_info, | ||
79 | }, | ||
69 | }; | 80 | }; |
70 | #endif | 81 | #endif |
71 | 82 | ||
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c index 1443e92d8b62..7443b26c80c5 100644 --- a/arch/blackfin/mach-bf533/boards/cm_bf533.c +++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c | |||
@@ -31,8 +31,10 @@ | |||
31 | #include <linux/platform_device.h> | 31 | #include <linux/platform_device.h> |
32 | #include <linux/mtd/mtd.h> | 32 | #include <linux/mtd/mtd.h> |
33 | #include <linux/mtd/partitions.h> | 33 | #include <linux/mtd/partitions.h> |
34 | #include <linux/mtd/physmap.h> | ||
34 | #include <linux/spi/spi.h> | 35 | #include <linux/spi/spi.h> |
35 | #include <linux/spi/flash.h> | 36 | #include <linux/spi/flash.h> |
37 | #include <linux/spi/mmc_spi.h> | ||
36 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | 38 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
37 | #include <linux/usb/isp1362.h> | 39 | #include <linux/usb/isp1362.h> |
38 | #endif | 40 | #endif |
@@ -130,7 +132,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
130 | 132 | ||
131 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 133 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) |
132 | { | 134 | { |
133 | .modalias = "ad1836-spi", | 135 | .modalias = "ad1836", |
134 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | 136 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
135 | .bus_num = 0, | 137 | .bus_num = 0, |
136 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 138 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
@@ -141,9 +143,9 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
141 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 143 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
142 | { | 144 | { |
143 | .modalias = "mmc_spi", | 145 | .modalias = "mmc_spi", |
144 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | 146 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ |
145 | .bus_num = 0, | 147 | .bus_num = 0, |
146 | .chip_select = 5, | 148 | .chip_select = 1, |
147 | .controller_data = &mmc_spi_chip_info, | 149 | .controller_data = &mmc_spi_chip_info, |
148 | .mode = SPI_MODE_3, | 150 | .mode = SPI_MODE_3, |
149 | }, | 151 | }, |
@@ -195,6 +197,14 @@ static struct platform_device rtc_device = { | |||
195 | #endif | 197 | #endif |
196 | 198 | ||
197 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 199 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
200 | #include <linux/smc91x.h> | ||
201 | |||
202 | static struct smc91x_platdata smc91x_info = { | ||
203 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
204 | .leda = RPC_LED_100_10, | ||
205 | .ledb = RPC_LED_TX_RX, | ||
206 | }; | ||
207 | |||
198 | static struct resource smc91x_resources[] = { | 208 | static struct resource smc91x_resources[] = { |
199 | { | 209 | { |
200 | .start = 0x20200300, | 210 | .start = 0x20200300, |
@@ -211,6 +221,43 @@ static struct platform_device smc91x_device = { | |||
211 | .id = 0, | 221 | .id = 0, |
212 | .num_resources = ARRAY_SIZE(smc91x_resources), | 222 | .num_resources = ARRAY_SIZE(smc91x_resources), |
213 | .resource = smc91x_resources, | 223 | .resource = smc91x_resources, |
224 | .dev = { | ||
225 | .platform_data = &smc91x_info, | ||
226 | }, | ||
227 | }; | ||
228 | #endif | ||
229 | |||
230 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | ||
231 | #include <linux/smsc911x.h> | ||
232 | |||
233 | static struct resource smsc911x_resources[] = { | ||
234 | { | ||
235 | .name = "smsc911x-memory", | ||
236 | .start = 0x20308000, | ||
237 | .end = 0x20308000 + 0xFF, | ||
238 | .flags = IORESOURCE_MEM, | ||
239 | }, { | ||
240 | .start = IRQ_PF8, | ||
241 | .end = IRQ_PF8, | ||
242 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | ||
243 | }, | ||
244 | }; | ||
245 | |||
246 | static struct smsc911x_platform_config smsc911x_config = { | ||
247 | .flags = SMSC911X_USE_16BIT, | ||
248 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | ||
249 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, | ||
250 | .phy_interface = PHY_INTERFACE_MODE_MII, | ||
251 | }; | ||
252 | |||
253 | static struct platform_device smsc911x_device = { | ||
254 | .name = "smsc911x", | ||
255 | .id = 0, | ||
256 | .num_resources = ARRAY_SIZE(smsc911x_resources), | ||
257 | .resource = smsc911x_resources, | ||
258 | .dev = { | ||
259 | .platform_data = &smsc911x_config, | ||
260 | }, | ||
214 | }; | 261 | }; |
215 | #endif | 262 | #endif |
216 | 263 | ||
@@ -324,6 +371,68 @@ static struct platform_device isp1362_hcd_device = { | |||
324 | }; | 371 | }; |
325 | #endif | 372 | #endif |
326 | 373 | ||
374 | |||
375 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | ||
376 | static struct resource net2272_bfin_resources[] = { | ||
377 | { | ||
378 | .start = 0x20300000, | ||
379 | .end = 0x20300000 + 0x100, | ||
380 | .flags = IORESOURCE_MEM, | ||
381 | }, { | ||
382 | .start = IRQ_PF6, | ||
383 | .end = IRQ_PF6, | ||
384 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
385 | }, | ||
386 | }; | ||
387 | |||
388 | static struct platform_device net2272_bfin_device = { | ||
389 | .name = "net2272", | ||
390 | .id = -1, | ||
391 | .num_resources = ARRAY_SIZE(net2272_bfin_resources), | ||
392 | .resource = net2272_bfin_resources, | ||
393 | }; | ||
394 | #endif | ||
395 | |||
396 | |||
397 | |||
398 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
399 | static struct mtd_partition para_partitions[] = { | ||
400 | { | ||
401 | .name = "bootloader(nor)", | ||
402 | .size = 0x40000, | ||
403 | .offset = 0, | ||
404 | }, { | ||
405 | .name = "linux+rootfs(nor)", | ||
406 | .size = MTDPART_SIZ_FULL, | ||
407 | .offset = MTDPART_OFS_APPEND, | ||
408 | }, | ||
409 | }; | ||
410 | |||
411 | static struct physmap_flash_data para_flash_data = { | ||
412 | .width = 2, | ||
413 | .parts = para_partitions, | ||
414 | .nr_parts = ARRAY_SIZE(para_partitions), | ||
415 | }; | ||
416 | |||
417 | static struct resource para_flash_resource = { | ||
418 | .start = 0x20000000, | ||
419 | .end = 0x201fffff, | ||
420 | .flags = IORESOURCE_MEM, | ||
421 | }; | ||
422 | |||
423 | static struct platform_device para_flash_device = { | ||
424 | .name = "physmap-flash", | ||
425 | .id = 0, | ||
426 | .dev = { | ||
427 | .platform_data = ¶_flash_data, | ||
428 | }, | ||
429 | .num_resources = 1, | ||
430 | .resource = ¶_flash_resource, | ||
431 | }; | ||
432 | #endif | ||
433 | |||
434 | |||
435 | |||
327 | static const unsigned int cclk_vlev_datasheet[] = | 436 | static const unsigned int cclk_vlev_datasheet[] = |
328 | { | 437 | { |
329 | VRPAIR(VLEV_085, 250000000), | 438 | VRPAIR(VLEV_085, 250000000), |
@@ -382,10 +491,22 @@ static struct platform_device *cm_bf533_devices[] __initdata = { | |||
382 | &smc91x_device, | 491 | &smc91x_device, |
383 | #endif | 492 | #endif |
384 | 493 | ||
494 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | ||
495 | &smsc911x_device, | ||
496 | #endif | ||
497 | |||
498 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | ||
499 | &net2272_bfin_device, | ||
500 | #endif | ||
501 | |||
385 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | 502 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
386 | &bfin_spi0_device, | 503 | &bfin_spi0_device, |
387 | #endif | 504 | #endif |
388 | 505 | ||
506 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
507 | ¶_flash_device, | ||
508 | #endif | ||
509 | |||
389 | &bfin_gpios_device, | 510 | &bfin_gpios_device, |
390 | }; | 511 | }; |
391 | 512 | ||
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index 4e3e511bf146..fd518e383b79 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c | |||
@@ -67,6 +67,14 @@ static struct platform_device bfin_fb_adv7393_device = { | |||
67 | * Driver needs to know address, irq and flag pin. | 67 | * Driver needs to know address, irq and flag pin. |
68 | */ | 68 | */ |
69 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 69 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
70 | #include <linux/smc91x.h> | ||
71 | |||
72 | static struct smc91x_platdata smc91x_info = { | ||
73 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
74 | .leda = RPC_LED_100_10, | ||
75 | .ledb = RPC_LED_TX_RX, | ||
76 | }; | ||
77 | |||
70 | static struct resource smc91x_resources[] = { | 78 | static struct resource smc91x_resources[] = { |
71 | { | 79 | { |
72 | .name = "smc91x-regs", | 80 | .name = "smc91x-regs", |
@@ -84,6 +92,9 @@ static struct platform_device smc91x_device = { | |||
84 | .id = 0, | 92 | .id = 0, |
85 | .num_resources = ARRAY_SIZE(smc91x_resources), | 93 | .num_resources = ARRAY_SIZE(smc91x_resources), |
86 | .resource = smc91x_resources, | 94 | .resource = smc91x_resources, |
95 | .dev = { | ||
96 | .platform_data = &smc91x_info, | ||
97 | }, | ||
87 | }; | 98 | }; |
88 | #endif | 99 | #endif |
89 | 100 | ||
@@ -263,7 +274,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
263 | 274 | ||
264 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 275 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) |
265 | { | 276 | { |
266 | .modalias = "ad1836-spi", | 277 | .modalias = "ad1836", |
267 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | 278 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
268 | .bus_num = 0, | 279 | .bus_num = 0, |
269 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 280 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index 3d743ccaff6a..729fd7c26336 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #include <linux/mtd/physmap.h> | 35 | #include <linux/mtd/physmap.h> |
36 | #include <linux/spi/spi.h> | 36 | #include <linux/spi/spi.h> |
37 | #include <linux/spi/flash.h> | 37 | #include <linux/spi/flash.h> |
38 | #include <linux/spi/mmc_spi.h> | ||
38 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | 39 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
39 | #include <linux/usb/isp1362.h> | 40 | #include <linux/usb/isp1362.h> |
40 | #endif | 41 | #endif |
@@ -62,6 +63,14 @@ static struct platform_device rtc_device = { | |||
62 | * Driver needs to know address, irq and flag pin. | 63 | * Driver needs to know address, irq and flag pin. |
63 | */ | 64 | */ |
64 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 65 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
66 | #include <linux/smc91x.h> | ||
67 | |||
68 | static struct smc91x_platdata smc91x_info = { | ||
69 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
70 | .leda = RPC_LED_100_10, | ||
71 | .ledb = RPC_LED_TX_RX, | ||
72 | }; | ||
73 | |||
65 | static struct resource smc91x_resources[] = { | 74 | static struct resource smc91x_resources[] = { |
66 | { | 75 | { |
67 | .name = "smc91x-regs", | 76 | .name = "smc91x-regs", |
@@ -80,6 +89,9 @@ static struct platform_device smc91x_device = { | |||
80 | .id = 0, | 89 | .id = 0, |
81 | .num_resources = ARRAY_SIZE(smc91x_resources), | 90 | .num_resources = ARRAY_SIZE(smc91x_resources), |
82 | .resource = smc91x_resources, | 91 | .resource = smc91x_resources, |
92 | .dev = { | ||
93 | .platform_data = &smc91x_info, | ||
94 | }, | ||
83 | }; | 95 | }; |
84 | #endif | 96 | #endif |
85 | 97 | ||
@@ -207,19 +219,38 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |||
207 | }; | 219 | }; |
208 | #endif | 220 | #endif |
209 | 221 | ||
210 | #if defined(CONFIG_PBX) | 222 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) |
211 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | 223 | static struct bfin5xx_spi_chip spidev_chip_info = { |
212 | .ctl_reg = 0x4, /* send zero */ | 224 | .enable_dma = 0, |
213 | .enable_dma = 0, | 225 | .bits_per_word = 8, |
214 | .bits_per_word = 8, | ||
215 | .cs_change_per_word = 1, | ||
216 | }; | 226 | }; |
217 | #endif | 227 | #endif |
218 | 228 | ||
219 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | 229 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
220 | static struct bfin5xx_spi_chip spidev_chip_info = { | 230 | #define MMC_SPI_CARD_DETECT_INT IRQ_PF5 |
231 | static int bfin_mmc_spi_init(struct device *dev, | ||
232 | irqreturn_t (*detect_int)(int, void *), void *data) | ||
233 | { | ||
234 | return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int, | ||
235 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | ||
236 | "mmc-spi-detect", data); | ||
237 | } | ||
238 | |||
239 | static void bfin_mmc_spi_exit(struct device *dev, void *data) | ||
240 | { | ||
241 | free_irq(MMC_SPI_CARD_DETECT_INT, data); | ||
242 | } | ||
243 | |||
244 | static struct mmc_spi_platform_data bfin_mmc_spi_pdata = { | ||
245 | .init = bfin_mmc_spi_init, | ||
246 | .exit = bfin_mmc_spi_exit, | ||
247 | .detect_delay = 100, /* msecs */ | ||
248 | }; | ||
249 | |||
250 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | ||
221 | .enable_dma = 0, | 251 | .enable_dma = 0, |
222 | .bits_per_word = 8, | 252 | .bits_per_word = 8, |
253 | .pio_interrupt = 0, | ||
223 | }; | 254 | }; |
224 | #endif | 255 | #endif |
225 | 256 | ||
@@ -250,33 +281,14 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
250 | 281 | ||
251 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 282 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) |
252 | { | 283 | { |
253 | .modalias = "ad1836-spi", | 284 | .modalias = "ad1836", |
254 | .max_speed_hz = 31250000, /* max spi clock (SCK) speed in HZ */ | 285 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
255 | .bus_num = 0, | 286 | .bus_num = 0, |
256 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 287 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
257 | .controller_data = &ad1836_spi_chip_info, | 288 | .controller_data = &ad1836_spi_chip_info, |
258 | }, | 289 | }, |
259 | #endif | 290 | #endif |
260 | 291 | ||
261 | #if defined(CONFIG_PBX) | ||
262 | { | ||
263 | .modalias = "fxs-spi", | ||
264 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
265 | .bus_num = 0, | ||
266 | .chip_select = 8 - CONFIG_J11_JUMPER, | ||
267 | .controller_data = &spi_si3xxx_chip_info, | ||
268 | .mode = SPI_MODE_3, | ||
269 | }, | ||
270 | { | ||
271 | .modalias = "fxo-spi", | ||
272 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
273 | .bus_num = 0, | ||
274 | .chip_select = 8 - CONFIG_J19_JUMPER, | ||
275 | .controller_data = &spi_si3xxx_chip_info, | ||
276 | .mode = SPI_MODE_3, | ||
277 | }, | ||
278 | #endif | ||
279 | |||
280 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | 292 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) |
281 | { | 293 | { |
282 | .modalias = "spidev", | 294 | .modalias = "spidev", |
@@ -286,6 +298,17 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
286 | .controller_data = &spidev_chip_info, | 298 | .controller_data = &spidev_chip_info, |
287 | }, | 299 | }, |
288 | #endif | 300 | #endif |
301 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | ||
302 | { | ||
303 | .modalias = "mmc_spi", | ||
304 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | ||
305 | .bus_num = 0, | ||
306 | .chip_select = 4, | ||
307 | .platform_data = &bfin_mmc_spi_pdata, | ||
308 | .controller_data = &mmc_spi_chip_info, | ||
309 | .mode = SPI_MODE_3, | ||
310 | }, | ||
311 | #endif | ||
289 | }; | 312 | }; |
290 | 313 | ||
291 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | 314 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
@@ -458,7 +481,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | |||
458 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 481 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
459 | }, | 482 | }, |
460 | #endif | 483 | #endif |
461 | #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) | 484 | #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE) |
462 | { | 485 | { |
463 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), | 486 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), |
464 | .irq = 39, | 487 | .irq = 39, |
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c index 0a6eb8f24d98..7a443c37fb9f 100644 --- a/arch/blackfin/mach-bf533/dma.c +++ b/arch/blackfin/mach-bf533/dma.c | |||
@@ -76,12 +76,12 @@ int channel2irq(unsigned int channel) | |||
76 | ret_irq = IRQ_SPI; | 76 | ret_irq = IRQ_SPI; |
77 | break; | 77 | break; |
78 | 78 | ||
79 | case CH_UART_RX: | 79 | case CH_UART0_RX: |
80 | ret_irq = IRQ_UART_RX; | 80 | ret_irq = IRQ_UART0_RX; |
81 | break; | 81 | break; |
82 | 82 | ||
83 | case CH_UART_TX: | 83 | case CH_UART0_TX: |
84 | ret_irq = IRQ_UART_TX; | 84 | ret_irq = IRQ_UART0_TX; |
85 | break; | 85 | break; |
86 | 86 | ||
87 | case CH_MEM_STREAM0_SRC: | 87 | case CH_MEM_STREAM0_SRC: |
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h index 4062e24e759b..6965b4088c44 100644 --- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h | |||
@@ -131,11 +131,11 @@ struct bfin_serial_res { | |||
131 | struct bfin_serial_res bfin_serial_resource[] = { | 131 | struct bfin_serial_res bfin_serial_resource[] = { |
132 | { | 132 | { |
133 | 0xFFC00400, | 133 | 0xFFC00400, |
134 | IRQ_UART_RX, | 134 | IRQ_UART0_RX, |
135 | IRQ_UART_ERROR, | 135 | IRQ_UART0_ERROR, |
136 | #ifdef CONFIG_SERIAL_BFIN_DMA | 136 | #ifdef CONFIG_SERIAL_BFIN_DMA |
137 | CH_UART_TX, | 137 | CH_UART0_TX, |
138 | CH_UART_RX, | 138 | CH_UART0_RX, |
139 | #endif | 139 | #endif |
140 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | 140 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
141 | CONFIG_UART0_CTS_PIN, | 141 | CONFIG_UART0_CTS_PIN, |
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h index 39aa175f19f5..499e897a4f4f 100644 --- a/arch/blackfin/mach-bf533/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h | |||
@@ -43,13 +43,6 @@ | |||
43 | 43 | ||
44 | #define BFIN_UART_NR_PORTS 1 | 44 | #define BFIN_UART_NR_PORTS 1 |
45 | 45 | ||
46 | #define CH_UART_RX CH_UART0_RX | ||
47 | #define CH_UART_TX CH_UART0_TX | ||
48 | |||
49 | #define IRQ_UART_ERROR IRQ_UART0_ERROR | ||
50 | #define IRQ_UART_RX IRQ_UART0_RX | ||
51 | #define IRQ_UART_TX IRQ_UART0_TX | ||
52 | |||
53 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | 46 | #define OFFSET_THR 0x00 /* Transmit Holding register */ |
54 | #define OFFSET_RBR 0x00 /* Receive Buffer register */ | 47 | #define OFFSET_RBR 0x00 /* Receive Buffer register */ |
55 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | 48 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ |
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig index 77c59da87e85..44132fda63be 100644 --- a/arch/blackfin/mach-bf537/boards/Kconfig +++ b/arch/blackfin/mach-bf537/boards/Kconfig | |||
@@ -9,11 +9,17 @@ config BFIN537_STAMP | |||
9 | help | 9 | help |
10 | BF537-STAMP board support. | 10 | BF537-STAMP board support. |
11 | 11 | ||
12 | config BFIN537_BLUETECHNIX_CM | 12 | config BFIN537_BLUETECHNIX_CM_E |
13 | bool "Bluetechnix CM-BF537" | 13 | bool "Bluetechnix CM-BF537E" |
14 | depends on (BF537) | 14 | depends on (BF537) |
15 | help | 15 | help |
16 | CM-BF537 support for EVAL- and DEV-Board. | 16 | CM-BF537E support for EVAL- and DEV-Board. |
17 | |||
18 | config BFIN537_BLUETECHNIX_CM_U | ||
19 | bool "Bluetechnix CM-BF537U" | ||
20 | depends on (BF537) | ||
21 | help | ||
22 | CM-BF537U support for EVAL- and DEV-Board. | ||
17 | 23 | ||
18 | config BFIN537_BLUETECHNIX_TCM | 24 | config BFIN537_BLUETECHNIX_TCM |
19 | bool "Bluetechnix TCM-BF537" | 25 | bool "Bluetechnix TCM-BF537" |
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile index 68b98a7af6a6..7e6aa4e5b205 100644 --- a/arch/blackfin/mach-bf537/boards/Makefile +++ b/arch/blackfin/mach-bf537/boards/Makefile | |||
@@ -3,7 +3,8 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | obj-$(CONFIG_BFIN537_STAMP) += stamp.o | 5 | obj-$(CONFIG_BFIN537_STAMP) += stamp.o |
6 | obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o | 6 | obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_E) += cm_bf537e.o |
7 | obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o | ||
7 | obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o | 8 | obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o |
8 | obj-$(CONFIG_PNAV10) += pnav10.o | 9 | obj-$(CONFIG_PNAV10) += pnav10.o |
9 | obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o | 10 | obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o |
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c new file mode 100644 index 000000000000..87acb7dd2df3 --- /dev/null +++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c | |||
@@ -0,0 +1,727 @@ | |||
1 | /* | ||
2 | * File: arch/blackfin/mach-bf537/boards/cm_bf537.c | ||
3 | * Based on: arch/blackfin/mach-bf533/boards/ezkit.c | ||
4 | * Author: Aidan Williams <aidan@nicta.com.au> | ||
5 | * | ||
6 | * Created: 2005 | ||
7 | * Description: Board description file | ||
8 | * | ||
9 | * Modified: | ||
10 | * Copyright 2005 National ICT Australia (NICTA) | ||
11 | * Copyright 2004-2006 Analog Devices Inc. | ||
12 | * | ||
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the GNU General Public License as published by | ||
17 | * the Free Software Foundation; either version 2 of the License, or | ||
18 | * (at your option) any later version. | ||
19 | * | ||
20 | * This program is distributed in the hope that it will be useful, | ||
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
23 | * GNU General Public License for more details. | ||
24 | * | ||
25 | * You should have received a copy of the GNU General Public License | ||
26 | * along with this program; if not, see the file COPYING, or write | ||
27 | * to the Free Software Foundation, Inc., | ||
28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
29 | */ | ||
30 | |||
31 | #include <linux/device.h> | ||
32 | #include <linux/etherdevice.h> | ||
33 | #include <linux/platform_device.h> | ||
34 | #include <linux/mtd/mtd.h> | ||
35 | #include <linux/mtd/partitions.h> | ||
36 | #include <linux/mtd/physmap.h> | ||
37 | #include <linux/spi/spi.h> | ||
38 | #include <linux/spi/flash.h> | ||
39 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | ||
40 | #include <linux/usb/isp1362.h> | ||
41 | #endif | ||
42 | #include <linux/ata_platform.h> | ||
43 | #include <linux/irq.h> | ||
44 | #include <asm/dma.h> | ||
45 | #include <asm/bfin5xx_spi.h> | ||
46 | #include <asm/portmux.h> | ||
47 | #include <asm/dpmc.h> | ||
48 | |||
49 | /* | ||
50 | * Name the Board for the /proc/cpuinfo | ||
51 | */ | ||
52 | const char bfin_board_name[] = "Bluetechnix CM BF537E"; | ||
53 | |||
54 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | ||
55 | /* all SPI peripherals info goes here */ | ||
56 | |||
57 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) | ||
58 | static struct mtd_partition bfin_spi_flash_partitions[] = { | ||
59 | { | ||
60 | .name = "bootloader(spi)", | ||
61 | .size = 0x00020000, | ||
62 | .offset = 0, | ||
63 | .mask_flags = MTD_CAP_ROM | ||
64 | }, { | ||
65 | .name = "linux kernel(spi)", | ||
66 | .size = 0xe0000, | ||
67 | .offset = 0x20000 | ||
68 | }, { | ||
69 | .name = "file system(spi)", | ||
70 | .size = 0x700000, | ||
71 | .offset = 0x00100000, | ||
72 | } | ||
73 | }; | ||
74 | |||
75 | static struct flash_platform_data bfin_spi_flash_data = { | ||
76 | .name = "m25p80", | ||
77 | .parts = bfin_spi_flash_partitions, | ||
78 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | ||
79 | .type = "m25p64", | ||
80 | }; | ||
81 | |||
82 | /* SPI flash chip (m25p64) */ | ||
83 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | ||
84 | .enable_dma = 0, /* use dma transfer with this chip*/ | ||
85 | .bits_per_word = 8, | ||
86 | }; | ||
87 | #endif | ||
88 | |||
89 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) | ||
90 | /* SPI ADC chip */ | ||
91 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | ||
92 | .enable_dma = 1, /* use dma transfer with this chip*/ | ||
93 | .bits_per_word = 16, | ||
94 | }; | ||
95 | #endif | ||
96 | |||
97 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | ||
98 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | ||
99 | .enable_dma = 0, | ||
100 | .bits_per_word = 16, | ||
101 | }; | ||
102 | #endif | ||
103 | |||
104 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | ||
105 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | ||
106 | .enable_dma = 0, | ||
107 | .bits_per_word = 8, | ||
108 | }; | ||
109 | #endif | ||
110 | |||
111 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | ||
112 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) | ||
113 | { | ||
114 | /* the modalias must be the same as spi device driver name */ | ||
115 | .modalias = "m25p80", /* Name of spi_driver for this device */ | ||
116 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
117 | .bus_num = 0, /* Framework bus number */ | ||
118 | .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ | ||
119 | .platform_data = &bfin_spi_flash_data, | ||
120 | .controller_data = &spi_flash_chip_info, | ||
121 | .mode = SPI_MODE_3, | ||
122 | }, | ||
123 | #endif | ||
124 | |||
125 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) | ||
126 | { | ||
127 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | ||
128 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | ||
129 | .bus_num = 0, /* Framework bus number */ | ||
130 | .chip_select = 1, /* Framework chip select. */ | ||
131 | .platform_data = NULL, /* No spi_driver specific config */ | ||
132 | .controller_data = &spi_adc_chip_info, | ||
133 | }, | ||
134 | #endif | ||
135 | |||
136 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | ||
137 | { | ||
138 | .modalias = "ad1836", | ||
139 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | ||
140 | .bus_num = 0, | ||
141 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | ||
142 | .controller_data = &ad1836_spi_chip_info, | ||
143 | }, | ||
144 | #endif | ||
145 | |||
146 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | ||
147 | { | ||
148 | .modalias = "mmc_spi", | ||
149 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | ||
150 | .bus_num = 0, | ||
151 | .chip_select = 1, | ||
152 | .controller_data = &mmc_spi_chip_info, | ||
153 | .mode = SPI_MODE_3, | ||
154 | }, | ||
155 | #endif | ||
156 | }; | ||
157 | |||
158 | /* SPI (0) */ | ||
159 | static struct resource bfin_spi0_resource[] = { | ||
160 | [0] = { | ||
161 | .start = SPI0_REGBASE, | ||
162 | .end = SPI0_REGBASE + 0xFF, | ||
163 | .flags = IORESOURCE_MEM, | ||
164 | }, | ||
165 | [1] = { | ||
166 | .start = CH_SPI, | ||
167 | .end = CH_SPI, | ||
168 | .flags = IORESOURCE_DMA, | ||
169 | }, | ||
170 | [2] = { | ||
171 | .start = IRQ_SPI, | ||
172 | .end = IRQ_SPI, | ||
173 | .flags = IORESOURCE_IRQ, | ||
174 | }, | ||
175 | }; | ||
176 | |||
177 | /* SPI controller data */ | ||
178 | static struct bfin5xx_spi_master bfin_spi0_info = { | ||
179 | .num_chipselect = 8, | ||
180 | .enable_dma = 1, /* master has the ability to do dma transfer */ | ||
181 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, | ||
182 | }; | ||
183 | |||
184 | static struct platform_device bfin_spi0_device = { | ||
185 | .name = "bfin-spi", | ||
186 | .id = 0, /* Bus number */ | ||
187 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | ||
188 | .resource = bfin_spi0_resource, | ||
189 | .dev = { | ||
190 | .platform_data = &bfin_spi0_info, /* Passed to driver */ | ||
191 | }, | ||
192 | }; | ||
193 | #endif /* spi master and devices */ | ||
194 | |||
195 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | ||
196 | static struct platform_device rtc_device = { | ||
197 | .name = "rtc-bfin", | ||
198 | .id = -1, | ||
199 | }; | ||
200 | #endif | ||
201 | |||
202 | #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) | ||
203 | static struct platform_device hitachi_fb_device = { | ||
204 | .name = "hitachi-tx09", | ||
205 | }; | ||
206 | #endif | ||
207 | |||
208 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | ||
209 | #include <linux/smc91x.h> | ||
210 | |||
211 | static struct smc91x_platdata smc91x_info = { | ||
212 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
213 | .leda = RPC_LED_100_10, | ||
214 | .ledb = RPC_LED_TX_RX, | ||
215 | }; | ||
216 | |||
217 | static struct resource smc91x_resources[] = { | ||
218 | { | ||
219 | .start = 0x20200300, | ||
220 | .end = 0x20200300 + 16, | ||
221 | .flags = IORESOURCE_MEM, | ||
222 | }, { | ||
223 | .start = IRQ_PF14, | ||
224 | .end = IRQ_PF14, | ||
225 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
226 | }, | ||
227 | }; | ||
228 | |||
229 | static struct platform_device smc91x_device = { | ||
230 | .name = "smc91x", | ||
231 | .id = 0, | ||
232 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
233 | .resource = smc91x_resources, | ||
234 | .dev = { | ||
235 | .platform_data = &smc91x_info, | ||
236 | }, | ||
237 | }; | ||
238 | #endif | ||
239 | |||
240 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | ||
241 | static struct resource isp1362_hcd_resources[] = { | ||
242 | { | ||
243 | .start = 0x20308000, | ||
244 | .end = 0x20308000, | ||
245 | .flags = IORESOURCE_MEM, | ||
246 | }, { | ||
247 | .start = 0x20308004, | ||
248 | .end = 0x20308004, | ||
249 | .flags = IORESOURCE_MEM, | ||
250 | }, { | ||
251 | .start = IRQ_PG15, | ||
252 | .end = IRQ_PG15, | ||
253 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
254 | }, | ||
255 | }; | ||
256 | |||
257 | static struct isp1362_platform_data isp1362_priv = { | ||
258 | .sel15Kres = 1, | ||
259 | .clknotstop = 0, | ||
260 | .oc_enable = 0, | ||
261 | .int_act_high = 0, | ||
262 | .int_edge_triggered = 0, | ||
263 | .remote_wakeup_connected = 0, | ||
264 | .no_power_switching = 1, | ||
265 | .power_switching_mode = 0, | ||
266 | }; | ||
267 | |||
268 | static struct platform_device isp1362_hcd_device = { | ||
269 | .name = "isp1362-hcd", | ||
270 | .id = 0, | ||
271 | .dev = { | ||
272 | .platform_data = &isp1362_priv, | ||
273 | }, | ||
274 | .num_resources = ARRAY_SIZE(isp1362_hcd_resources), | ||
275 | .resource = isp1362_hcd_resources, | ||
276 | }; | ||
277 | #endif | ||
278 | |||
279 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | ||
280 | static struct resource net2272_bfin_resources[] = { | ||
281 | { | ||
282 | .start = 0x20300000, | ||
283 | .end = 0x20300000 + 0x100, | ||
284 | .flags = IORESOURCE_MEM, | ||
285 | }, { | ||
286 | .start = IRQ_PG13, | ||
287 | .end = IRQ_PG13, | ||
288 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
289 | }, | ||
290 | }; | ||
291 | |||
292 | static struct platform_device net2272_bfin_device = { | ||
293 | .name = "net2272", | ||
294 | .id = -1, | ||
295 | .num_resources = ARRAY_SIZE(net2272_bfin_resources), | ||
296 | .resource = net2272_bfin_resources, | ||
297 | }; | ||
298 | #endif | ||
299 | |||
300 | static struct resource bfin_gpios_resources = { | ||
301 | .start = 0, | ||
302 | .end = MAX_BLACKFIN_GPIOS - 1, | ||
303 | .flags = IORESOURCE_IRQ, | ||
304 | }; | ||
305 | |||
306 | static struct platform_device bfin_gpios_device = { | ||
307 | .name = "simple-gpio", | ||
308 | .id = -1, | ||
309 | .num_resources = 1, | ||
310 | .resource = &bfin_gpios_resources, | ||
311 | }; | ||
312 | |||
313 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) | ||
314 | static struct mtd_partition cm_partitions[] = { | ||
315 | { | ||
316 | .name = "bootloader(nor)", | ||
317 | .size = 0x40000, | ||
318 | .offset = 0, | ||
319 | }, { | ||
320 | .name = "linux kernel(nor)", | ||
321 | .size = 0x100000, | ||
322 | .offset = MTDPART_OFS_APPEND, | ||
323 | }, { | ||
324 | .name = "file system(nor)", | ||
325 | .size = MTDPART_SIZ_FULL, | ||
326 | .offset = MTDPART_OFS_APPEND, | ||
327 | } | ||
328 | }; | ||
329 | |||
330 | static struct physmap_flash_data cm_flash_data = { | ||
331 | .width = 2, | ||
332 | .parts = cm_partitions, | ||
333 | .nr_parts = ARRAY_SIZE(cm_partitions), | ||
334 | }; | ||
335 | |||
336 | static unsigned cm_flash_gpios[] = { GPIO_PF4 }; | ||
337 | |||
338 | static struct resource cm_flash_resource[] = { | ||
339 | { | ||
340 | .name = "cfi_probe", | ||
341 | .start = 0x20000000, | ||
342 | .end = 0x201fffff, | ||
343 | .flags = IORESOURCE_MEM, | ||
344 | }, { | ||
345 | .start = (unsigned long)cm_flash_gpios, | ||
346 | .end = ARRAY_SIZE(cm_flash_gpios), | ||
347 | .flags = IORESOURCE_IRQ, | ||
348 | } | ||
349 | }; | ||
350 | |||
351 | static struct platform_device cm_flash_device = { | ||
352 | .name = "gpio-addr-flash", | ||
353 | .id = 0, | ||
354 | .dev = { | ||
355 | .platform_data = &cm_flash_data, | ||
356 | }, | ||
357 | .num_resources = ARRAY_SIZE(cm_flash_resource), | ||
358 | .resource = cm_flash_resource, | ||
359 | }; | ||
360 | #endif | ||
361 | |||
362 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | ||
363 | #ifdef CONFIG_SERIAL_BFIN_UART0 | ||
364 | static struct resource bfin_uart0_resources[] = { | ||
365 | { | ||
366 | .start = 0xFFC00400, | ||
367 | .end = 0xFFC004FF, | ||
368 | .flags = IORESOURCE_MEM, | ||
369 | }, | ||
370 | { | ||
371 | .start = IRQ_UART0_RX, | ||
372 | .end = IRQ_UART0_RX+1, | ||
373 | .flags = IORESOURCE_IRQ, | ||
374 | }, | ||
375 | { | ||
376 | .start = IRQ_UART0_ERROR, | ||
377 | .end = IRQ_UART0_ERROR, | ||
378 | .flags = IORESOURCE_IRQ, | ||
379 | }, | ||
380 | { | ||
381 | .start = CH_UART0_TX, | ||
382 | .end = CH_UART0_TX, | ||
383 | .flags = IORESOURCE_DMA, | ||
384 | }, | ||
385 | { | ||
386 | .start = CH_UART0_RX, | ||
387 | .end = CH_UART0_RX, | ||
388 | .flags = IORESOURCE_DMA, | ||
389 | }, | ||
390 | #ifdef CONFIG_BFIN_UART0_CTSRTS | ||
391 | { | ||
392 | /* | ||
393 | * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map. | ||
394 | */ | ||
395 | .start = -1, | ||
396 | .end = -1, | ||
397 | .flags = IORESOURCE_IO, | ||
398 | }, | ||
399 | { | ||
400 | /* | ||
401 | * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map. | ||
402 | */ | ||
403 | .start = -1, | ||
404 | .end = -1, | ||
405 | .flags = IORESOURCE_IO, | ||
406 | }, | ||
407 | #endif | ||
408 | }; | ||
409 | |||
410 | static struct platform_device bfin_uart0_device = { | ||
411 | .name = "bfin-uart", | ||
412 | .id = 0, | ||
413 | .num_resources = ARRAY_SIZE(bfin_uart0_resources), | ||
414 | .resource = bfin_uart0_resources, | ||
415 | }; | ||
416 | #endif | ||
417 | #ifdef CONFIG_SERIAL_BFIN_UART1 | ||
418 | static struct resource bfin_uart1_resources[] = { | ||
419 | { | ||
420 | .start = 0xFFC02000, | ||
421 | .end = 0xFFC020FF, | ||
422 | .flags = IORESOURCE_MEM, | ||
423 | }, | ||
424 | { | ||
425 | .start = IRQ_UART1_RX, | ||
426 | .end = IRQ_UART1_RX+1, | ||
427 | .flags = IORESOURCE_IRQ, | ||
428 | }, | ||
429 | { | ||
430 | .start = IRQ_UART1_ERROR, | ||
431 | .end = IRQ_UART1_ERROR, | ||
432 | .flags = IORESOURCE_IRQ, | ||
433 | }, | ||
434 | { | ||
435 | .start = CH_UART1_TX, | ||
436 | .end = CH_UART1_TX, | ||
437 | .flags = IORESOURCE_DMA, | ||
438 | }, | ||
439 | { | ||
440 | .start = CH_UART1_RX, | ||
441 | .end = CH_UART1_RX, | ||
442 | .flags = IORESOURCE_DMA, | ||
443 | }, | ||
444 | #ifdef CONFIG_BFIN_UART1_CTSRTS | ||
445 | { | ||
446 | /* | ||
447 | * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map. | ||
448 | */ | ||
449 | .start = -1, | ||
450 | .end = -1, | ||
451 | .flags = IORESOURCE_IO, | ||
452 | }, | ||
453 | { | ||
454 | /* | ||
455 | * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map. | ||
456 | */ | ||
457 | .start = -1, | ||
458 | .end = -1, | ||
459 | .flags = IORESOURCE_IO, | ||
460 | }, | ||
461 | #endif | ||
462 | }; | ||
463 | |||
464 | static struct platform_device bfin_uart1_device = { | ||
465 | .name = "bfin-uart", | ||
466 | .id = 1, | ||
467 | .num_resources = ARRAY_SIZE(bfin_uart1_resources), | ||
468 | .resource = bfin_uart1_resources, | ||
469 | }; | ||
470 | #endif | ||
471 | #endif | ||
472 | |||
473 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
474 | #ifdef CONFIG_BFIN_SIR0 | ||
475 | static struct resource bfin_sir0_resources[] = { | ||
476 | { | ||
477 | .start = 0xFFC00400, | ||
478 | .end = 0xFFC004FF, | ||
479 | .flags = IORESOURCE_MEM, | ||
480 | }, | ||
481 | { | ||
482 | .start = IRQ_UART0_RX, | ||
483 | .end = IRQ_UART0_RX+1, | ||
484 | .flags = IORESOURCE_IRQ, | ||
485 | }, | ||
486 | { | ||
487 | .start = CH_UART0_RX, | ||
488 | .end = CH_UART0_RX+1, | ||
489 | .flags = IORESOURCE_DMA, | ||
490 | }, | ||
491 | }; | ||
492 | static struct platform_device bfin_sir0_device = { | ||
493 | .name = "bfin_sir", | ||
494 | .id = 0, | ||
495 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
496 | .resource = bfin_sir0_resources, | ||
497 | }; | ||
498 | #endif | ||
499 | #ifdef CONFIG_BFIN_SIR1 | ||
500 | static struct resource bfin_sir1_resources[] = { | ||
501 | { | ||
502 | .start = 0xFFC02000, | ||
503 | .end = 0xFFC020FF, | ||
504 | .flags = IORESOURCE_MEM, | ||
505 | }, | ||
506 | { | ||
507 | .start = IRQ_UART1_RX, | ||
508 | .end = IRQ_UART1_RX+1, | ||
509 | .flags = IORESOURCE_IRQ, | ||
510 | }, | ||
511 | { | ||
512 | .start = CH_UART1_RX, | ||
513 | .end = CH_UART1_RX+1, | ||
514 | .flags = IORESOURCE_DMA, | ||
515 | }, | ||
516 | }; | ||
517 | static struct platform_device bfin_sir1_device = { | ||
518 | .name = "bfin_sir", | ||
519 | .id = 1, | ||
520 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), | ||
521 | .resource = bfin_sir1_resources, | ||
522 | }; | ||
523 | #endif | ||
524 | #endif | ||
525 | |||
526 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | ||
527 | static struct resource bfin_twi0_resource[] = { | ||
528 | [0] = { | ||
529 | .start = TWI0_REGBASE, | ||
530 | .end = TWI0_REGBASE, | ||
531 | .flags = IORESOURCE_MEM, | ||
532 | }, | ||
533 | [1] = { | ||
534 | .start = IRQ_TWI, | ||
535 | .end = IRQ_TWI, | ||
536 | .flags = IORESOURCE_IRQ, | ||
537 | }, | ||
538 | }; | ||
539 | |||
540 | static struct platform_device i2c_bfin_twi_device = { | ||
541 | .name = "i2c-bfin-twi", | ||
542 | .id = 0, | ||
543 | .num_resources = ARRAY_SIZE(bfin_twi0_resource), | ||
544 | .resource = bfin_twi0_resource, | ||
545 | }; | ||
546 | #endif | ||
547 | |||
548 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | ||
549 | static struct platform_device bfin_sport0_uart_device = { | ||
550 | .name = "bfin-sport-uart", | ||
551 | .id = 0, | ||
552 | }; | ||
553 | |||
554 | static struct platform_device bfin_sport1_uart_device = { | ||
555 | .name = "bfin-sport-uart", | ||
556 | .id = 1, | ||
557 | }; | ||
558 | #endif | ||
559 | |||
560 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | ||
561 | static struct platform_device bfin_mii_bus = { | ||
562 | .name = "bfin_mii_bus", | ||
563 | }; | ||
564 | |||
565 | static struct platform_device bfin_mac_device = { | ||
566 | .name = "bfin_mac", | ||
567 | .dev.platform_data = &bfin_mii_bus, | ||
568 | }; | ||
569 | #endif | ||
570 | |||
571 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) | ||
572 | #define PATA_INT IRQ_PF14 | ||
573 | |||
574 | static struct pata_platform_info bfin_pata_platform_data = { | ||
575 | .ioport_shift = 2, | ||
576 | .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED, | ||
577 | }; | ||
578 | |||
579 | static struct resource bfin_pata_resources[] = { | ||
580 | { | ||
581 | .start = 0x2030C000, | ||
582 | .end = 0x2030C01F, | ||
583 | .flags = IORESOURCE_MEM, | ||
584 | }, | ||
585 | { | ||
586 | .start = 0x2030D018, | ||
587 | .end = 0x2030D01B, | ||
588 | .flags = IORESOURCE_MEM, | ||
589 | }, | ||
590 | { | ||
591 | .start = PATA_INT, | ||
592 | .end = PATA_INT, | ||
593 | .flags = IORESOURCE_IRQ, | ||
594 | }, | ||
595 | }; | ||
596 | |||
597 | static struct platform_device bfin_pata_device = { | ||
598 | .name = "pata_platform", | ||
599 | .id = -1, | ||
600 | .num_resources = ARRAY_SIZE(bfin_pata_resources), | ||
601 | .resource = bfin_pata_resources, | ||
602 | .dev = { | ||
603 | .platform_data = &bfin_pata_platform_data, | ||
604 | } | ||
605 | }; | ||
606 | #endif | ||
607 | |||
608 | static const unsigned int cclk_vlev_datasheet[] = | ||
609 | { | ||
610 | VRPAIR(VLEV_085, 250000000), | ||
611 | VRPAIR(VLEV_090, 376000000), | ||
612 | VRPAIR(VLEV_095, 426000000), | ||
613 | VRPAIR(VLEV_100, 426000000), | ||
614 | VRPAIR(VLEV_105, 476000000), | ||
615 | VRPAIR(VLEV_110, 476000000), | ||
616 | VRPAIR(VLEV_115, 476000000), | ||
617 | VRPAIR(VLEV_120, 500000000), | ||
618 | VRPAIR(VLEV_125, 533000000), | ||
619 | VRPAIR(VLEV_130, 600000000), | ||
620 | }; | ||
621 | |||
622 | static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { | ||
623 | .tuple_tab = cclk_vlev_datasheet, | ||
624 | .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), | ||
625 | .vr_settling_time = 25 /* us */, | ||
626 | }; | ||
627 | |||
628 | static struct platform_device bfin_dpmc = { | ||
629 | .name = "bfin dpmc", | ||
630 | .dev = { | ||
631 | .platform_data = &bfin_dmpc_vreg_data, | ||
632 | }, | ||
633 | }; | ||
634 | |||
635 | static struct platform_device *cm_bf537e_devices[] __initdata = { | ||
636 | |||
637 | &bfin_dpmc, | ||
638 | |||
639 | #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) | ||
640 | &hitachi_fb_device, | ||
641 | #endif | ||
642 | |||
643 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | ||
644 | &rtc_device, | ||
645 | #endif | ||
646 | |||
647 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | ||
648 | #ifdef CONFIG_SERIAL_BFIN_UART0 | ||
649 | &bfin_uart0_device, | ||
650 | #endif | ||
651 | #ifdef CONFIG_SERIAL_BFIN_UART1 | ||
652 | &bfin_uart1_device, | ||
653 | #endif | ||
654 | #endif | ||
655 | |||
656 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
657 | #ifdef CONFIG_BFIN_SIR0 | ||
658 | &bfin_sir0_device, | ||
659 | #endif | ||
660 | #ifdef CONFIG_BFIN_SIR1 | ||
661 | &bfin_sir1_device, | ||
662 | #endif | ||
663 | #endif | ||
664 | |||
665 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | ||
666 | &i2c_bfin_twi_device, | ||
667 | #endif | ||
668 | |||
669 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | ||
670 | &bfin_sport0_uart_device, | ||
671 | &bfin_sport1_uart_device, | ||
672 | #endif | ||
673 | |||
674 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | ||
675 | &isp1362_hcd_device, | ||
676 | #endif | ||
677 | |||
678 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | ||
679 | &smc91x_device, | ||
680 | #endif | ||
681 | |||
682 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | ||
683 | &bfin_mii_bus, | ||
684 | &bfin_mac_device, | ||
685 | #endif | ||
686 | |||
687 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | ||
688 | &net2272_bfin_device, | ||
689 | #endif | ||
690 | |||
691 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | ||
692 | &bfin_spi0_device, | ||
693 | #endif | ||
694 | |||
695 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) | ||
696 | &bfin_pata_device, | ||
697 | #endif | ||
698 | |||
699 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) | ||
700 | &cm_flash_device, | ||
701 | #endif | ||
702 | |||
703 | &bfin_gpios_device, | ||
704 | }; | ||
705 | |||
706 | static int __init cm_bf537e_init(void) | ||
707 | { | ||
708 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | ||
709 | platform_add_devices(cm_bf537e_devices, ARRAY_SIZE(cm_bf537e_devices)); | ||
710 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | ||
711 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | ||
712 | #endif | ||
713 | |||
714 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) | ||
715 | irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; | ||
716 | #endif | ||
717 | return 0; | ||
718 | } | ||
719 | |||
720 | arch_initcall(cm_bf537e_init); | ||
721 | |||
722 | void bfin_get_ether_addr(char *addr) | ||
723 | { | ||
724 | random_ether_addr(addr); | ||
725 | printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); | ||
726 | } | ||
727 | EXPORT_SYMBOL(bfin_get_ether_addr); | ||
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c index 2a87d1cfcd06..8219dc3d65bd 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * File: arch/blackfin/mach-bf537/boards/cm_bf537.c | 2 | * File: arch/blackfin/mach-bf537/boards/cm_bf537u.c |
3 | * Based on: arch/blackfin/mach-bf533/boards/ezkit.c | 3 | * Based on: arch/blackfin/mach-bf533/boards/ezkit.c |
4 | * Author: Aidan Williams <aidan@nicta.com.au> | 4 | * Author: Aidan Williams <aidan@nicta.com.au> |
5 | * | 5 | * |
@@ -45,11 +45,12 @@ | |||
45 | #include <asm/bfin5xx_spi.h> | 45 | #include <asm/bfin5xx_spi.h> |
46 | #include <asm/portmux.h> | 46 | #include <asm/portmux.h> |
47 | #include <asm/dpmc.h> | 47 | #include <asm/dpmc.h> |
48 | #include <linux/spi/mmc_spi.h> | ||
48 | 49 | ||
49 | /* | 50 | /* |
50 | * Name the Board for the /proc/cpuinfo | 51 | * Name the Board for the /proc/cpuinfo |
51 | */ | 52 | */ |
52 | const char bfin_board_name[] = "Bluetechnix CM BF537"; | 53 | const char bfin_board_name[] = "Bluetechnix CM BF537U"; |
53 | 54 | ||
54 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | 55 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
55 | /* all SPI peripherals info goes here */ | 56 | /* all SPI peripherals info goes here */ |
@@ -101,13 +102,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |||
101 | }; | 102 | }; |
102 | #endif | 103 | #endif |
103 | 104 | ||
104 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
105 | static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | ||
106 | .enable_dma = 0, | ||
107 | .bits_per_word = 16, | ||
108 | }; | ||
109 | #endif | ||
110 | |||
111 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 105 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
112 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | 106 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
113 | .enable_dma = 0, | 107 | .enable_dma = 0, |
@@ -142,7 +136,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
142 | 136 | ||
143 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 137 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) |
144 | { | 138 | { |
145 | .modalias = "ad1836-spi", | 139 | .modalias = "ad1836", |
146 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | 140 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
147 | .bus_num = 0, | 141 | .bus_num = 0, |
148 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 142 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
@@ -150,16 +144,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
150 | }, | 144 | }, |
151 | #endif | 145 | #endif |
152 | 146 | ||
153 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
154 | { | ||
155 | .modalias = "ad9960-spi", | ||
156 | .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ | ||
157 | .bus_num = 0, | ||
158 | .chip_select = 1, | ||
159 | .controller_data = &ad9960_spi_chip_info, | ||
160 | }, | ||
161 | #endif | ||
162 | |||
163 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 147 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
164 | { | 148 | { |
165 | .modalias = "mmc_spi", | 149 | .modalias = "mmc_spi", |
@@ -223,6 +207,14 @@ static struct platform_device hitachi_fb_device = { | |||
223 | #endif | 207 | #endif |
224 | 208 | ||
225 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 209 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
210 | #include <linux/smc91x.h> | ||
211 | |||
212 | static struct smc91x_platdata smc91x_info = { | ||
213 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
214 | .leda = RPC_LED_100_10, | ||
215 | .ledb = RPC_LED_TX_RX, | ||
216 | }; | ||
217 | |||
226 | static struct resource smc91x_resources[] = { | 218 | static struct resource smc91x_resources[] = { |
227 | { | 219 | { |
228 | .start = 0x20200300, | 220 | .start = 0x20200300, |
@@ -240,6 +232,9 @@ static struct platform_device smc91x_device = { | |||
240 | .id = 0, | 232 | .id = 0, |
241 | .num_resources = ARRAY_SIZE(smc91x_resources), | 233 | .num_resources = ARRAY_SIZE(smc91x_resources), |
242 | .resource = smc91x_resources, | 234 | .resource = smc91x_resources, |
235 | .dev = { | ||
236 | .platform_data = &smc91x_info, | ||
237 | }, | ||
243 | }; | 238 | }; |
244 | #endif | 239 | #endif |
245 | 240 | ||
@@ -324,7 +319,7 @@ static struct mtd_partition cm_partitions[] = { | |||
324 | .offset = 0, | 319 | .offset = 0, |
325 | }, { | 320 | }, { |
326 | .name = "linux kernel(nor)", | 321 | .name = "linux kernel(nor)", |
327 | .size = 0xE0000, | 322 | .size = 0x100000, |
328 | .offset = MTDPART_OFS_APPEND, | 323 | .offset = MTDPART_OFS_APPEND, |
329 | }, { | 324 | }, { |
330 | .name = "file system(nor)", | 325 | .name = "file system(nor)", |
@@ -339,7 +334,7 @@ static struct physmap_flash_data cm_flash_data = { | |||
339 | .nr_parts = ARRAY_SIZE(cm_partitions), | 334 | .nr_parts = ARRAY_SIZE(cm_partitions), |
340 | }; | 335 | }; |
341 | 336 | ||
342 | static unsigned cm_flash_gpios[] = { GPIO_PF4 }; | 337 | static unsigned cm_flash_gpios[] = { GPIO_PH0 }; |
343 | 338 | ||
344 | static struct resource cm_flash_resource[] = { | 339 | static struct resource cm_flash_resource[] = { |
345 | { | 340 | { |
@@ -548,7 +543,7 @@ static struct platform_device bfin_dpmc = { | |||
548 | }, | 543 | }, |
549 | }; | 544 | }; |
550 | 545 | ||
551 | static struct platform_device *cm_bf537_devices[] __initdata = { | 546 | static struct platform_device *cm_bf537u_devices[] __initdata = { |
552 | 547 | ||
553 | &bfin_dpmc, | 548 | &bfin_dpmc, |
554 | 549 | ||
@@ -614,10 +609,10 @@ static struct platform_device *cm_bf537_devices[] __initdata = { | |||
614 | &bfin_gpios_device, | 609 | &bfin_gpios_device, |
615 | }; | 610 | }; |
616 | 611 | ||
617 | static int __init cm_bf537_init(void) | 612 | static int __init cm_bf537u_init(void) |
618 | { | 613 | { |
619 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | 614 | printk(KERN_INFO "%s(): registering device resources\n", __func__); |
620 | platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices)); | 615 | platform_add_devices(cm_bf537u_devices, ARRAY_SIZE(cm_bf537u_devices)); |
621 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | 616 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
622 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | 617 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); |
623 | #endif | 618 | #endif |
@@ -628,7 +623,7 @@ static int __init cm_bf537_init(void) | |||
628 | return 0; | 623 | return 0; |
629 | } | 624 | } |
630 | 625 | ||
631 | arch_initcall(cm_bf537_init); | 626 | arch_initcall(cm_bf537u_init); |
632 | 627 | ||
633 | void bfin_get_ether_addr(char *addr) | 628 | void bfin_get_ether_addr(char *addr) |
634 | { | 629 | { |
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index 838240f151f5..10b35b838bac 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c | |||
@@ -92,6 +92,14 @@ static struct platform_device rtc_device = { | |||
92 | #endif | 92 | #endif |
93 | 93 | ||
94 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 94 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
95 | #include <linux/smc91x.h> | ||
96 | |||
97 | static struct smc91x_platdata smc91x_info = { | ||
98 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
99 | .leda = RPC_LED_100_10, | ||
100 | .ledb = RPC_LED_TX_RX, | ||
101 | }; | ||
102 | |||
95 | static struct resource smc91x_resources[] = { | 103 | static struct resource smc91x_resources[] = { |
96 | { | 104 | { |
97 | .name = "smc91x-regs", | 105 | .name = "smc91x-regs", |
@@ -110,6 +118,9 @@ static struct platform_device smc91x_device = { | |||
110 | .id = 0, | 118 | .id = 0, |
111 | .num_resources = ARRAY_SIZE(smc91x_resources), | 119 | .num_resources = ARRAY_SIZE(smc91x_resources), |
112 | .resource = smc91x_resources, | 120 | .resource = smc91x_resources, |
121 | .dev = { | ||
122 | .platform_data = &smc91x_info, | ||
123 | }, | ||
113 | }; | 124 | }; |
114 | #endif | 125 | #endif |
115 | 126 | ||
@@ -282,13 +293,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |||
282 | }; | 293 | }; |
283 | #endif | 294 | #endif |
284 | 295 | ||
285 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
286 | static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | ||
287 | .enable_dma = 0, | ||
288 | .bits_per_word = 16, | ||
289 | }; | ||
290 | #endif | ||
291 | |||
292 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 296 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
293 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | 297 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
294 | .enable_dma = 0, | 298 | .enable_dma = 0, |
@@ -348,22 +352,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
348 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ | 352 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ |
349 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 353 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) |
350 | { | 354 | { |
351 | .modalias = "ad1836-spi", | 355 | .modalias = "ad1836", |
352 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | 356 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
353 | .bus_num = 0, | 357 | .bus_num = 0, |
354 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 358 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
355 | .controller_data = &ad1836_spi_chip_info, | 359 | .controller_data = &ad1836_spi_chip_info, |
356 | }, | 360 | }, |
357 | #endif | 361 | #endif |
358 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
359 | { | ||
360 | .modalias = "ad9960-spi", | ||
361 | .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ | ||
362 | .bus_num = 0, | ||
363 | .chip_select = 1, | ||
364 | .controller_data = &ad9960_spi_chip_info, | ||
365 | }, | ||
366 | #endif | ||
367 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 362 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
368 | { | 363 | { |
369 | .modalias = "mmc_spi", | 364 | .modalias = "mmc_spi", |
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index bd656907b8c0..9db6b40743e0 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c | |||
@@ -171,6 +171,14 @@ static struct platform_device rtc_device = { | |||
171 | #endif | 171 | #endif |
172 | 172 | ||
173 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 173 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
174 | #include <linux/smc91x.h> | ||
175 | |||
176 | static struct smc91x_platdata smc91x_info = { | ||
177 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
178 | .leda = RPC_LED_100_10, | ||
179 | .ledb = RPC_LED_TX_RX, | ||
180 | }; | ||
181 | |||
174 | static struct resource smc91x_resources[] = { | 182 | static struct resource smc91x_resources[] = { |
175 | { | 183 | { |
176 | .name = "smc91x-regs", | 184 | .name = "smc91x-regs", |
@@ -189,6 +197,9 @@ static struct platform_device smc91x_device = { | |||
189 | .id = 0, | 197 | .id = 0, |
190 | .num_resources = ARRAY_SIZE(smc91x_resources), | 198 | .num_resources = ARRAY_SIZE(smc91x_resources), |
191 | .resource = smc91x_resources, | 199 | .resource = smc91x_resources, |
200 | .dev = { | ||
201 | .platform_data = &smc91x_info, | ||
202 | }, | ||
192 | }; | 203 | }; |
193 | #endif | 204 | #endif |
194 | 205 | ||
@@ -196,10 +207,15 @@ static struct platform_device smc91x_device = { | |||
196 | static struct resource dm9000_resources[] = { | 207 | static struct resource dm9000_resources[] = { |
197 | [0] = { | 208 | [0] = { |
198 | .start = 0x203FB800, | 209 | .start = 0x203FB800, |
199 | .end = 0x203FB800 + 8, | 210 | .end = 0x203FB800 + 1, |
200 | .flags = IORESOURCE_MEM, | 211 | .flags = IORESOURCE_MEM, |
201 | }, | 212 | }, |
202 | [1] = { | 213 | [1] = { |
214 | .start = 0x203FB804, | ||
215 | .end = 0x203FB804 + 1, | ||
216 | .flags = IORESOURCE_MEM, | ||
217 | }, | ||
218 | [2] = { | ||
203 | .start = IRQ_PF9, | 219 | .start = IRQ_PF9, |
204 | .end = IRQ_PF9, | 220 | .end = IRQ_PF9, |
205 | .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), | 221 | .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), |
@@ -516,19 +532,135 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { | |||
516 | }; | 532 | }; |
517 | #endif | 533 | #endif |
518 | 534 | ||
519 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ | 535 | #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \ |
520 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 536 | || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE) |
521 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | 537 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { |
522 | .enable_dma = 0, | 538 | .enable_dma = 0, |
523 | .bits_per_word = 16, | 539 | .bits_per_word = 16, |
524 | }; | 540 | }; |
525 | #endif | 541 | #endif |
526 | 542 | ||
527 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | 543 | #if defined(CONFIG_SND_BF5XX_SOC_AD1938) \ |
528 | static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | 544 | || defined(CONFIG_SND_BF5XX_SOC_AD1938_MODULE) |
545 | static struct bfin5xx_spi_chip ad1938_spi_chip_info = { | ||
546 | .enable_dma = 0, | ||
547 | .bits_per_word = 8, | ||
548 | .cs_gpio = GPIO_PF5, | ||
549 | }; | ||
550 | #endif | ||
551 | |||
552 | #if defined(CONFIG_INPUT_EVAL_AD7147EBZ) | ||
553 | #include <linux/input.h> | ||
554 | #include <linux/input/ad714x.h> | ||
555 | static struct bfin5xx_spi_chip ad7147_spi_chip_info = { | ||
529 | .enable_dma = 0, | 556 | .enable_dma = 0, |
530 | .bits_per_word = 16, | 557 | .bits_per_word = 16, |
531 | }; | 558 | }; |
559 | |||
560 | static struct ad714x_slider_plat slider_plat[] = { | ||
561 | { | ||
562 | .start_stage = 0, | ||
563 | .end_stage = 7, | ||
564 | .max_coord = 128, | ||
565 | }, | ||
566 | }; | ||
567 | |||
568 | static struct ad714x_button_plat button_plat[] = { | ||
569 | { | ||
570 | .keycode = BTN_FORWARD, | ||
571 | .l_mask = 0, | ||
572 | .h_mask = 0x600, | ||
573 | }, | ||
574 | { | ||
575 | .keycode = BTN_LEFT, | ||
576 | .l_mask = 0, | ||
577 | .h_mask = 0x500, | ||
578 | }, | ||
579 | { | ||
580 | .keycode = BTN_MIDDLE, | ||
581 | .l_mask = 0, | ||
582 | .h_mask = 0x800, | ||
583 | }, | ||
584 | { | ||
585 | .keycode = BTN_RIGHT, | ||
586 | .l_mask = 0x100, | ||
587 | .h_mask = 0x400, | ||
588 | }, | ||
589 | { | ||
590 | .keycode = BTN_BACK, | ||
591 | .l_mask = 0x200, | ||
592 | .h_mask = 0x400, | ||
593 | }, | ||
594 | }; | ||
595 | static struct ad714x_platform_data ad7147_platfrom_data = { | ||
596 | .slider_num = 1, | ||
597 | .button_num = 5, | ||
598 | .slider = slider_plat, | ||
599 | .button = button_plat, | ||
600 | .stage_cfg_reg = { | ||
601 | {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600}, | ||
602 | {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650}, | ||
603 | {0xFFFF, 0x1FFE, 0, 0x2626, 1650, 1650, 1650, 1650}, | ||
604 | {0xFFFF, 0x1FFB, 0, 0x2626, 1650, 1650, 1650, 1650}, | ||
605 | {0xFFFF, 0x1FEF, 0, 0x2626, 1650, 1650, 1650, 1650}, | ||
606 | {0xFFFF, 0x1FBF, 0, 0x2626, 1650, 1650, 1650, 1650}, | ||
607 | {0xFFFF, 0x1EFF, 0, 0x2626, 1650, 1650, 1650, 1650}, | ||
608 | {0xFFFF, 0x1BFF, 0, 0x2626, 1600, 1600, 1600, 1600}, | ||
609 | {0xFF7B, 0x3FFF, 0x506, 0x2626, 1100, 1100, 1150, 1150}, | ||
610 | {0xFDFE, 0x3FFF, 0x606, 0x2626, 1100, 1100, 1150, 1150}, | ||
611 | {0xFEBA, 0x1FFF, 0x1400, 0x2626, 1200, 1200, 1300, 1300}, | ||
612 | {0xFFEF, 0x1FFF, 0x0, 0x2626, 1100, 1100, 1150, 1150}, | ||
613 | }, | ||
614 | .sys_cfg_reg = {0x2B2, 0x0, 0x3233, 0x819, 0x832, 0xCFF, 0xCFF, 0x0}, | ||
615 | }; | ||
616 | #endif | ||
617 | |||
618 | #if defined(CONFIG_INPUT_EVAL_AD7142EB) | ||
619 | #include <linux/input.h> | ||
620 | #include <linux/input/ad714x.h> | ||
621 | static struct ad714x_button_plat button_plat[] = { | ||
622 | { | ||
623 | .keycode = BTN_1, | ||
624 | .l_mask = 0, | ||
625 | .h_mask = 0x1, | ||
626 | }, | ||
627 | { | ||
628 | .keycode = BTN_2, | ||
629 | .l_mask = 0, | ||
630 | .h_mask = 0x2, | ||
631 | }, | ||
632 | { | ||
633 | .keycode = BTN_3, | ||
634 | .l_mask = 0, | ||
635 | .h_mask = 0x4, | ||
636 | }, | ||
637 | { | ||
638 | .keycode = BTN_4, | ||
639 | .l_mask = 0x0, | ||
640 | .h_mask = 0x8, | ||
641 | }, | ||
642 | }; | ||
643 | static struct ad714x_platform_data ad7142_platfrom_data = { | ||
644 | .button_num = 4, | ||
645 | .button = button_plat, | ||
646 | .stage_cfg_reg = { | ||
647 | /* fixme: figure out right setting for all comoponent according | ||
648 | * to hardware feature of EVAL-AD7142EB board */ | ||
649 | {0xE7FF, 0x3FFF, 0x0005, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A}, | ||
650 | {0xFDBF, 0x3FFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A}, | ||
651 | {0xFFFF, 0x2DFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A}, | ||
652 | {0xFFFF, 0x37BF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A}, | ||
653 | {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, | ||
654 | {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, | ||
655 | {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, | ||
656 | {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, | ||
657 | {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, | ||
658 | {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, | ||
659 | {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, | ||
660 | {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, | ||
661 | }, | ||
662 | .sys_cfg_reg = {0x0B2, 0x0, 0x690, 0x664, 0x290F, 0xF, 0xF, 0x0}, | ||
663 | }; | ||
532 | #endif | 664 | #endif |
533 | 665 | ||
534 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 666 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
@@ -555,15 +687,7 @@ static struct mmc_spi_platform_data bfin_mmc_spi_pdata = { | |||
555 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | 687 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
556 | .enable_dma = 0, | 688 | .enable_dma = 0, |
557 | .bits_per_word = 8, | 689 | .bits_per_word = 8, |
558 | }; | 690 | .pio_interrupt = 0, |
559 | #endif | ||
560 | |||
561 | #if defined(CONFIG_PBX) | ||
562 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | ||
563 | .ctl_reg = 0x4, /* send zero */ | ||
564 | .enable_dma = 0, | ||
565 | .bits_per_word = 8, | ||
566 | .cs_change_per_word = 1, | ||
567 | }; | 691 | }; |
568 | #endif | 692 | #endif |
569 | 693 | ||
@@ -743,25 +867,42 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
743 | }, | 867 | }, |
744 | #endif | 868 | #endif |
745 | 869 | ||
746 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ | 870 | #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \ |
747 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 871 | || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE) |
748 | { | 872 | { |
749 | .modalias = "ad1836-spi", | 873 | .modalias = "ad1836", |
750 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | 874 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
751 | .bus_num = 0, | 875 | .bus_num = 0, |
752 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 876 | .chip_select = 4,/* CONFIG_SND_BLACKFIN_SPI_PFBIT */ |
753 | .controller_data = &ad1836_spi_chip_info, | 877 | .controller_data = &ad1836_spi_chip_info, |
878 | .mode = SPI_MODE_3, | ||
754 | }, | 879 | }, |
755 | #endif | 880 | #endif |
756 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | 881 | |
882 | #if defined(CONFIG_SND_BF5XX_SOC_AD1938) || defined(CONFIG_SND_BF5XX_SOC_AD1938_MODULE) | ||
757 | { | 883 | { |
758 | .modalias = "ad9960-spi", | 884 | .modalias = "ad1938", |
759 | .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ | 885 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
760 | .bus_num = 0, | 886 | .bus_num = 0, |
761 | .chip_select = 1, | 887 | .chip_select = 0,/* CONFIG_SND_BLACKFIN_SPI_PFBIT */ |
762 | .controller_data = &ad9960_spi_chip_info, | 888 | .controller_data = &ad1938_spi_chip_info, |
889 | .mode = SPI_MODE_3, | ||
763 | }, | 890 | }, |
764 | #endif | 891 | #endif |
892 | |||
893 | #if defined(CONFIG_INPUT_EVAL_AD7147EBZ) | ||
894 | { | ||
895 | .modalias = "ad714x_captouch", | ||
896 | .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ | ||
897 | .irq = IRQ_PF4, | ||
898 | .bus_num = 0, | ||
899 | .chip_select = 5, | ||
900 | .mode = SPI_MODE_3, | ||
901 | .platform_data = &ad7147_platfrom_data, | ||
902 | .controller_data = &ad7147_spi_chip_info, | ||
903 | }, | ||
904 | #endif | ||
905 | |||
765 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 906 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
766 | { | 907 | { |
767 | .modalias = "mmc_spi", | 908 | .modalias = "mmc_spi", |
@@ -773,24 +914,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
773 | .mode = SPI_MODE_3, | 914 | .mode = SPI_MODE_3, |
774 | }, | 915 | }, |
775 | #endif | 916 | #endif |
776 | #if defined(CONFIG_PBX) | ||
777 | { | ||
778 | .modalias = "fxs-spi", | ||
779 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
780 | .bus_num = 0, | ||
781 | .chip_select = 8 - CONFIG_J11_JUMPER, | ||
782 | .controller_data = &spi_si3xxx_chip_info, | ||
783 | .mode = SPI_MODE_3, | ||
784 | }, | ||
785 | { | ||
786 | .modalias = "fxo-spi", | ||
787 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
788 | .bus_num = 0, | ||
789 | .chip_select = 8 - CONFIG_J19_JUMPER, | ||
790 | .controller_data = &spi_si3xxx_chip_info, | ||
791 | .mode = SPI_MODE_3, | ||
792 | }, | ||
793 | #endif | ||
794 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | 917 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
795 | { | 918 | { |
796 | .modalias = "ad7877", | 919 | .modalias = "ad7877", |
@@ -864,6 +987,11 @@ static struct resource bfin_spi0_resource[] = { | |||
864 | [1] = { | 987 | [1] = { |
865 | .start = CH_SPI, | 988 | .start = CH_SPI, |
866 | .end = CH_SPI, | 989 | .end = CH_SPI, |
990 | .flags = IORESOURCE_DMA, | ||
991 | }, | ||
992 | [2] = { | ||
993 | .start = IRQ_SPI, | ||
994 | .end = IRQ_SPI, | ||
867 | .flags = IORESOURCE_IRQ, | 995 | .flags = IORESOURCE_IRQ, |
868 | }, | 996 | }, |
869 | }; | 997 | }; |
@@ -1089,7 +1217,7 @@ static struct platform_device i2c_bfin_twi_device = { | |||
1089 | 1217 | ||
1090 | #if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE) | 1218 | #if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE) |
1091 | #include <linux/input.h> | 1219 | #include <linux/input.h> |
1092 | #include <linux/i2c/adp5588_keys.h> | 1220 | #include <linux/i2c/adp5588.h> |
1093 | static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = { | 1221 | static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = { |
1094 | [0] = KEY_GRAVE, | 1222 | [0] = KEY_GRAVE, |
1095 | [1] = KEY_1, | 1223 | [1] = KEY_1, |
@@ -1309,11 +1437,20 @@ static struct adp5520_platform_data adp5520_pdev_data = { | |||
1309 | 1437 | ||
1310 | #endif | 1438 | #endif |
1311 | 1439 | ||
1440 | #if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE) | ||
1441 | #include <linux/i2c/adp5588.h> | ||
1442 | static struct adp5588_gpio_platfrom_data adp5588_gpio_data = { | ||
1443 | .gpio_start = 50, | ||
1444 | .pullup_dis_mask = 0, | ||
1445 | }; | ||
1446 | #endif | ||
1447 | |||
1312 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | 1448 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { |
1313 | #if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE) | 1449 | #if defined(CONFIG_INPUT_EVAL_AD7142EB) |
1314 | { | 1450 | { |
1315 | I2C_BOARD_INFO("ad7142_joystick", 0x2C), | 1451 | I2C_BOARD_INFO("ad7142_captouch", 0x2C), |
1316 | .irq = IRQ_PG5, | 1452 | .irq = IRQ_PG5, |
1453 | .platform_data = (void *)&ad7142_platfrom_data, | ||
1317 | }, | 1454 | }, |
1318 | #endif | 1455 | #endif |
1319 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) | 1456 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) |
@@ -1321,7 +1458,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | |||
1321 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 1458 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
1322 | }, | 1459 | }, |
1323 | #endif | 1460 | #endif |
1324 | #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) | 1461 | #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE) |
1325 | { | 1462 | { |
1326 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), | 1463 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), |
1327 | .irq = IRQ_PG6, | 1464 | .irq = IRQ_PG6, |
@@ -1355,6 +1492,12 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | |||
1355 | .platform_data = (void *)&adxl34x_info, | 1492 | .platform_data = (void *)&adxl34x_info, |
1356 | }, | 1493 | }, |
1357 | #endif | 1494 | #endif |
1495 | #if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE) | ||
1496 | { | ||
1497 | I2C_BOARD_INFO("adp5588-gpio", 0x34), | ||
1498 | .platform_data = (void *)&adp5588_gpio_data, | ||
1499 | }, | ||
1500 | #endif | ||
1358 | }; | 1501 | }; |
1359 | 1502 | ||
1360 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | 1503 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
@@ -1456,6 +1599,13 @@ static struct platform_device bfin_dpmc = { | |||
1456 | }, | 1599 | }, |
1457 | }; | 1600 | }; |
1458 | 1601 | ||
1602 | #if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) | ||
1603 | static struct platform_device bfin_tdm = { | ||
1604 | .name = "bfin-tdm", | ||
1605 | /* TODO: add platform data here */ | ||
1606 | }; | ||
1607 | #endif | ||
1608 | |||
1459 | static struct platform_device *stamp_devices[] __initdata = { | 1609 | static struct platform_device *stamp_devices[] __initdata = { |
1460 | 1610 | ||
1461 | &bfin_dpmc, | 1611 | &bfin_dpmc, |
@@ -1561,6 +1711,10 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
1561 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | 1711 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
1562 | &stamp_flash_device, | 1712 | &stamp_flash_device, |
1563 | #endif | 1713 | #endif |
1714 | |||
1715 | #if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) | ||
1716 | &bfin_tdm, | ||
1717 | #endif | ||
1564 | }; | 1718 | }; |
1565 | 1719 | ||
1566 | static int __init stamp_init(void) | 1720 | static int __init stamp_init(void) |
@@ -1572,11 +1726,6 @@ static int __init stamp_init(void) | |||
1572 | platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); | 1726 | platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); |
1573 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | 1727 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); |
1574 | 1728 | ||
1575 | #if (defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)) \ | ||
1576 | && defined(PATA_INT) | ||
1577 | irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; | ||
1578 | #endif | ||
1579 | |||
1580 | return 0; | 1729 | return 0; |
1581 | } | 1730 | } |
1582 | 1731 | ||
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c index e523e6e610d0..61353f7bcb9e 100644 --- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c | |||
@@ -45,6 +45,7 @@ | |||
45 | #include <asm/bfin5xx_spi.h> | 45 | #include <asm/bfin5xx_spi.h> |
46 | #include <asm/portmux.h> | 46 | #include <asm/portmux.h> |
47 | #include <asm/dpmc.h> | 47 | #include <asm/dpmc.h> |
48 | #include <linux/spi/mmc_spi.h> | ||
48 | 49 | ||
49 | /* | 50 | /* |
50 | * Name the Board for the /proc/cpuinfo | 51 | * Name the Board for the /proc/cpuinfo |
@@ -101,13 +102,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |||
101 | }; | 102 | }; |
102 | #endif | 103 | #endif |
103 | 104 | ||
104 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
105 | static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | ||
106 | .enable_dma = 0, | ||
107 | .bits_per_word = 16, | ||
108 | }; | ||
109 | #endif | ||
110 | |||
111 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 105 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
112 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | 106 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
113 | .enable_dma = 0, | 107 | .enable_dma = 0, |
@@ -142,7 +136,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
142 | 136 | ||
143 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 137 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) |
144 | { | 138 | { |
145 | .modalias = "ad1836-spi", | 139 | .modalias = "ad1836", |
146 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | 140 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
147 | .bus_num = 0, | 141 | .bus_num = 0, |
148 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 142 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
@@ -150,22 +144,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
150 | }, | 144 | }, |
151 | #endif | 145 | #endif |
152 | 146 | ||
153 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
154 | { | ||
155 | .modalias = "ad9960-spi", | ||
156 | .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ | ||
157 | .bus_num = 0, | ||
158 | .chip_select = 1, | ||
159 | .controller_data = &ad9960_spi_chip_info, | ||
160 | }, | ||
161 | #endif | ||
162 | |||
163 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 147 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
164 | { | 148 | { |
165 | .modalias = "mmc_spi", | 149 | .modalias = "mmc_spi", |
166 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | 150 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ |
167 | .bus_num = 0, | 151 | .bus_num = 0, |
168 | .chip_select = 5, | 152 | .chip_select = 1, |
169 | .controller_data = &mmc_spi_chip_info, | 153 | .controller_data = &mmc_spi_chip_info, |
170 | .mode = SPI_MODE_3, | 154 | .mode = SPI_MODE_3, |
171 | }, | 155 | }, |
@@ -223,6 +207,14 @@ static struct platform_device hitachi_fb_device = { | |||
223 | #endif | 207 | #endif |
224 | 208 | ||
225 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 209 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
210 | #include <linux/smc91x.h> | ||
211 | |||
212 | static struct smc91x_platdata smc91x_info = { | ||
213 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
214 | .leda = RPC_LED_100_10, | ||
215 | .ledb = RPC_LED_TX_RX, | ||
216 | }; | ||
217 | |||
226 | static struct resource smc91x_resources[] = { | 218 | static struct resource smc91x_resources[] = { |
227 | { | 219 | { |
228 | .start = 0x20200300, | 220 | .start = 0x20200300, |
@@ -240,6 +232,9 @@ static struct platform_device smc91x_device = { | |||
240 | .id = 0, | 232 | .id = 0, |
241 | .num_resources = ARRAY_SIZE(smc91x_resources), | 233 | .num_resources = ARRAY_SIZE(smc91x_resources), |
242 | .resource = smc91x_resources, | 234 | .resource = smc91x_resources, |
235 | .dev = { | ||
236 | .platform_data = &smc91x_info, | ||
237 | }, | ||
243 | }; | 238 | }; |
244 | #endif | 239 | #endif |
245 | 240 | ||
@@ -285,12 +280,12 @@ static struct platform_device isp1362_hcd_device = { | |||
285 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | 280 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) |
286 | static struct resource net2272_bfin_resources[] = { | 281 | static struct resource net2272_bfin_resources[] = { |
287 | { | 282 | { |
288 | .start = 0x20200000, | 283 | .start = 0x20300000, |
289 | .end = 0x20200000 + 0x100, | 284 | .end = 0x20300000 + 0x100, |
290 | .flags = IORESOURCE_MEM, | 285 | .flags = IORESOURCE_MEM, |
291 | }, { | 286 | }, { |
292 | .start = IRQ_PH14, | 287 | .start = IRQ_PG13, |
293 | .end = IRQ_PH14, | 288 | .end = IRQ_PG13, |
294 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | 289 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, |
295 | }, | 290 | }, |
296 | }; | 291 | }; |
@@ -324,7 +319,7 @@ static struct mtd_partition cm_partitions[] = { | |||
324 | .offset = 0, | 319 | .offset = 0, |
325 | }, { | 320 | }, { |
326 | .name = "linux kernel(nor)", | 321 | .name = "linux kernel(nor)", |
327 | .size = 0xE0000, | 322 | .size = 0x100000, |
328 | .offset = MTDPART_OFS_APPEND, | 323 | .offset = MTDPART_OFS_APPEND, |
329 | }, { | 324 | }, { |
330 | .name = "file system(nor)", | 325 | .name = "file system(nor)", |
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c index 81185051de91..d23fc0edf2b9 100644 --- a/arch/blackfin/mach-bf537/dma.c +++ b/arch/blackfin/mach-bf537/dma.c | |||
@@ -96,12 +96,12 @@ int channel2irq(unsigned int channel) | |||
96 | ret_irq = IRQ_SPI; | 96 | ret_irq = IRQ_SPI; |
97 | break; | 97 | break; |
98 | 98 | ||
99 | case CH_UART_RX: | 99 | case CH_UART0_RX: |
100 | ret_irq = IRQ_UART_RX; | 100 | ret_irq = IRQ_UART0_RX; |
101 | break; | 101 | break; |
102 | 102 | ||
103 | case CH_UART_TX: | 103 | case CH_UART0_TX: |
104 | ret_irq = IRQ_UART_TX; | 104 | ret_irq = IRQ_UART0_TX; |
105 | break; | 105 | break; |
106 | 106 | ||
107 | case CH_MEM_STREAM0_SRC: | 107 | case CH_MEM_STREAM0_SRC: |
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h index e66aa131f517..f091ad2d8ea8 100644 --- a/arch/blackfin/mach-bf537/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h | |||
@@ -143,7 +143,7 @@ | |||
143 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | 143 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
144 | #define ANOMALY_05000371 (1) | 144 | #define ANOMALY_05000371 (1) |
145 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ | 145 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ |
146 | #define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) | 146 | #define ANOMALY_05000402 (__SILICON_REVISION__ == 2) |
147 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ | 147 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
148 | #define ANOMALY_05000403 (1) | 148 | #define ANOMALY_05000403 (1) |
149 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | 149 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ |
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h index f5e5015ad831..9ee8834c8f1a 100644 --- a/arch/blackfin/mach-bf537/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h | |||
@@ -45,96 +45,11 @@ | |||
45 | #if !defined(__ASSEMBLY__) | 45 | #if !defined(__ASSEMBLY__) |
46 | #include "cdefBF534.h" | 46 | #include "cdefBF534.h" |
47 | 47 | ||
48 | /* UART 0*/ | ||
49 | #define bfin_read_UART_THR() bfin_read_UART0_THR() | ||
50 | #define bfin_write_UART_THR(val) bfin_write_UART0_THR(val) | ||
51 | #define bfin_read_UART_RBR() bfin_read_UART0_RBR() | ||
52 | #define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val) | ||
53 | #define bfin_read_UART_DLL() bfin_read_UART0_DLL() | ||
54 | #define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val) | ||
55 | #define bfin_read_UART_IER() bfin_read_UART0_IER() | ||
56 | #define bfin_write_UART_IER(val) bfin_write_UART0_IER(val) | ||
57 | #define bfin_read_UART_DLH() bfin_read_UART0_DLH() | ||
58 | #define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val) | ||
59 | #define bfin_read_UART_IIR() bfin_read_UART0_IIR() | ||
60 | #define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val) | ||
61 | #define bfin_read_UART_LCR() bfin_read_UART0_LCR() | ||
62 | #define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val) | ||
63 | #define bfin_read_UART_MCR() bfin_read_UART0_MCR() | ||
64 | #define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val) | ||
65 | #define bfin_read_UART_LSR() bfin_read_UART0_LSR() | ||
66 | #define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val) | ||
67 | #define bfin_read_UART_SCR() bfin_read_UART0_SCR() | ||
68 | #define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val) | ||
69 | #define bfin_read_UART_GCTL() bfin_read_UART0_GCTL() | ||
70 | #define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) | ||
71 | |||
72 | #if defined(CONFIG_BF537) || defined(CONFIG_BF536) | 48 | #if defined(CONFIG_BF537) || defined(CONFIG_BF536) |
73 | #include "cdefBF537.h" | 49 | #include "cdefBF537.h" |
74 | #endif | 50 | #endif |
75 | #endif | 51 | #endif |
76 | 52 | ||
77 | /* MAP used DEFINES from BF533 to BF537 - so we don't need to change them in the driver, kernel, etc. */ | ||
78 | |||
79 | /* UART_IIR Register */ | ||
80 | #define STATUS(x) ((x << 1) & 0x06) | ||
81 | #define STATUS_P1 0x02 | ||
82 | #define STATUS_P0 0x01 | ||
83 | |||
84 | /* DMA Channel */ | ||
85 | #define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX() | ||
86 | #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val) | ||
87 | #define CH_UART_RX CH_UART0_RX | ||
88 | #define bfin_read_CH_UART_TX() bfin_read_CH_UART0_TX() | ||
89 | #define bfin_write_CH_UART_TX(val) bfin_write_CH_UART0_TX(val) | ||
90 | #define CH_UART_TX CH_UART0_TX | ||
91 | |||
92 | /* System Interrupt Controller */ | ||
93 | #define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART0_RX() | ||
94 | #define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART0_RX(val) | ||
95 | #define IRQ_UART_RX IRQ_UART0_RX | ||
96 | #define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART0_TX() | ||
97 | #define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART0_TX(val) | ||
98 | #define IRQ_UART_TX IRQ_UART0_TX | ||
99 | #define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART0_ERROR() | ||
100 | #define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART0_ERROR(val) | ||
101 | #define IRQ_UART_ERROR IRQ_UART0_ERROR | ||
102 | |||
103 | /* MMR Registers*/ | ||
104 | #define bfin_read_UART_THR() bfin_read_UART0_THR() | ||
105 | #define bfin_write_UART_THR(val) bfin_write_UART0_THR(val) | ||
106 | #define BFIN_UART_THR UART0_THR | ||
107 | #define bfin_read_UART_RBR() bfin_read_UART0_RBR() | ||
108 | #define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val) | ||
109 | #define BFIN_UART_RBR UART0_RBR | ||
110 | #define bfin_read_UART_DLL() bfin_read_UART0_DLL() | ||
111 | #define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val) | ||
112 | #define BFIN_UART_DLL UART0_DLL | ||
113 | #define bfin_read_UART_IER() bfin_read_UART0_IER() | ||
114 | #define bfin_write_UART_IER(val) bfin_write_UART0_IER(val) | ||
115 | #define BFIN_UART_IER UART0_IER | ||
116 | #define bfin_read_UART_DLH() bfin_read_UART0_DLH() | ||
117 | #define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val) | ||
118 | #define BFIN_UART_DLH UART0_DLH | ||
119 | #define bfin_read_UART_IIR() bfin_read_UART0_IIR() | ||
120 | #define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val) | ||
121 | #define BFIN_UART_IIR UART0_IIR | ||
122 | #define bfin_read_UART_LCR() bfin_read_UART0_LCR() | ||
123 | #define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val) | ||
124 | #define BFIN_UART_LCR UART0_LCR | ||
125 | #define bfin_read_UART_MCR() bfin_read_UART0_MCR() | ||
126 | #define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val) | ||
127 | #define BFIN_UART_MCR UART0_MCR | ||
128 | #define bfin_read_UART_LSR() bfin_read_UART0_LSR() | ||
129 | #define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val) | ||
130 | #define BFIN_UART_LSR UART0_LSR | ||
131 | #define bfin_read_UART_SCR() bfin_read_UART0_SCR() | ||
132 | #define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val) | ||
133 | #define BFIN_UART_SCR UART0_SCR | ||
134 | #define bfin_read_UART_GCTL() bfin_read_UART0_GCTL() | ||
135 | #define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) | ||
136 | #define BFIN_UART_GCTL UART0_GCTL | ||
137 | |||
138 | #define BFIN_UART_NR_PORTS 2 | 53 | #define BFIN_UART_NR_PORTS 2 |
139 | 54 | ||
140 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | 55 | #define OFFSET_THR 0x00 /* Transmit Holding register */ |
@@ -150,11 +65,6 @@ | |||
150 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | 65 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ |
151 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | 66 | #define OFFSET_GCTL 0x24 /* Global Control Register */ |
152 | 67 | ||
153 | /* DPMC*/ | ||
154 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | ||
155 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) | ||
156 | #define STOPCK_OFF STOPCK | ||
157 | |||
158 | /* PLL_DIV Masks */ | 68 | /* PLL_DIV Masks */ |
159 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | 69 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ |
160 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | 70 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ |
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c index 57695b4c3c09..f2ac3b0ebf24 100644 --- a/arch/blackfin/mach-bf538/boards/ezkit.c +++ b/arch/blackfin/mach-bf538/boards/ezkit.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include <linux/device.h> | 31 | #include <linux/device.h> |
32 | #include <linux/platform_device.h> | 32 | #include <linux/platform_device.h> |
33 | #include <linux/mtd/mtd.h> | 33 | #include <linux/mtd/mtd.h> |
34 | #include <linux/mtd/physmap.h> | ||
34 | #include <linux/mtd/partitions.h> | 35 | #include <linux/mtd/partitions.h> |
35 | #include <linux/spi/spi.h> | 36 | #include <linux/spi/spi.h> |
36 | #include <linux/spi/flash.h> | 37 | #include <linux/spi/flash.h> |
@@ -177,6 +178,14 @@ static struct platform_device bfin_sir2_device = { | |||
177 | * Driver needs to know address, irq and flag pin. | 178 | * Driver needs to know address, irq and flag pin. |
178 | */ | 179 | */ |
179 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 180 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
181 | #include <linux/smc91x.h> | ||
182 | |||
183 | static struct smc91x_platdata smc91x_info = { | ||
184 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
185 | .leda = RPC_LED_100_10, | ||
186 | .ledb = RPC_LED_TX_RX, | ||
187 | }; | ||
188 | |||
180 | static struct resource smc91x_resources[] = { | 189 | static struct resource smc91x_resources[] = { |
181 | { | 190 | { |
182 | .name = "smc91x-regs", | 191 | .name = "smc91x-regs", |
@@ -194,6 +203,9 @@ static struct platform_device smc91x_device = { | |||
194 | .id = 0, | 203 | .id = 0, |
195 | .num_resources = ARRAY_SIZE(smc91x_resources), | 204 | .num_resources = ARRAY_SIZE(smc91x_resources), |
196 | .resource = smc91x_resources, | 205 | .resource = smc91x_resources, |
206 | .dev = { | ||
207 | .platform_data = &smc91x_info, | ||
208 | }, | ||
197 | }; | 209 | }; |
198 | #endif | 210 | #endif |
199 | 211 | ||
@@ -390,6 +402,11 @@ static struct resource bfin_spi2_resource[] = { | |||
390 | [1] = { | 402 | [1] = { |
391 | .start = CH_SPI2, | 403 | .start = CH_SPI2, |
392 | .end = CH_SPI2, | 404 | .end = CH_SPI2, |
405 | .flags = IORESOURCE_DMA, | ||
406 | }, | ||
407 | [2] = { | ||
408 | .start = IRQ_SPI2, | ||
409 | .end = IRQ_SPI2, | ||
393 | .flags = IORESOURCE_IRQ, | 410 | .flags = IORESOURCE_IRQ, |
394 | } | 411 | } |
395 | }; | 412 | }; |
@@ -550,6 +567,50 @@ static struct platform_device bfin_dpmc = { | |||
550 | }, | 567 | }, |
551 | }; | 568 | }; |
552 | 569 | ||
570 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
571 | static struct mtd_partition ezkit_partitions[] = { | ||
572 | { | ||
573 | .name = "bootloader(nor)", | ||
574 | .size = 0x40000, | ||
575 | .offset = 0, | ||
576 | }, { | ||
577 | .name = "linux kernel(nor)", | ||
578 | .size = 0x180000, | ||
579 | .offset = MTDPART_OFS_APPEND, | ||
580 | }, { | ||
581 | .name = "file system(nor)", | ||
582 | .size = MTDPART_SIZ_FULL, | ||
583 | .offset = MTDPART_OFS_APPEND, | ||
584 | } | ||
585 | }; | ||
586 | |||
587 | static struct physmap_flash_data ezkit_flash_data = { | ||
588 | .width = 2, | ||
589 | .parts = ezkit_partitions, | ||
590 | .nr_parts = ARRAY_SIZE(ezkit_partitions), | ||
591 | }; | ||
592 | |||
593 | static struct resource ezkit_flash_resource = { | ||
594 | .start = 0x20000000, | ||
595 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | ||
596 | .end = 0x202fffff, | ||
597 | #else | ||
598 | .end = 0x203fffff, | ||
599 | #endif | ||
600 | .flags = IORESOURCE_MEM, | ||
601 | }; | ||
602 | |||
603 | static struct platform_device ezkit_flash_device = { | ||
604 | .name = "physmap-flash", | ||
605 | .id = 0, | ||
606 | .dev = { | ||
607 | .platform_data = &ezkit_flash_data, | ||
608 | }, | ||
609 | .num_resources = 1, | ||
610 | .resource = &ezkit_flash_resource, | ||
611 | }; | ||
612 | #endif | ||
613 | |||
553 | static struct platform_device *cm_bf538_devices[] __initdata = { | 614 | static struct platform_device *cm_bf538_devices[] __initdata = { |
554 | 615 | ||
555 | &bfin_dpmc, | 616 | &bfin_dpmc, |
@@ -598,6 +659,10 @@ static struct platform_device *cm_bf538_devices[] __initdata = { | |||
598 | #endif | 659 | #endif |
599 | 660 | ||
600 | &bfin_gpios_device, | 661 | &bfin_gpios_device, |
662 | |||
663 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
664 | &ezkit_flash_device, | ||
665 | #endif | ||
601 | }; | 666 | }; |
602 | 667 | ||
603 | static int __init ezkit_init(void) | 668 | static int __init ezkit_init(void) |
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h index 451cf8a82a42..26b76083e14c 100644 --- a/arch/blackfin/mach-bf538/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h | |||
@@ -113,7 +113,7 @@ | |||
113 | /* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */ | 113 | /* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */ |
114 | #define ANOMALY_05000375 (__SILICON_REVISION__ < 4) | 114 | #define ANOMALY_05000375 (__SILICON_REVISION__ < 4) |
115 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ | 115 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ |
116 | #define ANOMALY_05000402 (__SILICON_REVISION__ < 4) | 116 | #define ANOMALY_05000402 (__SILICON_REVISION__ == 3) |
117 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ | 117 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
118 | #define ANOMALY_05000403 (1) | 118 | #define ANOMALY_05000403 (1) |
119 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | 119 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ |
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h index 9496196ac164..5ecee1690957 100644 --- a/arch/blackfin/mach-bf538/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h | |||
@@ -47,11 +47,6 @@ | |||
47 | #endif | 47 | #endif |
48 | #endif | 48 | #endif |
49 | 49 | ||
50 | /* UART_IIR Register */ | ||
51 | #define STATUS(x) ((x << 1) & 0x06) | ||
52 | #define STATUS_P1 0x02 | ||
53 | #define STATUS_P0 0x01 | ||
54 | |||
55 | #define BFIN_UART_NR_PORTS 3 | 50 | #define BFIN_UART_NR_PORTS 3 |
56 | 51 | ||
57 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | 52 | #define OFFSET_THR 0x00 /* Transmit Holding register */ |
@@ -67,11 +62,6 @@ | |||
67 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | 62 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ |
68 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | 63 | #define OFFSET_GCTL 0x24 /* Global Control Register */ |
69 | 64 | ||
70 | /* DPMC*/ | ||
71 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | ||
72 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) | ||
73 | #define STOPCK_OFF STOPCK | ||
74 | |||
75 | /* PLL_DIV Masks */ | 65 | /* PLL_DIV Masks */ |
76 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | 66 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ |
77 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | 67 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ |
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h index 99ca3f4305e2..1de67515dc9d 100644 --- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h +++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h | |||
@@ -1310,6 +1310,7 @@ | |||
1310 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) | 1310 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) |
1311 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) | 1311 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) |
1312 | #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) | 1312 | #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) |
1313 | #define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS() | ||
1313 | #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) | 1314 | #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) |
1314 | #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) | 1315 | #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) |
1315 | #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) | 1316 | #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) |
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c index f5a3c30a41bd..e565aae11d72 100644 --- a/arch/blackfin/mach-bf548/boards/cm_bf548.c +++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c | |||
@@ -291,6 +291,8 @@ static struct platform_device bfin_sir3_device = { | |||
291 | #endif | 291 | #endif |
292 | 292 | ||
293 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | 293 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) |
294 | #include <linux/smsc911x.h> | ||
295 | |||
294 | static struct resource smsc911x_resources[] = { | 296 | static struct resource smsc911x_resources[] = { |
295 | { | 297 | { |
296 | .name = "smsc911x-memory", | 298 | .name = "smsc911x-memory", |
@@ -304,11 +306,22 @@ static struct resource smsc911x_resources[] = { | |||
304 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | 306 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, |
305 | }, | 307 | }, |
306 | }; | 308 | }; |
309 | |||
310 | static struct smsc911x_platform_config smsc911x_config = { | ||
311 | .flags = SMSC911X_USE_16BIT, | ||
312 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | ||
313 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, | ||
314 | .phy_interface = PHY_INTERFACE_MODE_MII, | ||
315 | }; | ||
316 | |||
307 | static struct platform_device smsc911x_device = { | 317 | static struct platform_device smsc911x_device = { |
308 | .name = "smsc911x", | 318 | .name = "smsc911x", |
309 | .id = 0, | 319 | .id = 0, |
310 | .num_resources = ARRAY_SIZE(smsc911x_resources), | 320 | .num_resources = ARRAY_SIZE(smsc911x_resources), |
311 | .resource = smsc911x_resources, | 321 | .resource = smsc911x_resources, |
322 | .dev = { | ||
323 | .platform_data = &smsc911x_config, | ||
324 | }, | ||
312 | }; | 325 | }; |
313 | #endif | 326 | #endif |
314 | 327 | ||
@@ -473,7 +486,7 @@ static struct mtd_partition para_partitions[] = { | |||
473 | .offset = 0, | 486 | .offset = 0, |
474 | }, { | 487 | }, { |
475 | .name = "linux kernel(nor)", | 488 | .name = "linux kernel(nor)", |
476 | .size = 0x400000, | 489 | .size = 0x100000, |
477 | .offset = MTDPART_OFS_APPEND, | 490 | .offset = MTDPART_OFS_APPEND, |
478 | }, { | 491 | }, { |
479 | .name = "file system(nor)", | 492 | .name = "file system(nor)", |
@@ -642,7 +655,7 @@ static struct resource bfin_spi1_resource[] = { | |||
642 | 655 | ||
643 | /* SPI controller data */ | 656 | /* SPI controller data */ |
644 | static struct bfin5xx_spi_master bf54x_spi_master_info0 = { | 657 | static struct bfin5xx_spi_master bf54x_spi_master_info0 = { |
645 | .num_chipselect = 8, | 658 | .num_chipselect = 3, |
646 | .enable_dma = 1, /* master has the ability to do dma transfer */ | 659 | .enable_dma = 1, /* master has the ability to do dma transfer */ |
647 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, | 660 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, |
648 | }; | 661 | }; |
@@ -658,7 +671,7 @@ static struct platform_device bf54x_spi_master0 = { | |||
658 | }; | 671 | }; |
659 | 672 | ||
660 | static struct bfin5xx_spi_master bf54x_spi_master_info1 = { | 673 | static struct bfin5xx_spi_master bf54x_spi_master_info1 = { |
661 | .num_chipselect = 8, | 674 | .num_chipselect = 3, |
662 | .enable_dma = 1, /* master has the ability to do dma transfer */ | 675 | .enable_dma = 1, /* master has the ability to do dma transfer */ |
663 | .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, | 676 | .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, |
664 | }; | 677 | }; |
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index dc0dd9b2bcef..c66f3801274f 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c | |||
@@ -99,8 +99,8 @@ static struct platform_device bfin_isp1760_device = { | |||
99 | #include <mach/bf54x-lq043.h> | 99 | #include <mach/bf54x-lq043.h> |
100 | 100 | ||
101 | static struct bfin_bf54xfb_mach_info bf54x_lq043_data = { | 101 | static struct bfin_bf54xfb_mach_info bf54x_lq043_data = { |
102 | .width = 480, | 102 | .width = 95, |
103 | .height = 272, | 103 | .height = 54, |
104 | .xres = {480, 480, 480}, | 104 | .xres = {480, 480, 480}, |
105 | .yres = {272, 272, 272}, | 105 | .yres = {272, 272, 272}, |
106 | .bpp = {24, 24, 24}, | 106 | .bpp = {24, 24, 24}, |
@@ -702,7 +702,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
702 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ | 702 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ |
703 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 703 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) |
704 | { | 704 | { |
705 | .modalias = "ad1836-spi", | 705 | .modalias = "ad1836", |
706 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | 706 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
707 | .bus_num = 1, | 707 | .bus_num = 1, |
708 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 708 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
@@ -783,7 +783,7 @@ static struct resource bfin_spi1_resource[] = { | |||
783 | 783 | ||
784 | /* SPI controller data */ | 784 | /* SPI controller data */ |
785 | static struct bfin5xx_spi_master bf54x_spi_master_info0 = { | 785 | static struct bfin5xx_spi_master bf54x_spi_master_info0 = { |
786 | .num_chipselect = 8, | 786 | .num_chipselect = 3, |
787 | .enable_dma = 1, /* master has the ability to do dma transfer */ | 787 | .enable_dma = 1, /* master has the ability to do dma transfer */ |
788 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, | 788 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, |
789 | }; | 789 | }; |
@@ -799,7 +799,7 @@ static struct platform_device bf54x_spi_master0 = { | |||
799 | }; | 799 | }; |
800 | 800 | ||
801 | static struct bfin5xx_spi_master bf54x_spi_master_info1 = { | 801 | static struct bfin5xx_spi_master bf54x_spi_master_info1 = { |
802 | .num_chipselect = 8, | 802 | .num_chipselect = 3, |
803 | .enable_dma = 1, /* master has the ability to do dma transfer */ | 803 | .enable_dma = 1, /* master has the ability to do dma transfer */ |
804 | .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, | 804 | .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, |
805 | }; | 805 | }; |
@@ -869,7 +869,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { | |||
869 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | 869 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), |
870 | }, | 870 | }, |
871 | #endif | 871 | #endif |
872 | #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) | 872 | #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE) |
873 | { | 873 | { |
874 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), | 874 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), |
875 | .irq = 212, | 875 | .irq = 212, |
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c index 535980652bf6..d9239bc05dd4 100644 --- a/arch/blackfin/mach-bf548/dma.c +++ b/arch/blackfin/mach-bf548/dma.c | |||
@@ -91,16 +91,16 @@ int channel2irq(unsigned int channel) | |||
91 | ret_irq = IRQ_SPI1; | 91 | ret_irq = IRQ_SPI1; |
92 | break; | 92 | break; |
93 | case CH_UART0_RX: | 93 | case CH_UART0_RX: |
94 | ret_irq = IRQ_UART_RX; | 94 | ret_irq = IRQ_UART0_RX; |
95 | break; | 95 | break; |
96 | case CH_UART0_TX: | 96 | case CH_UART0_TX: |
97 | ret_irq = IRQ_UART_TX; | 97 | ret_irq = IRQ_UART0_TX; |
98 | break; | 98 | break; |
99 | case CH_UART1_RX: | 99 | case CH_UART1_RX: |
100 | ret_irq = IRQ_UART_RX; | 100 | ret_irq = IRQ_UART1_RX; |
101 | break; | 101 | break; |
102 | case CH_UART1_TX: | 102 | case CH_UART1_TX: |
103 | ret_irq = IRQ_UART_TX; | 103 | ret_irq = IRQ_UART1_TX; |
104 | break; | 104 | break; |
105 | case CH_EPPI0: | 105 | case CH_EPPI0: |
106 | ret_irq = IRQ_EPPI0; | 106 | ret_irq = IRQ_EPPI0; |
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index cd040fe0bc5c..52b116ae522a 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h | |||
@@ -7,7 +7,7 @@ | |||
7 | */ | 7 | */ |
8 | 8 | ||
9 | /* This file should be up to date with: | 9 | /* This file should be up to date with: |
10 | * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List | 10 | * - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List |
11 | */ | 11 | */ |
12 | 12 | ||
13 | #ifndef _MACH_ANOMALY_H_ | 13 | #ifndef _MACH_ANOMALY_H_ |
@@ -162,6 +162,8 @@ | |||
162 | #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) | 162 | #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) |
163 | /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ | 163 | /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ |
164 | #define ANOMALY_05000431 (__SILICON_REVISION__ < 3) | 164 | #define ANOMALY_05000431 (__SILICON_REVISION__ < 3) |
165 | /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ | ||
166 | #define ANOMALY_05000434 (1) | ||
165 | /* OTP Write Accesses Not Supported */ | 167 | /* OTP Write Accesses Not Supported */ |
166 | #define ANOMALY_05000442 (__SILICON_REVISION__ < 1) | 168 | #define ANOMALY_05000442 (__SILICON_REVISION__ < 1) |
167 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | 169 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
@@ -176,12 +178,26 @@ | |||
176 | #define ANOMALY_05000449 (__SILICON_REVISION__ == 1) | 178 | #define ANOMALY_05000449 (__SILICON_REVISION__ == 1) |
177 | /* USB DMA Mode 1 Short Packet Data Corruption */ | 179 | /* USB DMA Mode 1 Short Packet Data Corruption */ |
178 | #define ANOMALY_05000450 (1) | 180 | #define ANOMALY_05000450 (1) |
181 | /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ | ||
182 | #define ANOMALY_05000452 (__SILICON_REVISION__ < 1) | ||
179 | /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ | 183 | /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ |
180 | #define ANOMALY_05000456 (__SILICON_REVISION__ < 3) | 184 | #define ANOMALY_05000456 (1) |
185 | /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ | ||
186 | #define ANOMALY_05000457 (1) | ||
187 | /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ | ||
188 | #define ANOMALY_05000460 (1) | ||
181 | /* False Hardware Error when RETI Points to Invalid Memory */ | 189 | /* False Hardware Error when RETI Points to Invalid Memory */ |
182 | #define ANOMALY_05000461 (1) | 190 | #define ANOMALY_05000461 (1) |
191 | /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ | ||
192 | #define ANOMALY_05000462 (1) | ||
193 | /* USB DMA RX Data Corruption */ | ||
194 | #define ANOMALY_05000463 (1) | ||
195 | /* USB TX DMA Hang */ | ||
196 | #define ANOMALY_05000464 (1) | ||
183 | /* USB Rx DMA hang */ | 197 | /* USB Rx DMA hang */ |
184 | #define ANOMALY_05000465 (1) | 198 | #define ANOMALY_05000465 (1) |
199 | /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ | ||
200 | #define ANOMALY_05000466 (1) | ||
185 | /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ | 201 | /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ |
186 | #define ANOMALY_05000467 (1) | 202 | #define ANOMALY_05000467 (1) |
187 | 203 | ||
@@ -230,6 +246,7 @@ | |||
230 | #define ANOMALY_05000364 (0) | 246 | #define ANOMALY_05000364 (0) |
231 | #define ANOMALY_05000380 (0) | 247 | #define ANOMALY_05000380 (0) |
232 | #define ANOMALY_05000400 (0) | 248 | #define ANOMALY_05000400 (0) |
249 | #define ANOMALY_05000402 (0) | ||
233 | #define ANOMALY_05000412 (0) | 250 | #define ANOMALY_05000412 (0) |
234 | #define ANOMALY_05000432 (0) | 251 | #define ANOMALY_05000432 (0) |
235 | #define ANOMALY_05000435 (0) | 252 | #define ANOMALY_05000435 (0) |
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h index 6b97396d817f..318667b2f036 100644 --- a/arch/blackfin/mach-bf548/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h | |||
@@ -72,97 +72,8 @@ | |||
72 | #include "cdefBF549.h" | 72 | #include "cdefBF549.h" |
73 | #endif | 73 | #endif |
74 | 74 | ||
75 | /* UART 1*/ | ||
76 | #define bfin_read_UART_THR() bfin_read_UART1_THR() | ||
77 | #define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) | ||
78 | #define bfin_read_UART_RBR() bfin_read_UART1_RBR() | ||
79 | #define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) | ||
80 | #define bfin_read_UART_DLL() bfin_read_UART1_DLL() | ||
81 | #define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) | ||
82 | #define bfin_read_UART_IER() bfin_read_UART1_IER() | ||
83 | #define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) | ||
84 | #define bfin_read_UART_DLH() bfin_read_UART1_DLH() | ||
85 | #define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) | ||
86 | #define bfin_read_UART_IIR() bfin_read_UART1_IIR() | ||
87 | #define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) | ||
88 | #define bfin_read_UART_LCR() bfin_read_UART1_LCR() | ||
89 | #define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) | ||
90 | #define bfin_read_UART_MCR() bfin_read_UART1_MCR() | ||
91 | #define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) | ||
92 | #define bfin_read_UART_LSR() bfin_read_UART1_LSR() | ||
93 | #define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) | ||
94 | #define bfin_read_UART_SCR() bfin_read_UART1_SCR() | ||
95 | #define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) | ||
96 | #define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() | ||
97 | #define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) | ||
98 | |||
99 | #endif | 75 | #endif |
100 | 76 | ||
101 | /* MAP used DEFINES from BF533 to BF54x - so we don't need to change | ||
102 | * them in the driver, kernel, etc. */ | ||
103 | |||
104 | /* UART_IIR Register */ | ||
105 | #define STATUS(x) ((x << 1) & 0x06) | ||
106 | #define STATUS_P1 0x02 | ||
107 | #define STATUS_P0 0x01 | ||
108 | |||
109 | /* UART 0*/ | ||
110 | |||
111 | /* DMA Channel */ | ||
112 | #define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX() | ||
113 | #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val) | ||
114 | #define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX() | ||
115 | #define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val) | ||
116 | #define CH_UART_RX CH_UART1_RX | ||
117 | #define CH_UART_TX CH_UART1_TX | ||
118 | |||
119 | /* System Interrupt Controller */ | ||
120 | #define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX() | ||
121 | #define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val) | ||
122 | #define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX() | ||
123 | #define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val) | ||
124 | #define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR() | ||
125 | #define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val) | ||
126 | #define IRQ_UART_RX IRQ_UART1_RX | ||
127 | #define IRQ_UART_TX IRQ_UART1_TX | ||
128 | #define IRQ_UART_ERROR IRQ_UART1_ERROR | ||
129 | |||
130 | /* MMR Registers*/ | ||
131 | #define bfin_read_UART_THR() bfin_read_UART1_THR() | ||
132 | #define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) | ||
133 | #define bfin_read_UART_RBR() bfin_read_UART1_RBR() | ||
134 | #define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) | ||
135 | #define bfin_read_UART_DLL() bfin_read_UART1_DLL() | ||
136 | #define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) | ||
137 | #define bfin_read_UART_IER() bfin_read_UART1_IER() | ||
138 | #define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) | ||
139 | #define bfin_read_UART_DLH() bfin_read_UART1_DLH() | ||
140 | #define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) | ||
141 | #define bfin_read_UART_IIR() bfin_read_UART1_IIR() | ||
142 | #define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) | ||
143 | #define bfin_read_UART_LCR() bfin_read_UART1_LCR() | ||
144 | #define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) | ||
145 | #define bfin_read_UART_MCR() bfin_read_UART1_MCR() | ||
146 | #define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) | ||
147 | #define bfin_read_UART_LSR() bfin_read_UART1_LSR() | ||
148 | #define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) | ||
149 | #define bfin_read_UART_SCR() bfin_read_UART1_SCR() | ||
150 | #define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) | ||
151 | #define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() | ||
152 | #define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) | ||
153 | |||
154 | #define BFIN_UART_THR UART1_THR | ||
155 | #define BFIN_UART_RBR UART1_RBR | ||
156 | #define BFIN_UART_DLL UART1_DLL | ||
157 | #define BFIN_UART_IER UART1_IER | ||
158 | #define BFIN_UART_DLH UART1_DLH | ||
159 | #define BFIN_UART_IIR UART1_IIR | ||
160 | #define BFIN_UART_LCR UART1_LCR | ||
161 | #define BFIN_UART_MCR UART1_MCR | ||
162 | #define BFIN_UART_LSR UART1_LSR | ||
163 | #define BFIN_UART_SCR UART1_SCR | ||
164 | #define BFIN_UART_GCTL UART1_GCTL | ||
165 | |||
166 | #define BFIN_UART_NR_PORTS 4 | 77 | #define BFIN_UART_NR_PORTS 4 |
167 | 78 | ||
168 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | 79 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ |
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index 0c9d72c5f5ba..6577ecfcf11e 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c | |||
@@ -42,6 +42,7 @@ | |||
42 | #include <asm/bfin5xx_spi.h> | 42 | #include <asm/bfin5xx_spi.h> |
43 | #include <asm/portmux.h> | 43 | #include <asm/portmux.h> |
44 | #include <asm/dpmc.h> | 44 | #include <asm/dpmc.h> |
45 | #include <linux/mtd/physmap.h> | ||
45 | 46 | ||
46 | /* | 47 | /* |
47 | * Name the Board for the /proc/cpuinfo | 48 | * Name the Board for the /proc/cpuinfo |
@@ -98,13 +99,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |||
98 | }; | 99 | }; |
99 | #endif | 100 | #endif |
100 | 101 | ||
101 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
102 | static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | ||
103 | .enable_dma = 0, | ||
104 | .bits_per_word = 16, | ||
105 | }; | ||
106 | #endif | ||
107 | |||
108 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 102 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
109 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | 103 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
110 | .enable_dma = 0, | 104 | .enable_dma = 0, |
@@ -139,28 +133,19 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
139 | 133 | ||
140 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 134 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) |
141 | { | 135 | { |
142 | .modalias = "ad1836-spi", | 136 | .modalias = "ad1836", |
143 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | 137 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
144 | .bus_num = 0, | 138 | .bus_num = 0, |
145 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 139 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
146 | .controller_data = &ad1836_spi_chip_info, | 140 | .controller_data = &ad1836_spi_chip_info, |
147 | }, | 141 | }, |
148 | #endif | 142 | #endif |
149 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
150 | { | ||
151 | .modalias = "ad9960-spi", | ||
152 | .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ | ||
153 | .bus_num = 0, | ||
154 | .chip_select = 1, | ||
155 | .controller_data = &ad9960_spi_chip_info, | ||
156 | }, | ||
157 | #endif | ||
158 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | 143 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
159 | { | 144 | { |
160 | .modalias = "mmc_spi", | 145 | .modalias = "mmc_spi", |
161 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | 146 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ |
162 | .bus_num = 0, | 147 | .bus_num = 0, |
163 | .chip_select = 5, | 148 | .chip_select = 1, |
164 | .controller_data = &mmc_spi_chip_info, | 149 | .controller_data = &mmc_spi_chip_info, |
165 | .mode = SPI_MODE_3, | 150 | .mode = SPI_MODE_3, |
166 | }, | 151 | }, |
@@ -213,6 +198,13 @@ static struct platform_device hitachi_fb_device = { | |||
213 | 198 | ||
214 | 199 | ||
215 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 200 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
201 | #include <linux/smc91x.h> | ||
202 | |||
203 | static struct smc91x_platdata smc91x_info = { | ||
204 | .flags = SMC91X_USE_32BIT | SMC91X_NOWAIT, | ||
205 | .leda = RPC_LED_100_10, | ||
206 | .ledb = RPC_LED_TX_RX, | ||
207 | }; | ||
216 | 208 | ||
217 | static struct resource smc91x_resources[] = { | 209 | static struct resource smc91x_resources[] = { |
218 | { | 210 | { |
@@ -231,6 +223,65 @@ static struct platform_device smc91x_device = { | |||
231 | .id = 0, | 223 | .id = 0, |
232 | .num_resources = ARRAY_SIZE(smc91x_resources), | 224 | .num_resources = ARRAY_SIZE(smc91x_resources), |
233 | .resource = smc91x_resources, | 225 | .resource = smc91x_resources, |
226 | .dev = { | ||
227 | .platform_data = &smc91x_info, | ||
228 | }, | ||
229 | }; | ||
230 | #endif | ||
231 | |||
232 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | ||
233 | #include <linux/smsc911x.h> | ||
234 | |||
235 | static struct resource smsc911x_resources[] = { | ||
236 | { | ||
237 | .name = "smsc911x-memory", | ||
238 | .start = 0x24008000, | ||
239 | .end = 0x24008000 + 0xFF, | ||
240 | .flags = IORESOURCE_MEM, | ||
241 | }, | ||
242 | { | ||
243 | .start = IRQ_PF43, | ||
244 | .end = IRQ_PF43, | ||
245 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | ||
246 | }, | ||
247 | }; | ||
248 | |||
249 | static struct smsc911x_platform_config smsc911x_config = { | ||
250 | .flags = SMSC911X_USE_16BIT, | ||
251 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | ||
252 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, | ||
253 | .phy_interface = PHY_INTERFACE_MODE_MII, | ||
254 | }; | ||
255 | |||
256 | static struct platform_device smsc911x_device = { | ||
257 | .name = "smsc911x", | ||
258 | .id = 0, | ||
259 | .num_resources = ARRAY_SIZE(smsc911x_resources), | ||
260 | .resource = smsc911x_resources, | ||
261 | .dev = { | ||
262 | .platform_data = &smsc911x_config, | ||
263 | }, | ||
264 | }; | ||
265 | #endif | ||
266 | |||
267 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | ||
268 | static struct resource net2272_bfin_resources[] = { | ||
269 | { | ||
270 | .start = 0x24000000, | ||
271 | .end = 0x24000000 + 0x100, | ||
272 | .flags = IORESOURCE_MEM, | ||
273 | }, { | ||
274 | .start = IRQ_PF45, | ||
275 | .end = IRQ_PF45, | ||
276 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
277 | }, | ||
278 | }; | ||
279 | |||
280 | static struct platform_device net2272_bfin_device = { | ||
281 | .name = "net2272", | ||
282 | .id = -1, | ||
283 | .num_resources = ARRAY_SIZE(net2272_bfin_resources), | ||
284 | .resource = net2272_bfin_resources, | ||
234 | }; | 285 | }; |
235 | #endif | 286 | #endif |
236 | 287 | ||
@@ -369,6 +420,46 @@ static struct platform_device bfin_pata_device = { | |||
369 | }; | 420 | }; |
370 | #endif | 421 | #endif |
371 | 422 | ||
423 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
424 | static struct mtd_partition para_partitions[] = { | ||
425 | { | ||
426 | .name = "bootloader(nor)", | ||
427 | .size = 0x40000, | ||
428 | .offset = 0, | ||
429 | }, { | ||
430 | .name = "linux kernel(nor)", | ||
431 | .size = 0x100000, | ||
432 | .offset = MTDPART_OFS_APPEND, | ||
433 | }, { | ||
434 | .name = "file system(nor)", | ||
435 | .size = MTDPART_SIZ_FULL, | ||
436 | .offset = MTDPART_OFS_APPEND, | ||
437 | } | ||
438 | }; | ||
439 | |||
440 | static struct physmap_flash_data para_flash_data = { | ||
441 | .width = 2, | ||
442 | .parts = para_partitions, | ||
443 | .nr_parts = ARRAY_SIZE(para_partitions), | ||
444 | }; | ||
445 | |||
446 | static struct resource para_flash_resource = { | ||
447 | .start = 0x20000000, | ||
448 | .end = 0x207fffff, | ||
449 | .flags = IORESOURCE_MEM, | ||
450 | }; | ||
451 | |||
452 | static struct platform_device para_flash_device = { | ||
453 | .name = "physmap-flash", | ||
454 | .id = 0, | ||
455 | .dev = { | ||
456 | .platform_data = ¶_flash_data, | ||
457 | }, | ||
458 | .num_resources = 1, | ||
459 | .resource = ¶_flash_resource, | ||
460 | }; | ||
461 | #endif | ||
462 | |||
372 | static const unsigned int cclk_vlev_datasheet[] = | 463 | static const unsigned int cclk_vlev_datasheet[] = |
373 | { | 464 | { |
374 | VRPAIR(VLEV_085, 250000000), | 465 | VRPAIR(VLEV_085, 250000000), |
@@ -422,6 +513,14 @@ static struct platform_device *cm_bf561_devices[] __initdata = { | |||
422 | &smc91x_device, | 513 | &smc91x_device, |
423 | #endif | 514 | #endif |
424 | 515 | ||
516 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | ||
517 | &smsc911x_device, | ||
518 | #endif | ||
519 | |||
520 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | ||
521 | &net2272_bfin_device, | ||
522 | #endif | ||
523 | |||
425 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | 524 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
426 | &bfin_spi0_device, | 525 | &bfin_spi0_device, |
427 | #endif | 526 | #endif |
@@ -430,6 +529,10 @@ static struct platform_device *cm_bf561_devices[] __initdata = { | |||
430 | &bfin_pata_device, | 529 | &bfin_pata_device, |
431 | #endif | 530 | #endif |
432 | 531 | ||
532 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
533 | ¶_flash_device, | ||
534 | #endif | ||
535 | |||
433 | &bfin_gpios_device, | 536 | &bfin_gpios_device, |
434 | }; | 537 | }; |
435 | 538 | ||
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 4df904f9e90a..caed96bb957e 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c | |||
@@ -147,6 +147,14 @@ static struct platform_device net2272_bfin_device = { | |||
147 | * Driver needs to know address, irq and flag pin. | 147 | * Driver needs to know address, irq and flag pin. |
148 | */ | 148 | */ |
149 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 149 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
150 | #include <linux/smc91x.h> | ||
151 | |||
152 | static struct smc91x_platdata smc91x_info = { | ||
153 | .flags = SMC91X_USE_32BIT | SMC91X_NOWAIT, | ||
154 | .leda = RPC_LED_100_10, | ||
155 | .ledb = RPC_LED_TX_RX, | ||
156 | }; | ||
157 | |||
150 | static struct resource smc91x_resources[] = { | 158 | static struct resource smc91x_resources[] = { |
151 | { | 159 | { |
152 | .name = "smc91x-regs", | 160 | .name = "smc91x-regs", |
@@ -166,6 +174,9 @@ static struct platform_device smc91x_device = { | |||
166 | .id = 0, | 174 | .id = 0, |
167 | .num_resources = ARRAY_SIZE(smc91x_resources), | 175 | .num_resources = ARRAY_SIZE(smc91x_resources), |
168 | .resource = smc91x_resources, | 176 | .resource = smc91x_resources, |
177 | .dev = { | ||
178 | .platform_data = &smc91x_info, | ||
179 | }, | ||
169 | }; | 180 | }; |
170 | #endif | 181 | #endif |
171 | 182 | ||
@@ -334,7 +345,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
334 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ | 345 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ |
335 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | 346 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) |
336 | { | 347 | { |
337 | .modalias = "ad1836-spi", | 348 | .modalias = "ad1836", |
338 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | 349 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
339 | .bus_num = 0, | 350 | .bus_num = 0, |
340 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 351 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index a5312b2d267e..70da495c9665 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h | |||
@@ -262,6 +262,8 @@ | |||
262 | #define ANOMALY_05000366 (1) | 262 | #define ANOMALY_05000366 (1) |
263 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | 263 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
264 | #define ANOMALY_05000371 (1) | 264 | #define ANOMALY_05000371 (1) |
265 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ | ||
266 | #define ANOMALY_05000402 (__SILICON_REVISION__ == 4) | ||
265 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ | 267 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
266 | #define ANOMALY_05000403 (1) | 268 | #define ANOMALY_05000403 (1) |
267 | /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ | 269 | /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ |
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S index 35280f06b7b6..f72a6af20c4f 100644 --- a/arch/blackfin/mach-bf561/secondary.S +++ b/arch/blackfin/mach-bf561/secondary.S | |||
@@ -85,16 +85,10 @@ ENTRY(_coreb_trampoline_start) | |||
85 | R0 = ~ENICPLB; | 85 | R0 = ~ENICPLB; |
86 | R0 = R0 & R1; | 86 | R0 = R0 & R1; |
87 | 87 | ||
88 | /* Anomaly 05000125 */ | 88 | /* Disabling of CPLBs should be proceeded by a CSYNC */ |
89 | #ifdef ANOMALY_05000125 | 89 | CSYNC; |
90 | CLI R2; | ||
91 | SSYNC; | ||
92 | #endif | ||
93 | [p0] = R0; | 90 | [p0] = R0; |
94 | SSYNC; | 91 | SSYNC; |
95 | #ifdef ANOMALY_05000125 | ||
96 | STI R2; | ||
97 | #endif | ||
98 | 92 | ||
99 | /* Turn off the dcache */ | 93 | /* Turn off the dcache */ |
100 | p0.l = LO(DMEM_CONTROL); | 94 | p0.l = LO(DMEM_CONTROL); |
@@ -103,16 +97,10 @@ ENTRY(_coreb_trampoline_start) | |||
103 | R0 = ~ENDCPLB; | 97 | R0 = ~ENDCPLB; |
104 | R0 = R0 & R1; | 98 | R0 = R0 & R1; |
105 | 99 | ||
106 | /* Anomaly 05000125 */ | 100 | /* Disabling of CPLBs should be proceeded by a CSYNC */ |
107 | #ifdef ANOMALY_05000125 | 101 | CSYNC; |
108 | CLI R2; | ||
109 | SSYNC; | ||
110 | #endif | ||
111 | [p0] = R0; | 102 | [p0] = R0; |
112 | SSYNC; | 103 | SSYNC; |
113 | #ifdef ANOMALY_05000125 | ||
114 | STI R2; | ||
115 | #endif | ||
116 | 104 | ||
117 | /* in case of double faults, save a few things */ | 105 | /* in case of double faults, save a few things */ |
118 | p0.l = _init_retx_coreb; | 106 | p0.l = _init_retx_coreb; |
@@ -126,22 +114,22 @@ ENTRY(_coreb_trampoline_start) | |||
126 | * below | 114 | * below |
127 | */ | 115 | */ |
128 | GET_PDA(p0, r0); | 116 | GET_PDA(p0, r0); |
129 | r7 = [p0 + PDA_RETX]; | 117 | r7 = [p0 + PDA_DF_RETX]; |
130 | p1.l = _init_saved_retx_coreb; | 118 | p1.l = _init_saved_retx_coreb; |
131 | p1.h = _init_saved_retx_coreb; | 119 | p1.h = _init_saved_retx_coreb; |
132 | [p1] = r7; | 120 | [p1] = r7; |
133 | 121 | ||
134 | r7 = [p0 + PDA_DCPLB]; | 122 | r7 = [p0 + PDA_DF_DCPLB]; |
135 | p1.l = _init_saved_dcplb_fault_addr_coreb; | 123 | p1.l = _init_saved_dcplb_fault_addr_coreb; |
136 | p1.h = _init_saved_dcplb_fault_addr_coreb; | 124 | p1.h = _init_saved_dcplb_fault_addr_coreb; |
137 | [p1] = r7; | 125 | [p1] = r7; |
138 | 126 | ||
139 | r7 = [p0 + PDA_ICPLB]; | 127 | r7 = [p0 + PDA_DF_ICPLB]; |
140 | p1.l = _init_saved_icplb_fault_addr_coreb; | 128 | p1.l = _init_saved_icplb_fault_addr_coreb; |
141 | p1.h = _init_saved_icplb_fault_addr_coreb; | 129 | p1.h = _init_saved_icplb_fault_addr_coreb; |
142 | [p1] = r7; | 130 | [p1] = r7; |
143 | 131 | ||
144 | r7 = [p0 + PDA_SEQSTAT]; | 132 | r7 = [p0 + PDA_DF_SEQSTAT]; |
145 | p1.l = _init_saved_seqstat_coreb; | 133 | p1.l = _init_saved_seqstat_coreb; |
146 | p1.h = _init_saved_seqstat_coreb; | 134 | p1.h = _init_saved_seqstat_coreb; |
147 | [p1] = r7; | 135 | [p1] = r7; |
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile index dd8b2dc97f56..814cb483853b 100644 --- a/arch/blackfin/mach-common/Makefile +++ b/arch/blackfin/mach-common/Makefile | |||
@@ -6,7 +6,6 @@ obj-y := \ | |||
6 | cache.o cache-c.o entry.o head.o \ | 6 | cache.o cache-c.o entry.o head.o \ |
7 | interrupt.o arch_checks.o ints-priority.o | 7 | interrupt.o arch_checks.o ints-priority.o |
8 | 8 | ||
9 | obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o | ||
10 | obj-$(CONFIG_PM) += pm.o dpmc_modes.o | 9 | obj-$(CONFIG_PM) += pm.o dpmc_modes.o |
11 | obj-$(CONFIG_CPU_FREQ) += cpufreq.o | 10 | obj-$(CONFIG_CPU_FREQ) += cpufreq.o |
12 | obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o | 11 | obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o |
diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c index b59ce3cb3807..4ebbd78db3a4 100644 --- a/arch/blackfin/mach-common/cache-c.c +++ b/arch/blackfin/mach-common/cache-c.c | |||
@@ -1,14 +1,16 @@ | |||
1 | /* | 1 | /* |
2 | * Blackfin cache control code (simpler control-style functions) | 2 | * Blackfin cache control code (simpler control-style functions) |
3 | * | 3 | * |
4 | * Copyright 2004-2008 Analog Devices Inc. | 4 | * Copyright 2004-2009 Analog Devices Inc. |
5 | * | 5 | * |
6 | * Enter bugs at http://blackfin.uclinux.org/ | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
7 | * | 7 | * |
8 | * Licensed under the GPL-2 or later. | 8 | * Licensed under the GPL-2 or later. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/init.h> | ||
11 | #include <asm/blackfin.h> | 12 | #include <asm/blackfin.h> |
13 | #include <asm/cplbinit.h> | ||
12 | 14 | ||
13 | /* Invalidate the Entire Data cache by | 15 | /* Invalidate the Entire Data cache by |
14 | * clearing DMC[1:0] bits | 16 | * clearing DMC[1:0] bits |
@@ -34,3 +36,43 @@ void blackfin_invalidate_entire_icache(void) | |||
34 | SSYNC(); | 36 | SSYNC(); |
35 | } | 37 | } |
36 | 38 | ||
39 | #if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE) | ||
40 | |||
41 | static void | ||
42 | bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr, | ||
43 | unsigned long cplb_data, unsigned long mem_control, | ||
44 | unsigned long mem_mask) | ||
45 | { | ||
46 | int i; | ||
47 | |||
48 | for (i = 0; i < MAX_CPLBS; i++) { | ||
49 | bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr); | ||
50 | bfin_write32(cplb_data + i * 4, cplb_tbl[i].data); | ||
51 | } | ||
52 | |||
53 | _enable_cplb(mem_control, mem_mask); | ||
54 | } | ||
55 | |||
56 | #ifdef CONFIG_BFIN_ICACHE | ||
57 | void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl) | ||
58 | { | ||
59 | bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL, | ||
60 | (IMC | ENICPLB)); | ||
61 | } | ||
62 | #endif | ||
63 | |||
64 | #ifdef CONFIG_BFIN_DCACHE | ||
65 | void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) | ||
66 | { | ||
67 | /* | ||
68 | * Anomaly notes: | ||
69 | * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL | ||
70 | * register, so that the port preferences for DAG0 and DAG1 are set | ||
71 | * to port B | ||
72 | */ | ||
73 | bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL, | ||
74 | (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0))); | ||
75 | } | ||
76 | #endif | ||
77 | |||
78 | #endif | ||
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index fb1795d5be2a..01af24cde362 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S | |||
@@ -301,27 +301,31 @@ ENTRY(_ex_replaceable) | |||
301 | nop; | 301 | nop; |
302 | 302 | ||
303 | ENTRY(_ex_trap_c) | 303 | ENTRY(_ex_trap_c) |
304 | /* The only thing that has been saved in this context is | ||
305 | * (R7:6,P5:4), ASTAT & SP - don't use anything else | ||
306 | */ | ||
307 | |||
308 | GET_PDA(p5, r6); | ||
309 | |||
304 | /* Make sure we are not in a double fault */ | 310 | /* Make sure we are not in a double fault */ |
305 | p4.l = lo(IPEND); | 311 | p4.l = lo(IPEND); |
306 | p4.h = hi(IPEND); | 312 | p4.h = hi(IPEND); |
307 | r7 = [p4]; | 313 | r7 = [p4]; |
308 | CC = BITTST (r7, 5); | 314 | CC = BITTST (r7, 5); |
309 | if CC jump _double_fault; | 315 | if CC jump _double_fault; |
316 | [p5 + PDA_EXIPEND] = r7; | ||
310 | 317 | ||
311 | /* Call C code (trap_c) to handle the exception, which most | 318 | /* Call C code (trap_c) to handle the exception, which most |
312 | * likely involves sending a signal to the current process. | 319 | * likely involves sending a signal to the current process. |
313 | * To avoid double faults, lower our priority to IRQ5 first. | 320 | * To avoid double faults, lower our priority to IRQ5 first. |
314 | */ | 321 | */ |
315 | P5.h = _exception_to_level5; | 322 | r7.h = _exception_to_level5; |
316 | P5.l = _exception_to_level5; | 323 | r7.l = _exception_to_level5; |
317 | p4.l = lo(EVT5); | 324 | p4.l = lo(EVT5); |
318 | p4.h = hi(EVT5); | 325 | p4.h = hi(EVT5); |
319 | [p4] = p5; | 326 | [p4] = r7; |
320 | csync; | 327 | csync; |
321 | 328 | ||
322 | GET_PDA(p5, r6); | ||
323 | #ifndef CONFIG_DEBUG_DOUBLEFAULT | ||
324 | |||
325 | /* | 329 | /* |
326 | * Save these registers, as they are only valid in exception context | 330 | * Save these registers, as they are only valid in exception context |
327 | * (where we are now - as soon as we defer to IRQ5, they can change) | 331 | * (where we are now - as soon as we defer to IRQ5, they can change) |
@@ -341,7 +345,10 @@ ENTRY(_ex_trap_c) | |||
341 | 345 | ||
342 | r6 = retx; | 346 | r6 = retx; |
343 | [p5 + PDA_RETX] = r6; | 347 | [p5 + PDA_RETX] = r6; |
344 | #endif | 348 | |
349 | r6 = SEQSTAT; | ||
350 | [p5 + PDA_SEQSTAT] = r6; | ||
351 | |||
345 | /* Save the state of single stepping */ | 352 | /* Save the state of single stepping */ |
346 | r6 = SYSCFG; | 353 | r6 = SYSCFG; |
347 | [p5 + PDA_SYSCFG] = r6; | 354 | [p5 + PDA_SYSCFG] = r6; |
@@ -349,8 +356,7 @@ ENTRY(_ex_trap_c) | |||
349 | BITCLR(r6, SYSCFG_SSSTEP_P); | 356 | BITCLR(r6, SYSCFG_SSSTEP_P); |
350 | SYSCFG = r6; | 357 | SYSCFG = r6; |
351 | 358 | ||
352 | /* Disable all interrupts, but make sure level 5 is enabled so | 359 | /* Save the current IMASK, since we change in order to jump to level 5 */ |
353 | * we can switch to that level. Save the old mask. */ | ||
354 | cli r6; | 360 | cli r6; |
355 | [p5 + PDA_EXIMASK] = r6; | 361 | [p5 + PDA_EXIMASK] = r6; |
356 | 362 | ||
@@ -358,9 +364,21 @@ ENTRY(_ex_trap_c) | |||
358 | p4.h = hi(SAFE_USER_INSTRUCTION); | 364 | p4.h = hi(SAFE_USER_INSTRUCTION); |
359 | retx = p4; | 365 | retx = p4; |
360 | 366 | ||
367 | /* Disable all interrupts, but make sure level 5 is enabled so | ||
368 | * we can switch to that level. | ||
369 | */ | ||
361 | r6 = 0x3f; | 370 | r6 = 0x3f; |
362 | sti r6; | 371 | sti r6; |
363 | 372 | ||
373 | /* In case interrupts are disabled IPEND[4] (global interrupt disable bit) | ||
374 | * clear it (re-enabling interrupts again) by the special sequence of pushing | ||
375 | * RETI onto the stack. This way we can lower ourselves to IVG5 even if the | ||
376 | * exception was taken after the interrupt handler was called but before it | ||
377 | * got a chance to enable global interrupts itself. | ||
378 | */ | ||
379 | [--sp] = reti; | ||
380 | sp += 4; | ||
381 | |||
364 | raise 5; | 382 | raise 5; |
365 | jump.s _bfin_return_from_exception; | 383 | jump.s _bfin_return_from_exception; |
366 | ENDPROC(_ex_trap_c) | 384 | ENDPROC(_ex_trap_c) |
@@ -379,8 +397,7 @@ ENTRY(_double_fault) | |||
379 | 397 | ||
380 | R5 = [P4]; /* Control Register*/ | 398 | R5 = [P4]; /* Control Register*/ |
381 | BITCLR(R5,ENICPLB_P); | 399 | BITCLR(R5,ENICPLB_P); |
382 | SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ | 400 | CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */ |
383 | .align 8; | ||
384 | [P4] = R5; | 401 | [P4] = R5; |
385 | SSYNC; | 402 | SSYNC; |
386 | 403 | ||
@@ -388,8 +405,7 @@ ENTRY(_double_fault) | |||
388 | P4.H = HI(DMEM_CONTROL); | 405 | P4.H = HI(DMEM_CONTROL); |
389 | R5 = [P4]; | 406 | R5 = [P4]; |
390 | BITCLR(R5,ENDCPLB_P); | 407 | BITCLR(R5,ENDCPLB_P); |
391 | SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ | 408 | CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */ |
392 | .align 8; | ||
393 | [P4] = R5; | 409 | [P4] = R5; |
394 | SSYNC; | 410 | SSYNC; |
395 | 411 | ||
@@ -420,47 +436,55 @@ ENDPROC(_double_fault) | |||
420 | ENTRY(_exception_to_level5) | 436 | ENTRY(_exception_to_level5) |
421 | SAVE_ALL_SYS | 437 | SAVE_ALL_SYS |
422 | 438 | ||
423 | GET_PDA(p4, r7); /* Fetch current PDA */ | 439 | GET_PDA(p5, r7); /* Fetch current PDA */ |
424 | r6 = [p4 + PDA_RETX]; | 440 | r6 = [p5 + PDA_RETX]; |
425 | [sp + PT_PC] = r6; | 441 | [sp + PT_PC] = r6; |
426 | 442 | ||
427 | r6 = [p4 + PDA_SYSCFG]; | 443 | r6 = [p5 + PDA_SYSCFG]; |
428 | [sp + PT_SYSCFG] = r6; | 444 | [sp + PT_SYSCFG] = r6; |
429 | 445 | ||
430 | /* Restore interrupt mask. We haven't pushed RETI, so this | 446 | r6 = [p5 + PDA_SEQSTAT]; /* Read back seqstat */ |
431 | * doesn't enable interrupts until we return from this handler. */ | 447 | [sp + PT_SEQSTAT] = r6; |
432 | r6 = [p4 + PDA_EXIMASK]; | ||
433 | sti r6; | ||
434 | 448 | ||
435 | /* Restore the hardware error vector. */ | 449 | /* Restore the hardware error vector. */ |
436 | P5.h = _evt_ivhw; | 450 | r7.h = _evt_ivhw; |
437 | P5.l = _evt_ivhw; | 451 | r7.l = _evt_ivhw; |
438 | p4.l = lo(EVT5); | 452 | p4.l = lo(EVT5); |
439 | p4.h = hi(EVT5); | 453 | p4.h = hi(EVT5); |
440 | [p4] = p5; | 454 | [p4] = r7; |
441 | csync; | 455 | csync; |
442 | 456 | ||
443 | p2.l = lo(IPEND); | 457 | #ifdef CONFIG_DEBUG_DOUBLEFAULT |
444 | p2.h = hi(IPEND); | 458 | /* Now that we have the hardware error vector programmed properly |
445 | csync; | 459 | * we can re-enable interrupts (IPEND[4]), so if the _trap_c causes |
446 | r0 = [p2]; /* Read current IPEND */ | 460 | * another hardware error, we can catch it (self-nesting). |
447 | [sp + PT_IPEND] = r0; /* Store IPEND */ | 461 | */ |
462 | [--sp] = reti; | ||
463 | sp += 4; | ||
464 | #endif | ||
465 | |||
466 | r7 = [p5 + PDA_EXIPEND] /* Read the IPEND from the Exception state */ | ||
467 | [sp + PT_IPEND] = r7; /* Store IPEND onto the stack */ | ||
448 | 468 | ||
449 | r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ | 469 | r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ |
450 | SP += -12; | 470 | SP += -12; |
451 | call _trap_c; | 471 | call _trap_c; |
452 | SP += 12; | 472 | SP += 12; |
453 | 473 | ||
454 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | 474 | /* If interrupts were off during the exception (IPEND[4] = 1), turn them off |
455 | /* Grab ILAT */ | 475 | * before we return. |
456 | p2.l = lo(ILAT); | 476 | */ |
457 | p2.h = hi(ILAT); | 477 | CC = BITTST(r7, EVT_IRPTEN_P) |
458 | r0 = [p2]; | 478 | if !CC jump 1f; |
459 | r1 = 0x20; /* Did I just cause anther HW error? */ | 479 | /* this will load a random value into the reti register - but that is OK, |
460 | r0 = r0 & r1; | 480 | * since we do restore it to the correct value in the 'RESTORE_ALL_SYS' macro |
461 | CC = R0 == R1; | 481 | */ |
462 | if CC JUMP _double_fault; | 482 | sp += -4; |
463 | #endif | 483 | reti = [sp++]; |
484 | 1: | ||
485 | /* restore the interrupt mask (IMASK) */ | ||
486 | r6 = [p5 + PDA_EXIMASK]; | ||
487 | sti r6; | ||
464 | 488 | ||
465 | call _ret_from_exception; | 489 | call _ret_from_exception; |
466 | RESTORE_ALL_SYS | 490 | RESTORE_ALL_SYS |
@@ -474,7 +498,7 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/ | |||
474 | */ | 498 | */ |
475 | EX_SCRATCH_REG = sp; | 499 | EX_SCRATCH_REG = sp; |
476 | GET_PDA_SAFE(sp); | 500 | GET_PDA_SAFE(sp); |
477 | sp = [sp + PDA_EXSTACK] | 501 | sp = [sp + PDA_EXSTACK]; |
478 | /* Try to deal with syscalls quickly. */ | 502 | /* Try to deal with syscalls quickly. */ |
479 | [--sp] = ASTAT; | 503 | [--sp] = ASTAT; |
480 | [--sp] = (R7:6,P5:4); | 504 | [--sp] = (R7:6,P5:4); |
@@ -489,14 +513,7 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/ | |||
489 | ssync; | 513 | ssync; |
490 | #endif | 514 | #endif |
491 | 515 | ||
492 | #if ANOMALY_05000283 || ANOMALY_05000315 | 516 | ANOMALY_283_315_WORKAROUND(p5, r7) |
493 | cc = r7 == r7; | ||
494 | p5.h = HI(CHIPID); | ||
495 | p5.l = LO(CHIPID); | ||
496 | if cc jump 1f; | ||
497 | r7.l = W[p5]; | ||
498 | 1: | ||
499 | #endif | ||
500 | 517 | ||
501 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | 518 | #ifdef CONFIG_DEBUG_DOUBLEFAULT |
502 | /* | 519 | /* |
@@ -510,18 +527,18 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/ | |||
510 | p4.l = lo(DCPLB_FAULT_ADDR); | 527 | p4.l = lo(DCPLB_FAULT_ADDR); |
511 | p4.h = hi(DCPLB_FAULT_ADDR); | 528 | p4.h = hi(DCPLB_FAULT_ADDR); |
512 | r7 = [p4]; | 529 | r7 = [p4]; |
513 | [p5 + PDA_DCPLB] = r7; | 530 | [p5 + PDA_DF_DCPLB] = r7; |
514 | 531 | ||
515 | p4.l = lo(ICPLB_FAULT_ADDR); | 532 | p4.l = lo(ICPLB_FAULT_ADDR); |
516 | p4.h = hi(ICPLB_FAULT_ADDR); | 533 | p4.h = hi(ICPLB_FAULT_ADDR); |
517 | r7 = [p4]; | 534 | r7 = [p4]; |
518 | [p5 + PDA_ICPLB] = r7; | 535 | [p5 + PDA_DF_ICPLB] = r7; |
519 | 536 | ||
520 | r6 = retx; | 537 | r7 = retx; |
521 | [p5 + PDA_RETX] = r6; | 538 | [p5 + PDA_DF_RETX] = r7; |
522 | 539 | ||
523 | r7 = SEQSTAT; /* reason code is in bit 5:0 */ | 540 | r7 = SEQSTAT; /* reason code is in bit 5:0 */ |
524 | [p5 + PDA_SEQSTAT] = r7; | 541 | [p5 + PDA_DF_SEQSTAT] = r7; |
525 | #else | 542 | #else |
526 | r7 = SEQSTAT; /* reason code is in bit 5:0 */ | 543 | r7 = SEQSTAT; /* reason code is in bit 5:0 */ |
527 | #endif | 544 | #endif |
@@ -686,8 +703,14 @@ ENTRY(_system_call) | |||
686 | #ifdef CONFIG_IPIPE | 703 | #ifdef CONFIG_IPIPE |
687 | cc = BITTST(r7, TIF_IRQ_SYNC); | 704 | cc = BITTST(r7, TIF_IRQ_SYNC); |
688 | if !cc jump .Lsyscall_no_irqsync; | 705 | if !cc jump .Lsyscall_no_irqsync; |
706 | /* | ||
707 | * Clear IPEND[4] manually to undo what resume_userspace_1 just did; | ||
708 | * we need this so that high priority domain interrupts may still | ||
709 | * preempt the current domain while the pipeline log is being played | ||
710 | * back. | ||
711 | */ | ||
689 | [--sp] = reti; | 712 | [--sp] = reti; |
690 | r0 = [sp++]; | 713 | SP += 4; /* don't merge with next insn to keep the pattern obvious */ |
691 | SP += -12; | 714 | SP += -12; |
692 | call ___ipipe_sync_root; | 715 | call ___ipipe_sync_root; |
693 | SP += 12; | 716 | SP += 12; |
@@ -699,7 +722,7 @@ ENTRY(_system_call) | |||
699 | 722 | ||
700 | /* Reenable interrupts. */ | 723 | /* Reenable interrupts. */ |
701 | [--sp] = reti; | 724 | [--sp] = reti; |
702 | r0 = [sp++]; | 725 | sp += 4; |
703 | 726 | ||
704 | SP += -12; | 727 | SP += -12; |
705 | call _schedule; | 728 | call _schedule; |
@@ -715,7 +738,7 @@ ENTRY(_system_call) | |||
715 | .Lsyscall_do_signals: | 738 | .Lsyscall_do_signals: |
716 | /* Reenable interrupts. */ | 739 | /* Reenable interrupts. */ |
717 | [--sp] = reti; | 740 | [--sp] = reti; |
718 | r0 = [sp++]; | 741 | sp += 4; |
719 | 742 | ||
720 | r0 = sp; | 743 | r0 = sp; |
721 | SP += -12; | 744 | SP += -12; |
@@ -725,10 +748,6 @@ ENTRY(_system_call) | |||
725 | .Lsyscall_really_exit: | 748 | .Lsyscall_really_exit: |
726 | r5 = [sp + PT_RESERVED]; | 749 | r5 = [sp + PT_RESERVED]; |
727 | rets = r5; | 750 | rets = r5; |
728 | #ifdef CONFIG_IPIPE | ||
729 | [--sp] = reti; | ||
730 | r5 = [sp++]; | ||
731 | #endif /* CONFIG_IPIPE */ | ||
732 | rts; | 751 | rts; |
733 | ENDPROC(_system_call) | 752 | ENDPROC(_system_call) |
734 | 753 | ||
@@ -816,13 +835,13 @@ ENDPROC(_resume) | |||
816 | 835 | ||
817 | ENTRY(_ret_from_exception) | 836 | ENTRY(_ret_from_exception) |
818 | #ifdef CONFIG_IPIPE | 837 | #ifdef CONFIG_IPIPE |
819 | [--sp] = rets; | 838 | p2.l = _per_cpu__ipipe_percpu_domain; |
820 | SP += -12; | 839 | p2.h = _per_cpu__ipipe_percpu_domain; |
821 | call ___ipipe_check_root | 840 | r0.l = _ipipe_root; |
822 | SP += 12 | 841 | r0.h = _ipipe_root; |
823 | rets = [sp++]; | 842 | r2 = [p2]; |
824 | cc = r0 == 0; | 843 | cc = r0 == r2; |
825 | if cc jump 4f; /* not on behalf of Linux, get out */ | 844 | if !cc jump 4f; /* not on behalf of the root domain, get out */ |
826 | #endif /* CONFIG_IPIPE */ | 845 | #endif /* CONFIG_IPIPE */ |
827 | p2.l = lo(IPEND); | 846 | p2.l = lo(IPEND); |
828 | p2.h = hi(IPEND); | 847 | p2.h = hi(IPEND); |
@@ -882,14 +901,9 @@ ENDPROC(_ret_from_exception) | |||
882 | 901 | ||
883 | #ifdef CONFIG_IPIPE | 902 | #ifdef CONFIG_IPIPE |
884 | 903 | ||
885 | _sync_root_irqs: | ||
886 | [--sp] = reti; /* Reenable interrupts */ | ||
887 | r0 = [sp++]; | ||
888 | jump.l ___ipipe_sync_root | ||
889 | |||
890 | _resume_kernel_from_int: | 904 | _resume_kernel_from_int: |
891 | r0.l = _sync_root_irqs | 905 | r0.l = ___ipipe_sync_root; |
892 | r0.h = _sync_root_irqs | 906 | r0.h = ___ipipe_sync_root; |
893 | [--sp] = rets; | 907 | [--sp] = rets; |
894 | [--sp] = ( r7:4, p5:3 ); | 908 | [--sp] = ( r7:4, p5:3 ); |
895 | SP += -12; | 909 | SP += -12; |
@@ -953,10 +967,10 @@ ENTRY(_lower_to_irq14) | |||
953 | #endif | 967 | #endif |
954 | 968 | ||
955 | #ifdef CONFIG_DEBUG_HWERR | 969 | #ifdef CONFIG_DEBUG_HWERR |
956 | /* enable irq14 & hwerr interrupt, until we transition to _evt14_softirq */ | 970 | /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */ |
957 | r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); | 971 | r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); |
958 | #else | 972 | #else |
959 | /* Only enable irq14 interrupt, until we transition to _evt14_softirq */ | 973 | /* Only enable irq14 interrupt, until we transition to _evt_evt14 */ |
960 | r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); | 974 | r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); |
961 | #endif | 975 | #endif |
962 | sti r0; | 976 | sti r0; |
@@ -964,7 +978,7 @@ ENTRY(_lower_to_irq14) | |||
964 | rti; | 978 | rti; |
965 | ENDPROC(_lower_to_irq14) | 979 | ENDPROC(_lower_to_irq14) |
966 | 980 | ||
967 | ENTRY(_evt14_softirq) | 981 | ENTRY(_evt_evt14) |
968 | #ifdef CONFIG_DEBUG_HWERR | 982 | #ifdef CONFIG_DEBUG_HWERR |
969 | r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); | 983 | r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); |
970 | sti r0; | 984 | sti r0; |
@@ -974,7 +988,7 @@ ENTRY(_evt14_softirq) | |||
974 | [--sp] = RETI; | 988 | [--sp] = RETI; |
975 | SP += 4; | 989 | SP += 4; |
976 | rts; | 990 | rts; |
977 | ENDPROC(_evt14_softirq) | 991 | ENDPROC(_evt_evt14) |
978 | 992 | ||
979 | ENTRY(_schedule_and_signal_from_int) | 993 | ENTRY(_schedule_and_signal_from_int) |
980 | /* To end up here, vector 15 was changed - so we have to change it | 994 | /* To end up here, vector 15 was changed - so we have to change it |
@@ -1004,6 +1018,12 @@ ENTRY(_schedule_and_signal_from_int) | |||
1004 | #endif | 1018 | #endif |
1005 | sti r0; | 1019 | sti r0; |
1006 | 1020 | ||
1021 | /* finish the userspace "atomic" functions for it */ | ||
1022 | r1 = FIXED_CODE_END; | ||
1023 | r2 = [sp + PT_PC]; | ||
1024 | cc = r1 <= r2; | ||
1025 | if cc jump .Lresume_userspace (bp); | ||
1026 | |||
1007 | r0 = sp; | 1027 | r0 = sp; |
1008 | sp += -12; | 1028 | sp += -12; |
1009 | call _finish_atomic_sections; | 1029 | call _finish_atomic_sections; |
@@ -1107,14 +1127,7 @@ ENTRY(_early_trap) | |||
1107 | SAVE_ALL_SYS | 1127 | SAVE_ALL_SYS |
1108 | trace_buffer_stop(p0,r0); | 1128 | trace_buffer_stop(p0,r0); |
1109 | 1129 | ||
1110 | #if ANOMALY_05000283 || ANOMALY_05000315 | 1130 | ANOMALY_283_315_WORKAROUND(p4, r5) |
1111 | cc = r5 == r5; | ||
1112 | p4.h = HI(CHIPID); | ||
1113 | p4.l = LO(CHIPID); | ||
1114 | if cc jump 1f; | ||
1115 | r5.l = W[p4]; | ||
1116 | 1: | ||
1117 | #endif | ||
1118 | 1131 | ||
1119 | /* Turn caches off, to ensure we don't get double exceptions */ | 1132 | /* Turn caches off, to ensure we don't get double exceptions */ |
1120 | 1133 | ||
@@ -1123,9 +1136,7 @@ ENTRY(_early_trap) | |||
1123 | 1136 | ||
1124 | R5 = [P4]; /* Control Register*/ | 1137 | R5 = [P4]; /* Control Register*/ |
1125 | BITCLR(R5,ENICPLB_P); | 1138 | BITCLR(R5,ENICPLB_P); |
1126 | CLI R1; | 1139 | CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */ |
1127 | SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ | ||
1128 | .align 8; | ||
1129 | [P4] = R5; | 1140 | [P4] = R5; |
1130 | SSYNC; | 1141 | SSYNC; |
1131 | 1142 | ||
@@ -1133,11 +1144,9 @@ ENTRY(_early_trap) | |||
1133 | P4.H = HI(DMEM_CONTROL); | 1144 | P4.H = HI(DMEM_CONTROL); |
1134 | R5 = [P4]; | 1145 | R5 = [P4]; |
1135 | BITCLR(R5,ENDCPLB_P); | 1146 | BITCLR(R5,ENDCPLB_P); |
1136 | SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ | 1147 | CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */ |
1137 | .align 8; | ||
1138 | [P4] = R5; | 1148 | [P4] = R5; |
1139 | SSYNC; | 1149 | SSYNC; |
1140 | STI R1; | ||
1141 | 1150 | ||
1142 | r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ | 1151 | r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ |
1143 | r1 = RETX; | 1152 | r1 = RETX; |
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S index f826f6b9f917..9c79dfea2a53 100644 --- a/arch/blackfin/mach-common/head.S +++ b/arch/blackfin/mach-common/head.S | |||
@@ -124,22 +124,22 @@ ENTRY(__start) | |||
124 | * below | 124 | * below |
125 | */ | 125 | */ |
126 | GET_PDA(p0, r0); | 126 | GET_PDA(p0, r0); |
127 | r6 = [p0 + PDA_RETX]; | 127 | r6 = [p0 + PDA_DF_RETX]; |
128 | p1.l = _init_saved_retx; | 128 | p1.l = _init_saved_retx; |
129 | p1.h = _init_saved_retx; | 129 | p1.h = _init_saved_retx; |
130 | [p1] = r6; | 130 | [p1] = r6; |
131 | 131 | ||
132 | r6 = [p0 + PDA_DCPLB]; | 132 | r6 = [p0 + PDA_DF_DCPLB]; |
133 | p1.l = _init_saved_dcplb_fault_addr; | 133 | p1.l = _init_saved_dcplb_fault_addr; |
134 | p1.h = _init_saved_dcplb_fault_addr; | 134 | p1.h = _init_saved_dcplb_fault_addr; |
135 | [p1] = r6; | 135 | [p1] = r6; |
136 | 136 | ||
137 | r6 = [p0 + PDA_ICPLB]; | 137 | r6 = [p0 + PDA_DF_ICPLB]; |
138 | p1.l = _init_saved_icplb_fault_addr; | 138 | p1.l = _init_saved_icplb_fault_addr; |
139 | p1.h = _init_saved_icplb_fault_addr; | 139 | p1.h = _init_saved_icplb_fault_addr; |
140 | [p1] = r6; | 140 | [p1] = r6; |
141 | 141 | ||
142 | r6 = [p0 + PDA_SEQSTAT]; | 142 | r6 = [p0 + PDA_DF_SEQSTAT]; |
143 | p1.l = _init_saved_seqstat; | 143 | p1.l = _init_saved_seqstat; |
144 | p1.h = _init_saved_seqstat; | 144 | p1.h = _init_saved_seqstat; |
145 | [p1] = r6; | 145 | [p1] = r6; |
@@ -153,6 +153,8 @@ ENTRY(__start) | |||
153 | 153 | ||
154 | #ifdef CONFIG_EARLY_PRINTK | 154 | #ifdef CONFIG_EARLY_PRINTK |
155 | call _init_early_exception_vectors; | 155 | call _init_early_exception_vectors; |
156 | r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); | ||
157 | sti r0; | ||
156 | #endif | 158 | #endif |
157 | 159 | ||
158 | r0 = 0 (x); | 160 | r0 = 0 (x); |
@@ -212,12 +214,21 @@ ENTRY(__start) | |||
212 | [p0] = p1; | 214 | [p0] = p1; |
213 | csync; | 215 | csync; |
214 | 216 | ||
217 | #ifdef CONFIG_EARLY_PRINTK | ||
218 | r0 = (EVT_IVG15 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU) (z); | ||
219 | #else | ||
215 | r0 = EVT_IVG15 (z); | 220 | r0 = EVT_IVG15 (z); |
221 | #endif | ||
216 | sti r0; | 222 | sti r0; |
217 | 223 | ||
218 | raise 15; | 224 | raise 15; |
225 | #ifdef CONFIG_EARLY_PRINTK | ||
226 | p0.l = _early_trap; | ||
227 | p0.h = _early_trap; | ||
228 | #else | ||
219 | p0.l = .LWAIT_HERE; | 229 | p0.l = .LWAIT_HERE; |
220 | p0.h = .LWAIT_HERE; | 230 | p0.h = .LWAIT_HERE; |
231 | #endif | ||
221 | reti = p0; | 232 | reti = p0; |
222 | #if ANOMALY_05000281 | 233 | #if ANOMALY_05000281 |
223 | nop; nop; nop; | 234 | nop; nop; nop; |
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S index 9c46680186e4..82d417ef4b5b 100644 --- a/arch/blackfin/mach-common/interrupt.S +++ b/arch/blackfin/mach-common/interrupt.S | |||
@@ -119,14 +119,8 @@ __common_int_entry: | |||
119 | fp = 0; | 119 | fp = 0; |
120 | #endif | 120 | #endif |
121 | 121 | ||
122 | #if ANOMALY_05000283 || ANOMALY_05000315 | 122 | ANOMALY_283_315_WORKAROUND(p5, r7) |
123 | cc = r7 == r7; | 123 | |
124 | p5.h = HI(CHIPID); | ||
125 | p5.l = LO(CHIPID); | ||
126 | if cc jump 1f; | ||
127 | r7.l = W[p5]; | ||
128 | 1: | ||
129 | #endif | ||
130 | r1 = sp; | 124 | r1 = sp; |
131 | SP += -12; | 125 | SP += -12; |
132 | #ifdef CONFIG_IPIPE | 126 | #ifdef CONFIG_IPIPE |
@@ -158,14 +152,7 @@ ENTRY(_evt_ivhw) | |||
158 | fp = 0; | 152 | fp = 0; |
159 | #endif | 153 | #endif |
160 | 154 | ||
161 | #if ANOMALY_05000283 || ANOMALY_05000315 | 155 | ANOMALY_283_315_WORKAROUND(p5, r7) |
162 | cc = r7 == r7; | ||
163 | p5.h = HI(CHIPID); | ||
164 | p5.l = LO(CHIPID); | ||
165 | if cc jump 1f; | ||
166 | r7.l = W[p5]; | ||
167 | 1: | ||
168 | #endif | ||
169 | 156 | ||
170 | /* Handle all stacked hardware errors | 157 | /* Handle all stacked hardware errors |
171 | * To make sure we don't hang forever, only do it 10 times | 158 | * To make sure we don't hang forever, only do it 10 times |
@@ -261,6 +248,31 @@ ENTRY(_evt_system_call) | |||
261 | ENDPROC(_evt_system_call) | 248 | ENDPROC(_evt_system_call) |
262 | 249 | ||
263 | #ifdef CONFIG_IPIPE | 250 | #ifdef CONFIG_IPIPE |
251 | /* | ||
252 | * __ipipe_call_irqtail: lowers the current priority level to EVT15 | ||
253 | * before running a user-defined routine, then raises the priority | ||
254 | * level to EVT14 to prepare the caller for a normal interrupt | ||
255 | * return through RTI. | ||
256 | * | ||
257 | * We currently use this facility in two occasions: | ||
258 | * | ||
259 | * - to branch to __ipipe_irq_tail_hook as requested by a high | ||
260 | * priority domain after the pipeline delivered an interrupt, | ||
261 | * e.g. such as Xenomai, in order to start its rescheduling | ||
262 | * procedure, since we may not switch tasks when IRQ levels are | ||
263 | * nested on the Blackfin, so we have to fake an interrupt return | ||
264 | * so that we may reschedule immediately. | ||
265 | * | ||
266 | * - to branch to sync_root_irqs, in order to play any interrupt | ||
267 | * pending for the root domain (i.e. the Linux kernel). This lowers | ||
268 | * the core priority level enough so that Linux IRQ handlers may | ||
269 | * never delay interrupts handled by high priority domains; we defer | ||
270 | * those handlers until this point instead. This is a substitute | ||
271 | * to using a threaded interrupt model for the Linux kernel. | ||
272 | * | ||
273 | * r0: address of user-defined routine | ||
274 | * context: caller must have preempted EVT15, hw interrupts must be off. | ||
275 | */ | ||
264 | ENTRY(___ipipe_call_irqtail) | 276 | ENTRY(___ipipe_call_irqtail) |
265 | p0 = r0; | 277 | p0 = r0; |
266 | r0.l = 1f; | 278 | r0.l = 1f; |
@@ -276,33 +288,19 @@ ENTRY(___ipipe_call_irqtail) | |||
276 | ( r7:4, p5:3 ) = [sp++]; | 288 | ( r7:4, p5:3 ) = [sp++]; |
277 | rets = [sp++]; | 289 | rets = [sp++]; |
278 | 290 | ||
279 | [--sp] = reti; | 291 | #ifdef CONFIG_DEBUG_HWERR |
280 | reti = [sp++]; /* IRQs are off. */ | 292 | /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */ |
281 | r0.h = 3f; | 293 | r0 = (EVT_IVG14 | EVT_IVHW | \ |
282 | r0.l = 3f; | 294 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); |
283 | p0.l = lo(EVT14); | 295 | #else |
284 | p0.h = hi(EVT14); | 296 | /* Only enable irq14 interrupt, until we transition to _evt_evt14 */ |
285 | [p0] = r0; | 297 | r0 = (EVT_IVG14 | \ |
286 | csync; | 298 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); |
287 | r0 = 0x401f (z); | 299 | #endif |
288 | sti r0; | 300 | sti r0; |
289 | raise 14; | 301 | raise 14; /* Branches to _evt_evt14 */ |
290 | [--sp] = reti; /* IRQs on. */ | ||
291 | 2: | 302 | 2: |
292 | jump 2b; /* Likely paranoid. */ | 303 | jump 2b; /* Likely paranoid. */ |
293 | 3: | ||
294 | sp += 4; /* Discard saved RETI */ | ||
295 | r0.h = _evt14_softirq; | ||
296 | r0.l = _evt14_softirq; | ||
297 | p0.l = lo(EVT14); | ||
298 | p0.h = hi(EVT14); | ||
299 | [p0] = r0; | ||
300 | csync; | ||
301 | p0.l = _bfin_irq_flags; | ||
302 | p0.h = _bfin_irq_flags; | ||
303 | r0 = [p0]; | ||
304 | sti r0; | ||
305 | rts; | ||
306 | ENDPROC(___ipipe_call_irqtail) | 304 | ENDPROC(___ipipe_call_irqtail) |
307 | 305 | ||
308 | #endif /* CONFIG_IPIPE */ | 306 | #endif /* CONFIG_IPIPE */ |
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index b42150190d0e..6ffda78aaf9d 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c | |||
@@ -967,7 +967,7 @@ void __cpuinit init_exception_vectors(void) | |||
967 | bfin_write_EVT11(evt_evt11); | 967 | bfin_write_EVT11(evt_evt11); |
968 | bfin_write_EVT12(evt_evt12); | 968 | bfin_write_EVT12(evt_evt12); |
969 | bfin_write_EVT13(evt_evt13); | 969 | bfin_write_EVT13(evt_evt13); |
970 | bfin_write_EVT14(evt14_softirq); | 970 | bfin_write_EVT14(evt_evt14); |
971 | bfin_write_EVT15(evt_system_call); | 971 | bfin_write_EVT15(evt_system_call); |
972 | CSYNC(); | 972 | CSYNC(); |
973 | } | 973 | } |
@@ -1052,18 +1052,26 @@ int __init init_arch_irq(void) | |||
1052 | set_irq_chained_handler(irq, bfin_demux_error_irq); | 1052 | set_irq_chained_handler(irq, bfin_demux_error_irq); |
1053 | break; | 1053 | break; |
1054 | #endif | 1054 | #endif |
1055 | |||
1055 | #ifdef CONFIG_SMP | 1056 | #ifdef CONFIG_SMP |
1057 | #ifdef CONFIG_TICKSOURCE_GPTMR0 | ||
1058 | case IRQ_TIMER0: | ||
1059 | #endif | ||
1060 | #ifdef CONFIG_TICKSOURCE_CORETMR | ||
1061 | case IRQ_CORETMR: | ||
1062 | #endif | ||
1056 | case IRQ_SUPPLE_0: | 1063 | case IRQ_SUPPLE_0: |
1057 | case IRQ_SUPPLE_1: | 1064 | case IRQ_SUPPLE_1: |
1058 | set_irq_handler(irq, handle_percpu_irq); | 1065 | set_irq_handler(irq, handle_percpu_irq); |
1059 | break; | 1066 | break; |
1060 | #endif | 1067 | #endif |
1068 | |||
1061 | #ifdef CONFIG_IPIPE | 1069 | #ifdef CONFIG_IPIPE |
1062 | #ifndef CONFIG_TICKSOURCE_CORETMR | 1070 | #ifndef CONFIG_TICKSOURCE_CORETMR |
1063 | case IRQ_TIMER0: | 1071 | case IRQ_TIMER0: |
1064 | set_irq_handler(irq, handle_simple_irq); | 1072 | set_irq_handler(irq, handle_simple_irq); |
1065 | break; | 1073 | break; |
1066 | #endif /* !CONFIG_TICKSOURCE_CORETMR */ | 1074 | #endif |
1067 | case IRQ_CORETMR: | 1075 | case IRQ_CORETMR: |
1068 | set_irq_handler(irq, handle_simple_irq); | 1076 | set_irq_handler(irq, handle_simple_irq); |
1069 | break; | 1077 | break; |
@@ -1071,15 +1079,10 @@ int __init init_arch_irq(void) | |||
1071 | set_irq_handler(irq, handle_level_irq); | 1079 | set_irq_handler(irq, handle_level_irq); |
1072 | break; | 1080 | break; |
1073 | #else /* !CONFIG_IPIPE */ | 1081 | #else /* !CONFIG_IPIPE */ |
1074 | #ifdef CONFIG_TICKSOURCE_GPTMR0 | ||
1075 | case IRQ_TIMER0: | ||
1076 | set_irq_handler(irq, handle_percpu_irq); | ||
1077 | break; | ||
1078 | #endif /* CONFIG_TICKSOURCE_GPTMR0 */ | ||
1079 | default: | 1082 | default: |
1080 | set_irq_handler(irq, handle_simple_irq); | 1083 | set_irq_handler(irq, handle_simple_irq); |
1081 | break; | 1084 | break; |
1082 | #endif /* !CONFIG_IPIPE */ | 1085 | #endif /* !CONFIG_IPIPE */ |
1083 | } | 1086 | } |
1084 | } | 1087 | } |
1085 | 1088 | ||
diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S deleted file mode 100644 index 6c5f5f0ea7fe..000000000000 --- a/arch/blackfin/mach-common/lock.S +++ /dev/null | |||
@@ -1,223 +0,0 @@ | |||
1 | /* | ||
2 | * File: arch/blackfin/mach-common/lock.S | ||
3 | * Based on: | ||
4 | * Author: LG Soft India | ||
5 | * | ||
6 | * Created: ? | ||
7 | * Description: kernel locks | ||
8 | * | ||
9 | * Modified: | ||
10 | * Copyright 2004-2006 Analog Devices Inc. | ||
11 | * | ||
12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License as published by | ||
16 | * the Free Software Foundation; either version 2 of the License, or | ||
17 | * (at your option) any later version. | ||
18 | * | ||
19 | * This program is distributed in the hope that it will be useful, | ||
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
22 | * GNU General Public License for more details. | ||
23 | * | ||
24 | * You should have received a copy of the GNU General Public License | ||
25 | * along with this program; if not, see the file COPYING, or write | ||
26 | * to the Free Software Foundation, Inc., | ||
27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
28 | */ | ||
29 | |||
30 | #include <linux/linkage.h> | ||
31 | #include <asm/blackfin.h> | ||
32 | |||
33 | .text | ||
34 | |||
35 | /* When you come here, it is assumed that | ||
36 | * R0 - Which way to be locked | ||
37 | */ | ||
38 | |||
39 | ENTRY(_cache_grab_lock) | ||
40 | |||
41 | [--SP]=( R7:0,P5:0 ); | ||
42 | |||
43 | P1.H = HI(IMEM_CONTROL); | ||
44 | P1.L = LO(IMEM_CONTROL); | ||
45 | P5.H = HI(ICPLB_ADDR0); | ||
46 | P5.L = LO(ICPLB_ADDR0); | ||
47 | P4.H = HI(ICPLB_DATA0); | ||
48 | P4.L = LO(ICPLB_DATA0); | ||
49 | R7 = R0; | ||
50 | |||
51 | /* If the code of interest already resides in the cache | ||
52 | * invalidate the entire cache itself. | ||
53 | * invalidate_entire_icache; | ||
54 | */ | ||
55 | |||
56 | SP += -12; | ||
57 | [--SP] = RETS; | ||
58 | CALL _invalidate_entire_icache; | ||
59 | RETS = [SP++]; | ||
60 | SP += 12; | ||
61 | |||
62 | /* Disable the Interrupts*/ | ||
63 | |||
64 | CLI R3; | ||
65 | |||
66 | .LLOCK_WAY: | ||
67 | |||
68 | /* Way0 - 0xFFA133E0 | ||
69 | * Way1 - 0xFFA137E0 | ||
70 | * Way2 - 0xFFA13BE0 Total Way Size = 4K | ||
71 | * Way3 - 0xFFA13FE0 | ||
72 | */ | ||
73 | |||
74 | /* Procedure Ex. -Set the locks for other ways by setting ILOC[3:1] | ||
75 | * Only Way0 of the instruction cache can now be | ||
76 | * replaced by a new code | ||
77 | */ | ||
78 | |||
79 | R5 = R7; | ||
80 | CC = BITTST(R7,0); | ||
81 | IF CC JUMP .LCLEAR1; | ||
82 | R7 = 0; | ||
83 | BITSET(R7,0); | ||
84 | JUMP .LDONE1; | ||
85 | |||
86 | .LCLEAR1: | ||
87 | R7 = 0; | ||
88 | BITCLR(R7,0); | ||
89 | .LDONE1: R4 = R7 << 3; | ||
90 | R7 = [P1]; | ||
91 | R7 = R7 | R4; | ||
92 | SSYNC; /* SSYNC required writing to IMEM_CONTROL. */ | ||
93 | .align 8; | ||
94 | [P1] = R7; | ||
95 | SSYNC; | ||
96 | |||
97 | R7 = R5; | ||
98 | CC = BITTST(R7,1); | ||
99 | IF CC JUMP .LCLEAR2; | ||
100 | R7 = 0; | ||
101 | BITSET(R7,1); | ||
102 | JUMP .LDONE2; | ||
103 | |||
104 | .LCLEAR2: | ||
105 | R7 = 0; | ||
106 | BITCLR(R7,1); | ||
107 | .LDONE2: R4 = R7 << 3; | ||
108 | R7 = [P1]; | ||
109 | R7 = R7 | R4; | ||
110 | SSYNC; /* SSYNC required writing to IMEM_CONTROL. */ | ||
111 | .align 8; | ||
112 | [P1] = R7; | ||
113 | SSYNC; | ||
114 | |||
115 | R7 = R5; | ||
116 | CC = BITTST(R7,2); | ||
117 | IF CC JUMP .LCLEAR3; | ||
118 | R7 = 0; | ||
119 | BITSET(R7,2); | ||
120 | JUMP .LDONE3; | ||
121 | .LCLEAR3: | ||
122 | R7 = 0; | ||
123 | BITCLR(R7,2); | ||
124 | .LDONE3: R4 = R7 << 3; | ||
125 | R7 = [P1]; | ||
126 | R7 = R7 | R4; | ||
127 | SSYNC; /* SSYNC required writing to IMEM_CONTROL. */ | ||
128 | .align 8; | ||
129 | [P1] = R7; | ||
130 | SSYNC; | ||
131 | |||
132 | |||
133 | R7 = R5; | ||
134 | CC = BITTST(R7,3); | ||
135 | IF CC JUMP .LCLEAR4; | ||
136 | R7 = 0; | ||
137 | BITSET(R7,3); | ||
138 | JUMP .LDONE4; | ||
139 | .LCLEAR4: | ||
140 | R7 = 0; | ||
141 | BITCLR(R7,3); | ||
142 | .LDONE4: R4 = R7 << 3; | ||
143 | R7 = [P1]; | ||
144 | R7 = R7 | R4; | ||
145 | SSYNC; /* SSYNC required writing to IMEM_CONTROL. */ | ||
146 | .align 8; | ||
147 | [P1] = R7; | ||
148 | SSYNC; | ||
149 | |||
150 | STI R3; | ||
151 | |||
152 | ( R7:0,P5:0 ) = [SP++]; | ||
153 | |||
154 | RTS; | ||
155 | ENDPROC(_cache_grab_lock) | ||
156 | |||
157 | /* After the execution of critical code, the code is now locked into | ||
158 | * the cache way. Now we need to set ILOC. | ||
159 | * | ||
160 | * R0 - Which way to be locked | ||
161 | */ | ||
162 | |||
163 | ENTRY(_bfin_cache_lock) | ||
164 | |||
165 | [--SP]=( R7:0,P5:0 ); | ||
166 | |||
167 | P1.H = HI(IMEM_CONTROL); | ||
168 | P1.L = LO(IMEM_CONTROL); | ||
169 | |||
170 | /* Disable the Interrupts*/ | ||
171 | CLI R3; | ||
172 | |||
173 | R7 = [P1]; | ||
174 | R2 = ~(0x78) (X); /* mask out ILOC */ | ||
175 | R7 = R7 & R2; | ||
176 | R0 = R0 << 3; | ||
177 | R7 = R0 | R7; | ||
178 | SSYNC; /* SSYNC required writing to IMEM_CONTROL. */ | ||
179 | .align 8; | ||
180 | [P1] = R7; | ||
181 | SSYNC; | ||
182 | /* Renable the Interrupts */ | ||
183 | STI R3; | ||
184 | |||
185 | ( R7:0,P5:0 ) = [SP++]; | ||
186 | RTS; | ||
187 | ENDPROC(_bfin_cache_lock) | ||
188 | |||
189 | /* Invalidate the Entire Instruction cache by | ||
190 | * disabling IMC bit | ||
191 | */ | ||
192 | ENTRY(_invalidate_entire_icache) | ||
193 | [--SP] = ( R7:5); | ||
194 | |||
195 | P0.L = LO(IMEM_CONTROL); | ||
196 | P0.H = HI(IMEM_CONTROL); | ||
197 | R7 = [P0]; | ||
198 | |||
199 | /* Clear the IMC bit , All valid bits in the instruction | ||
200 | * cache are set to the invalid state | ||
201 | */ | ||
202 | BITCLR(R7,IMC_P); | ||
203 | CLI R6; | ||
204 | SSYNC; /* SSYNC required before invalidating cache. */ | ||
205 | .align 8; | ||
206 | [P0] = R7; | ||
207 | SSYNC; | ||
208 | STI R6; | ||
209 | |||
210 | /* Configures the instruction cache agian */ | ||
211 | R6 = (IMC | ENICPLB); | ||
212 | R7 = R7 | R6; | ||
213 | |||
214 | CLI R6; | ||
215 | SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ | ||
216 | .align 8; | ||
217 | [P0] = R7; | ||
218 | SSYNC; | ||
219 | STI R6; | ||
220 | |||
221 | ( R7:5) = [SP++]; | ||
222 | RTS; | ||
223 | ENDPROC(_invalidate_entire_icache) | ||
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index 9e7e27b7fc8d..0e3d4ff9d8b6 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c | |||
@@ -38,6 +38,7 @@ | |||
38 | #include <linux/io.h> | 38 | #include <linux/io.h> |
39 | #include <linux/irq.h> | 39 | #include <linux/irq.h> |
40 | 40 | ||
41 | #include <asm/cplb.h> | ||
41 | #include <asm/gpio.h> | 42 | #include <asm/gpio.h> |
42 | #include <asm/dma.h> | 43 | #include <asm/dma.h> |
43 | #include <asm/dpmc.h> | 44 | #include <asm/dpmc.h> |
@@ -170,58 +171,6 @@ static void flushinv_all_dcache(void) | |||
170 | } | 171 | } |
171 | #endif | 172 | #endif |
172 | 173 | ||
173 | static inline void dcache_disable(void) | ||
174 | { | ||
175 | #ifdef CONFIG_BFIN_DCACHE | ||
176 | unsigned long ctrl; | ||
177 | |||
178 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) | ||
179 | flushinv_all_dcache(); | ||
180 | #endif | ||
181 | SSYNC(); | ||
182 | ctrl = bfin_read_DMEM_CONTROL(); | ||
183 | ctrl &= ~ENDCPLB; | ||
184 | bfin_write_DMEM_CONTROL(ctrl); | ||
185 | SSYNC(); | ||
186 | #endif | ||
187 | } | ||
188 | |||
189 | static inline void dcache_enable(void) | ||
190 | { | ||
191 | #ifdef CONFIG_BFIN_DCACHE | ||
192 | unsigned long ctrl; | ||
193 | SSYNC(); | ||
194 | ctrl = bfin_read_DMEM_CONTROL(); | ||
195 | ctrl |= ENDCPLB; | ||
196 | bfin_write_DMEM_CONTROL(ctrl); | ||
197 | SSYNC(); | ||
198 | #endif | ||
199 | } | ||
200 | |||
201 | static inline void icache_disable(void) | ||
202 | { | ||
203 | #ifdef CONFIG_BFIN_ICACHE | ||
204 | unsigned long ctrl; | ||
205 | SSYNC(); | ||
206 | ctrl = bfin_read_IMEM_CONTROL(); | ||
207 | ctrl &= ~ENICPLB; | ||
208 | bfin_write_IMEM_CONTROL(ctrl); | ||
209 | SSYNC(); | ||
210 | #endif | ||
211 | } | ||
212 | |||
213 | static inline void icache_enable(void) | ||
214 | { | ||
215 | #ifdef CONFIG_BFIN_ICACHE | ||
216 | unsigned long ctrl; | ||
217 | SSYNC(); | ||
218 | ctrl = bfin_read_IMEM_CONTROL(); | ||
219 | ctrl |= ENICPLB; | ||
220 | bfin_write_IMEM_CONTROL(ctrl); | ||
221 | SSYNC(); | ||
222 | #endif | ||
223 | } | ||
224 | |||
225 | int bfin_pm_suspend_mem_enter(void) | 174 | int bfin_pm_suspend_mem_enter(void) |
226 | { | 175 | { |
227 | unsigned long flags; | 176 | unsigned long flags; |
@@ -258,16 +207,19 @@ int bfin_pm_suspend_mem_enter(void) | |||
258 | 207 | ||
259 | bfin_gpio_pm_hibernate_suspend(); | 208 | bfin_gpio_pm_hibernate_suspend(); |
260 | 209 | ||
261 | dcache_disable(); | 210 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
262 | icache_disable(); | 211 | flushinv_all_dcache(); |
212 | #endif | ||
213 | _disable_dcplb(); | ||
214 | _disable_icplb(); | ||
263 | bf53x_suspend_l1_mem(memptr); | 215 | bf53x_suspend_l1_mem(memptr); |
264 | 216 | ||
265 | do_hibernate(wakeup | vr_wakeup); /* Goodbye */ | 217 | do_hibernate(wakeup | vr_wakeup); /* Goodbye */ |
266 | 218 | ||
267 | bf53x_resume_l1_mem(memptr); | 219 | bf53x_resume_l1_mem(memptr); |
268 | 220 | ||
269 | icache_enable(); | 221 | _enable_icplb(); |
270 | dcache_enable(); | 222 | _enable_dcplb(); |
271 | 223 | ||
272 | bfin_gpio_pm_hibernate_restore(); | 224 | bfin_gpio_pm_hibernate_restore(); |
273 | blackfin_dma_resume(); | 225 | blackfin_dma_resume(); |
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index 68bd0bd680cd..b88ce7fda548 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c | |||
@@ -33,6 +33,7 @@ | |||
33 | #include <asm/bfin-global.h> | 33 | #include <asm/bfin-global.h> |
34 | #include <asm/pda.h> | 34 | #include <asm/pda.h> |
35 | #include <asm/cplbinit.h> | 35 | #include <asm/cplbinit.h> |
36 | #include <asm/early_printk.h> | ||
36 | #include "blackfin_sram.h" | 37 | #include "blackfin_sram.h" |
37 | 38 | ||
38 | /* | 39 | /* |
@@ -113,6 +114,8 @@ asmlinkage void __init init_pda(void) | |||
113 | { | 114 | { |
114 | unsigned int cpu = raw_smp_processor_id(); | 115 | unsigned int cpu = raw_smp_processor_id(); |
115 | 116 | ||
117 | early_shadow_stamp(); | ||
118 | |||
116 | /* Initialize the PDA fields holding references to other parts | 119 | /* Initialize the PDA fields holding references to other parts |
117 | of the memory. The content of such memory is still | 120 | of the memory. The content of such memory is still |
118 | undefined at the time of the call, we are only setting up | 121 | undefined at the time of the call, we are only setting up |
diff --git a/arch/blackfin/mm/isram-driver.c b/arch/blackfin/mm/isram-driver.c index c080e70f98b0..beb1a608824c 100644 --- a/arch/blackfin/mm/isram-driver.c +++ b/arch/blackfin/mm/isram-driver.c | |||
@@ -16,6 +16,8 @@ | |||
16 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | 16 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
17 | */ | 17 | */ |
18 | 18 | ||
19 | #define pr_fmt(fmt) "isram: " fmt | ||
20 | |||
19 | #include <linux/module.h> | 21 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
21 | #include <linux/types.h> | 23 | #include <linux/types.h> |
@@ -23,6 +25,7 @@ | |||
23 | #include <linux/sched.h> | 25 | #include <linux/sched.h> |
24 | 26 | ||
25 | #include <asm/blackfin.h> | 27 | #include <asm/blackfin.h> |
28 | #include <asm/dma.h> | ||
26 | 29 | ||
27 | /* | 30 | /* |
28 | * IMPORTANT WARNING ABOUT THESE FUNCTIONS | 31 | * IMPORTANT WARNING ABOUT THESE FUNCTIONS |
@@ -50,10 +53,12 @@ static DEFINE_SPINLOCK(dtest_lock); | |||
50 | #define IADDR2DTEST(x) \ | 53 | #define IADDR2DTEST(x) \ |
51 | ({ unsigned long __addr = (unsigned long)(x); \ | 54 | ({ unsigned long __addr = (unsigned long)(x); \ |
52 | (__addr & 0x47F8) | /* address bits 14 & 10:3 */ \ | 55 | (__addr & 0x47F8) | /* address bits 14 & 10:3 */ \ |
56 | (__addr & 0x8000) << 23 | /* Bank A/B */ \ | ||
53 | (__addr & 0x0800) << 15 | /* address bit 11 */ \ | 57 | (__addr & 0x0800) << 15 | /* address bit 11 */ \ |
54 | (__addr & 0x3000) << 4 | /* address bits 13:12 */ \ | 58 | (__addr & 0x3000) << 4 | /* address bits 13:12 */ \ |
55 | (__addr & 0x8000) << 8 | /* address bit 15 */ \ | 59 | (__addr & 0x8000) << 8 | /* address bit 15 */ \ |
56 | (0x1000004); /* isram access */ \ | 60 | (0x1000000) | /* instruction access = 1 */ \ |
61 | (0x4); /* data array = 1 */ \ | ||
57 | }) | 62 | }) |
58 | 63 | ||
59 | /* Takes a pointer, and returns the offset (in bits) which things should be shifted */ | 64 | /* Takes a pointer, and returns the offset (in bits) which things should be shifted */ |
@@ -70,7 +75,7 @@ static void isram_write(const void *addr, uint64_t data) | |||
70 | if (addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH)) | 75 | if (addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH)) |
71 | return; | 76 | return; |
72 | 77 | ||
73 | cmd = IADDR2DTEST(addr) | 1; /* write */ | 78 | cmd = IADDR2DTEST(addr) | 2; /* write */ |
74 | 79 | ||
75 | /* | 80 | /* |
76 | * Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND | 81 | * Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND |
@@ -127,8 +132,7 @@ static bool isram_check_addr(const void *addr, size_t n) | |||
127 | (addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) { | 132 | (addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) { |
128 | if ((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH)) { | 133 | if ((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH)) { |
129 | show_stack(NULL, NULL); | 134 | show_stack(NULL, NULL); |
130 | printk(KERN_ERR "isram_memcpy: copy involving %p length " | 135 | pr_err("copy involving %p length (%zu) too long\n", addr, n); |
131 | "(%zu) too long\n", addr, n); | ||
132 | } | 136 | } |
133 | return true; | 137 | return true; |
134 | } | 138 | } |
@@ -199,3 +203,209 @@ void *isram_memcpy(void *dest, const void *src, size_t n) | |||
199 | } | 203 | } |
200 | EXPORT_SYMBOL(isram_memcpy); | 204 | EXPORT_SYMBOL(isram_memcpy); |
201 | 205 | ||
206 | #ifdef CONFIG_BFIN_ISRAM_SELF_TEST | ||
207 | |||
208 | #define TEST_LEN 0x100 | ||
209 | |||
210 | static __init void hex_dump(unsigned char *buf, int len) | ||
211 | { | ||
212 | while (len--) | ||
213 | pr_cont("%02x", *buf++); | ||
214 | } | ||
215 | |||
216 | static __init int isram_read_test(char *sdram, void *l1inst) | ||
217 | { | ||
218 | int i, ret = 0; | ||
219 | uint64_t data1, data2; | ||
220 | |||
221 | pr_info("INFO: running isram_read tests\n"); | ||
222 | |||
223 | /* setup some different data to play with */ | ||
224 | for (i = 0; i < TEST_LEN; ++i) | ||
225 | sdram[i] = i; | ||
226 | dma_memcpy(l1inst, sdram, TEST_LEN); | ||
227 | |||
228 | /* make sure we can read the L1 inst */ | ||
229 | for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) { | ||
230 | data1 = isram_read(l1inst + i); | ||
231 | memcpy(&data2, sdram + i, sizeof(data2)); | ||
232 | if (memcmp(&data1, &data2, sizeof(uint64_t))) { | ||
233 | pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n", | ||
234 | l1inst + i, data1, data2); | ||
235 | ++ret; | ||
236 | } | ||
237 | } | ||
238 | |||
239 | return ret; | ||
240 | } | ||
241 | |||
242 | static __init int isram_write_test(char *sdram, void *l1inst) | ||
243 | { | ||
244 | int i, ret = 0; | ||
245 | uint64_t data1, data2; | ||
246 | |||
247 | pr_info("INFO: running isram_write tests\n"); | ||
248 | |||
249 | /* setup some different data to play with */ | ||
250 | memset(sdram, 0, TEST_LEN * 2); | ||
251 | dma_memcpy(l1inst, sdram, TEST_LEN); | ||
252 | for (i = 0; i < TEST_LEN; ++i) | ||
253 | sdram[i] = i; | ||
254 | |||
255 | /* make sure we can write the L1 inst */ | ||
256 | for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) { | ||
257 | memcpy(&data1, sdram + i, sizeof(data1)); | ||
258 | isram_write(l1inst + i, data1); | ||
259 | data2 = isram_read(l1inst + i); | ||
260 | if (memcmp(&data1, &data2, sizeof(uint64_t))) { | ||
261 | pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n", | ||
262 | l1inst + i, data1, data2); | ||
263 | ++ret; | ||
264 | } | ||
265 | } | ||
266 | |||
267 | dma_memcpy(sdram + TEST_LEN, l1inst, TEST_LEN); | ||
268 | if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) { | ||
269 | pr_err("FAIL: isram_write() did not work properly\n"); | ||
270 | ++ret; | ||
271 | } | ||
272 | |||
273 | return ret; | ||
274 | } | ||
275 | |||
276 | static __init int | ||
277 | _isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy, | ||
278 | void *(*fmemcpy)(void *, const void *, size_t)) | ||
279 | { | ||
280 | memset(sdram, pattern, TEST_LEN); | ||
281 | fmemcpy(l1inst, sdram, TEST_LEN); | ||
282 | fmemcpy(sdram + TEST_LEN, l1inst, TEST_LEN); | ||
283 | if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) { | ||
284 | pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n", | ||
285 | smemcpy, l1inst, sdram, TEST_LEN, pattern); | ||
286 | return 1; | ||
287 | } | ||
288 | return 0; | ||
289 | } | ||
290 | #define _isram_memcpy_test(a, b, c, d) _isram_memcpy_test(a, b, c, #d, d) | ||
291 | |||
292 | static __init int isram_memcpy_test(char *sdram, void *l1inst) | ||
293 | { | ||
294 | int i, j, thisret, ret = 0; | ||
295 | |||
296 | /* check broad isram_memcpy() */ | ||
297 | pr_info("INFO: running broad isram_memcpy tests\n"); | ||
298 | for (i = 0xf; i >= 0; --i) | ||
299 | ret += _isram_memcpy_test(i, sdram, l1inst, isram_memcpy); | ||
300 | |||
301 | /* check read of small, unaligned, and hardware 64bit limits */ | ||
302 | pr_info("INFO: running isram_memcpy (read) tests\n"); | ||
303 | |||
304 | for (i = 0; i < TEST_LEN; ++i) | ||
305 | sdram[i] = i; | ||
306 | dma_memcpy(l1inst, sdram, TEST_LEN); | ||
307 | |||
308 | thisret = 0; | ||
309 | for (i = 0; i < TEST_LEN - 32; ++i) { | ||
310 | unsigned char cmp[32]; | ||
311 | for (j = 1; j <= 32; ++j) { | ||
312 | memset(cmp, 0, sizeof(cmp)); | ||
313 | isram_memcpy(cmp, l1inst + i, j); | ||
314 | if (memcmp(cmp, sdram + i, j)) { | ||
315 | pr_err("FAIL: %p:", l1inst + 1); | ||
316 | hex_dump(cmp, j); | ||
317 | pr_cont(" SDRAM:"); | ||
318 | hex_dump(sdram + i, j); | ||
319 | pr_cont("\n"); | ||
320 | if (++thisret > 20) { | ||
321 | pr_err("FAIL: skipping remaining series\n"); | ||
322 | i = TEST_LEN; | ||
323 | break; | ||
324 | } | ||
325 | } | ||
326 | } | ||
327 | } | ||
328 | ret += thisret; | ||
329 | |||
330 | /* check write of small, unaligned, and hardware 64bit limits */ | ||
331 | pr_info("INFO: running isram_memcpy (write) tests\n"); | ||
332 | |||
333 | memset(sdram + TEST_LEN, 0, TEST_LEN); | ||
334 | dma_memcpy(l1inst, sdram + TEST_LEN, TEST_LEN); | ||
335 | |||
336 | thisret = 0; | ||
337 | for (i = 0; i < TEST_LEN - 32; ++i) { | ||
338 | unsigned char cmp[32]; | ||
339 | for (j = 1; j <= 32; ++j) { | ||
340 | isram_memcpy(l1inst + i, sdram + i, j); | ||
341 | dma_memcpy(cmp, l1inst + i, j); | ||
342 | if (memcmp(cmp, sdram + i, j)) { | ||
343 | pr_err("FAIL: %p:", l1inst + i); | ||
344 | hex_dump(cmp, j); | ||
345 | pr_cont(" SDRAM:"); | ||
346 | hex_dump(sdram + i, j); | ||
347 | pr_cont("\n"); | ||
348 | if (++thisret > 20) { | ||
349 | pr_err("FAIL: skipping remaining series\n"); | ||
350 | i = TEST_LEN; | ||
351 | break; | ||
352 | } | ||
353 | } | ||
354 | } | ||
355 | } | ||
356 | ret += thisret; | ||
357 | |||
358 | return ret; | ||
359 | } | ||
360 | |||
361 | static __init int isram_test_init(void) | ||
362 | { | ||
363 | int ret; | ||
364 | char *sdram; | ||
365 | void *l1inst; | ||
366 | |||
367 | sdram = kmalloc(TEST_LEN * 2, GFP_KERNEL); | ||
368 | if (!sdram) { | ||
369 | pr_warning("SKIP: could not allocate sdram\n"); | ||
370 | return 0; | ||
371 | } | ||
372 | |||
373 | l1inst = l1_inst_sram_alloc(TEST_LEN); | ||
374 | if (!l1inst) { | ||
375 | kfree(sdram); | ||
376 | pr_warning("SKIP: could not allocate L1 inst\n"); | ||
377 | return 0; | ||
378 | } | ||
379 | |||
380 | /* sanity check initial L1 inst state */ | ||
381 | ret = 1; | ||
382 | pr_info("INFO: running initial dma_memcpy checks\n"); | ||
383 | if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy)) | ||
384 | goto abort; | ||
385 | if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy)) | ||
386 | goto abort; | ||
387 | |||
388 | ret = 0; | ||
389 | ret += isram_read_test(sdram, l1inst); | ||
390 | ret += isram_write_test(sdram, l1inst); | ||
391 | ret += isram_memcpy_test(sdram, l1inst); | ||
392 | |||
393 | abort: | ||
394 | sram_free(l1inst); | ||
395 | kfree(sdram); | ||
396 | |||
397 | if (ret) | ||
398 | return -EIO; | ||
399 | |||
400 | pr_info("PASS: all tests worked !\n"); | ||
401 | return 0; | ||
402 | } | ||
403 | late_initcall(isram_test_init); | ||
404 | |||
405 | static __exit void isram_test_exit(void) | ||
406 | { | ||
407 | /* stub to allow unloading */ | ||
408 | } | ||
409 | module_exit(isram_test_exit); | ||
410 | |||
411 | #endif | ||
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c index 99e4dbb1dfd1..eb63ab353e5a 100644 --- a/arch/blackfin/mm/sram-alloc.c +++ b/arch/blackfin/mm/sram-alloc.c | |||
@@ -42,11 +42,6 @@ | |||
42 | #include <asm/mem_map.h> | 42 | #include <asm/mem_map.h> |
43 | #include "blackfin_sram.h" | 43 | #include "blackfin_sram.h" |
44 | 44 | ||
45 | static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1sram_lock); | ||
46 | static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_data_sram_lock); | ||
47 | static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_inst_sram_lock); | ||
48 | static spinlock_t l2_sram_lock ____cacheline_aligned_in_smp; | ||
49 | |||
50 | /* the data structure for L1 scratchpad and DATA SRAM */ | 45 | /* the data structure for L1 scratchpad and DATA SRAM */ |
51 | struct sram_piece { | 46 | struct sram_piece { |
52 | void *paddr; | 47 | void *paddr; |
@@ -55,6 +50,7 @@ struct sram_piece { | |||
55 | struct sram_piece *next; | 50 | struct sram_piece *next; |
56 | }; | 51 | }; |
57 | 52 | ||
53 | static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1sram_lock); | ||
58 | static DEFINE_PER_CPU(struct sram_piece, free_l1_ssram_head); | 54 | static DEFINE_PER_CPU(struct sram_piece, free_l1_ssram_head); |
59 | static DEFINE_PER_CPU(struct sram_piece, used_l1_ssram_head); | 55 | static DEFINE_PER_CPU(struct sram_piece, used_l1_ssram_head); |
60 | 56 | ||
@@ -68,12 +64,18 @@ static DEFINE_PER_CPU(struct sram_piece, free_l1_data_B_sram_head); | |||
68 | static DEFINE_PER_CPU(struct sram_piece, used_l1_data_B_sram_head); | 64 | static DEFINE_PER_CPU(struct sram_piece, used_l1_data_B_sram_head); |
69 | #endif | 65 | #endif |
70 | 66 | ||
67 | #if L1_DATA_A_LENGTH || L1_DATA_B_LENGTH | ||
68 | static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_data_sram_lock); | ||
69 | #endif | ||
70 | |||
71 | #if L1_CODE_LENGTH != 0 | 71 | #if L1_CODE_LENGTH != 0 |
72 | static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_inst_sram_lock); | ||
72 | static DEFINE_PER_CPU(struct sram_piece, free_l1_inst_sram_head); | 73 | static DEFINE_PER_CPU(struct sram_piece, free_l1_inst_sram_head); |
73 | static DEFINE_PER_CPU(struct sram_piece, used_l1_inst_sram_head); | 74 | static DEFINE_PER_CPU(struct sram_piece, used_l1_inst_sram_head); |
74 | #endif | 75 | #endif |
75 | 76 | ||
76 | #if L2_LENGTH != 0 | 77 | #if L2_LENGTH != 0 |
78 | static spinlock_t l2_sram_lock ____cacheline_aligned_in_smp; | ||
77 | static struct sram_piece free_l2_sram_head, used_l2_sram_head; | 79 | static struct sram_piece free_l2_sram_head, used_l2_sram_head; |
78 | #endif | 80 | #endif |
79 | 81 | ||
@@ -225,10 +227,10 @@ static void __init l2_sram_init(void) | |||
225 | printk(KERN_INFO "Blackfin L2 SRAM: %d KB (%d KB free)\n", | 227 | printk(KERN_INFO "Blackfin L2 SRAM: %d KB (%d KB free)\n", |
226 | L2_LENGTH >> 10, | 228 | L2_LENGTH >> 10, |
227 | free_l2_sram_head.next->size >> 10); | 229 | free_l2_sram_head.next->size >> 10); |
228 | #endif | ||
229 | 230 | ||
230 | /* mutex initialize */ | 231 | /* mutex initialize */ |
231 | spin_lock_init(&l2_sram_lock); | 232 | spin_lock_init(&l2_sram_lock); |
233 | #endif | ||
232 | } | 234 | } |
233 | 235 | ||
234 | static int __init bfin_sram_init(void) | 236 | static int __init bfin_sram_init(void) |
@@ -416,18 +418,17 @@ EXPORT_SYMBOL(sram_free); | |||
416 | 418 | ||
417 | void *l1_data_A_sram_alloc(size_t size) | 419 | void *l1_data_A_sram_alloc(size_t size) |
418 | { | 420 | { |
421 | #if L1_DATA_A_LENGTH != 0 | ||
419 | unsigned long flags; | 422 | unsigned long flags; |
420 | void *addr = NULL; | 423 | void *addr; |
421 | unsigned int cpu; | 424 | unsigned int cpu; |
422 | 425 | ||
423 | cpu = get_cpu(); | 426 | cpu = get_cpu(); |
424 | /* add mutex operation */ | 427 | /* add mutex operation */ |
425 | spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags); | 428 | spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags); |
426 | 429 | ||
427 | #if L1_DATA_A_LENGTH != 0 | ||
428 | addr = _sram_alloc(size, &per_cpu(free_l1_data_A_sram_head, cpu), | 430 | addr = _sram_alloc(size, &per_cpu(free_l1_data_A_sram_head, cpu), |
429 | &per_cpu(used_l1_data_A_sram_head, cpu)); | 431 | &per_cpu(used_l1_data_A_sram_head, cpu)); |
430 | #endif | ||
431 | 432 | ||
432 | /* add mutex operation */ | 433 | /* add mutex operation */ |
433 | spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags); | 434 | spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags); |
@@ -437,11 +438,15 @@ void *l1_data_A_sram_alloc(size_t size) | |||
437 | (long unsigned int)addr, size); | 438 | (long unsigned int)addr, size); |
438 | 439 | ||
439 | return addr; | 440 | return addr; |
441 | #else | ||
442 | return NULL; | ||
443 | #endif | ||
440 | } | 444 | } |
441 | EXPORT_SYMBOL(l1_data_A_sram_alloc); | 445 | EXPORT_SYMBOL(l1_data_A_sram_alloc); |
442 | 446 | ||
443 | int l1_data_A_sram_free(const void *addr) | 447 | int l1_data_A_sram_free(const void *addr) |
444 | { | 448 | { |
449 | #if L1_DATA_A_LENGTH != 0 | ||
445 | unsigned long flags; | 450 | unsigned long flags; |
446 | int ret; | 451 | int ret; |
447 | unsigned int cpu; | 452 | unsigned int cpu; |
@@ -450,18 +455,17 @@ int l1_data_A_sram_free(const void *addr) | |||
450 | /* add mutex operation */ | 455 | /* add mutex operation */ |
451 | spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags); | 456 | spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags); |
452 | 457 | ||
453 | #if L1_DATA_A_LENGTH != 0 | ||
454 | ret = _sram_free(addr, &per_cpu(free_l1_data_A_sram_head, cpu), | 458 | ret = _sram_free(addr, &per_cpu(free_l1_data_A_sram_head, cpu), |
455 | &per_cpu(used_l1_data_A_sram_head, cpu)); | 459 | &per_cpu(used_l1_data_A_sram_head, cpu)); |
456 | #else | ||
457 | ret = -1; | ||
458 | #endif | ||
459 | 460 | ||
460 | /* add mutex operation */ | 461 | /* add mutex operation */ |
461 | spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags); | 462 | spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags); |
462 | put_cpu(); | 463 | put_cpu(); |
463 | 464 | ||
464 | return ret; | 465 | return ret; |
466 | #else | ||
467 | return -1; | ||
468 | #endif | ||
465 | } | 469 | } |
466 | EXPORT_SYMBOL(l1_data_A_sram_free); | 470 | EXPORT_SYMBOL(l1_data_A_sram_free); |
467 | 471 | ||