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-rw-r--r--arch/blackfin/Kconfig59
-rw-r--r--arch/blackfin/Makefile2
-rw-r--r--arch/blackfin/boot/Makefile3
-rw-r--r--arch/blackfin/configs/BF548-EZKIT_defconfig1100
-rw-r--r--arch/blackfin/kernel/Makefile7
-rw-r--r--arch/blackfin/kernel/asm-offsets.c7
-rw-r--r--arch/blackfin/kernel/bfin_dma_5xx.c251
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c11
-rw-r--r--arch/blackfin/kernel/bfin_ksyms.c5
-rw-r--r--arch/blackfin/kernel/cacheinit.c66
-rw-r--r--arch/blackfin/kernel/cplbinit.c433
-rw-r--r--arch/blackfin/kernel/dma-mapping.c13
-rw-r--r--arch/blackfin/kernel/dualcore_test.c6
-rw-r--r--arch/blackfin/kernel/fixed_code.S132
-rw-r--r--arch/blackfin/kernel/flat.c55
-rw-r--r--arch/blackfin/kernel/irqchip.c2
-rw-r--r--arch/blackfin/kernel/kgdb.c421
-rw-r--r--arch/blackfin/kernel/module.c32
-rw-r--r--arch/blackfin/kernel/process.c75
-rw-r--r--arch/blackfin/kernel/ptrace.c6
-rw-r--r--arch/blackfin/kernel/setup.c368
-rw-r--r--arch/blackfin/kernel/signal.c10
-rw-r--r--arch/blackfin/kernel/sys_bfin.c8
-rw-r--r--arch/blackfin/kernel/time.c4
-rw-r--r--arch/blackfin/kernel/traps.c62
-rw-r--r--arch/blackfin/kernel/vmlinux.lds.S12
-rw-r--r--arch/blackfin/lib/strcmp.c3
-rw-r--r--arch/blackfin/lib/strcpy.c3
-rw-r--r--arch/blackfin/lib/strncmp.c3
-rw-r--r--arch/blackfin/lib/strncpy.c3
-rw-r--r--arch/blackfin/mach-bf533/Makefile4
-rw-r--r--arch/blackfin/mach-bf533/boards/cm_bf533.c14
-rw-r--r--arch/blackfin/mach-bf533/boards/ezkit.c8
-rw-r--r--arch/blackfin/mach-bf533/boards/generic_board.c6
-rw-r--r--arch/blackfin/mach-bf533/boards/stamp.c30
-rw-r--r--arch/blackfin/mach-bf533/cpu.c3
-rw-r--r--arch/blackfin/mach-bf533/dma.c95
-rw-r--r--arch/blackfin/mach-bf533/head.S5
-rw-r--r--arch/blackfin/mach-bf533/ints-priority.c2
-rw-r--r--arch/blackfin/mach-bf537/Makefile2
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537.c16
-rw-r--r--arch/blackfin/mach-bf537/boards/eth_mac.c5
-rw-r--r--arch/blackfin/mach-bf537/boards/generic_board.c36
-rw-r--r--arch/blackfin/mach-bf537/boards/pnav10.c54
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c77
-rw-r--r--arch/blackfin/mach-bf537/dma.c115
-rw-r--r--arch/blackfin/mach-bf537/head.S6
-rw-r--r--arch/blackfin/mach-bf537/ints-priority.c2
-rw-r--r--arch/blackfin/mach-bf548/Kconfig316
-rw-r--r--arch/blackfin/mach-bf548/Makefile9
-rw-r--r--arch/blackfin/mach-bf548/boards/Makefile5
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c114
-rw-r--r--arch/blackfin/mach-bf548/boards/led.S172
-rw-r--r--arch/blackfin/mach-bf548/cpu.c159
-rw-r--r--arch/blackfin/mach-bf548/dma.c156
-rw-r--r--arch/blackfin/mach-bf548/gpio.c323
-rw-r--r--arch/blackfin/mach-bf548/head.S512
-rw-r--r--arch/blackfin/mach-bf548/ints-priority.c137
-rw-r--r--arch/blackfin/mach-bf561/Makefile2
-rw-r--r--arch/blackfin/mach-bf561/boards/cm_bf561.c32
-rw-r--r--arch/blackfin/mach-bf561/boards/ezkit.c33
-rw-r--r--arch/blackfin/mach-bf561/boards/generic_board.c6
-rw-r--r--arch/blackfin/mach-bf561/boards/tepla.c6
-rw-r--r--arch/blackfin/mach-bf561/coreb.c18
-rw-r--r--arch/blackfin/mach-bf561/dma.c131
-rw-r--r--arch/blackfin/mach-bf561/head.S6
-rw-r--r--arch/blackfin/mach-bf561/ints-priority.c2
-rw-r--r--arch/blackfin/mach-common/Makefile4
-rw-r--r--arch/blackfin/mach-common/cacheinit.S89
-rw-r--r--arch/blackfin/mach-common/cplbinfo.c13
-rw-r--r--arch/blackfin/mach-common/entry.S76
-rw-r--r--arch/blackfin/mach-common/interrupt.S8
-rw-r--r--arch/blackfin/mach-common/ints-priority-dc.c13
-rw-r--r--arch/blackfin/mach-common/ints-priority-sc.c405
-rw-r--r--arch/blackfin/mach-common/pm.c4
-rw-r--r--arch/blackfin/mm/blackfin_sram.c4
-rw-r--r--arch/blackfin/mm/init.c47
-rw-r--r--arch/blackfin/oprofile/common.c6
-rw-r--r--arch/blackfin/oprofile/op_model_bf533.c6
-rw-r--r--arch/blackfin/oprofile/timer_int.c3
80 files changed, 5359 insertions, 1100 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index d98bafcaca59..017defaa525b 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -71,6 +71,7 @@ config GENERIC_CALIBRATE_DELAY
71 71
72config IRQCHIP_DEMUX_GPIO 72config IRQCHIP_DEMUX_GPIO
73 bool 73 bool
74 depends on (BF53x || BF561 || BF54x)
74 default y 75 default y
75 76
76source "init/Kconfig" 77source "init/Kconfig"
@@ -114,6 +115,26 @@ config BF537
114 help 115 help
115 BF537 Processor Support. 116 BF537 Processor Support.
116 117
118config BF542
119 bool "BF542"
120 help
121 BF542 Processor Support.
122
123config BF544
124 bool "BF544"
125 help
126 BF544 Processor Support.
127
128config BF548
129 bool "BF548"
130 help
131 BF548 Processor Support.
132
133config BF549
134 bool "BF549"
135 help
136 BF549 Processor Support.
137
117config BF561 138config BF561
118 bool "BF561" 139 bool "BF561"
119 help 140 help
@@ -125,6 +146,11 @@ choice
125 prompt "Silicon Rev" 146 prompt "Silicon Rev"
126 default BF_REV_0_2 if BF537 147 default BF_REV_0_2 if BF537
127 default BF_REV_0_3 if BF533 148 default BF_REV_0_3 if BF533
149 default BF_REV_0_0 if BF549
150
151config BF_REV_0_0
152 bool "0.0"
153 depends on (BF549)
128 154
129config BF_REV_0_2 155config BF_REV_0_2
130 bool "0.2" 156 bool "0.2"
@@ -150,6 +176,16 @@ config BF_REV_NONE
150 176
151endchoice 177endchoice
152 178
179config BF53x
180 bool
181 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
182 default y
183
184config BF54x
185 bool
186 depends on (BF542 || BF544 || BF548 || BF549)
187 default y
188
153config BFIN_DUAL_CORE 189config BFIN_DUAL_CORE
154 bool 190 bool
155 depends on (BF561) 191 depends on (BF561)
@@ -198,6 +234,12 @@ config BFIN537_BLUETECHNIX_CM
198 help 234 help
199 CM-BF537 support for EVAL- and DEV-Board. 235 CM-BF537 support for EVAL- and DEV-Board.
200 236
237config BFIN548_EZKIT
238 bool "BF548-EZKIT"
239 depends on (BF548 || BF549)
240 help
241 BFIN548-EZKIT board Support.
242
201config BFIN561_BLUETECHNIX_CM 243config BFIN561_BLUETECHNIX_CM
202 bool "Bluetechnix CM-BF561" 244 bool "Bluetechnix CM-BF561"
203 depends on (BF561) 245 depends on (BF561)
@@ -265,6 +307,7 @@ config BFIN_SHARED_FLASH_ENET
265source "arch/blackfin/mach-bf533/Kconfig" 307source "arch/blackfin/mach-bf533/Kconfig"
266source "arch/blackfin/mach-bf561/Kconfig" 308source "arch/blackfin/mach-bf561/Kconfig"
267source "arch/blackfin/mach-bf537/Kconfig" 309source "arch/blackfin/mach-bf537/Kconfig"
310source "arch/blackfin/mach-bf548/Kconfig"
268 311
269menu "Board customizations" 312menu "Board customizations"
270 313
@@ -497,7 +540,8 @@ config IP_CHECKSUM_L1
497 540
498config CACHELINE_ALIGNED_L1 541config CACHELINE_ALIGNED_L1
499 bool "Locate cacheline_aligned data to L1 Data Memory" 542 bool "Locate cacheline_aligned data to L1 Data Memory"
500 default y 543 default y if !BF54x
544 default n if BF54x
501 depends on !BF531 545 depends on !BF531
502 help 546 help
503 If enabled cacheline_anligned data is linked 547 If enabled cacheline_anligned data is linked
@@ -541,9 +585,17 @@ endchoice
541 585
542source "mm/Kconfig" 586source "mm/Kconfig"
543 587
588config LARGE_ALLOCS
589 bool "Allow allocating large blocks (> 1MB) of memory"
590 help
591 Allow the slab memory allocator to keep chains for very large
592 memory sizes - upto 32MB. You may need this if your system has
593 a lot of RAM, and you need to able to allocate very large
594 contiguous chunks. If unsure, say N.
595
544config BFIN_DMA_5XX 596config BFIN_DMA_5XX
545 bool "Enable DMA Support" 597 bool "Enable DMA Support"
546 depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561) 598 depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561 || BF54x)
547 default y 599 default y
548 help 600 help
549 DMA driver for BF5xx. 601 DMA driver for BF5xx.
@@ -686,6 +738,7 @@ config C_AMCKEN
686 738
687config C_CDPRIO 739config C_CDPRIO
688 bool "DMA has priority over core for ext. accesses" 740 bool "DMA has priority over core for ext. accesses"
741 depends on !BF54x
689 default n 742 default n
690 743
691config C_B0PEN 744config C_B0PEN
@@ -839,7 +892,7 @@ endchoice
839 892
840endmenu 893endmenu
841 894
842if (BF537 || BF533) 895if (BF537 || BF533 || BF54x)
843 896
844menu "CPU Frequency scaling" 897menu "CPU Frequency scaling"
845 898
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 6971a4418dfe..1b75672dfc8f 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -24,6 +24,8 @@ machine-$(CONFIG_BF533) := bf533
24machine-$(CONFIG_BF534) := bf537 24machine-$(CONFIG_BF534) := bf537
25machine-$(CONFIG_BF536) := bf537 25machine-$(CONFIG_BF536) := bf537
26machine-$(CONFIG_BF537) := bf537 26machine-$(CONFIG_BF537) := bf537
27machine-$(CONFIG_BF548) := bf548
28machine-$(CONFIG_BF549) := bf548
27machine-$(CONFIG_BF561) := bf561 29machine-$(CONFIG_BF561) := bf561
28MACHINE := $(machine-y) 30MACHINE := $(machine-y)
29export MACHINE 31export MACHINE
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index 49e8098d4c21..8cd33560e817 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -13,7 +13,8 @@ extra-y += vmlinux.bin vmlinux.gz
13 13
14quiet_cmd_uimage = UIMAGE $@ 14quiet_cmd_uimage = UIMAGE $@
15 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \ 15 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
16 -C gzip -a $(CONFIG_BOOT_LOAD) -e $(CONFIG_BOOT_LOAD) -n 'Linux-$(KERNELRELEASE)' \ 16 -C gzip -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \
17 -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
17 -d $< $@ 18 -d $< $@
18 19
19$(obj)/vmlinux.bin: vmlinux FORCE 20$(obj)/vmlinux.bin: vmlinux FORCE
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
new file mode 100644
index 000000000000..ac8390fafa9c
--- /dev/null
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -0,0 +1,1100 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.21.5
4#
5# CONFIG_MMU is not set
6# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y
8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
9CONFIG_BLACKFIN=y
10CONFIG_ZONE_DMA=y
11CONFIG_BFIN=y
12CONFIG_SEMAPHORE_SLEEPERS=y
13CONFIG_GENERIC_FIND_NEXT_BIT=y
14CONFIG_GENERIC_HWEIGHT=y
15CONFIG_GENERIC_HARDIRQS=y
16CONFIG_GENERIC_IRQ_PROBE=y
17# CONFIG_GENERIC_TIME is not set
18CONFIG_GENERIC_CALIBRATE_DELAY=y
19CONFIG_FORCE_MAX_ZONEORDER=14
20CONFIG_IRQCHIP_DEMUX_GPIO=y
21CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
22
23#
24# Code maturity level options
25#
26CONFIG_EXPERIMENTAL=y
27CONFIG_BROKEN_ON_SMP=y
28CONFIG_INIT_ENV_ARG_LIMIT=32
29
30#
31# General setup
32#
33CONFIG_LOCALVERSION=""
34CONFIG_LOCALVERSION_AUTO=y
35CONFIG_SYSVIPC=y
36# CONFIG_IPC_NS is not set
37CONFIG_SYSVIPC_SYSCTL=y
38# CONFIG_POSIX_MQUEUE is not set
39# CONFIG_BSD_PROCESS_ACCT is not set
40# CONFIG_TASKSTATS is not set
41# CONFIG_UTS_NS is not set
42# CONFIG_AUDIT is not set
43# CONFIG_IKCONFIG is not set
44CONFIG_SYSFS_DEPRECATED=y
45# CONFIG_RELAY is not set
46CONFIG_BLK_DEV_INITRD=y
47CONFIG_INITRAMFS_SOURCE=""
48# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
49CONFIG_SYSCTL=y
50CONFIG_EMBEDDED=y
51CONFIG_UID16=y
52CONFIG_SYSCTL_SYSCALL=y
53CONFIG_KALLSYMS=y
54# CONFIG_KALLSYMS_ALL is not set
55# CONFIG_KALLSYMS_EXTRA_PASS is not set
56CONFIG_HOTPLUG=y
57CONFIG_PRINTK=y
58CONFIG_BUG=y
59CONFIG_ELF_CORE=y
60CONFIG_BASE_FULL=y
61CONFIG_FUTEX=y
62CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
63# CONFIG_NP2 is not set
64CONFIG_SLAB=y
65CONFIG_VM_EVENT_COUNTERS=y
66CONFIG_RT_MUTEXES=y
67CONFIG_TINY_SHMEM=y
68CONFIG_BASE_SMALL=0
69# CONFIG_SLOB is not set
70
71#
72# Loadable module support
73#
74CONFIG_MODULES=y
75CONFIG_MODULE_UNLOAD=y
76# CONFIG_MODULE_FORCE_UNLOAD is not set
77# CONFIG_MODVERSIONS is not set
78# CONFIG_MODULE_SRCVERSION_ALL is not set
79CONFIG_KMOD=y
80
81#
82# Block layer
83#
84CONFIG_BLOCK=y
85# CONFIG_LBD is not set
86# CONFIG_BLK_DEV_IO_TRACE is not set
87# CONFIG_LSF is not set
88
89#
90# IO Schedulers
91#
92CONFIG_IOSCHED_NOOP=y
93CONFIG_IOSCHED_AS=y
94# CONFIG_IOSCHED_DEADLINE is not set
95CONFIG_IOSCHED_CFQ=y
96CONFIG_DEFAULT_AS=y
97# CONFIG_DEFAULT_DEADLINE is not set
98# CONFIG_DEFAULT_CFQ is not set
99# CONFIG_DEFAULT_NOOP is not set
100CONFIG_DEFAULT_IOSCHED="anticipatory"
101# CONFIG_PREEMPT_NONE is not set
102CONFIG_PREEMPT_VOLUNTARY=y
103# CONFIG_PREEMPT is not set
104
105#
106# Blackfin Processor Options
107#
108
109#
110# Processor and Board Settings
111#
112# CONFIG_BF531 is not set
113# CONFIG_BF532 is not set
114# CONFIG_BF533 is not set
115# CONFIG_BF534 is not set
116# CONFIG_BF536 is not set
117# CONFIG_BF537 is not set
118# CONFIG_BF542 is not set
119# CONFIG_BF544 is not set
120# CONFIG_BF548 is not set
121CONFIG_BF549=y
122# CONFIG_BF561 is not set
123CONFIG_BF_REV_0_0=y
124# CONFIG_BF_REV_0_2 is not set
125# CONFIG_BF_REV_0_3 is not set
126# CONFIG_BF_REV_0_4 is not set
127# CONFIG_BF_REV_0_5 is not set
128# CONFIG_BF_REV_ANY is not set
129# CONFIG_BF_REV_NONE is not set
130CONFIG_BF54x=y
131CONFIG_BFIN_SINGLE_CORE=y
132# CONFIG_BFIN533_EZKIT is not set
133# CONFIG_BFIN533_STAMP is not set
134# CONFIG_BFIN537_STAMP is not set
135# CONFIG_BFIN533_BLUETECHNIX_CM is not set
136# CONFIG_BFIN537_BLUETECHNIX_CM is not set
137CONFIG_BFIN548_EZKIT=y
138# CONFIG_BFIN561_BLUETECHNIX_CM is not set
139# CONFIG_BFIN561_EZKIT is not set
140# CONFIG_BFIN561_TEPLA is not set
141# CONFIG_PNAV10 is not set
142# CONFIG_GENERIC_BOARD is not set
143CONFIG_IRQ_PLL_WAKEUP=7
144CONFIG_IRQ_TIMER0=11
145CONFIG_IRQ_TIMER1=11
146CONFIG_IRQ_TIMER2=11
147CONFIG_IRQ_TIMER3=11
148CONFIG_IRQ_TIMER4=11
149CONFIG_IRQ_TIMER5=11
150CONFIG_IRQ_TIMER6=11
151CONFIG_IRQ_TIMER7=11
152CONFIG_IRQ_TIMER8=11
153CONFIG_IRQ_TIMER9=11
154CONFIG_IRQ_TIMER10=11
155CONFIG_IRQ_RTC=8
156CONFIG_IRQ_SPORT0_RX=9
157CONFIG_IRQ_SPORT0_TX=9
158CONFIG_IRQ_SPORT1_RX=9
159CONFIG_IRQ_SPORT1_TX=9
160CONFIG_IRQ_UART0_RX=10
161CONFIG_IRQ_UART0_TX=10
162CONFIG_IRQ_UART1_RX=10
163CONFIG_IRQ_UART1_TX=10
164
165#
166# BF548 Specific Configuration
167#
168
169#
170# Interrupt Priority Assignment
171#
172
173#
174# Priority
175#
176CONFIG_IRQ_DMAC0_ERR=7
177CONFIG_IRQ_EPPI0_ERR=7
178CONFIG_IRQ_SPORT0_ERR=7
179CONFIG_IRQ_SPORT1_ERR=7
180CONFIG_IRQ_SPI0_ERR=7
181CONFIG_IRQ_UART0_ERR=7
182CONFIG_IRQ_EPPI0=8
183CONFIG_IRQ_SPI0=10
184CONFIG_IRQ_PINT0=12
185CONFIG_IRQ_PINT1=12
186CONFIG_IRQ_MDMAS0=13
187CONFIG_IRQ_MDMAS1=13
188CONFIG_IRQ_WATCHDOG=13
189CONFIG_IRQ_DMAC1_ERR=7
190CONFIG_IRQ_SPORT2_ERR=7
191CONFIG_IRQ_SPORT3_ERR=7
192CONFIG_IRQ_MXVR_DATA=7
193CONFIG_IRQ_SPI1_ERR=7
194CONFIG_IRQ_SPI2_ERR=7
195CONFIG_IRQ_UART1_ERR=7
196CONFIG_IRQ_UART2_ERR=7
197CONFIG_IRQ_CAN0_ERR=7
198CONFIG_IRQ_SPORT2_RX=9
199CONFIG_IRQ_SPORT2_TX=9
200CONFIG_IRQ_SPORT3_RX=9
201CONFIG_IRQ_SPORT3_TX=9
202CONFIG_IRQ_EPPI1=9
203CONFIG_IRQ_EPPI2=9
204CONFIG_IRQ_SPI1=10
205CONFIG_IRQ_SPI2=10
206CONFIG_IRQ_ATAPI_RX=10
207CONFIG_IRQ_ATAPI_TX=10
208CONFIG_IRQ_TWI0=11
209CONFIG_IRQ_TWI1=11
210CONFIG_IRQ_CAN0_RX=11
211CONFIG_IRQ_CAN0_TX=11
212CONFIG_IRQ_MDMAS2=13
213CONFIG_IRQ_MDMAS3=13
214CONFIG_IRQ_MXVR_ERR=11
215CONFIG_IRQ_MXVR_MSG=11
216CONFIG_IRQ_MXVR_PKT=11
217CONFIG_IRQ_EPPI1_ERR=7
218CONFIG_IRQ_EPPI2_ERR=7
219CONFIG_IRQ_UART3_ERR=7
220CONFIG_IRQ_HOST_ERR=7
221CONFIG_IRQ_PIXC_ERR=7
222CONFIG_IRQ_NFC_ERR=7
223CONFIG_IRQ_ATAPI_ERR=7
224CONFIG_IRQ_CAN1_ERR=7
225CONFIG_IRQ_HS_DMA_ERR=7
226CONFIG_IRQ_PIXC_IN0=8
227CONFIG_IRQ_PIXC_IN1=8
228CONFIG_IRQ_PIXC_OUT=8
229CONFIG_IRQ_SDH=8
230CONFIG_IRQ_CNT=8
231CONFIG_IRQ_KEY=8
232CONFIG_IRQ_CAN1_RX=11
233CONFIG_IRQ_CAN1_TX=11
234CONFIG_IRQ_SDH_MASK0=11
235CONFIG_IRQ_SDH_MASK1=11
236CONFIG_IRQ_USB_INT0=11
237CONFIG_IRQ_USB_INT1=11
238CONFIG_IRQ_USB_INT2=11
239CONFIG_IRQ_USB_DMA=11
240CONFIG_IRQ_OTPSEC=11
241CONFIG_IRQ_PINT2=11
242CONFIG_IRQ_PINT3=11
243
244#
245# Board customizations
246#
247# CONFIG_CMDLINE_BOOL is not set
248
249#
250# Board Setup
251#
252CONFIG_CLKIN_HZ=25000000
253CONFIG_MEM_SIZE=64
254CONFIG_MEM_ADD_WIDTH=10
255CONFIG_BOOT_LOAD=0x1000
256
257#
258# Blackfin Kernel Optimizations
259#
260
261#
262# Timer Tick
263#
264# CONFIG_HZ_100 is not set
265CONFIG_HZ_250=y
266# CONFIG_HZ_300 is not set
267# CONFIG_HZ_1000 is not set
268CONFIG_HZ=250
269
270#
271# Memory Optimizations
272#
273CONFIG_I_ENTRY_L1=y
274CONFIG_EXCPT_IRQ_SYSC_L1=y
275CONFIG_DO_IRQ_L1=y
276CONFIG_CORE_TIMER_IRQ_L1=y
277CONFIG_IDLE_L1=y
278CONFIG_SCHEDULE_L1=y
279CONFIG_ARITHMETIC_OPS_L1=y
280CONFIG_ACCESS_OK_L1=y
281CONFIG_MEMSET_L1=y
282CONFIG_MEMCPY_L1=y
283CONFIG_SYS_BFIN_SPINLOCK_L1=y
284# CONFIG_IP_CHECKSUM_L1 is not set
285CONFIG_CACHELINE_ALIGNED_L1=y
286# CONFIG_SYSCALL_TAB_L1 is not set
287# CONFIG_CPLB_SWITCH_TAB_L1 is not set
288CONFIG_RAMKERNEL=y
289# CONFIG_ROMKERNEL is not set
290CONFIG_SELECT_MEMORY_MODEL=y
291CONFIG_FLATMEM_MANUAL=y
292# CONFIG_DISCONTIGMEM_MANUAL is not set
293# CONFIG_SPARSEMEM_MANUAL is not set
294CONFIG_FLATMEM=y
295CONFIG_FLAT_NODE_MEM_MAP=y
296# CONFIG_SPARSEMEM_STATIC is not set
297CONFIG_SPLIT_PTLOCK_CPUS=4
298# CONFIG_RESOURCES_64BIT is not set
299CONFIG_ZONE_DMA_FLAG=1
300CONFIG_LARGE_ALLOCS=y
301CONFIG_BFIN_DMA_5XX=y
302# CONFIG_DMA_UNCACHED_2M is not set
303CONFIG_DMA_UNCACHED_1M=y
304# CONFIG_DMA_UNCACHED_NONE is not set
305
306#
307# Cache Support
308#
309CONFIG_BLKFIN_CACHE=y
310CONFIG_BLKFIN_DCACHE=y
311# CONFIG_BLKFIN_DCACHE_BANKA is not set
312# CONFIG_BLKFIN_CACHE_LOCK is not set
313# CONFIG_BLKFIN_WB is not set
314CONFIG_BLKFIN_WT=y
315CONFIG_L1_MAX_PIECE=16
316
317#
318# Clock Settings
319#
320# CONFIG_BFIN_KERNEL_CLOCK is not set
321
322#
323# Asynchonous Memory Configuration
324#
325
326#
327# EBIU_AMBCTL Global Control
328#
329CONFIG_C_AMCKEN=y
330CONFIG_C_CDPRIO=y
331# CONFIG_C_AMBEN is not set
332# CONFIG_C_AMBEN_B0 is not set
333# CONFIG_C_AMBEN_B0_B1 is not set
334# CONFIG_C_AMBEN_B0_B1_B2 is not set
335CONFIG_C_AMBEN_ALL=y
336
337#
338# EBIU_AMBCTL Control
339#
340CONFIG_BANK_0=0x7BB0
341CONFIG_BANK_1=0x7BB0
342CONFIG_BANK_2=0x7BB0
343CONFIG_BANK_3=0x99B3
344
345#
346# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
347#
348# CONFIG_PCI is not set
349
350#
351# PCCARD (PCMCIA/CardBus) support
352#
353# CONFIG_PCCARD is not set
354
355#
356# PCI Hotplug Support
357#
358
359#
360# Executable file formats
361#
362CONFIG_BINFMT_ELF_FDPIC=y
363CONFIG_BINFMT_FLAT=y
364CONFIG_BINFMT_ZFLAT=y
365# CONFIG_BINFMT_SHARED_FLAT is not set
366# CONFIG_BINFMT_MISC is not set
367
368#
369# Power management options
370#
371# CONFIG_PM is not set
372
373#
374# CPU Frequency scaling
375#
376# CONFIG_CPU_FREQ is not set
377
378#
379# Networking
380#
381CONFIG_NET=y
382
383#
384# Networking options
385#
386# CONFIG_NETDEBUG is not set
387CONFIG_PACKET=y
388# CONFIG_PACKET_MMAP is not set
389CONFIG_UNIX=y
390CONFIG_XFRM=y
391# CONFIG_XFRM_USER is not set
392# CONFIG_XFRM_SUB_POLICY is not set
393# CONFIG_XFRM_MIGRATE is not set
394# CONFIG_NET_KEY is not set
395CONFIG_INET=y
396# CONFIG_IP_MULTICAST is not set
397# CONFIG_IP_ADVANCED_ROUTER is not set
398CONFIG_IP_FIB_HASH=y
399CONFIG_IP_PNP=y
400# CONFIG_IP_PNP_DHCP is not set
401# CONFIG_IP_PNP_BOOTP is not set
402# CONFIG_IP_PNP_RARP is not set
403# CONFIG_NET_IPIP is not set
404# CONFIG_NET_IPGRE is not set
405# CONFIG_ARPD is not set
406CONFIG_SYN_COOKIES=y
407# CONFIG_INET_AH is not set
408# CONFIG_INET_ESP is not set
409# CONFIG_INET_IPCOMP is not set
410# CONFIG_INET_XFRM_TUNNEL is not set
411# CONFIG_INET_TUNNEL is not set
412CONFIG_INET_XFRM_MODE_TRANSPORT=y
413CONFIG_INET_XFRM_MODE_TUNNEL=y
414CONFIG_INET_XFRM_MODE_BEET=y
415CONFIG_INET_DIAG=y
416CONFIG_INET_TCP_DIAG=y
417# CONFIG_TCP_CONG_ADVANCED is not set
418CONFIG_TCP_CONG_CUBIC=y
419CONFIG_DEFAULT_TCP_CONG="cubic"
420# CONFIG_TCP_MD5SIG is not set
421# CONFIG_IPV6 is not set
422# CONFIG_INET6_XFRM_TUNNEL is not set
423# CONFIG_INET6_TUNNEL is not set
424# CONFIG_NETLABEL is not set
425# CONFIG_NETWORK_SECMARK is not set
426# CONFIG_NETFILTER is not set
427
428#
429# DCCP Configuration (EXPERIMENTAL)
430#
431# CONFIG_IP_DCCP is not set
432
433#
434# SCTP Configuration (EXPERIMENTAL)
435#
436# CONFIG_IP_SCTP is not set
437
438#
439# TIPC Configuration (EXPERIMENTAL)
440#
441# CONFIG_TIPC is not set
442# CONFIG_ATM is not set
443# CONFIG_BRIDGE is not set
444# CONFIG_VLAN_8021Q is not set
445# CONFIG_DECNET is not set
446# CONFIG_LLC2 is not set
447# CONFIG_IPX is not set
448# CONFIG_ATALK is not set
449# CONFIG_X25 is not set
450# CONFIG_LAPB is not set
451# CONFIG_ECONET is not set
452# CONFIG_WAN_ROUTER is not set
453
454#
455# QoS and/or fair queueing
456#
457# CONFIG_NET_SCHED is not set
458
459#
460# Network testing
461#
462# CONFIG_NET_PKTGEN is not set
463# CONFIG_HAMRADIO is not set
464# CONFIG_IRDA is not set
465# CONFIG_BT is not set
466# CONFIG_IEEE80211 is not set
467
468#
469# Device Drivers
470#
471
472#
473# Generic Driver Options
474#
475CONFIG_STANDALONE=y
476CONFIG_PREVENT_FIRMWARE_BUILD=y
477# CONFIG_FW_LOADER is not set
478# CONFIG_DEBUG_DRIVER is not set
479# CONFIG_DEBUG_DEVRES is not set
480# CONFIG_SYS_HYPERVISOR is not set
481
482#
483# Connector - unified userspace <-> kernelspace linker
484#
485# CONFIG_CONNECTOR is not set
486
487#
488# Memory Technology Devices (MTD)
489#
490CONFIG_MTD=y
491# CONFIG_MTD_DEBUG is not set
492# CONFIG_MTD_CONCAT is not set
493CONFIG_MTD_PARTITIONS=y
494# CONFIG_MTD_REDBOOT_PARTS is not set
495# CONFIG_MTD_CMDLINE_PARTS is not set
496
497#
498# User Modules And Translation Layers
499#
500# CONFIG_MTD_CHAR is not set
501CONFIG_MTD_BLKDEVS=y
502CONFIG_MTD_BLOCK=y
503# CONFIG_FTL is not set
504# CONFIG_NFTL is not set
505# CONFIG_INFTL is not set
506# CONFIG_RFD_FTL is not set
507# CONFIG_SSFDC is not set
508
509#
510# RAM/ROM/Flash chip drivers
511#
512# CONFIG_MTD_CFI is not set
513# CONFIG_MTD_JEDECPROBE is not set
514CONFIG_MTD_MAP_BANK_WIDTH_1=y
515CONFIG_MTD_MAP_BANK_WIDTH_2=y
516CONFIG_MTD_MAP_BANK_WIDTH_4=y
517# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
518# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
519# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
520CONFIG_MTD_CFI_I1=y
521CONFIG_MTD_CFI_I2=y
522# CONFIG_MTD_CFI_I4 is not set
523# CONFIG_MTD_CFI_I8 is not set
524CONFIG_MTD_RAM=y
525# CONFIG_MTD_ROM is not set
526# CONFIG_MTD_ABSENT is not set
527# CONFIG_MTD_OBSOLETE_CHIPS is not set
528
529#
530# Mapping drivers for chip access
531#
532CONFIG_MTD_COMPLEX_MAPPINGS=y
533# CONFIG_MTD_BF5xx is not set
534CONFIG_MTD_UCLINUX=y
535# CONFIG_MTD_PLATRAM is not set
536
537#
538# Self-contained MTD device drivers
539#
540# CONFIG_MTD_SLRAM is not set
541# CONFIG_MTD_PHRAM is not set
542# CONFIG_MTD_MTDRAM is not set
543# CONFIG_MTD_BLOCK2MTD is not set
544
545#
546# Disk-On-Chip Device Drivers
547#
548# CONFIG_MTD_DOC2000 is not set
549# CONFIG_MTD_DOC2001 is not set
550# CONFIG_MTD_DOC2001PLUS is not set
551
552#
553# NAND Flash Device Drivers
554#
555# CONFIG_MTD_NAND is not set
556
557#
558# OneNAND Flash Device Drivers
559#
560# CONFIG_MTD_ONENAND is not set
561
562#
563# Parallel port support
564#
565# CONFIG_PARPORT is not set
566
567#
568# Plug and Play support
569#
570# CONFIG_PNPACPI is not set
571
572#
573# Block devices
574#
575# CONFIG_BLK_DEV_COW_COMMON is not set
576# CONFIG_BLK_DEV_LOOP is not set
577# CONFIG_BLK_DEV_NBD is not set
578CONFIG_BLK_DEV_RAM=y
579CONFIG_BLK_DEV_RAM_COUNT=16
580CONFIG_BLK_DEV_RAM_SIZE=4096
581CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
582# CONFIG_CDROM_PKTCDVD is not set
583# CONFIG_ATA_OVER_ETH is not set
584
585#
586# Misc devices
587#
588
589#
590# ATA/ATAPI/MFM/RLL support
591#
592# CONFIG_IDE is not set
593
594#
595# SCSI device support
596#
597# CONFIG_RAID_ATTRS is not set
598# CONFIG_SCSI is not set
599# CONFIG_SCSI_NETLINK is not set
600
601#
602# Serial ATA (prod) and Parallel ATA (experimental) drivers
603#
604# CONFIG_ATA is not set
605
606#
607# Multi-device support (RAID and LVM)
608#
609# CONFIG_MD is not set
610
611#
612# Fusion MPT device support
613#
614# CONFIG_FUSION is not set
615
616#
617# IEEE 1394 (FireWire) support
618#
619
620#
621# I2O device support
622#
623
624#
625# Network device support
626#
627CONFIG_NETDEVICES=y
628# CONFIG_DUMMY is not set
629# CONFIG_BONDING is not set
630# CONFIG_EQUALIZER is not set
631# CONFIG_TUN is not set
632
633#
634# PHY device support
635#
636# CONFIG_PHYLIB is not set
637
638#
639# Ethernet (10 or 100Mbit)
640#
641CONFIG_NET_ETHERNET=y
642CONFIG_MII=y
643# CONFIG_SMC91X is not set
644# CONFIG_SMSC911X is not set
645
646#
647# Ethernet (1000 Mbit)
648#
649
650#
651# Ethernet (10000 Mbit)
652#
653
654#
655# Token Ring devices
656#
657
658#
659# Wireless LAN (non-hamradio)
660#
661# CONFIG_NET_RADIO is not set
662
663#
664# Wan interfaces
665#
666# CONFIG_WAN is not set
667# CONFIG_PPP is not set
668# CONFIG_SLIP is not set
669# CONFIG_SHAPER is not set
670# CONFIG_NETCONSOLE is not set
671# CONFIG_NETPOLL is not set
672# CONFIG_NET_POLL_CONTROLLER is not set
673
674#
675# ISDN subsystem
676#
677# CONFIG_ISDN is not set
678
679#
680# Telephony Support
681#
682# CONFIG_PHONE is not set
683
684#
685# Input device support
686#
687CONFIG_INPUT=y
688# CONFIG_INPUT_FF_MEMLESS is not set
689
690#
691# Userland interfaces
692#
693# CONFIG_INPUT_MOUSEDEV is not set
694# CONFIG_INPUT_JOYDEV is not set
695# CONFIG_INPUT_TSDEV is not set
696# CONFIG_INPUT_EVDEV is not set
697# CONFIG_INPUT_EVBUG is not set
698
699#
700# Input Device Drivers
701#
702# CONFIG_INPUT_KEYBOARD is not set
703# CONFIG_INPUT_MOUSE is not set
704# CONFIG_INPUT_JOYSTICK is not set
705# CONFIG_INPUT_TOUCHSCREEN is not set
706CONFIG_INPUT_MISC=y
707# CONFIG_INPUT_UINPUT is not set
708# CONFIG_BF53X_PFBUTTONS is not set
709
710#
711# Hardware I/O ports
712#
713# CONFIG_SERIO is not set
714# CONFIG_GAMEPORT is not set
715
716#
717# Character devices
718#
719# CONFIG_AD9960 is not set
720# CONFIG_SPI_ADC_BF533 is not set
721# CONFIG_BF5xx_PFLAGS is not set
722# CONFIG_BF5xx_PPIFCD is not set
723# CONFIG_BF5xx_TIMERS is not set
724# CONFIG_BF5xx_PPI is not set
725# CONFIG_BFIN_SPORT is not set
726# CONFIG_BFIN_TIMER_LATENCY is not set
727# CONFIG_BF5xx_FBDMA is not set
728# CONFIG_VT is not set
729# CONFIG_SERIAL_NONSTANDARD is not set
730
731#
732# Serial drivers
733#
734# CONFIG_SERIAL_8250 is not set
735
736#
737# Non-8250 serial port support
738#
739CONFIG_SERIAL_BFIN=y
740CONFIG_SERIAL_BFIN_CONSOLE=y
741# CONFIG_SERIAL_BFIN_DMA is not set
742CONFIG_SERIAL_BFIN_PIO=y
743# CONFIG_SERIAL_BFIN_UART0 is not set
744CONFIG_SERIAL_BFIN_UART1=y
745# CONFIG_BFIN_UART1_CTSRTS is not set
746# CONFIG_SERIAL_BFIN_UART2 is not set
747# CONFIG_SERIAL_BFIN_UART3 is not set
748CONFIG_SERIAL_CORE=y
749CONFIG_SERIAL_CORE_CONSOLE=y
750# CONFIG_SERIAL_BFIN_SPORT is not set
751CONFIG_UNIX98_PTYS=y
752# CONFIG_LEGACY_PTYS is not set
753
754#
755# CAN, the car bus and industrial fieldbus
756#
757# CONFIG_CAN4LINUX is not set
758
759#
760# IPMI
761#
762# CONFIG_IPMI_HANDLER is not set
763
764#
765# Watchdog Cards
766#
767# CONFIG_WATCHDOG is not set
768CONFIG_HW_RANDOM=y
769# CONFIG_GEN_RTC is not set
770# CONFIG_DTLK is not set
771# CONFIG_R3964 is not set
772# CONFIG_RAW_DRIVER is not set
773
774#
775# TPM devices
776#
777# CONFIG_TCG_TPM is not set
778
779#
780# I2C support
781#
782# CONFIG_I2C is not set
783
784#
785# SPI support
786#
787# CONFIG_SPI is not set
788# CONFIG_SPI_MASTER is not set
789
790#
791# Dallas's 1-wire bus
792#
793# CONFIG_W1 is not set
794
795#
796# Hardware Monitoring support
797#
798CONFIG_HWMON=y
799# CONFIG_HWMON_VID is not set
800# CONFIG_SENSORS_ABITUGURU is not set
801# CONFIG_SENSORS_F71805F is not set
802# CONFIG_SENSORS_PC87427 is not set
803# CONFIG_SENSORS_VT1211 is not set
804# CONFIG_HWMON_DEBUG_CHIP is not set
805
806#
807# Multifunction device drivers
808#
809# CONFIG_MFD_SM501 is not set
810
811#
812# Multimedia devices
813#
814# CONFIG_VIDEO_DEV is not set
815
816#
817# Digital Video Broadcasting Devices
818#
819# CONFIG_DVB is not set
820
821#
822# Graphics support
823#
824# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
825# CONFIG_FB is not set
826
827#
828# Sound
829#
830# CONFIG_SOUND is not set
831
832#
833# HID Devices
834#
835CONFIG_HID=y
836# CONFIG_HID_DEBUG is not set
837
838#
839# USB support
840#
841CONFIG_USB_ARCH_HAS_HCD=y
842# CONFIG_USB_ARCH_HAS_OHCI is not set
843# CONFIG_USB_ARCH_HAS_EHCI is not set
844# CONFIG_USB is not set
845
846#
847# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
848#
849
850#
851# USB Gadget Support
852#
853# CONFIG_USB_GADGET is not set
854
855#
856# MMC/SD Card support
857#
858# CONFIG_MMC is not set
859
860#
861# LED devices
862#
863# CONFIG_NEW_LEDS is not set
864
865#
866# LED drivers
867#
868
869#
870# LED Triggers
871#
872
873#
874# InfiniBand support
875#
876
877#
878# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
879#
880
881#
882# Real Time Clock
883#
884CONFIG_RTC_LIB=y
885CONFIG_RTC_CLASS=y
886CONFIG_RTC_HCTOSYS=y
887CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
888# CONFIG_RTC_DEBUG is not set
889
890#
891# RTC interfaces
892#
893CONFIG_RTC_INTF_SYSFS=y
894CONFIG_RTC_INTF_PROC=y
895CONFIG_RTC_INTF_DEV=y
896# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
897
898#
899# RTC drivers
900#
901# CONFIG_RTC_DRV_DS1553 is not set
902# CONFIG_RTC_DRV_DS1742 is not set
903# CONFIG_RTC_DRV_M48T86 is not set
904# CONFIG_RTC_DRV_TEST is not set
905# CONFIG_RTC_DRV_V3020 is not set
906CONFIG_RTC_DRV_BFIN=y
907
908#
909# DMA Engine support
910#
911# CONFIG_DMA_ENGINE is not set
912
913#
914# DMA Clients
915#
916
917#
918# DMA Devices
919#
920
921#
922# Auxiliary Display support
923#
924
925#
926# Virtualization
927#
928
929#
930# PBX support
931#
932# CONFIG_PBX is not set
933
934#
935# File systems
936#
937CONFIG_EXT2_FS=y
938CONFIG_EXT2_FS_XATTR=y
939# CONFIG_EXT2_FS_POSIX_ACL is not set
940# CONFIG_EXT2_FS_SECURITY is not set
941# CONFIG_EXT3_FS is not set
942# CONFIG_EXT4DEV_FS is not set
943CONFIG_FS_MBCACHE=y
944# CONFIG_REISERFS_FS is not set
945# CONFIG_JFS_FS is not set
946# CONFIG_FS_POSIX_ACL is not set
947# CONFIG_XFS_FS is not set
948# CONFIG_GFS2_FS is not set
949# CONFIG_OCFS2_FS is not set
950# CONFIG_MINIX_FS is not set
951# CONFIG_ROMFS_FS is not set
952CONFIG_INOTIFY=y
953CONFIG_INOTIFY_USER=y
954# CONFIG_QUOTA is not set
955CONFIG_DNOTIFY=y
956# CONFIG_AUTOFS_FS is not set
957# CONFIG_AUTOFS4_FS is not set
958# CONFIG_FUSE_FS is not set
959
960#
961# CD-ROM/DVD Filesystems
962#
963# CONFIG_ISO9660_FS is not set
964# CONFIG_UDF_FS is not set
965
966#
967# DOS/FAT/NT Filesystems
968#
969# CONFIG_MSDOS_FS is not set
970# CONFIG_VFAT_FS is not set
971# CONFIG_NTFS_FS is not set
972
973#
974# Pseudo filesystems
975#
976CONFIG_PROC_FS=y
977CONFIG_PROC_SYSCTL=y
978CONFIG_SYSFS=y
979# CONFIG_TMPFS is not set
980# CONFIG_HUGETLB_PAGE is not set
981CONFIG_RAMFS=y
982# CONFIG_CONFIGFS_FS is not set
983
984#
985# Miscellaneous filesystems
986#
987# CONFIG_ADFS_FS is not set
988# CONFIG_AFFS_FS is not set
989# CONFIG_HFS_FS is not set
990# CONFIG_HFSPLUS_FS is not set
991# CONFIG_BEFS_FS is not set
992# CONFIG_BFS_FS is not set
993# CONFIG_EFS_FS is not set
994# CONFIG_YAFFS_FS is not set
995# CONFIG_JFFS2_FS is not set
996# CONFIG_CRAMFS is not set
997# CONFIG_VXFS_FS is not set
998# CONFIG_HPFS_FS is not set
999# CONFIG_QNX4FS_FS is not set
1000# CONFIG_SYSV_FS is not set
1001# CONFIG_UFS_FS is not set
1002
1003#
1004# Network File Systems
1005#
1006# CONFIG_NFS_FS is not set
1007# CONFIG_NFSD is not set
1008# CONFIG_SMB_FS is not set
1009# CONFIG_CIFS is not set
1010# CONFIG_NCP_FS is not set
1011# CONFIG_CODA_FS is not set
1012# CONFIG_AFS_FS is not set
1013# CONFIG_9P_FS is not set
1014
1015#
1016# Partition Types
1017#
1018# CONFIG_PARTITION_ADVANCED is not set
1019CONFIG_MSDOS_PARTITION=y
1020
1021#
1022# Native Language Support
1023#
1024# CONFIG_NLS is not set
1025
1026#
1027# Distributed Lock Manager
1028#
1029# CONFIG_DLM is not set
1030
1031#
1032# Profiling support
1033#
1034# CONFIG_PROFILING is not set
1035
1036#
1037# Kernel hacking
1038#
1039# CONFIG_PRINTK_TIME is not set
1040CONFIG_ENABLE_MUST_CHECK=y
1041CONFIG_MAGIC_SYSRQ=y
1042# CONFIG_UNUSED_SYMBOLS is not set
1043# CONFIG_DEBUG_FS is not set
1044# CONFIG_HEADERS_CHECK is not set
1045CONFIG_DEBUG_KERNEL=y
1046# CONFIG_DEBUG_SHIRQ is not set
1047CONFIG_LOG_BUF_SHIFT=14
1048CONFIG_DETECT_SOFTLOCKUP=y
1049# CONFIG_SCHEDSTATS is not set
1050# CONFIG_TIMER_STATS is not set
1051# CONFIG_DEBUG_SLAB is not set
1052# CONFIG_DEBUG_RT_MUTEXES is not set
1053# CONFIG_RT_MUTEX_TESTER is not set
1054# CONFIG_DEBUG_SPINLOCK is not set
1055# CONFIG_DEBUG_MUTEXES is not set
1056# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1057# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1058# CONFIG_DEBUG_KOBJECT is not set
1059# CONFIG_DEBUG_BUGVERBOSE is not set
1060CONFIG_DEBUG_INFO=y
1061# CONFIG_DEBUG_VM is not set
1062# CONFIG_DEBUG_LIST is not set
1063CONFIG_FRAME_POINTER=y
1064CONFIG_FORCED_INLINING=y
1065# CONFIG_RCU_TORTURE_TEST is not set
1066# CONFIG_FAULT_INJECTION is not set
1067CONFIG_DEBUG_HWERR=y
1068# CONFIG_DEBUG_ICACHE_CHECK is not set
1069# CONFIG_DEBUG_KERNEL_START is not set
1070# CONFIG_DEBUG_SERIAL_EARLY_INIT is not set
1071CONFIG_DEBUG_HUNT_FOR_ZERO=y
1072# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
1073CONFIG_CPLB_INFO=y
1074CONFIG_ACCESS_CHECK=y
1075
1076#
1077# Security options
1078#
1079# CONFIG_KEYS is not set
1080CONFIG_SECURITY=y
1081# CONFIG_SECURITY_NETWORK is not set
1082CONFIG_SECURITY_CAPABILITIES=y
1083
1084#
1085# Cryptographic options
1086#
1087# CONFIG_CRYPTO is not set
1088
1089#
1090# Library routines
1091#
1092CONFIG_BITREVERSE=y
1093# CONFIG_CRC_CCITT is not set
1094# CONFIG_CRC16 is not set
1095CONFIG_CRC32=y
1096# CONFIG_LIBCRC32C is not set
1097CONFIG_ZLIB_INFLATE=y
1098CONFIG_PLIST=y
1099CONFIG_HAS_IOMEM=y
1100CONFIG_HAS_IOPORT=y
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index f3b7d2f9d49c..f429ebc3a961 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -6,9 +6,12 @@ extra-y := init_task.o vmlinux.lds
6 6
7obj-y := \ 7obj-y := \
8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ 8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
9 sys_bfin.o time.o traps.o irqchip.o dma-mapping.o bfin_gpio.o \ 9 sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \
10 flat.o 10 fixed_code.o cplbinit.o cacheinit.o
11 11
12obj-$(CONFIG_BF53x) += bfin_gpio.o
13obj-$(CONFIG_BF561) += bfin_gpio.o
12obj-$(CONFIG_MODULES) += module.o 14obj-$(CONFIG_MODULES) += module.o
13obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o 15obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o
14obj-$(CONFIG_DUAL_CORE_TEST_MODULE) += dualcore_test.o 16obj-$(CONFIG_DUAL_CORE_TEST_MODULE) += dualcore_test.o
17obj-$(CONFIG_KGDB) += kgdb.o
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c
index e455f4504509..b56b2741cdea 100644
--- a/arch/blackfin/kernel/asm-offsets.c
+++ b/arch/blackfin/kernel/asm-offsets.c
@@ -32,11 +32,10 @@
32#include <linux/kernel_stat.h> 32#include <linux/kernel_stat.h>
33#include <linux/ptrace.h> 33#include <linux/ptrace.h>
34#include <linux/hardirq.h> 34#include <linux/hardirq.h>
35#include <asm/irq.h> 35#include <linux/irq.h>
36#include <asm/thread_info.h> 36#include <linux/thread_info.h>
37 37
38#define DEFINE(sym, val) \ 38#define DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val))
39 asm volatile("\n->" #sym " %0 " #val : : "i" (val))
40 39
41int main(void) 40int main(void)
42{ 41{
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 069a896a8f26..7cf02f02a1db 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -34,6 +34,7 @@
34#include <linux/kernel.h> 34#include <linux/kernel.h>
35#include <linux/param.h> 35#include <linux/param.h>
36 36
37#include <asm/blackfin.h>
37#include <asm/dma.h> 38#include <asm/dma.h>
38#include <asm/cacheflush.h> 39#include <asm/cacheflush.h>
39 40
@@ -45,67 +46,6 @@
45***************************************************************************/ 46***************************************************************************/
46 47
47static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL]; 48static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL];
48#if defined (CONFIG_BF561)
49static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
50 (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
51 (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
52 (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
53 (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
54 (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
55 (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
56 (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
57 (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
58 (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
59 (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
60 (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
61 (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
62 (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
63 (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
64 (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
65 (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
66 (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
67 (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
68 (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
69 (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
70 (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
71 (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
72 (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
73 (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
74 (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
75 (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
76 (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
77 (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
78 (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
79 (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
80 (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
81 (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
82 (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
83 (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
84 (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
85 (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
86};
87#else
88static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
89 (struct dma_register *) DMA0_NEXT_DESC_PTR,
90 (struct dma_register *) DMA1_NEXT_DESC_PTR,
91 (struct dma_register *) DMA2_NEXT_DESC_PTR,
92 (struct dma_register *) DMA3_NEXT_DESC_PTR,
93 (struct dma_register *) DMA4_NEXT_DESC_PTR,
94 (struct dma_register *) DMA5_NEXT_DESC_PTR,
95 (struct dma_register *) DMA6_NEXT_DESC_PTR,
96 (struct dma_register *) DMA7_NEXT_DESC_PTR,
97#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
98 (struct dma_register *) DMA8_NEXT_DESC_PTR,
99 (struct dma_register *) DMA9_NEXT_DESC_PTR,
100 (struct dma_register *) DMA10_NEXT_DESC_PTR,
101 (struct dma_register *) DMA11_NEXT_DESC_PTR,
102#endif
103 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
104 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
105 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
106 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
107};
108#endif
109 49
110/*------------------------------------------------------------------------------ 50/*------------------------------------------------------------------------------
111 * Set the Buffer Clear bit in the Configuration register of specific DMA 51 * Set the Buffer Clear bit in the Configuration register of specific DMA
@@ -138,149 +78,6 @@ static int __init blackfin_dma_init(void)
138 78
139arch_initcall(blackfin_dma_init); 79arch_initcall(blackfin_dma_init);
140 80
141/*
142 * Form the channel find the irq number for that channel.
143 */
144#if !defined(CONFIG_BF561)
145
146static int bf533_channel2irq(unsigned int channel)
147{
148 int ret_irq = -1;
149
150 switch (channel) {
151 case CH_PPI:
152 ret_irq = IRQ_PPI;
153 break;
154
155#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
156 case CH_EMAC_RX:
157 ret_irq = IRQ_MAC_RX;
158 break;
159
160 case CH_EMAC_TX:
161 ret_irq = IRQ_MAC_TX;
162 break;
163
164 case CH_UART1_RX:
165 ret_irq = IRQ_UART1_RX;
166 break;
167
168 case CH_UART1_TX:
169 ret_irq = IRQ_UART1_TX;
170 break;
171#endif
172
173 case CH_SPORT0_RX:
174 ret_irq = IRQ_SPORT0_RX;
175 break;
176
177 case CH_SPORT0_TX:
178 ret_irq = IRQ_SPORT0_TX;
179 break;
180
181 case CH_SPORT1_RX:
182 ret_irq = IRQ_SPORT1_RX;
183 break;
184
185 case CH_SPORT1_TX:
186 ret_irq = IRQ_SPORT1_TX;
187 break;
188
189 case CH_SPI:
190 ret_irq = IRQ_SPI;
191 break;
192
193 case CH_UART_RX:
194 ret_irq = IRQ_UART_RX;
195 break;
196
197 case CH_UART_TX:
198 ret_irq = IRQ_UART_TX;
199 break;
200
201 case CH_MEM_STREAM0_SRC:
202 case CH_MEM_STREAM0_DEST:
203 ret_irq = IRQ_MEM_DMA0;
204 break;
205
206 case CH_MEM_STREAM1_SRC:
207 case CH_MEM_STREAM1_DEST:
208 ret_irq = IRQ_MEM_DMA1;
209 break;
210 }
211 return ret_irq;
212}
213
214# define channel2irq(channel) bf533_channel2irq(channel)
215
216#else
217
218static int bf561_channel2irq(unsigned int channel)
219{
220 int ret_irq = -1;
221
222 switch (channel) {
223 case CH_PPI0:
224 ret_irq = IRQ_PPI0;
225 break;
226 case CH_PPI1:
227 ret_irq = IRQ_PPI1;
228 break;
229 case CH_SPORT0_RX:
230 ret_irq = IRQ_SPORT0_RX;
231 break;
232 case CH_SPORT0_TX:
233 ret_irq = IRQ_SPORT0_TX;
234 break;
235 case CH_SPORT1_RX:
236 ret_irq = IRQ_SPORT1_RX;
237 break;
238 case CH_SPORT1_TX:
239 ret_irq = IRQ_SPORT1_TX;
240 break;
241 case CH_SPI:
242 ret_irq = IRQ_SPI;
243 break;
244 case CH_UART_RX:
245 ret_irq = IRQ_UART_RX;
246 break;
247 case CH_UART_TX:
248 ret_irq = IRQ_UART_TX;
249 break;
250
251 case CH_MEM_STREAM0_SRC:
252 case CH_MEM_STREAM0_DEST:
253 ret_irq = IRQ_MEM_DMA0;
254 break;
255 case CH_MEM_STREAM1_SRC:
256 case CH_MEM_STREAM1_DEST:
257 ret_irq = IRQ_MEM_DMA1;
258 break;
259 case CH_MEM_STREAM2_SRC:
260 case CH_MEM_STREAM2_DEST:
261 ret_irq = IRQ_MEM_DMA2;
262 break;
263 case CH_MEM_STREAM3_SRC:
264 case CH_MEM_STREAM3_DEST:
265 ret_irq = IRQ_MEM_DMA3;
266 break;
267
268 case CH_IMEM_STREAM0_SRC:
269 case CH_IMEM_STREAM0_DEST:
270 ret_irq = IRQ_IMEM_DMA0;
271 break;
272 case CH_IMEM_STREAM1_SRC:
273 case CH_IMEM_STREAM1_DEST:
274 ret_irq = IRQ_IMEM_DMA1;
275 break;
276 }
277 return ret_irq;
278}
279
280# define channel2irq(channel) bf561_channel2irq(channel)
281
282#endif
283
284/*------------------------------------------------------------------------------ 81/*------------------------------------------------------------------------------
285 * Request the specific DMA channel from the system. 82 * Request the specific DMA channel from the system.
286 *-----------------------------------------------------------------------------*/ 83 *-----------------------------------------------------------------------------*/
@@ -535,7 +332,7 @@ set_bfin_dma_config(char direction, char flow_mode,
535} 332}
536EXPORT_SYMBOL(set_bfin_dma_config); 333EXPORT_SYMBOL(set_bfin_dma_config);
537 334
538void set_dma_sg(unsigned int channel, struct dmasg * sg, int nr_sg) 335void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg)
539{ 336{
540 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE 337 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
541 && channel < MAX_BLACKFIN_DMA_CHANNEL)); 338 && channel < MAX_BLACKFIN_DMA_CHANNEL));
@@ -604,7 +401,7 @@ static void *__dma_memcpy(void *dest, const void *src, size_t size)
604 401
605 if (size <= 0) 402 if (size <= 0)
606 return NULL; 403 return NULL;
607 404
608 local_irq_save(flags); 405 local_irq_save(flags);
609 406
610 if ((unsigned long)src < memory_end) 407 if ((unsigned long)src < memory_end)
@@ -748,7 +545,6 @@ void *dma_memcpy(void *dest, const void *src, size_t size)
748 addr = __dma_memcpy(dest+bulk, src+bulk, rest); 545 addr = __dma_memcpy(dest+bulk, src+bulk, rest);
749 return addr; 546 return addr;
750} 547}
751
752EXPORT_SYMBOL(dma_memcpy); 548EXPORT_SYMBOL(dma_memcpy);
753 549
754void *safe_dma_memcpy(void *dest, const void *src, size_t size) 550void *safe_dma_memcpy(void *dest, const void *src, size_t size)
@@ -761,14 +557,13 @@ EXPORT_SYMBOL(safe_dma_memcpy);
761 557
762void dma_outsb(void __iomem *addr, const void *buf, unsigned short len) 558void dma_outsb(void __iomem *addr, const void *buf, unsigned short len)
763{ 559{
764
765 unsigned long flags; 560 unsigned long flags;
766 561
767 local_irq_save(flags); 562 local_irq_save(flags);
768
769 blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len);
770 563
771 bfin_write_MDMA_D0_START_ADDR(addr); 564 blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
565
566 bfin_write_MDMA_D0_START_ADDR(addr);
772 bfin_write_MDMA_D0_X_COUNT(len); 567 bfin_write_MDMA_D0_X_COUNT(len);
773 bfin_write_MDMA_D0_X_MODIFY(0); 568 bfin_write_MDMA_D0_X_MODIFY(0);
774 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 569 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -796,9 +591,9 @@ EXPORT_SYMBOL(dma_outsb);
796void dma_insb(const void __iomem *addr, void *buf, unsigned short len) 591void dma_insb(const void __iomem *addr, void *buf, unsigned short len)
797{ 592{
798 unsigned long flags; 593 unsigned long flags;
799 594
800 local_irq_save(flags); 595 local_irq_save(flags);
801 bfin_write_MDMA_D0_START_ADDR(buf); 596 bfin_write_MDMA_D0_START_ADDR(buf);
802 bfin_write_MDMA_D0_X_COUNT(len); 597 bfin_write_MDMA_D0_X_COUNT(len);
803 bfin_write_MDMA_D0_X_MODIFY(1); 598 bfin_write_MDMA_D0_X_MODIFY(1);
804 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 599 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -827,12 +622,12 @@ EXPORT_SYMBOL(dma_insb);
827void dma_outsw(void __iomem *addr, const void *buf, unsigned short len) 622void dma_outsw(void __iomem *addr, const void *buf, unsigned short len)
828{ 623{
829 unsigned long flags; 624 unsigned long flags;
830 625
831 local_irq_save(flags); 626 local_irq_save(flags);
832
833 blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len);
834 627
835 bfin_write_MDMA_D0_START_ADDR(addr); 628 blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
629
630 bfin_write_MDMA_D0_START_ADDR(addr);
836 bfin_write_MDMA_D0_X_COUNT(len); 631 bfin_write_MDMA_D0_X_COUNT(len);
837 bfin_write_MDMA_D0_X_MODIFY(0); 632 bfin_write_MDMA_D0_X_MODIFY(0);
838 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 633 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -859,10 +654,10 @@ EXPORT_SYMBOL(dma_outsw);
859void dma_insw(const void __iomem *addr, void *buf, unsigned short len) 654void dma_insw(const void __iomem *addr, void *buf, unsigned short len)
860{ 655{
861 unsigned long flags; 656 unsigned long flags;
862 657
863 local_irq_save(flags); 658 local_irq_save(flags);
864 659
865 bfin_write_MDMA_D0_START_ADDR(buf); 660 bfin_write_MDMA_D0_START_ADDR(buf);
866 bfin_write_MDMA_D0_X_COUNT(len); 661 bfin_write_MDMA_D0_X_COUNT(len);
867 bfin_write_MDMA_D0_X_MODIFY(2); 662 bfin_write_MDMA_D0_X_MODIFY(2);
868 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 663 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -891,12 +686,12 @@ EXPORT_SYMBOL(dma_insw);
891void dma_outsl(void __iomem *addr, const void *buf, unsigned short len) 686void dma_outsl(void __iomem *addr, const void *buf, unsigned short len)
892{ 687{
893 unsigned long flags; 688 unsigned long flags;
894 689
895 local_irq_save(flags); 690 local_irq_save(flags);
896
897 blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len);
898 691
899 bfin_write_MDMA_D0_START_ADDR(addr); 692 blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
693
694 bfin_write_MDMA_D0_START_ADDR(addr);
900 bfin_write_MDMA_D0_X_COUNT(len); 695 bfin_write_MDMA_D0_X_COUNT(len);
901 bfin_write_MDMA_D0_X_MODIFY(0); 696 bfin_write_MDMA_D0_X_MODIFY(0);
902 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 697 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -923,10 +718,10 @@ EXPORT_SYMBOL(dma_outsl);
923void dma_insl(const void __iomem *addr, void *buf, unsigned short len) 718void dma_insl(const void __iomem *addr, void *buf, unsigned short len)
924{ 719{
925 unsigned long flags; 720 unsigned long flags;
926 721
927 local_irq_save(flags); 722 local_irq_save(flags);
928 723
929 bfin_write_MDMA_D0_START_ADDR(buf); 724 bfin_write_MDMA_D0_START_ADDR(buf);
930 bfin_write_MDMA_D0_X_COUNT(len); 725 bfin_write_MDMA_D0_X_COUNT(len);
931 bfin_write_MDMA_D0_X_MODIFY(4); 726 bfin_write_MDMA_D0_X_MODIFY(4);
932 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 727 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index bb1f4fb2467c..bafcfa52142b 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -162,7 +162,7 @@ static void port_setup(unsigned short gpio, unsigned short usage)
162 162
163static void default_gpio(unsigned short gpio) 163static void default_gpio(unsigned short gpio)
164{ 164{
165 unsigned short bank,bitmask; 165 unsigned short bank, bitmask;
166 166
167 bank = gpio_bank(gpio); 167 bank = gpio_bank(gpio);
168 bitmask = gpio_bit(gpio); 168 bitmask = gpio_bit(gpio);
@@ -183,7 +183,7 @@ static int __init bfin_gpio_init(void)
183 183
184 printk(KERN_INFO "Blackfin GPIO Controller\n"); 184 printk(KERN_INFO "Blackfin GPIO Controller\n");
185 185
186 for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE) 186 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE)
187 reserved_map[gpio_bank(i)] = 0; 187 reserved_map[gpio_bank(i)] = 0;
188 188
189#if defined(BF537_FAMILY) && (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) 189#if defined(BF537_FAMILY) && (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
@@ -478,7 +478,7 @@ u32 gpio_pm_setup(void)
478 u32 sic_iwr = 0; 478 u32 sic_iwr = 0;
479 u16 bank, mask, i, gpio; 479 u16 bank, mask, i, gpio;
480 480
481 for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE) { 481 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
482 mask = wakeup_map[gpio_bank(i)]; 482 mask = wakeup_map[gpio_bank(i)];
483 bank = gpio_bank(i); 483 bank = gpio_bank(i);
484 484
@@ -522,12 +522,11 @@ u32 gpio_pm_setup(void)
522 return IWR_ENABLE_ALL; 522 return IWR_ENABLE_ALL;
523} 523}
524 524
525
526void gpio_pm_restore(void) 525void gpio_pm_restore(void)
527{ 526{
528 u16 bank, mask, i; 527 u16 bank, mask, i;
529 528
530 for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE) { 529 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
531 mask = wakeup_map[gpio_bank(i)]; 530 mask = wakeup_map[gpio_bank(i)];
532 bank = gpio_bank(i); 531 bank = gpio_bank(i);
533 532
@@ -591,7 +590,6 @@ int gpio_request(unsigned short gpio, const char *label)
591} 590}
592EXPORT_SYMBOL(gpio_request); 591EXPORT_SYMBOL(gpio_request);
593 592
594
595void gpio_free(unsigned short gpio) 593void gpio_free(unsigned short gpio)
596{ 594{
597 unsigned long flags; 595 unsigned long flags;
@@ -616,7 +614,6 @@ void gpio_free(unsigned short gpio)
616} 614}
617EXPORT_SYMBOL(gpio_free); 615EXPORT_SYMBOL(gpio_free);
618 616
619
620void gpio_direction_input(unsigned short gpio) 617void gpio_direction_input(unsigned short gpio)
621{ 618{
622 unsigned long flags; 619 unsigned long flags;
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
index f64ecb638fab..70455949cfd2 100644
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ b/arch/blackfin/kernel/bfin_ksyms.c
@@ -28,10 +28,11 @@
28 */ 28 */
29 29
30#include <linux/module.h> 30#include <linux/module.h>
31#include <asm/irq.h> 31#include <linux/irq.h>
32#include <linux/uaccess.h>
33
32#include <asm/checksum.h> 34#include <asm/checksum.h>
33#include <asm/cacheflush.h> 35#include <asm/cacheflush.h>
34#include <asm/uaccess.h>
35 36
36/* platform dependent support */ 37/* platform dependent support */
37 38
diff --git a/arch/blackfin/kernel/cacheinit.c b/arch/blackfin/kernel/cacheinit.c
new file mode 100644
index 000000000000..4d41a40e8133
--- /dev/null
+++ b/arch/blackfin/kernel/cacheinit.c
@@ -0,0 +1,66 @@
1/*
2 * Copyright 2004-2007 Analog Devices Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see the file COPYING, or write
16 * to the Free Software Foundation, Inc.,
17 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <linux/cpu.h>
21
22#include <asm/cacheflush.h>
23#include <asm/blackfin.h>
24#include <asm/cplbinit.h>
25
26#if defined(CONFIG_BLKFIN_CACHE)
27void bfin_icache_init(void)
28{
29 unsigned long *table = icplb_table;
30 unsigned long ctrl;
31 int i;
32
33 for (i = 0; i < MAX_CPLBS; i++) {
34 unsigned long addr = *table++;
35 unsigned long data = *table++;
36 if (addr == (unsigned long)-1)
37 break;
38 bfin_write32(ICPLB_ADDR0 + i * 4, addr);
39 bfin_write32(ICPLB_DATA0 + i * 4, data);
40 }
41 ctrl = bfin_read_IMEM_CONTROL();
42 ctrl |= IMC | ENICPLB;
43 bfin_write_IMEM_CONTROL(ctrl);
44}
45#endif
46
47#if defined(CONFIG_BLKFIN_DCACHE)
48void bfin_dcache_init(void)
49{
50 unsigned long *table = dcplb_table;
51 unsigned long ctrl;
52 int i;
53
54 for (i = 0; i < MAX_CPLBS; i++) {
55 unsigned long addr = *table++;
56 unsigned long data = *table++;
57 if (addr == (unsigned long)-1)
58 break;
59 bfin_write32(DCPLB_ADDR0 + i * 4, addr);
60 bfin_write32(DCPLB_DATA0 + i * 4, data);
61 }
62 ctrl = bfin_read_DMEM_CONTROL();
63 ctrl |= DMEM_CNTR;
64 bfin_write_DMEM_CONTROL(ctrl);
65}
66#endif
diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplbinit.c
new file mode 100644
index 000000000000..bbdb403fcb55
--- /dev/null
+++ b/arch/blackfin/kernel/cplbinit.c
@@ -0,0 +1,433 @@
1/*
2 * Blackfin CPLB initialization
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Bugs: Enter bugs at http://blackfin.uclinux.org/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see the file COPYING, or write
20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23#include <linux/module.h>
24
25#include <asm/blackfin.h>
26#include <asm/cplbinit.h>
27
28u_long icplb_table[MAX_CPLBS+1];
29u_long dcplb_table[MAX_CPLBS+1];
30
31#ifdef CONFIG_CPLB_SWITCH_TAB_L1
32u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
33u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
34
35#ifdef CONFIG_CPLB_INFO
36u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
37u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
38#endif /* CONFIG_CPLB_INFO */
39
40#else
41
42u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
43u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
44
45#ifdef CONFIG_CPLB_INFO
46u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
47u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
48#endif /* CONFIG_CPLB_INFO */
49
50#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
51
52struct s_cplb {
53 struct cplb_tab init_i;
54 struct cplb_tab init_d;
55 struct cplb_tab switch_i;
56 struct cplb_tab switch_d;
57};
58
59#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
60static struct cplb_desc cplb_data[] = {
61 {
62 .start = 0,
63 .end = SIZE_1K,
64 .psize = SIZE_1K,
65 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
66 .i_conf = SDRAM_OOPS,
67 .d_conf = SDRAM_OOPS,
68#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
69 .valid = 1,
70#else
71 .valid = 0,
72#endif
73 .name = "ZERO Pointer Saveguard",
74 },
75 {
76 .start = L1_CODE_START,
77 .end = L1_CODE_START + L1_CODE_LENGTH,
78 .psize = SIZE_4M,
79 .attr = INITIAL_T | SWITCH_T | I_CPLB,
80 .i_conf = L1_IMEMORY,
81 .d_conf = 0,
82 .valid = 1,
83 .name = "L1 I-Memory",
84 },
85 {
86 .start = L1_DATA_A_START,
87 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
88 .psize = SIZE_4M,
89 .attr = INITIAL_T | SWITCH_T | D_CPLB,
90 .i_conf = 0,
91 .d_conf = L1_DMEMORY,
92#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
93 .valid = 1,
94#else
95 .valid = 0,
96#endif
97 .name = "L1 D-Memory",
98 },
99 {
100 .start = 0,
101 .end = 0, /* dynamic */
102 .psize = 0,
103 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
104 .i_conf = SDRAM_IGENERIC,
105 .d_conf = SDRAM_DGENERIC,
106 .valid = 1,
107 .name = "SDRAM Kernel",
108 },
109 {
110 .start = 0, /* dynamic */
111 .end = 0, /* dynamic */
112 .psize = 0,
113 .attr = INITIAL_T | SWITCH_T | D_CPLB,
114 .i_conf = SDRAM_IGENERIC,
115 .d_conf = SDRAM_DNON_CHBL,
116 .valid = 1,
117 .name = "SDRAM RAM MTD",
118 },
119 {
120 .start = 0, /* dynamic */
121 .end = 0, /* dynamic */
122 .psize = SIZE_1M,
123 .attr = INITIAL_T | SWITCH_T | D_CPLB,
124 .d_conf = SDRAM_DNON_CHBL,
125 .valid = 1,
126 .name = "SDRAM Uncached DMA ZONE",
127 },
128 {
129 .start = 0, /* dynamic */
130 .end = 0, /* dynamic */
131 .psize = 0,
132 .attr = SWITCH_T | D_CPLB,
133 .i_conf = 0, /* dynamic */
134 .d_conf = 0, /* dynamic */
135 .valid = 1,
136 .name = "SDRAM Reserved Memory",
137 },
138 {
139 .start = ASYNC_BANK0_BASE,
140 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
141 .psize = 0,
142 .attr = SWITCH_T | D_CPLB,
143 .d_conf = SDRAM_EBIU,
144 .valid = 1,
145 .name = "ASYNC Memory",
146 },
147 {
148#if defined(CONFIG_BF561)
149 .start = L2_SRAM,
150 .end = L2_SRAM_END,
151 .psize = SIZE_1M,
152 .attr = SWITCH_T | D_CPLB,
153 .i_conf = L2_MEMORY,
154 .d_conf = L2_MEMORY,
155 .valid = 1,
156#else
157 .valid = 0,
158#endif
159 .name = "L2 Memory",
160 }
161};
162
163static u16 __init lock_kernel_check(u32 start, u32 end)
164{
165 if ((start <= (u32) _stext && end >= (u32) _end)
166 || (start >= (u32) _stext && end <= (u32) _end))
167 return IN_KERNEL;
168 return 0;
169}
170
171static unsigned short __init
172fill_cplbtab(struct cplb_tab *table,
173 unsigned long start, unsigned long end,
174 unsigned long block_size, unsigned long cplb_data)
175{
176 int i;
177
178 switch (block_size) {
179 case SIZE_4M:
180 i = 3;
181 break;
182 case SIZE_1M:
183 i = 2;
184 break;
185 case SIZE_4K:
186 i = 1;
187 break;
188 case SIZE_1K:
189 default:
190 i = 0;
191 break;
192 }
193
194 cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
195
196 while ((start < end) && (table->pos < table->size)) {
197
198 table->tab[table->pos++] = start;
199
200 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
201 table->tab[table->pos++] =
202 cplb_data | CPLB_LOCK | CPLB_DIRTY;
203 else
204 table->tab[table->pos++] = cplb_data;
205
206 start += block_size;
207 }
208 return 0;
209}
210
211static unsigned short __init
212close_cplbtab(struct cplb_tab *table)
213{
214
215 while (table->pos < table->size) {
216
217 table->tab[table->pos++] = 0;
218 table->tab[table->pos++] = 0; /* !CPLB_VALID */
219 }
220 return 0;
221}
222
223/* helper function */
224static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
225{
226 if (cplb_data[i].psize) {
227 fill_cplbtab(t,
228 cplb_data[i].start,
229 cplb_data[i].end,
230 cplb_data[i].psize,
231 cplb_data[i].i_conf);
232 } else {
233#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
234 if (i == SDRAM_KERN) {
235 fill_cplbtab(t,
236 cplb_data[i].start,
237 cplb_data[i].end,
238 SIZE_4M,
239 cplb_data[i].i_conf);
240 } else
241#endif
242 {
243 fill_cplbtab(t,
244 cplb_data[i].start,
245 a_start,
246 SIZE_1M,
247 cplb_data[i].i_conf);
248 fill_cplbtab(t,
249 a_start,
250 a_end,
251 SIZE_4M,
252 cplb_data[i].i_conf);
253 fill_cplbtab(t, a_end,
254 cplb_data[i].end,
255 SIZE_1M,
256 cplb_data[i].i_conf);
257 }
258 }
259}
260
261static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
262{
263 if (cplb_data[i].psize) {
264 fill_cplbtab(t,
265 cplb_data[i].start,
266 cplb_data[i].end,
267 cplb_data[i].psize,
268 cplb_data[i].d_conf);
269 } else {
270 fill_cplbtab(t,
271 cplb_data[i].start,
272 a_start, SIZE_1M,
273 cplb_data[i].d_conf);
274 fill_cplbtab(t, a_start,
275 a_end, SIZE_4M,
276 cplb_data[i].d_conf);
277 fill_cplbtab(t, a_end,
278 cplb_data[i].end,
279 SIZE_1M,
280 cplb_data[i].d_conf);
281 }
282}
283
284void __init generate_cpl_tables(void)
285{
286
287 u16 i, j, process;
288 u32 a_start, a_end, as, ae, as_1m;
289
290 struct cplb_tab *t_i = NULL;
291 struct cplb_tab *t_d = NULL;
292 struct s_cplb cplb;
293
294 cplb.init_i.size = MAX_CPLBS;
295 cplb.init_d.size = MAX_CPLBS;
296 cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
297 cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
298
299 cplb.init_i.pos = 0;
300 cplb.init_d.pos = 0;
301 cplb.switch_i.pos = 0;
302 cplb.switch_d.pos = 0;
303
304 cplb.init_i.tab = icplb_table;
305 cplb.init_d.tab = dcplb_table;
306 cplb.switch_i.tab = ipdt_table;
307 cplb.switch_d.tab = dpdt_table;
308
309 cplb_data[SDRAM_KERN].end = memory_end;
310
311#ifdef CONFIG_MTD_UCLINUX
312 cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
313 cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
314 cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
315# if defined(CONFIG_ROMFS_FS)
316 cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
317
318 /*
319 * The ROMFS_FS size is often not multiple of 1MB.
320 * This can cause multiple CPLB sets covering the same memory area.
321 * This will then cause multiple CPLB hit exceptions.
322 * Workaround: We ensure a contiguous memory area by extending the kernel
323 * memory section over the mtd section.
324 * For ROMFS_FS memory must be covered with ICPLBs anyways.
325 * So there is no difference between kernel and mtd memory setup.
326 */
327
328 cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
329 cplb_data[SDRAM_RAM_MTD].valid = 0;
330
331# endif
332#else
333 cplb_data[SDRAM_RAM_MTD].valid = 0;
334#endif
335
336 cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
337 cplb_data[SDRAM_DMAZ].end = _ramend;
338
339 cplb_data[RES_MEM].start = _ramend;
340 cplb_data[RES_MEM].end = physical_mem_end;
341
342 if (reserved_mem_dcache_on)
343 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
344 else
345 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
346
347 if (reserved_mem_icache_on)
348 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
349 else
350 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
351
352 for (i = ZERO_P; i <= L2_MEM; i++) {
353 if (!cplb_data[i].valid)
354 continue;
355
356 as_1m = cplb_data[i].start % SIZE_1M;
357
358 /* We need to make sure all sections are properly 1M aligned
359 * However between Kernel Memory and the Kernel mtd section, depending on the
360 * rootfs size, there can be overlapping memory areas.
361 */
362
363 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
364#ifdef CONFIG_MTD_UCLINUX
365 if (i == SDRAM_RAM_MTD) {
366 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
367 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
368 else
369 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
370 } else
371#endif
372 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
373 cplb_data[i].name, cplb_data[i].start);
374 }
375
376 as = cplb_data[i].start % SIZE_4M;
377 ae = cplb_data[i].end % SIZE_4M;
378
379 if (as)
380 a_start = cplb_data[i].start + (SIZE_4M - (as));
381 else
382 a_start = cplb_data[i].start;
383
384 a_end = cplb_data[i].end - ae;
385
386 for (j = INITIAL_T; j <= SWITCH_T; j++) {
387
388 switch (j) {
389 case INITIAL_T:
390 if (cplb_data[i].attr & INITIAL_T) {
391 t_i = &cplb.init_i;
392 t_d = &cplb.init_d;
393 process = 1;
394 } else
395 process = 0;
396 break;
397 case SWITCH_T:
398 if (cplb_data[i].attr & SWITCH_T) {
399 t_i = &cplb.switch_i;
400 t_d = &cplb.switch_d;
401 process = 1;
402 } else
403 process = 0;
404 break;
405 default:
406 process = 0;
407 break;
408 }
409
410 if (!process)
411 continue;
412 if (cplb_data[i].attr & I_CPLB)
413 __fill_code_cplbtab(t_i, i, a_start, a_end);
414
415 if (cplb_data[i].attr & D_CPLB)
416 __fill_data_cplbtab(t_d, i, a_start, a_end);
417 }
418 }
419
420/* close tables */
421
422 close_cplbtab(&cplb.init_i);
423 close_cplbtab(&cplb.init_d);
424
425 cplb.init_i.tab[cplb.init_i.pos] = -1;
426 cplb.init_d.tab[cplb.init_d.pos] = -1;
427 cplb.switch_i.tab[cplb.switch_i.pos] = -1;
428 cplb.switch_d.tab[cplb.switch_d.pos] = -1;
429
430}
431
432#endif
433
diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c
index 539eb24e062f..ea48d5b13f11 100644
--- a/arch/blackfin/kernel/dma-mapping.c
+++ b/arch/blackfin/kernel/dma-mapping.c
@@ -34,8 +34,8 @@
34#include <linux/spinlock.h> 34#include <linux/spinlock.h>
35#include <linux/device.h> 35#include <linux/device.h>
36#include <linux/dma-mapping.h> 36#include <linux/dma-mapping.h>
37#include <linux/io.h>
37#include <asm/cacheflush.h> 38#include <asm/cacheflush.h>
38#include <asm/io.h>
39#include <asm/bfin-global.h> 39#include <asm/bfin-global.h>
40 40
41static spinlock_t dma_page_lock; 41static spinlock_t dma_page_lock;
@@ -159,10 +159,13 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
159 159
160 BUG_ON(direction == DMA_NONE); 160 BUG_ON(direction == DMA_NONE);
161 161
162 for (i = 0; i < nents; i++) 162 for (i = 0; i < nents; i++, sg++) {
163 invalidate_dcache_range(sg_dma_address(&sg[i]), 163 sg->dma_address = page_address(sg->page) + sg->offset;
164 sg_dma_address(&sg[i]) + 164
165 sg_dma_len(&sg[i])); 165 invalidate_dcache_range(sg_dma_address(sg),
166 sg_dma_address(sg) +
167 sg_dma_len(sg));
168 }
166 169
167 return nents; 170 return nents;
168} 171}
diff --git a/arch/blackfin/kernel/dualcore_test.c b/arch/blackfin/kernel/dualcore_test.c
index 8b89c99f9dfa..0fcba74840b7 100644
--- a/arch/blackfin/kernel/dualcore_test.c
+++ b/arch/blackfin/kernel/dualcore_test.c
@@ -30,19 +30,19 @@
30#include <linux/init.h> 30#include <linux/init.h>
31#include <linux/module.h> 31#include <linux/module.h>
32 32
33static int *testarg = (int*)0xfeb00000; 33static int *testarg = (int *)0xfeb00000;
34 34
35static int test_init(void) 35static int test_init(void)
36{ 36{
37 *testarg = 1; 37 *testarg = 1;
38 printk("Dual core test module inserted: set testarg = [%d]\n @ [%p]\n", 38 printk(KERN_INFO "Dual core test module inserted: set testarg = [%d]\n @ [%p]\n",
39 *testarg, testarg); 39 *testarg, testarg);
40 return 0; 40 return 0;
41} 41}
42 42
43static void test_exit(void) 43static void test_exit(void)
44{ 44{
45 printk("Dual core test module removed: testarg = [%d]\n", *testarg); 45 printk(KERN_INFO "Dual core test module removed: testarg = [%d]\n", *testarg);
46} 46}
47 47
48module_init(test_init); 48module_init(test_init);
diff --git a/arch/blackfin/kernel/fixed_code.S b/arch/blackfin/kernel/fixed_code.S
new file mode 100644
index 000000000000..d8b1ebc70996
--- /dev/null
+++ b/arch/blackfin/kernel/fixed_code.S
@@ -0,0 +1,132 @@
1/*
2 * This file contains sequences of code that will be copied to a
3 * fixed location, defined in <asm/atomic_seq.h>. The interrupt
4 * handlers ensure that these sequences appear to be atomic when
5 * executed from userspace.
6 * These are aligned to 16 bytes, so that we have some space to replace
7 * these sequences with something else (e.g. kernel traps if we ever do
8 * BF561 SMP).
9 */
10#include <linux/linkage.h>
11#include <linux/unistd.h>
12#include <asm/entry.h>
13
14.text
15ENTRY(_fixed_code_start)
16
17.align 16
18ENTRY(_sigreturn_stub)
19 P0 = __NR_rt_sigreturn;
20 EXCPT 0;
21 /* Speculative execution paranoia. */
220: JUMP.S 0b;
23ENDPROC (_sigreturn_stub)
24
25.align 16
26 /*
27 * Atomic swap, 8 bit.
28 * Inputs: P0: memory address to use
29 * R1: value to store
30 * Output: R0: old contents of the memory address, zero extended.
31 */
32ENTRY(_atomic_xchg32)
33 R0 = [P0];
34 [P0] = R1;
35 rts;
36ENDPROC (_atomic_xchg32)
37
38.align 16
39 /*
40 * Compare and swap, 32 bit.
41 * Inputs: P0: memory address to use
42 * R1: compare value
43 * R2: new value to store
44 * The new value is stored if the contents of the memory
45 * address is equal to the compare value.
46 * Output: R0: old contents of the memory address.
47 */
48ENTRY(_atomic_cas32)
49 R0 = [P0];
50 CC = R0 == R1;
51 IF !CC JUMP 1f;
52 [P0] = R2;
531:
54 rts;
55ENDPROC (_atomic_cas32)
56
57.align 16
58 /*
59 * Atomic add, 32 bit.
60 * Inputs: P0: memory address to use
61 * R0: value to add
62 * Outputs: R0: new contents of the memory address.
63 * R1: previous contents of the memory address.
64 */
65ENTRY(_atomic_add32)
66 R1 = [P0];
67 R0 = R1 + R0;
68 [P0] = R0;
69 rts;
70ENDPROC (_atomic_add32)
71
72.align 16
73 /*
74 * Atomic sub, 32 bit.
75 * Inputs: P0: memory address to use
76 * R0: value to subtract
77 * Outputs: R0: new contents of the memory address.
78 * R1: previous contents of the memory address.
79 */
80ENTRY(_atomic_sub32)
81 R1 = [P0];
82 R0 = R1 - R0;
83 [P0] = R0;
84 rts;
85ENDPROC (_atomic_sub32)
86
87.align 16
88 /*
89 * Atomic ior, 32 bit.
90 * Inputs: P0: memory address to use
91 * R0: value to ior
92 * Outputs: R0: new contents of the memory address.
93 * R1: previous contents of the memory address.
94 */
95ENTRY(_atomic_ior32)
96 R1 = [P0];
97 R0 = R1 | R0;
98 [P0] = R0;
99 rts;
100ENDPROC (_atomic_ior32)
101
102.align 16
103 /*
104 * Atomic ior, 32 bit.
105 * Inputs: P0: memory address to use
106 * R0: value to ior
107 * Outputs: R0: new contents of the memory address.
108 * R1: previous contents of the memory address.
109 */
110ENTRY(_atomic_and32)
111 R1 = [P0];
112 R0 = R1 & R0;
113 [P0] = R0;
114 rts;
115ENDPROC (_atomic_ior32)
116
117.align 16
118 /*
119 * Atomic ior, 32 bit.
120 * Inputs: P0: memory address to use
121 * R0: value to ior
122 * Outputs: R0: new contents of the memory address.
123 * R1: previous contents of the memory address.
124 */
125ENTRY(_atomic_xor32)
126 R1 = [P0];
127 R0 = R1 ^ R0;
128 [P0] = R0;
129 rts;
130ENDPROC (_atomic_ior32)
131
132ENTRY(_fixed_code_end)
diff --git a/arch/blackfin/kernel/flat.c b/arch/blackfin/kernel/flat.c
index a92587b628b5..d188b2430536 100644
--- a/arch/blackfin/kernel/flat.c
+++ b/arch/blackfin/kernel/flat.c
@@ -36,24 +36,22 @@ unsigned long bfin_get_addr_from_rp(unsigned long *ptr,
36 unsigned long val; 36 unsigned long val;
37 37
38 switch (type) { 38 switch (type) {
39 case FLAT_BFIN_RELOC_TYPE_16_BIT: 39 case FLAT_BFIN_RELOC_TYPE_16_BIT:
40 case FLAT_BFIN_RELOC_TYPE_16H_BIT: 40 case FLAT_BFIN_RELOC_TYPE_16H_BIT:
41 usptr = (unsigned short *)ptr; 41 usptr = (unsigned short *)ptr;
42 pr_debug("*usptr = %x", get_unaligned(usptr)); 42 pr_debug("*usptr = %x", get_unaligned(usptr));
43 val = get_unaligned(usptr); 43 val = get_unaligned(usptr);
44 val += *persistent; 44 val += *persistent;
45 break; 45 break;
46 46
47 case FLAT_BFIN_RELOC_TYPE_32_BIT: 47 case FLAT_BFIN_RELOC_TYPE_32_BIT:
48 pr_debug("*ptr = %lx", get_unaligned(ptr)); 48 pr_debug("*ptr = %lx", get_unaligned(ptr));
49 val = get_unaligned(ptr); 49 val = get_unaligned(ptr);
50 break; 50 break;
51 51
52 default: 52 default:
53 pr_debug("BINFMT_FLAT: Unknown relocation type %x\n", 53 pr_debug("BINFMT_FLAT: Unknown relocation type %x\n", type);
54 type); 54 return 0;
55
56 return 0;
57 } 55 }
58 56
59 /* 57 /*
@@ -81,21 +79,20 @@ void bfin_put_addr_at_rp(unsigned long *ptr, unsigned long addr,
81 int type = (relval >> 26) & 7; 79 int type = (relval >> 26) & 7;
82 80
83 switch (type) { 81 switch (type) {
84 case FLAT_BFIN_RELOC_TYPE_16_BIT: 82 case FLAT_BFIN_RELOC_TYPE_16_BIT:
85 put_unaligned(addr, usptr); 83 put_unaligned(addr, usptr);
86 pr_debug("new value %x at %p", get_unaligned(usptr), 84 pr_debug("new value %x at %p", get_unaligned(usptr), usptr);
87 usptr); 85 break;
88 break;
89 86
90 case FLAT_BFIN_RELOC_TYPE_16H_BIT: 87 case FLAT_BFIN_RELOC_TYPE_16H_BIT:
91 put_unaligned(addr >> 16, usptr); 88 put_unaligned(addr >> 16, usptr);
92 pr_debug("new value %x", get_unaligned(usptr)); 89 pr_debug("new value %x", get_unaligned(usptr));
93 break; 90 break;
94 91
95 case FLAT_BFIN_RELOC_TYPE_32_BIT: 92 case FLAT_BFIN_RELOC_TYPE_32_BIT:
96 put_unaligned(addr, ptr); 93 put_unaligned(addr, ptr);
97 pr_debug("new ptr =%lx", get_unaligned(ptr)); 94 pr_debug("new ptr =%lx", get_unaligned(ptr));
98 break; 95 break;
99 } 96 }
100} 97}
101EXPORT_SYMBOL(bfin_put_addr_at_rp); 98EXPORT_SYMBOL(bfin_put_addr_at_rp);
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 80996a1a94ca..1fc001c7abda 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -82,7 +82,7 @@ int show_interrupts(struct seq_file *p, void *v)
82 seq_printf(p, ", %s", action->name); 82 seq_printf(p, ", %s", action->name);
83 83
84 seq_putc(p, '\n'); 84 seq_putc(p, '\n');
85 unlock: 85 unlock:
86 spin_unlock_irqrestore(&irq_desc[i].lock, flags); 86 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
87 } else if (i == NR_IRQS) { 87 } else if (i == NR_IRQS) {
88 seq_printf(p, "Err: %10lu\n", irq_err_count); 88 seq_printf(p, "Err: %10lu\n", irq_err_count);
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
new file mode 100644
index 000000000000..a9c15515bfd7
--- /dev/null
+++ b/arch/blackfin/kernel/kgdb.c
@@ -0,0 +1,421 @@
1/*
2 * File: arch/blackfin/kernel/kgdb.c
3 * Based on:
4 * Author: Sonic Zhang
5 *
6 * Created:
7 * Description:
8 *
9 * Rev: $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $
10 *
11 * Modified:
12 * Copyright 2005-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see the file COPYING, or write
28 * to the Free Software Foundation, Inc.,
29 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 */
31
32#include <linux/string.h>
33#include <linux/kernel.h>
34#include <linux/sched.h>
35#include <linux/smp.h>
36#include <linux/spinlock.h>
37#include <linux/delay.h>
38#include <linux/ptrace.h> /* for linux pt_regs struct */
39#include <linux/kgdb.h>
40#include <linux/console.h>
41#include <linux/init.h>
42#include <linux/debugger.h>
43#include <linux/errno.h>
44#include <linux/irq.h>
45#include <asm/system.h>
46#include <asm/traps.h>
47#include <asm/blackfin.h>
48
49/* Put the error code here just in case the user cares. */
50int gdb_bf533errcode;
51/* Likewise, the vector number here (since GDB only gets the signal
52 number through the usual means, and that's not very specific). */
53int gdb_bf533vector = -1;
54
55#if KGDB_MAX_NO_CPUS != 8
56#error change the definition of slavecpulocks
57#endif
58
59void regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
60{
61 gdb_regs[BFIN_R0] = regs->r0;
62 gdb_regs[BFIN_R1] = regs->r1;
63 gdb_regs[BFIN_R2] = regs->r2;
64 gdb_regs[BFIN_R3] = regs->r3;
65 gdb_regs[BFIN_R4] = regs->r4;
66 gdb_regs[BFIN_R5] = regs->r5;
67 gdb_regs[BFIN_R6] = regs->r6;
68 gdb_regs[BFIN_R7] = regs->r7;
69 gdb_regs[BFIN_P0] = regs->p0;
70 gdb_regs[BFIN_P1] = regs->p1;
71 gdb_regs[BFIN_P2] = regs->p2;
72 gdb_regs[BFIN_P3] = regs->p3;
73 gdb_regs[BFIN_P4] = regs->p4;
74 gdb_regs[BFIN_P5] = regs->p5;
75 gdb_regs[BFIN_SP] = regs->reserved;
76 gdb_regs[BFIN_FP] = regs->fp;
77 gdb_regs[BFIN_I0] = regs->i0;
78 gdb_regs[BFIN_I1] = regs->i1;
79 gdb_regs[BFIN_I2] = regs->i2;
80 gdb_regs[BFIN_I3] = regs->i3;
81 gdb_regs[BFIN_M0] = regs->m0;
82 gdb_regs[BFIN_M1] = regs->m1;
83 gdb_regs[BFIN_M2] = regs->m2;
84 gdb_regs[BFIN_M3] = regs->m3;
85 gdb_regs[BFIN_B0] = regs->b0;
86 gdb_regs[BFIN_B1] = regs->b1;
87 gdb_regs[BFIN_B2] = regs->b2;
88 gdb_regs[BFIN_B3] = regs->b3;
89 gdb_regs[BFIN_L0] = regs->l0;
90 gdb_regs[BFIN_L1] = regs->l1;
91 gdb_regs[BFIN_L2] = regs->l2;
92 gdb_regs[BFIN_L3] = regs->l3;
93 gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
94 gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
95 gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
96 gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
97 gdb_regs[BFIN_ASTAT] = regs->astat;
98 gdb_regs[BFIN_RETS] = regs->rets;
99 gdb_regs[BFIN_LC0] = regs->lc0;
100 gdb_regs[BFIN_LT0] = regs->lt0;
101 gdb_regs[BFIN_LB0] = regs->lb0;
102 gdb_regs[BFIN_LC1] = regs->lc1;
103 gdb_regs[BFIN_LT1] = regs->lt1;
104 gdb_regs[BFIN_LB1] = regs->lb1;
105 gdb_regs[BFIN_CYCLES] = 0;
106 gdb_regs[BFIN_CYCLES2] = 0;
107 gdb_regs[BFIN_USP] = regs->usp;
108 gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
109 gdb_regs[BFIN_SYSCFG] = regs->syscfg;
110 gdb_regs[BFIN_RETI] = regs->pc;
111 gdb_regs[BFIN_RETX] = regs->retx;
112 gdb_regs[BFIN_RETN] = regs->retn;
113 gdb_regs[BFIN_RETE] = regs->rete;
114 gdb_regs[BFIN_PC] = regs->pc;
115 gdb_regs[BFIN_CC] = 0;
116 gdb_regs[BFIN_EXTRA1] = 0;
117 gdb_regs[BFIN_EXTRA2] = 0;
118 gdb_regs[BFIN_EXTRA3] = 0;
119 gdb_regs[BFIN_IPEND] = regs->ipend;
120}
121
122/*
123 * Extracts ebp, esp and eip values understandable by gdb from the values
124 * saved by switch_to.
125 * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
126 * prior to entering switch_to is 8 greater then the value that is saved.
127 * If switch_to changes, change following code appropriately.
128 */
129void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
130{
131 gdb_regs[BFIN_SP] = p->thread.ksp;
132 gdb_regs[BFIN_PC] = p->thread.pc;
133 gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
134}
135
136void gdb_regs_to_regs(unsigned long *gdb_regs, struct pt_regs *regs)
137{
138 regs->r0 = gdb_regs[BFIN_R0];
139 regs->r1 = gdb_regs[BFIN_R1];
140 regs->r2 = gdb_regs[BFIN_R2];
141 regs->r3 = gdb_regs[BFIN_R3];
142 regs->r4 = gdb_regs[BFIN_R4];
143 regs->r5 = gdb_regs[BFIN_R5];
144 regs->r6 = gdb_regs[BFIN_R6];
145 regs->r7 = gdb_regs[BFIN_R7];
146 regs->p0 = gdb_regs[BFIN_P0];
147 regs->p1 = gdb_regs[BFIN_P1];
148 regs->p2 = gdb_regs[BFIN_P2];
149 regs->p3 = gdb_regs[BFIN_P3];
150 regs->p4 = gdb_regs[BFIN_P4];
151 regs->p5 = gdb_regs[BFIN_P5];
152 regs->fp = gdb_regs[BFIN_FP];
153 regs->i0 = gdb_regs[BFIN_I0];
154 regs->i1 = gdb_regs[BFIN_I1];
155 regs->i2 = gdb_regs[BFIN_I2];
156 regs->i3 = gdb_regs[BFIN_I3];
157 regs->m0 = gdb_regs[BFIN_M0];
158 regs->m1 = gdb_regs[BFIN_M1];
159 regs->m2 = gdb_regs[BFIN_M2];
160 regs->m3 = gdb_regs[BFIN_M3];
161 regs->b0 = gdb_regs[BFIN_B0];
162 regs->b1 = gdb_regs[BFIN_B1];
163 regs->b2 = gdb_regs[BFIN_B2];
164 regs->b3 = gdb_regs[BFIN_B3];
165 regs->l0 = gdb_regs[BFIN_L0];
166 regs->l1 = gdb_regs[BFIN_L1];
167 regs->l2 = gdb_regs[BFIN_L2];
168 regs->l3 = gdb_regs[BFIN_L3];
169 regs->a0x = gdb_regs[BFIN_A0_DOT_X];
170 regs->a0w = gdb_regs[BFIN_A0_DOT_W];
171 regs->a1x = gdb_regs[BFIN_A1_DOT_X];
172 regs->a1w = gdb_regs[BFIN_A1_DOT_W];
173 regs->rets = gdb_regs[BFIN_RETS];
174 regs->lc0 = gdb_regs[BFIN_LC0];
175 regs->lt0 = gdb_regs[BFIN_LT0];
176 regs->lb0 = gdb_regs[BFIN_LB0];
177 regs->lc1 = gdb_regs[BFIN_LC1];
178 regs->lt1 = gdb_regs[BFIN_LT1];
179 regs->lb1 = gdb_regs[BFIN_LB1];
180 regs->usp = gdb_regs[BFIN_USP];
181 regs->syscfg = gdb_regs[BFIN_SYSCFG];
182 regs->retx = gdb_regs[BFIN_PC];
183 regs->retn = gdb_regs[BFIN_RETN];
184 regs->rete = gdb_regs[BFIN_RETE];
185 regs->pc = gdb_regs[BFIN_PC];
186
187#if 0 /* can't change these */
188 regs->astat = gdb_regs[BFIN_ASTAT];
189 regs->seqstat = gdb_regs[BFIN_SEQSTAT];
190 regs->ipend = gdb_regs[BFIN_IPEND];
191#endif
192}
193
194struct hw_breakpoint {
195 unsigned int occupied:1;
196 unsigned int skip:1;
197 unsigned int enabled:1;
198 unsigned int type:1;
199 unsigned int dataacc:2;
200 unsigned short count;
201 unsigned int addr;
202} breakinfo[HW_BREAKPOINT_NUM];
203
204int kgdb_arch_init(void)
205{
206 kgdb_remove_all_hw_break();
207 return 0;
208}
209
210int kgdb_set_hw_break(unsigned long addr)
211{
212 int breakno;
213 for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++)
214 if (!breakinfo[breakno].occupied) {
215 breakinfo[breakno].occupied = 1;
216 breakinfo[breakno].enabled = 1;
217 breakinfo[breakno].type = 1;
218 breakinfo[breakno].addr = addr;
219 return 0;
220 }
221
222 return -ENOSPC;
223}
224
225int kgdb_remove_hw_break(unsigned long addr)
226{
227 int breakno;
228 for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++)
229 if (breakinfo[breakno].addr == addr)
230 memset(&(breakinfo[breakno]), 0, sizeof(struct hw_breakpoint));
231
232 return 0;
233}
234
235void kgdb_remove_all_hw_break(void)
236{
237 memset(breakinfo, 0, sizeof(struct hw_breakpoint)*8);
238}
239
240/*
241void kgdb_show_info(void)
242{
243 printk(KERN_DEBUG "hwd: wpia0=0x%x, wpiacnt0=%d, wpiactl=0x%x, wpstat=0x%x\n",
244 bfin_read_WPIA0(), bfin_read_WPIACNT0(),
245 bfin_read_WPIACTL(), bfin_read_WPSTAT());
246}
247*/
248
249void kgdb_correct_hw_break(void)
250{
251 int breakno;
252 int correctit;
253 uint32_t wpdactl = bfin_read_WPDACTL();
254
255 correctit = 0;
256 for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++) {
257 if (breakinfo[breakno].type == 1) {
258 switch (breakno) {
259 case 0:
260 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN0)) {
261 correctit = 1;
262 wpdactl &= ~(WPIREN01|EMUSW0);
263 wpdactl |= WPIAEN0|WPICNTEN0;
264 bfin_write_WPIA0(breakinfo[breakno].addr);
265 bfin_write_WPIACNT0(breakinfo[breakno].skip);
266 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN0)) {
267 correctit = 1;
268 wpdactl &= ~WPIAEN0;
269 }
270 break;
271
272 case 1:
273 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN1)) {
274 correctit = 1;
275 wpdactl &= ~(WPIREN01|EMUSW1);
276 wpdactl |= WPIAEN1|WPICNTEN1;
277 bfin_write_WPIA1(breakinfo[breakno].addr);
278 bfin_write_WPIACNT1(breakinfo[breakno].skip);
279 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN1)) {
280 correctit = 1;
281 wpdactl &= ~WPIAEN1;
282 }
283 break;
284
285 case 2:
286 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN2)) {
287 correctit = 1;
288 wpdactl &= ~(WPIREN23|EMUSW2);
289 wpdactl |= WPIAEN2|WPICNTEN2;
290 bfin_write_WPIA2(breakinfo[breakno].addr);
291 bfin_write_WPIACNT2(breakinfo[breakno].skip);
292 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN2)) {
293 correctit = 1;
294 wpdactl &= ~WPIAEN2;
295 }
296 break;
297
298 case 3:
299 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN3)) {
300 correctit = 1;
301 wpdactl &= ~(WPIREN23|EMUSW3);
302 wpdactl |= WPIAEN3|WPICNTEN3;
303 bfin_write_WPIA3(breakinfo[breakno].addr);
304 bfin_write_WPIACNT3(breakinfo[breakno].skip);
305 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN3)) {
306 correctit = 1;
307 wpdactl &= ~WPIAEN3;
308 }
309 break;
310 case 4:
311 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN4)) {
312 correctit = 1;
313 wpdactl &= ~(WPIREN45|EMUSW4);
314 wpdactl |= WPIAEN4|WPICNTEN4;
315 bfin_write_WPIA4(breakinfo[breakno].addr);
316 bfin_write_WPIACNT4(breakinfo[breakno].skip);
317 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN4)) {
318 correctit = 1;
319 wpdactl &= ~WPIAEN4;
320 }
321 break;
322 case 5:
323 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN5)) {
324 correctit = 1;
325 wpdactl &= ~(WPIREN45|EMUSW5);
326 wpdactl |= WPIAEN5|WPICNTEN5;
327 bfin_write_WPIA5(breakinfo[breakno].addr);
328 bfin_write_WPIACNT5(breakinfo[breakno].skip);
329 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN5)) {
330 correctit = 1;
331 wpdactl &= ~WPIAEN5;
332 }
333 break;
334 }
335 }
336 }
337 if (correctit) {
338 wpdactl &= ~WPAND;
339 wpdactl |= WPPWR;
340 /*printk("correct_hw_break: wpdactl=0x%x\n", wpdactl);*/
341 bfin_write_WPDACTL(wpdactl);
342 CSYNC();
343 /*kgdb_show_info();*/
344 }
345}
346
347void kgdb_disable_hw_debug(struct pt_regs *regs)
348{
349 /* Disable hardware debugging while we are in kgdb */
350 bfin_write_WPIACTL(bfin_read_WPIACTL() & ~0x1);
351 CSYNC();
352}
353
354void kgdb_post_master_code(struct pt_regs *regs, int eVector, int err_code)
355{
356 /* Master processor is completely in the debugger */
357 gdb_bf533vector = eVector;
358 gdb_bf533errcode = err_code;
359}
360
361int kgdb_arch_handle_exception(int exceptionVector, int signo,
362 int err_code, char *remcom_in_buffer,
363 char *remcom_out_buffer,
364 struct pt_regs *linux_regs)
365{
366 long addr;
367 long breakno;
368 char *ptr;
369 int newPC;
370 int wp_status;
371
372 switch (remcom_in_buffer[0]) {
373 case 'c':
374 case 's':
375 if (kgdb_contthread && kgdb_contthread != current) {
376 strcpy(remcom_out_buffer, "E00");
377 break;
378 }
379
380 kgdb_contthread = NULL;
381
382 /* try to read optional parameter, pc unchanged if no parm */
383 ptr = &remcom_in_buffer[1];
384 if (kgdb_hex2long(&ptr, &addr)) {
385 linux_regs->retx = addr;
386 }
387 newPC = linux_regs->retx;
388
389 /* clear the trace bit */
390 linux_regs->syscfg &= 0xfffffffe;
391
392 /* set the trace bit if we're stepping */
393 if (remcom_in_buffer[0] == 's') {
394 linux_regs->syscfg |= 0x1;
395 debugger_step = 1;
396 }
397
398 wp_status = bfin_read_WPSTAT();
399 CSYNC();
400
401 if (exceptionVector == VEC_WATCH) {
402 for (breakno = 0; breakno < 6; ++breakno) {
403 if (wp_status & (1 << breakno)) {
404 breakinfo->skip = 1;
405 break;
406 }
407 }
408 }
409 kgdb_correct_hw_break();
410
411 bfin_write_WPSTAT(0);
412
413 return 0;
414 } /* switch */
415 return -1; /* this means that we do not want to exit from the handler */
416}
417
418struct kgdb_arch arch_kgdb_ops = {
419 .gdb_bpt_instr = {0xa1},
420 .flags = KGDB_HW_BREAKPOINT,
421};
diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c
index 372f756f1ad9..8b9fe29d03f4 100644
--- a/arch/blackfin/kernel/module.c
+++ b/arch/blackfin/kernel/module.c
@@ -165,8 +165,8 @@ module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs,
165 165
166 for (s = sechdrs; s < sechdrs_end; ++s) { 166 for (s = sechdrs; s < sechdrs_end; ++s) {
167 if ((strcmp(".l1.text", secstrings + s->sh_name) == 0) || 167 if ((strcmp(".l1.text", secstrings + s->sh_name) == 0) ||
168 ((strcmp(".text", secstrings + s->sh_name)==0) && 168 ((strcmp(".text", secstrings + s->sh_name) == 0) &&
169 (hdr->e_flags & FLG_CODE_IN_L1) && (s->sh_size > 0))) { 169 (hdr->e_flags & FLG_CODE_IN_L1) && (s->sh_size > 0))) {
170 mod->arch.text_l1 = s; 170 mod->arch.text_l1 = s;
171 dest = l1_inst_sram_alloc(s->sh_size); 171 dest = l1_inst_sram_alloc(s->sh_size);
172 if (dest == NULL) { 172 if (dest == NULL) {
@@ -179,9 +179,9 @@ module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs,
179 s->sh_flags &= ~SHF_ALLOC; 179 s->sh_flags &= ~SHF_ALLOC;
180 s->sh_addr = (unsigned long)dest; 180 s->sh_addr = (unsigned long)dest;
181 } 181 }
182 if ((strcmp(".l1.data", secstrings + s->sh_name) == 0)|| 182 if ((strcmp(".l1.data", secstrings + s->sh_name) == 0) ||
183 ((strcmp(".data", secstrings + s->sh_name)==0) && 183 ((strcmp(".data", secstrings + s->sh_name) == 0) &&
184 (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) { 184 (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) {
185 mod->arch.data_a_l1 = s; 185 mod->arch.data_a_l1 = s;
186 dest = l1_data_sram_alloc(s->sh_size); 186 dest = l1_data_sram_alloc(s->sh_size);
187 if (dest == NULL) { 187 if (dest == NULL) {
@@ -195,8 +195,8 @@ module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs,
195 s->sh_addr = (unsigned long)dest; 195 s->sh_addr = (unsigned long)dest;
196 } 196 }
197 if (strcmp(".l1.bss", secstrings + s->sh_name) == 0 || 197 if (strcmp(".l1.bss", secstrings + s->sh_name) == 0 ||
198 ((strcmp(".bss", secstrings + s->sh_name)==0) && 198 ((strcmp(".bss", secstrings + s->sh_name) == 0) &&
199 (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) { 199 (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) {
200 mod->arch.bss_a_l1 = s; 200 mod->arch.bss_a_l1 = s;
201 dest = l1_data_sram_alloc(s->sh_size); 201 dest = l1_data_sram_alloc(s->sh_size);
202 if (dest == NULL) { 202 if (dest == NULL) {
@@ -326,7 +326,7 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
326 pr_debug("before %x after %x\n", *location16, 326 pr_debug("before %x after %x\n", *location16,
327 (value & 0xffff)); 327 (value & 0xffff));
328 tmp = (value & 0xffff); 328 tmp = (value & 0xffff);
329 if((unsigned long)location16 >= L1_CODE_START) { 329 if ((unsigned long)location16 >= L1_CODE_START) {
330 dma_memcpy(location16, &tmp, 2); 330 dma_memcpy(location16, &tmp, 2);
331 } else 331 } else
332 *location16 = tmp; 332 *location16 = tmp;
@@ -335,7 +335,7 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
335 pr_debug("before %x after %x\n", *location16, 335 pr_debug("before %x after %x\n", *location16,
336 ((value >> 16) & 0xffff)); 336 ((value >> 16) & 0xffff));
337 tmp = ((value >> 16) & 0xffff); 337 tmp = ((value >> 16) & 0xffff);
338 if((unsigned long)location16 >= L1_CODE_START) { 338 if ((unsigned long)location16 >= L1_CODE_START) {
339 dma_memcpy(location16, &tmp, 2); 339 dma_memcpy(location16, &tmp, 2);
340 } else 340 } else
341 *location16 = tmp; 341 *location16 = tmp;
@@ -404,8 +404,8 @@ module_finalize(const Elf_Ehdr * hdr,
404 continue; 404 continue;
405 405
406 if ((sechdrs[i].sh_type == SHT_RELA) && 406 if ((sechdrs[i].sh_type == SHT_RELA) &&
407 ((strcmp(".rela.l1.text", secstrings + sechdrs[i].sh_name) == 0)|| 407 ((strcmp(".rela.l1.text", secstrings + sechdrs[i].sh_name) == 0) ||
408 ((strcmp(".rela.text", secstrings + sechdrs[i].sh_name) == 0) && 408 ((strcmp(".rela.text", secstrings + sechdrs[i].sh_name) == 0) &&
409 (hdr->e_flags & FLG_CODE_IN_L1)))) { 409 (hdr->e_flags & FLG_CODE_IN_L1)))) {
410 apply_relocate_add((Elf_Shdr *) sechdrs, strtab, 410 apply_relocate_add((Elf_Shdr *) sechdrs, strtab,
411 symindex, i, mod); 411 symindex, i, mod);
@@ -417,13 +417,13 @@ module_finalize(const Elf_Ehdr * hdr,
417void module_arch_cleanup(struct module *mod) 417void module_arch_cleanup(struct module *mod)
418{ 418{
419 if ((mod->arch.text_l1) && (mod->arch.text_l1->sh_addr)) 419 if ((mod->arch.text_l1) && (mod->arch.text_l1->sh_addr))
420 l1_inst_sram_free((void*)mod->arch.text_l1->sh_addr); 420 l1_inst_sram_free((void *)mod->arch.text_l1->sh_addr);
421 if ((mod->arch.data_a_l1) && (mod->arch.data_a_l1->sh_addr)) 421 if ((mod->arch.data_a_l1) && (mod->arch.data_a_l1->sh_addr))
422 l1_data_sram_free((void*)mod->arch.data_a_l1->sh_addr); 422 l1_data_sram_free((void *)mod->arch.data_a_l1->sh_addr);
423 if ((mod->arch.bss_a_l1) && (mod->arch.bss_a_l1->sh_addr)) 423 if ((mod->arch.bss_a_l1) && (mod->arch.bss_a_l1->sh_addr))
424 l1_data_sram_free((void*)mod->arch.bss_a_l1->sh_addr); 424 l1_data_sram_free((void *)mod->arch.bss_a_l1->sh_addr);
425 if ((mod->arch.data_b_l1) && (mod->arch.data_b_l1->sh_addr)) 425 if ((mod->arch.data_b_l1) && (mod->arch.data_b_l1->sh_addr))
426 l1_data_B_sram_free((void*)mod->arch.data_b_l1->sh_addr); 426 l1_data_B_sram_free((void *)mod->arch.data_b_l1->sh_addr);
427 if ((mod->arch.bss_b_l1) && (mod->arch.bss_b_l1->sh_addr)) 427 if ((mod->arch.bss_b_l1) && (mod->arch.bss_b_l1->sh_addr))
428 l1_data_B_sram_free((void*)mod->arch.bss_b_l1->sh_addr); 428 l1_data_B_sram_free((void *)mod->arch.bss_b_l1->sh_addr);
429} 429}
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 3eff7439d8d3..5a51dd6ab280 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -32,9 +32,10 @@
32#include <linux/unistd.h> 32#include <linux/unistd.h>
33#include <linux/user.h> 33#include <linux/user.h>
34#include <linux/a.out.h> 34#include <linux/a.out.h>
35#include <linux/uaccess.h>
35 36
36#include <asm/blackfin.h> 37#include <asm/blackfin.h>
37#include <asm/uaccess.h> 38#include <asm/fixed_code.h>
38 39
39#define LED_ON 0 40#define LED_ON 0
40#define LED_OFF 1 41#define LED_OFF 1
@@ -173,8 +174,8 @@ void show_regs(struct pt_regs *regs)
173 printk(KERN_NOTICE "R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", 174 printk(KERN_NOTICE "R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
174 regs->r4, regs->r5, regs->r6, regs->r7); 175 regs->r4, regs->r5, regs->r6, regs->r7);
175 176
176 if (!(regs->ipend)) 177 if (!regs->ipend)
177 printk("USP: %08lx\n", rdusp()); 178 printk(KERN_NOTICE "USP: %08lx\n", rdusp());
178} 179}
179 180
180/* Fill in the fpu structure for a core dump. */ 181/* Fill in the fpu structure for a core dump. */
@@ -322,7 +323,7 @@ asmlinkage int sys_execve(char *name, char **argv, char **envp)
322 goto out; 323 goto out;
323 error = do_execve(filename, argv, envp, regs); 324 error = do_execve(filename, argv, envp, regs);
324 putname(filename); 325 putname(filename);
325 out: 326 out:
326 unlock_kernel(); 327 unlock_kernel();
327 return error; 328 return error;
328} 329}
@@ -350,13 +351,77 @@ unsigned long get_wchan(struct task_struct *p)
350 return 0; 351 return 0;
351} 352}
352 353
354void finish_atomic_sections (struct pt_regs *regs)
355{
356 if (regs->pc < ATOMIC_SEQS_START || regs->pc >= ATOMIC_SEQS_END)
357 return;
358
359 switch (regs->pc) {
360 case ATOMIC_XCHG32 + 2:
361 put_user(regs->r1, (int *)regs->p0);
362 regs->pc += 2;
363 break;
364
365 case ATOMIC_CAS32 + 2:
366 case ATOMIC_CAS32 + 4:
367 if (regs->r0 == regs->r1)
368 put_user(regs->r2, (int *)regs->p0);
369 regs->pc = ATOMIC_CAS32 + 8;
370 break;
371 case ATOMIC_CAS32 + 6:
372 put_user(regs->r2, (int *)regs->p0);
373 regs->pc += 2;
374 break;
375
376 case ATOMIC_ADD32 + 2:
377 regs->r0 = regs->r1 + regs->r0;
378 /* fall through */
379 case ATOMIC_ADD32 + 4:
380 put_user(regs->r0, (int *)regs->p0);
381 regs->pc = ATOMIC_ADD32 + 6;
382 break;
383
384 case ATOMIC_SUB32 + 2:
385 regs->r0 = regs->r1 - regs->r0;
386 /* fall through */
387 case ATOMIC_SUB32 + 4:
388 put_user(regs->r0, (int *)regs->p0);
389 regs->pc = ATOMIC_SUB32 + 6;
390 break;
391
392 case ATOMIC_IOR32 + 2:
393 regs->r0 = regs->r1 | regs->r0;
394 /* fall through */
395 case ATOMIC_IOR32 + 4:
396 put_user(regs->r0, (int *)regs->p0);
397 regs->pc = ATOMIC_IOR32 + 6;
398 break;
399
400 case ATOMIC_AND32 + 2:
401 regs->r0 = regs->r1 & regs->r0;
402 /* fall through */
403 case ATOMIC_AND32 + 4:
404 put_user(regs->r0, (int *)regs->p0);
405 regs->pc = ATOMIC_AND32 + 6;
406 break;
407
408 case ATOMIC_XOR32 + 2:
409 regs->r0 = regs->r1 ^ regs->r0;
410 /* fall through */
411 case ATOMIC_XOR32 + 4:
412 put_user(regs->r0, (int *)regs->p0);
413 regs->pc = ATOMIC_XOR32 + 6;
414 break;
415 }
416}
417
353#if defined(CONFIG_ACCESS_CHECK) 418#if defined(CONFIG_ACCESS_CHECK)
354int _access_ok(unsigned long addr, unsigned long size) 419int _access_ok(unsigned long addr, unsigned long size)
355{ 420{
356 421
357 if (addr > (addr + size)) 422 if (addr > (addr + size))
358 return 0; 423 return 0;
359 if (segment_eq(get_fs(),KERNEL_DS)) 424 if (segment_eq(get_fs(), KERNEL_DS))
360 return 1; 425 return 1;
361#ifdef CONFIG_MTD_UCLINUX 426#ifdef CONFIG_MTD_UCLINUX
362 if (addr >= memory_start && (addr + size) <= memory_end) 427 if (addr >= memory_start && (addr + size) <= memory_end)
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index e718bb4a1ef0..ed800c7456dd 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -36,8 +36,8 @@
36#include <linux/ptrace.h> 36#include <linux/ptrace.h>
37#include <linux/user.h> 37#include <linux/user.h>
38#include <linux/signal.h> 38#include <linux/signal.h>
39#include <linux/uaccess.h>
39 40
40#include <asm/uaccess.h>
41#include <asm/page.h> 41#include <asm/page.h>
42#include <asm/pgtable.h> 42#include <asm/pgtable.h>
43#include <asm/system.h> 43#include <asm/system.h>
@@ -122,7 +122,7 @@ static inline long get_reg(struct task_struct *task, int regno)
122static inline int 122static inline int
123put_reg(struct task_struct *task, int regno, unsigned long data) 123put_reg(struct task_struct *task, int regno, unsigned long data)
124{ 124{
125 char * reg_ptr; 125 char *reg_ptr;
126 126
127 struct pt_regs *regs = 127 struct pt_regs *regs =
128 (struct pt_regs *)((unsigned long)task_stack_page(task) + 128 (struct pt_regs *)((unsigned long)task_stack_page(task) +
@@ -146,7 +146,7 @@ put_reg(struct task_struct *task, int regno, unsigned long data)
146 break; 146 break;
147 default: 147 default:
148 if (regno <= 216) 148 if (regno <= 216)
149 *(long *)(reg_ptr + regno) = data; 149 *(long *)(reg_ptr + regno) = data;
150 } 150 }
151 return 0; 151 return 0;
152} 152}
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 83060f98d15d..f59dcee7bae3 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -42,6 +42,7 @@
42#include <asm/cacheflush.h> 42#include <asm/cacheflush.h>
43#include <asm/blackfin.h> 43#include <asm/blackfin.h>
44#include <asm/cplbinit.h> 44#include <asm/cplbinit.h>
45#include <asm/fixed_code.h>
45 46
46u16 _bfin_swrst; 47u16 _bfin_swrst;
47 48
@@ -63,10 +64,6 @@ EXPORT_SYMBOL(mtd_size);
63 64
64char __initdata command_line[COMMAND_LINE_SIZE]; 65char __initdata command_line[COMMAND_LINE_SIZE];
65 66
66#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
67static void generate_cpl_tables(void);
68#endif
69
70void __init bf53x_cache_init(void) 67void __init bf53x_cache_init(void)
71{ 68{
72#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) 69#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
@@ -197,6 +194,17 @@ void __init setup_arch(char **cmdline_p)
197 /* this give a chance to get printk() working before crash. */ 194 /* this give a chance to get printk() working before crash. */
198#endif 195#endif
199 196
197 printk(KERN_INFO "Hardware Trace ");
198 if (bfin_read_TBUFCTL() & 0x1 )
199 printk("Active ");
200 else
201 printk("Off ");
202 if (bfin_read_TBUFCTL() & 0x2)
203 printk("and Enabled\n");
204 else
205 printk("and Disabled\n");
206
207
200#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH) 208#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
201 /* we need to initialize the Flashrom device here since we might 209 /* we need to initialize the Flashrom device here since we might
202 * do things with flash early on in the boot 210 * do things with flash early on in the boot
@@ -354,15 +362,15 @@ void __init setup_arch(char **cmdline_p)
354 , _stext, _etext, 362 , _stext, _etext,
355 __start_rodata, __end_rodata, 363 __start_rodata, __end_rodata,
356 _sdata, _edata, 364 _sdata, _edata,
357 (void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000), 365 (void *)&init_thread_union, (void *)((int)(&init_thread_union) + 0x2000),
358 __init_begin, __init_end, 366 __init_begin, __init_end,
359 __bss_start, __bss_stop, 367 __bss_start, __bss_stop,
360 (void*)_ramstart, (void*)memory_end 368 (void *)_ramstart, (void *)memory_end
361#ifdef CONFIG_MTD_UCLINUX 369#ifdef CONFIG_MTD_UCLINUX
362 , (void*)memory_mtd_start, (void*)(memory_mtd_start + mtd_size) 370 , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
363#endif 371#endif
364#if DMA_UNCACHED_REGION > 0 372#if DMA_UNCACHED_REGION > 0
365 , (void*)(_ramend - DMA_UNCACHED_REGION), (void*)(_ramend) 373 , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
366#endif 374#endif
367 ); 375 );
368 376
@@ -388,11 +396,11 @@ void __init setup_arch(char **cmdline_p)
388 /* check the size of the l1 area */ 396 /* check the size of the l1 area */
389 l1_length = _etext_l1 - _stext_l1; 397 l1_length = _etext_l1 - _stext_l1;
390 if (l1_length > L1_CODE_LENGTH) 398 if (l1_length > L1_CODE_LENGTH)
391 panic("L1 memory overflow\n"); 399 panic("L1 code memory overflow\n");
392 400
393 l1_length = _ebss_l1 - _sdata_l1; 401 l1_length = _ebss_l1 - _sdata_l1;
394 if (l1_length > L1_DATA_A_LENGTH) 402 if (l1_length > L1_DATA_A_LENGTH)
395 panic("L1 memory overflow\n"); 403 panic("L1 data memory overflow\n");
396 404
397#ifdef BF561_FAMILY 405#ifdef BF561_FAMILY
398 _bfin_swrst = bfin_read_SICA_SWRST(); 406 _bfin_swrst = bfin_read_SICA_SWRST();
@@ -400,10 +408,28 @@ void __init setup_arch(char **cmdline_p)
400 _bfin_swrst = bfin_read_SWRST(); 408 _bfin_swrst = bfin_read_SWRST();
401#endif 409#endif
402 410
403 bf53x_cache_init(); 411 /* Copy atomic sequences to their fixed location, and sanity check that
412 these locations are the ones that we advertise to userspace. */
413 memcpy((void *)FIXED_CODE_START, &fixed_code_start,
414 FIXED_CODE_END - FIXED_CODE_START);
415 BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
416 != SIGRETURN_STUB - FIXED_CODE_START);
417 BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
418 != ATOMIC_XCHG32 - FIXED_CODE_START);
419 BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
420 != ATOMIC_CAS32 - FIXED_CODE_START);
421 BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
422 != ATOMIC_ADD32 - FIXED_CODE_START);
423 BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
424 != ATOMIC_SUB32 - FIXED_CODE_START);
425 BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
426 != ATOMIC_IOR32 - FIXED_CODE_START);
427 BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
428 != ATOMIC_AND32 - FIXED_CODE_START);
429 BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
430 != ATOMIC_XOR32 - FIXED_CODE_START);
404 431
405 printk(KERN_INFO "Hardware Trace Enabled\n"); 432 bf53x_cache_init();
406 bfin_write_TBUFCTL(0x03);
407} 433}
408 434
409static int __init topology_init(void) 435static int __init topology_init(void)
@@ -421,286 +447,6 @@ static int __init topology_init(void)
421 447
422subsys_initcall(topology_init); 448subsys_initcall(topology_init);
423 449
424#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
425static u16 __init lock_kernel_check(u32 start, u32 end)
426{
427 if ((start <= (u32) _stext && end >= (u32) _end)
428 || (start >= (u32) _stext && end <= (u32) _end))
429 return IN_KERNEL;
430 return 0;
431}
432
433static unsigned short __init
434fill_cplbtab(struct cplb_tab *table,
435 unsigned long start, unsigned long end,
436 unsigned long block_size, unsigned long cplb_data)
437{
438 int i;
439
440 switch (block_size) {
441 case SIZE_4M:
442 i = 3;
443 break;
444 case SIZE_1M:
445 i = 2;
446 break;
447 case SIZE_4K:
448 i = 1;
449 break;
450 case SIZE_1K:
451 default:
452 i = 0;
453 break;
454 }
455
456 cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
457
458 while ((start < end) && (table->pos < table->size)) {
459
460 table->tab[table->pos++] = start;
461
462 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
463 table->tab[table->pos++] =
464 cplb_data | CPLB_LOCK | CPLB_DIRTY;
465 else
466 table->tab[table->pos++] = cplb_data;
467
468 start += block_size;
469 }
470 return 0;
471}
472
473static unsigned short __init
474close_cplbtab(struct cplb_tab *table)
475{
476
477 while (table->pos < table->size) {
478
479 table->tab[table->pos++] = 0;
480 table->tab[table->pos++] = 0; /* !CPLB_VALID */
481 }
482 return 0;
483}
484
485/* helper function */
486static void __fill_code_cplbtab(struct cplb_tab *t, int i,
487 u32 a_start, u32 a_end)
488{
489 if (cplb_data[i].psize) {
490 fill_cplbtab(t,
491 cplb_data[i].start,
492 cplb_data[i].end,
493 cplb_data[i].psize,
494 cplb_data[i].i_conf);
495 } else {
496#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
497 if (i == SDRAM_KERN) {
498 fill_cplbtab(t,
499 cplb_data[i].start,
500 cplb_data[i].end,
501 SIZE_4M,
502 cplb_data[i].i_conf);
503 } else {
504#endif
505 fill_cplbtab(t,
506 cplb_data[i].start,
507 a_start,
508 SIZE_1M,
509 cplb_data[i].i_conf);
510 fill_cplbtab(t,
511 a_start,
512 a_end,
513 SIZE_4M,
514 cplb_data[i].i_conf);
515 fill_cplbtab(t, a_end,
516 cplb_data[i].end,
517 SIZE_1M,
518 cplb_data[i].i_conf);
519 }
520 }
521}
522
523static void __fill_data_cplbtab(struct cplb_tab *t, int i,
524 u32 a_start, u32 a_end)
525{
526 if (cplb_data[i].psize) {
527 fill_cplbtab(t,
528 cplb_data[i].start,
529 cplb_data[i].end,
530 cplb_data[i].psize,
531 cplb_data[i].d_conf);
532 } else {
533 fill_cplbtab(t,
534 cplb_data[i].start,
535 a_start, SIZE_1M,
536 cplb_data[i].d_conf);
537 fill_cplbtab(t, a_start,
538 a_end, SIZE_4M,
539 cplb_data[i].d_conf);
540 fill_cplbtab(t, a_end,
541 cplb_data[i].end,
542 SIZE_1M,
543 cplb_data[i].d_conf);
544 }
545}
546static void __init generate_cpl_tables(void)
547{
548
549 u16 i, j, process;
550 u32 a_start, a_end, as, ae, as_1m;
551
552 struct cplb_tab *t_i = NULL;
553 struct cplb_tab *t_d = NULL;
554 struct s_cplb cplb;
555
556 cplb.init_i.size = MAX_CPLBS;
557 cplb.init_d.size = MAX_CPLBS;
558 cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
559 cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
560
561 cplb.init_i.pos = 0;
562 cplb.init_d.pos = 0;
563 cplb.switch_i.pos = 0;
564 cplb.switch_d.pos = 0;
565
566 cplb.init_i.tab = icplb_table;
567 cplb.init_d.tab = dcplb_table;
568 cplb.switch_i.tab = ipdt_table;
569 cplb.switch_d.tab = dpdt_table;
570
571 cplb_data[SDRAM_KERN].end = memory_end;
572
573#ifdef CONFIG_MTD_UCLINUX
574 cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
575 cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
576 cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
577# if defined(CONFIG_ROMFS_FS)
578 cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
579
580 /*
581 * The ROMFS_FS size is often not multiple of 1MB.
582 * This can cause multiple CPLB sets covering the same memory area.
583 * This will then cause multiple CPLB hit exceptions.
584 * Workaround: We ensure a contiguous memory area by extending the kernel
585 * memory section over the mtd section.
586 * For ROMFS_FS memory must be covered with ICPLBs anyways.
587 * So there is no difference between kernel and mtd memory setup.
588 */
589
590 cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
591 cplb_data[SDRAM_RAM_MTD].valid = 0;
592
593# endif
594#else
595 cplb_data[SDRAM_RAM_MTD].valid = 0;
596#endif
597
598 cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
599 cplb_data[SDRAM_DMAZ].end = _ramend;
600
601 cplb_data[RES_MEM].start = _ramend;
602 cplb_data[RES_MEM].end = physical_mem_end;
603
604 if (reserved_mem_dcache_on)
605 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
606 else
607 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
608
609 if (reserved_mem_icache_on)
610 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
611 else
612 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
613
614 for (i = ZERO_P; i <= L2_MEM; i++) {
615 if (!cplb_data[i].valid)
616 continue;
617
618 as_1m = cplb_data[i].start % SIZE_1M;
619
620 /*
621 * We need to make sure all sections are properly 1M aligned
622 * However between Kernel Memory and the Kernel mtd section,
623 * depending on the rootfs size, there can be overlapping
624 * memory areas.
625 */
626
627 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
628#ifdef CONFIG_MTD_UCLINUX
629 if (i == SDRAM_RAM_MTD) {
630 if ((cplb_data[SDRAM_KERN].end + 1) >
631 cplb_data[SDRAM_RAM_MTD].start)
632 cplb_data[SDRAM_RAM_MTD].start =
633 (cplb_data[i].start &
634 (-2*SIZE_1M)) + SIZE_1M;
635 else
636 cplb_data[SDRAM_RAM_MTD].start =
637 (cplb_data[i].start &
638 (-2*SIZE_1M));
639 } else
640#endif
641 printk(KERN_WARNING
642 "Unaligned Start of %s at 0x%X\n",
643 cplb_data[i].name, cplb_data[i].start);
644 }
645
646 as = cplb_data[i].start % SIZE_4M;
647 ae = cplb_data[i].end % SIZE_4M;
648
649 if (as)
650 a_start = cplb_data[i].start + (SIZE_4M - (as));
651 else
652 a_start = cplb_data[i].start;
653
654 a_end = cplb_data[i].end - ae;
655
656 for (j = INITIAL_T; j <= SWITCH_T; j++) {
657
658 switch (j) {
659 case INITIAL_T:
660 if (cplb_data[i].attr & INITIAL_T) {
661 t_i = &cplb.init_i;
662 t_d = &cplb.init_d;
663 process = 1;
664 } else
665 process = 0;
666 break;
667 case SWITCH_T:
668 if (cplb_data[i].attr & SWITCH_T) {
669 t_i = &cplb.switch_i;
670 t_d = &cplb.switch_d;
671 process = 1;
672 } else
673 process = 0;
674 break;
675 default:
676 process = 0;
677 break;
678 }
679
680 if (!process)
681 continue;
682 if (cplb_data[i].attr & I_CPLB)
683 __fill_code_cplbtab(t_i, i, a_start, a_end);
684
685 if (cplb_data[i].attr & D_CPLB)
686 __fill_data_cplbtab(t_d, i, a_start, a_end);
687 }
688 }
689
690/* close tables */
691
692 close_cplbtab(&cplb.init_i);
693 close_cplbtab(&cplb.init_d);
694
695 cplb.init_i.tab[cplb.init_i.pos] = -1;
696 cplb.init_d.tab[cplb.init_d.pos] = -1;
697 cplb.switch_i.tab[cplb.switch_i.pos] = -1;
698 cplb.switch_d.tab[cplb.switch_d.pos] = -1;
699
700}
701
702#endif
703
704static u_long get_vco(void) 450static u_long get_vco(void)
705{ 451{
706 u_long msel; 452 u_long msel;
@@ -730,7 +476,6 @@ u_long get_cclk(void)
730 return get_vco() / ssel; 476 return get_vco() / ssel;
731 return get_vco() >> csel; 477 return get_vco() >> csel;
732} 478}
733
734EXPORT_SYMBOL(get_cclk); 479EXPORT_SYMBOL(get_cclk);
735 480
736/* Get the System clock */ 481/* Get the System clock */
@@ -749,7 +494,6 @@ u_long get_sclk(void)
749 494
750 return get_vco() / ssel; 495 return get_vco() / ssel;
751} 496}
752
753EXPORT_SYMBOL(get_sclk); 497EXPORT_SYMBOL(get_sclk);
754 498
755/* 499/*
@@ -804,23 +548,23 @@ static int show_cpuinfo(struct seq_file *m, void *v)
804 seq_printf(m, "D-CACHE:\tOFF\n"); 548 seq_printf(m, "D-CACHE:\tOFF\n");
805 549
806 550
807 switch(bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) { 551 switch (bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
808 case ACACHE_BSRAM: 552 case ACACHE_BSRAM:
809 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n"); 553 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n");
810 dcache_size = 16; 554 dcache_size = 16;
811 dsup_banks = 1; 555 dsup_banks = 1;
812 break; 556 break;
813 case ACACHE_BCACHE: 557 case ACACHE_BCACHE:
814 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n"); 558 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n");
815 dcache_size = 32; 559 dcache_size = 32;
816 dsup_banks = 2; 560 dsup_banks = 2;
817 break; 561 break;
818 case ASRAM_BSRAM: 562 case ASRAM_BSRAM:
819 seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n"); 563 seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n");
820 dcache_size = 0; 564 dcache_size = 0;
821 dsup_banks = 0; 565 dsup_banks = 0;
822 break; 566 break;
823 default: 567 default:
824 break; 568 break;
825 } 569 }
826 570
diff --git a/arch/blackfin/kernel/signal.c b/arch/blackfin/kernel/signal.c
index 316e65c3439d..5564c9588aa8 100644
--- a/arch/blackfin/kernel/signal.c
+++ b/arch/blackfin/kernel/signal.c
@@ -34,8 +34,8 @@
34#include <linux/personality.h> 34#include <linux/personality.h>
35#include <linux/binfmts.h> 35#include <linux/binfmts.h>
36#include <linux/freezer.h> 36#include <linux/freezer.h>
37#include <linux/uaccess.h>
37 38
38#include <asm/uaccess.h>
39#include <asm/cacheflush.h> 39#include <asm/cacheflush.h>
40#include <asm/ucontext.h> 40#include <asm/ucontext.h>
41 41
@@ -124,7 +124,7 @@ asmlinkage int do_rt_sigreturn(unsigned long __unused)
124 124
125 return r0; 125 return r0;
126 126
127 badframe: 127 badframe:
128 force_sig(SIGSEGV, current); 128 force_sig(SIGSEGV, current);
129 return 0; 129 return 0;
130} 130}
@@ -239,7 +239,7 @@ setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t * info,
239 239
240 return 0; 240 return 0;
241 241
242 give_sigsegv: 242 give_sigsegv:
243 if (sig == SIGSEGV) 243 if (sig == SIGSEGV)
244 ka->sa.sa_handler = SIG_DFL; 244 ka->sa.sa_handler = SIG_DFL;
245 force_sig(SIGSEGV, current); 245 force_sig(SIGSEGV, current);
@@ -263,7 +263,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
263 } 263 }
264 /* fallthrough */ 264 /* fallthrough */
265 case -ERESTARTNOINTR: 265 case -ERESTARTNOINTR:
266 do_restart: 266 do_restart:
267 regs->p0 = regs->orig_p0; 267 regs->p0 = regs->orig_p0;
268 regs->r0 = regs->orig_r0; 268 regs->r0 = regs->orig_r0;
269 regs->pc -= 2; 269 regs->pc -= 2;
@@ -341,7 +341,7 @@ asmlinkage void do_signal(struct pt_regs *regs)
341 return; 341 return;
342 } 342 }
343 343
344no_signal: 344 no_signal:
345 /* Did we come from a system call? */ 345 /* Did we come from a system call? */
346 if (regs->orig_p0 >= 0) 346 if (regs->orig_p0 >= 0)
347 /* Restart the system call - no handlers present */ 347 /* Restart the system call - no handlers present */
diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c
index f436e6743f5a..f5e1ae3d1705 100644
--- a/arch/blackfin/kernel/sys_bfin.c
+++ b/arch/blackfin/kernel/sys_bfin.c
@@ -37,12 +37,12 @@
37#include <linux/syscalls.h> 37#include <linux/syscalls.h>
38#include <linux/mman.h> 38#include <linux/mman.h>
39#include <linux/file.h> 39#include <linux/file.h>
40#include <linux/uaccess.h>
41#include <linux/ipc.h>
42#include <linux/unistd.h>
40 43
41#include <asm/cacheflush.h> 44#include <asm/cacheflush.h>
42#include <asm/uaccess.h>
43#include <asm/ipc.h>
44#include <asm/dma.h> 45#include <asm/dma.h>
45#include <asm/unistd.h>
46 46
47/* 47/*
48 * sys_pipe() is the normal C calling standard for creating 48 * sys_pipe() is the normal C calling standard for creating
@@ -83,7 +83,7 @@ do_mmap2(unsigned long addr, unsigned long len,
83 83
84 if (file) 84 if (file)
85 fput(file); 85 fput(file);
86 out: 86 out:
87 return error; 87 return error;
88} 88}
89 89
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index f578176b6d92..beef057bd1dc 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -87,7 +87,7 @@ void __init init_leds(void)
87static inline void do_leds(void) 87static inline void do_leds(void)
88{ 88{
89 static unsigned int count = 50; 89 static unsigned int count = 50;
90 static int flag = 0; 90 static int flag;
91 unsigned short tmp = 0; 91 unsigned short tmp = 0;
92 92
93 if (--count == 0) { 93 if (--count == 0) {
@@ -200,7 +200,7 @@ irqreturn_t timer_interrupt(int irq, void *dummy)__attribute__((l1_text));
200irqreturn_t timer_interrupt(int irq, void *dummy) 200irqreturn_t timer_interrupt(int irq, void *dummy)
201{ 201{
202 /* last time the cmos clock got updated */ 202 /* last time the cmos clock got updated */
203 static long last_rtc_update = 0; 203 static long last_rtc_update;
204 204
205 write_seqlock(&xtime_lock); 205 write_seqlock(&xtime_lock);
206 206
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 56058b0b6d4a..3909f5b35536 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -27,15 +27,15 @@
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */ 28 */
29 29
30#include <asm/uaccess.h> 30#include <linux/uaccess.h>
31#include <linux/interrupt.h>
32#include <linux/module.h>
33#include <linux/kallsyms.h>
31#include <asm/traps.h> 34#include <asm/traps.h>
32#include <asm/cacheflush.h> 35#include <asm/cacheflush.h>
33#include <asm/blackfin.h> 36#include <asm/blackfin.h>
34#include <asm/uaccess.h>
35#include <asm/irq_handler.h> 37#include <asm/irq_handler.h>
36#include <linux/interrupt.h> 38#include <asm/trace.h>
37#include <linux/module.h>
38#include <linux/kallsyms.h>
39 39
40#ifdef CONFIG_KGDB 40#ifdef CONFIG_KGDB
41# include <linux/debugger.h> 41# include <linux/debugger.h>
@@ -76,7 +76,7 @@ static int printk_address(unsigned long address)
76 if (!modname) 76 if (!modname)
77 modname = delim = ""; 77 modname = delim = "";
78 return printk("<0x%p> { %s%s%s%s + 0x%lx }", 78 return printk("<0x%p> { %s%s%s%s + 0x%lx }",
79 (void*)address, delim, modname, delim, symname, 79 (void *)address, delim, modname, delim, symname,
80 (unsigned long)offset); 80 (unsigned long)offset);
81 81
82 } 82 }
@@ -119,7 +119,7 @@ static int printk_address(unsigned long address)
119 119
120 write_unlock_irq(&tasklist_lock); 120 write_unlock_irq(&tasklist_lock);
121 return printk("<0x%p> [ %s + 0x%lx ]", 121 return printk("<0x%p> [ %s + 0x%lx ]",
122 (void*)address, name, offset); 122 (void *)address, name, offset);
123 } 123 }
124 124
125 vml = vml->next; 125 vml = vml->next;
@@ -128,19 +128,9 @@ static int printk_address(unsigned long address)
128 write_unlock_irq(&tasklist_lock); 128 write_unlock_irq(&tasklist_lock);
129 129
130 /* we were unable to find this address anywhere */ 130 /* we were unable to find this address anywhere */
131 return printk("[<0x%p>]", (void*)address); 131 return printk("[<0x%p>]", (void *)address);
132} 132}
133 133
134#define trace_buffer_save(x) \
135 do { \
136 (x) = bfin_read_TBUFCTL(); \
137 bfin_write_TBUFCTL((x) & ~TBUFEN); \
138 } while (0)
139#define trace_buffer_restore(x) \
140 do { \
141 bfin_write_TBUFCTL((x)); \
142 } while (0)
143
144asmlinkage void trap_c(struct pt_regs *fp) 134asmlinkage void trap_c(struct pt_regs *fp)
145{ 135{
146 int j, sig = 0; 136 int j, sig = 0;
@@ -203,15 +193,14 @@ asmlinkage void trap_c(struct pt_regs *fp)
203#else 193#else
204 /* 0x02 - User Defined, Caught by default */ 194 /* 0x02 - User Defined, Caught by default */
205#endif 195#endif
206 /* 0x03 - Atomic test and set */ 196 /* 0x03 - User Defined, userspace stack overflow */
207 case VEC_EXCPT03: 197 case VEC_EXCPT03:
208 info.si_code = SEGV_STACKFLOW; 198 info.si_code = SEGV_STACKFLOW;
209 sig = SIGSEGV; 199 sig = SIGSEGV;
210 printk(KERN_EMERG EXC_0x03); 200 printk(KERN_EMERG EXC_0x03);
211 CHK_DEBUGGER_TRAP(); 201 CHK_DEBUGGER_TRAP();
212 break; 202 break;
213 /* 0x04 - spinlock - handled by _ex_spinlock, 203 /* 0x04 - User Defined, Caught by default */
214 getting here is an error */
215 /* 0x05 - User Defined, Caught by default */ 204 /* 0x05 - User Defined, Caught by default */
216 /* 0x06 - User Defined, Caught by default */ 205 /* 0x06 - User Defined, Caught by default */
217 /* 0x07 - User Defined, Caught by default */ 206 /* 0x07 - User Defined, Caught by default */
@@ -547,29 +536,28 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
547 printk(KERN_EMERG "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n" 536 printk(KERN_EMERG "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n"
548 KERN_EMERG "BSS = 0x%p-0x%p USER-STACK = 0x%p\n" 537 KERN_EMERG "BSS = 0x%p-0x%p USER-STACK = 0x%p\n"
549 KERN_EMERG "\n", 538 KERN_EMERG "\n",
550 (void*)current->mm->start_code, 539 (void *)current->mm->start_code,
551 (void*)current->mm->end_code, 540 (void *)current->mm->end_code,
552 (void*)current->mm->start_data, 541 (void *)current->mm->start_data,
553 (void*)current->mm->end_data, 542 (void *)current->mm->end_data,
554 (void*)current->mm->end_data, 543 (void *)current->mm->end_data,
555 (void*)current->mm->brk, 544 (void *)current->mm->brk,
556 (void*)current->mm->start_stack); 545 (void *)current->mm->start_stack);
557 } 546 }
558 547
559 printk(KERN_EMERG "return address: [0x%p]; contents of:", retaddr); 548 printk(KERN_EMERG "return address: [0x%p]; contents of:", retaddr);
560 if (retaddr != 0 && retaddr <= (void*)physical_mem_end 549 if (retaddr != 0 && retaddr <= (void *)physical_mem_end
561#if L1_CODE_LENGTH != 0 550#if L1_CODE_LENGTH != 0
562 /* FIXME: Copy the code out of L1 Instruction SRAM through dma 551 /* FIXME: Copy the code out of L1 Instruction SRAM through dma
563 memcpy. */ 552 memcpy. */
564 && !(retaddr >= (void*)L1_CODE_START 553 && !(retaddr >= (void *)L1_CODE_START
565 && retaddr < (void*)(L1_CODE_START + L1_CODE_LENGTH)) 554 && retaddr < (void *)(L1_CODE_START + L1_CODE_LENGTH))
566#endif 555#endif
567 ) { 556 ) {
568 int i = ((unsigned int)retaddr & 0xFFFFFFF0) - 32; 557 int i = ((unsigned int)retaddr & 0xFFFFFFF0) - 32;
569 unsigned short x = 0; 558 unsigned short x = 0;
570 for (; i < ((unsigned int)retaddr & 0xFFFFFFF0 ) + 32 ; 559 for (; i < ((unsigned int)retaddr & 0xFFFFFFF0) + 32; i += 2) {
571 i += 2) { 560 if (!(i & 0xF))
572 if ( !(i & 0xF) )
573 printk(KERN_EMERG "\n" KERN_EMERG 561 printk(KERN_EMERG "\n" KERN_EMERG
574 "0x%08x: ", i); 562 "0x%08x: ", i);
575 563
@@ -588,7 +576,7 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
588 " The rest of this error" 576 " The rest of this error"
589 " is meanless\n"); 577 " is meanless\n");
590#endif 578#endif
591 if ( i == (unsigned int)retaddr ) 579 if (i == (unsigned int)retaddr)
592 printk("[%04x]", x); 580 printk("[%04x]", x);
593 else 581 else
594 printk(" %04x ", x); 582 printk(" %04x ", x);
@@ -681,8 +669,8 @@ void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
681 break; 669 break;
682 } 670 }
683 671
684 printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void*)bfin_read_DCPLB_FAULT_ADDR()); 672 printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void *)bfin_read_DCPLB_FAULT_ADDR());
685 printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void*)bfin_read_ICPLB_FAULT_ADDR()); 673 printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void *)bfin_read_ICPLB_FAULT_ADDR());
686 dump_bfin_regs(fp, (void *)fp->retx); 674 dump_bfin_regs(fp, (void *)fp->retx);
687 dump_stack(); 675 dump_stack();
688 panic("Unrecoverable event\n"); 676 panic("Unrecoverable event\n");
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index 1ef1e36b3957..d06f860f4790 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -31,6 +31,7 @@
31 31
32#include <asm-generic/vmlinux.lds.h> 32#include <asm-generic/vmlinux.lds.h>
33#include <asm/mem_map.h> 33#include <asm/mem_map.h>
34#include <asm/page.h>
34 35
35OUTPUT_FORMAT("elf32-bfin") 36OUTPUT_FORMAT("elf32-bfin")
36ENTRY(__start) 37ENTRY(__start)
@@ -63,8 +64,8 @@ SECTIONS
63 64
64 .data : 65 .data :
65 { 66 {
67 . = ALIGN(PAGE_SIZE);
66 __sdata = .; 68 __sdata = .;
67 . = ALIGN(0x2000);
68 *(.data.init_task) 69 *(.data.init_task)
69 DATA_DATA 70 DATA_DATA
70 CONSTRUCTORS 71 CONSTRUCTORS
@@ -72,14 +73,14 @@ SECTIONS
72 . = ALIGN(32); 73 . = ALIGN(32);
73 *(.data.cacheline_aligned) 74 *(.data.cacheline_aligned)
74 75
75 . = ALIGN(0x2000); 76 . = ALIGN(PAGE_SIZE);
76 __edata = .; 77 __edata = .;
77 } 78 }
78 79
80 . = ALIGN(PAGE_SIZE);
79 ___init_begin = .; 81 ___init_begin = .;
80 .init : 82 .init :
81 { 83 {
82 . = ALIGN(4096);
83 __sinittext = .; 84 __sinittext = .;
84 *(.init.text) 85 *(.init.text)
85 __einittext = .; 86 __einittext = .;
@@ -152,9 +153,10 @@ SECTIONS
152 __ebss_b_l1 = .; 153 __ebss_b_l1 = .;
153 } 154 }
154 155
155 ___init_end = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1); 156 . = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
157 ___init_end = ALIGN(PAGE_SIZE);
156 158
157 .bss LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1) : 159 .bss ___init_end :
158 { 160 {
159 . = ALIGN(4); 161 . = ALIGN(4);
160 ___bss_start = .; 162 ___bss_start = .;
diff --git a/arch/blackfin/lib/strcmp.c b/arch/blackfin/lib/strcmp.c
index 2ad47c4254ba..4eeefd86907f 100644
--- a/arch/blackfin/lib/strcmp.c
+++ b/arch/blackfin/lib/strcmp.c
@@ -6,6 +6,5 @@
6 6
7int strcmp(const char *dest, const char *src) 7int strcmp(const char *dest, const char *src)
8{ 8{
9 return __inline_strcmp(dest, src); 9 return __inline_strcmp(dest, src);
10} 10}
11
diff --git a/arch/blackfin/lib/strcpy.c b/arch/blackfin/lib/strcpy.c
index 4dc835a8a19b..534589db7256 100644
--- a/arch/blackfin/lib/strcpy.c
+++ b/arch/blackfin/lib/strcpy.c
@@ -6,6 +6,5 @@
6 6
7char *strcpy(char *dest, const char *src) 7char *strcpy(char *dest, const char *src)
8{ 8{
9 return __inline_strcpy(dest, src); 9 return __inline_strcpy(dest, src);
10} 10}
11
diff --git a/arch/blackfin/lib/strncmp.c b/arch/blackfin/lib/strncmp.c
index 947bcfe3f3bb..d791f120bff7 100644
--- a/arch/blackfin/lib/strncmp.c
+++ b/arch/blackfin/lib/strncmp.c
@@ -6,6 +6,5 @@
6 6
7int strncmp(const char *cs, const char *ct, size_t count) 7int strncmp(const char *cs, const char *ct, size_t count)
8{ 8{
9 return __inline_strncmp(cs, ct, count); 9 return __inline_strncmp(cs, ct, count);
10} 10}
11
diff --git a/arch/blackfin/lib/strncpy.c b/arch/blackfin/lib/strncpy.c
index 77a9b2e95097..1fecb5c71ffb 100644
--- a/arch/blackfin/lib/strncpy.c
+++ b/arch/blackfin/lib/strncpy.c
@@ -6,6 +6,5 @@
6 6
7char *strncpy(char *dest, const char *src, size_t n) 7char *strncpy(char *dest, const char *src, size_t n)
8{ 8{
9 return __inline_strncpy(dest, src, n); 9 return __inline_strncpy(dest, src, n);
10} 10}
11
diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile
index 76d2c2b8579a..8cce1736360d 100644
--- a/arch/blackfin/mach-bf533/Makefile
+++ b/arch/blackfin/mach-bf533/Makefile
@@ -4,6 +4,6 @@
4 4
5extra-y := head.o 5extra-y := head.o
6 6
7obj-y := ints-priority.o 7obj-y := ints-priority.o dma.o
8 8
9obj-$(CONFIG_CPU_FREQ_BF533) += cpu.o 9obj-$(CONFIG_CPU_FREQ) += cpu.o
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index edd31ce4f8d2..4545f363e641 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -34,7 +34,7 @@
34#include <linux/spi/spi.h> 34#include <linux/spi/spi.h>
35#include <linux/spi/flash.h> 35#include <linux/spi/flash.h>
36#include <linux/usb_isp1362.h> 36#include <linux/usb_isp1362.h>
37#include <asm/irq.h> 37#include <linux/irq.h>
38#include <asm/bfin5xx_spi.h> 38#include <asm/bfin5xx_spi.h>
39 39
40/* 40/*
@@ -51,11 +51,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
51 .size = 0x00020000, 51 .size = 0x00020000,
52 .offset = 0, 52 .offset = 0,
53 .mask_flags = MTD_CAP_ROM 53 .mask_flags = MTD_CAP_ROM
54 },{ 54 }, {
55 .name = "kernel", 55 .name = "kernel",
56 .size = 0xe0000, 56 .size = 0xe0000,
57 .offset = 0x20000 57 .offset = 0x20000
58 },{ 58 }, {
59 .name = "file system", 59 .name = "file system",
60 .size = 0x700000, 60 .size = 0x700000,
61 .offset = 0x00100000, 61 .offset = 0x00100000,
@@ -98,7 +98,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
98 .platform_data = &bfin_spi_flash_data, 98 .platform_data = &bfin_spi_flash_data,
99 .controller_data = &spi_flash_chip_info, 99 .controller_data = &spi_flash_chip_info,
100 .mode = SPI_MODE_3, 100 .mode = SPI_MODE_3,
101 },{ 101 }, {
102 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ 102 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
103 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ 103 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
104 .bus_num = 1, /* Framework bus number */ 104 .bus_num = 1, /* Framework bus number */
@@ -145,7 +145,7 @@ static struct resource smc91x_resources[] = {
145 .start = 0x20200300, 145 .start = 0x20200300,
146 .end = 0x20200300 + 16, 146 .end = 0x20200300 + 16,
147 .flags = IORESOURCE_MEM, 147 .flags = IORESOURCE_MEM,
148 },{ 148 }, {
149 .start = IRQ_PF0, 149 .start = IRQ_PF0,
150 .end = IRQ_PF0, 150 .end = IRQ_PF0,
151 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 151 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -194,11 +194,11 @@ static struct resource isp1362_hcd_resources[] = {
194 .start = 0x20308000, 194 .start = 0x20308000,
195 .end = 0x20308000, 195 .end = 0x20308000,
196 .flags = IORESOURCE_MEM, 196 .flags = IORESOURCE_MEM,
197 },{ 197 }, {
198 .start = 0x20308004, 198 .start = 0x20308004,
199 .end = 0x20308004, 199 .end = 0x20308004,
200 .flags = IORESOURCE_MEM, 200 .flags = IORESOURCE_MEM,
201 },{ 201 }, {
202 .start = IRQ_PF4, 202 .start = IRQ_PF4,
203 .end = IRQ_PF4, 203 .end = IRQ_PF4,
204 .flags = IORESOURCE_IRQ, 204 .flags = IORESOURCE_IRQ,
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index 0b522d95160d..0000b8f1239c 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -35,7 +35,7 @@
35#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h> 36#include <linux/spi/flash.h>
37#include <linux/usb_isp1362.h> 37#include <linux/usb_isp1362.h>
38#include <asm/irq.h> 38#include <linux/irq.h>
39#include <asm/bfin5xx_spi.h> 39#include <asm/bfin5xx_spi.h>
40 40
41/* 41/*
@@ -61,7 +61,7 @@ static struct resource smc91x_resources[] = {
61 .start = 0x20310300, 61 .start = 0x20310300,
62 .end = 0x20310300 + 16, 62 .end = 0x20310300 + 16,
63 .flags = IORESOURCE_MEM, 63 .flags = IORESOURCE_MEM,
64 },{ 64 }, {
65 .start = IRQ_PF9, 65 .start = IRQ_PF9,
66 .end = IRQ_PF9, 66 .end = IRQ_PF9,
67 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 67 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -85,11 +85,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
85 .size = 0x00020000, 85 .size = 0x00020000,
86 .offset = 0, 86 .offset = 0,
87 .mask_flags = MTD_CAP_ROM 87 .mask_flags = MTD_CAP_ROM
88 },{ 88 }, {
89 .name = "kernel", 89 .name = "kernel",
90 .size = 0xe0000, 90 .size = 0xe0000,
91 .offset = 0x20000 91 .offset = 0x20000
92 },{ 92 }, {
93 .name = "file system", 93 .name = "file system",
94 .size = 0x700000, 94 .size = 0x700000,
95 .offset = 0x00100000, 95 .offset = 0x00100000,
diff --git a/arch/blackfin/mach-bf533/boards/generic_board.c b/arch/blackfin/mach-bf533/boards/generic_board.c
index c0f43ccfbfb5..9bc1f0d0ab50 100644
--- a/arch/blackfin/mach-bf533/boards/generic_board.c
+++ b/arch/blackfin/mach-bf533/boards/generic_board.c
@@ -30,7 +30,7 @@
30 30
31#include <linux/device.h> 31#include <linux/device.h>
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <asm/irq.h> 33#include <linux/irq.h>
34 34
35/* 35/*
36 * Name the Board for the /proc/cpuinfo 36 * Name the Board for the /proc/cpuinfo
@@ -53,11 +53,11 @@ static struct resource smc91x_resources[] = {
53 .start = 0x20300300, 53 .start = 0x20300300,
54 .end = 0x20300300 + 16, 54 .end = 0x20300300 + 16,
55 .flags = IORESOURCE_MEM, 55 .flags = IORESOURCE_MEM,
56 },{ 56 }, {
57 .start = IRQ_PROG_INTB, 57 .start = IRQ_PROG_INTB,
58 .end = IRQ_PROG_INTB, 58 .end = IRQ_PROG_INTB,
59 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 59 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
60 },{ 60 }, {
61 /* 61 /*
62 * denotes the flag pin and is used directly if 62 * denotes the flag pin and is used directly if
63 * CONFIG_IRQCHIP_DEMUX_GPIO is defined. 63 * CONFIG_IRQCHIP_DEMUX_GPIO is defined.
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 9a472fe15833..a9143c4cbdcd 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -37,7 +37,7 @@
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
38#include <linux/usb_isp1362.h> 38#include <linux/usb_isp1362.h>
39#endif 39#endif
40#include <asm/irq.h> 40#include <linux/irq.h>
41#include <asm/bfin5xx_spi.h> 41#include <asm/bfin5xx_spi.h>
42 42
43/* 43/*
@@ -62,7 +62,7 @@ static struct resource smc91x_resources[] = {
62 .start = 0x20300300, 62 .start = 0x20300300,
63 .end = 0x20300300 + 16, 63 .end = 0x20300300 + 16,
64 .flags = IORESOURCE_MEM, 64 .flags = IORESOURCE_MEM,
65 },{ 65 }, {
66 .start = IRQ_PF7, 66 .start = IRQ_PF7,
67 .end = IRQ_PF7, 67 .end = IRQ_PF7,
68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -83,7 +83,7 @@ static struct resource net2272_bfin_resources[] = {
83 .start = 0x20300000, 83 .start = 0x20300000,
84 .end = 0x20300000 + 0x100, 84 .end = 0x20300000 + 0x100,
85 .flags = IORESOURCE_MEM, 85 .flags = IORESOURCE_MEM,
86 },{ 86 }, {
87 .start = IRQ_PF10, 87 .start = IRQ_PF10,
88 .end = IRQ_PF10, 88 .end = IRQ_PF10,
89 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 89 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -108,11 +108,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
108 .size = 0x00020000, 108 .size = 0x00020000,
109 .offset = 0, 109 .offset = 0,
110 .mask_flags = MTD_CAP_ROM 110 .mask_flags = MTD_CAP_ROM
111 },{ 111 }, {
112 .name = "kernel", 112 .name = "kernel",
113 .size = 0xe0000, 113 .size = 0xe0000,
114 .offset = 0x20000 114 .offset = 0x20000
115 },{ 115 }, {
116 .name = "file system", 116 .name = "file system",
117 .size = 0x700000, 117 .size = 0x700000,
118 .offset = 0x00100000, 118 .offset = 0x00100000,
@@ -229,19 +229,19 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
229 229
230#if defined(CONFIG_PBX) 230#if defined(CONFIG_PBX)
231 { 231 {
232 .modalias = "fxs-spi", 232 .modalias = "fxs-spi",
233 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 233 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
234 .bus_num = 1, 234 .bus_num = 1,
235 .chip_select = 3, 235 .chip_select = 3,
236 .controller_data= &spi_si3xxx_chip_info, 236 .controller_data = &spi_si3xxx_chip_info,
237 .mode = SPI_MODE_3, 237 .mode = SPI_MODE_3,
238 }, 238 },
239 { 239 {
240 .modalias = "fxo-spi", 240 .modalias = "fxo-spi",
241 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 241 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
242 .bus_num = 1, 242 .bus_num = 1,
243 .chip_select = 2, 243 .chip_select = 2,
244 .controller_data= &spi_si3xxx_chip_info, 244 .controller_data = &spi_si3xxx_chip_info,
245 .mode = SPI_MODE_3, 245 .mode = SPI_MODE_3,
246 }, 246 },
247#endif 247#endif
diff --git a/arch/blackfin/mach-bf533/cpu.c b/arch/blackfin/mach-bf533/cpu.c
index 99547c4c290e..6fd9cfd0a31b 100644
--- a/arch/blackfin/mach-bf533/cpu.c
+++ b/arch/blackfin/mach-bf533/cpu.c
@@ -79,8 +79,7 @@ static int bf533_target(struct cpufreq_policy *policy,
79 int i; 79 int i;
80 80
81 struct cpufreq_freqs freqs; 81 struct cpufreq_freqs freqs;
82 if (cpufreq_frequency_table_target 82 if (cpufreq_frequency_table_target(policy, bf533_freq_table, target_freq, relation, &index))
83 (policy, bf533_freq_table, target_freq, relation, &index))
84 return -EINVAL; 83 return -EINVAL;
85 cclk_mhz = bf533_freq_table[index].frequency; 84 cclk_mhz = bf533_freq_table[index].frequency;
86 vco_mhz = bf533_freq_table[index].index; 85 vco_mhz = bf533_freq_table[index].index;
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c
new file mode 100644
index 000000000000..6c909cf4f7bf
--- /dev/null
+++ b/arch/blackfin/mach-bf533/dma.c
@@ -0,0 +1,95 @@
1/*
2 * File: arch/blackfin/mach-bf533/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#include <asm/blackfin.h>
30#include <asm/dma.h>
31
32struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
33 (struct dma_register *) DMA0_NEXT_DESC_PTR,
34 (struct dma_register *) DMA1_NEXT_DESC_PTR,
35 (struct dma_register *) DMA2_NEXT_DESC_PTR,
36 (struct dma_register *) DMA3_NEXT_DESC_PTR,
37 (struct dma_register *) DMA4_NEXT_DESC_PTR,
38 (struct dma_register *) DMA5_NEXT_DESC_PTR,
39 (struct dma_register *) DMA6_NEXT_DESC_PTR,
40 (struct dma_register *) DMA7_NEXT_DESC_PTR,
41 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
42 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
43 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
44 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
45};
46
47int channel2irq(unsigned int channel)
48{
49 int ret_irq = -1;
50
51 switch (channel) {
52 case CH_PPI:
53 ret_irq = IRQ_PPI;
54 break;
55
56 case CH_SPORT0_RX:
57 ret_irq = IRQ_SPORT0_RX;
58 break;
59
60 case CH_SPORT0_TX:
61 ret_irq = IRQ_SPORT0_TX;
62 break;
63
64 case CH_SPORT1_RX:
65 ret_irq = IRQ_SPORT1_RX;
66 break;
67
68 case CH_SPORT1_TX:
69 ret_irq = IRQ_SPORT1_TX;
70 break;
71
72 case CH_SPI:
73 ret_irq = IRQ_SPI;
74 break;
75
76 case CH_UART_RX:
77 ret_irq = IRQ_UART_RX;
78 break;
79
80 case CH_UART_TX:
81 ret_irq = IRQ_UART_TX;
82 break;
83
84 case CH_MEM_STREAM0_SRC:
85 case CH_MEM_STREAM0_DEST:
86 ret_irq = IRQ_MEM_DMA0;
87 break;
88
89 case CH_MEM_STREAM1_SRC:
90 case CH_MEM_STREAM1_DEST:
91 ret_irq = IRQ_MEM_DMA1;
92 break;
93 }
94 return ret_irq;
95}
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 7e2aa8d0f44f..7dd0e9c3a936 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -30,6 +30,7 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h>
33#if CONFIG_BFIN_KERNEL_CLOCK 34#if CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach/mem_init.h> 35#include <asm/mach/mem_init.h>
35#endif 36#endif
@@ -96,6 +97,10 @@ ENTRY(__start)
96 M2 = r0; 97 M2 = r0;
97 M3 = r0; 98 M3 = r0;
98 99
100 trace_buffer_start(p0,r0);
101 P0 = R1;
102 R0 = R1;
103
99#if CONFIG_DEBUG_KERNEL_START 104#if CONFIG_DEBUG_KERNEL_START
100 105
101/* 106/*
diff --git a/arch/blackfin/mach-bf533/ints-priority.c b/arch/blackfin/mach-bf533/ints-priority.c
index a3e1789167be..7d79e0f9503d 100644
--- a/arch/blackfin/mach-bf533/ints-priority.c
+++ b/arch/blackfin/mach-bf533/ints-priority.c
@@ -28,8 +28,8 @@
28 */ 28 */
29 29
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/irq.h>
31#include <asm/blackfin.h> 32#include <asm/blackfin.h>
32#include <asm/irq.h>
33 33
34void program_IAR(void) 34void program_IAR(void)
35{ 35{
diff --git a/arch/blackfin/mach-bf537/Makefile b/arch/blackfin/mach-bf537/Makefile
index f32d44215bb7..7e7c9c8ac5b2 100644
--- a/arch/blackfin/mach-bf537/Makefile
+++ b/arch/blackfin/mach-bf537/Makefile
@@ -4,6 +4,6 @@
4 4
5extra-y := head.o 5extra-y := head.o
6 6
7obj-y := ints-priority.o 7obj-y := ints-priority.o dma.o
8 8
9obj-$(CONFIG_CPU_FREQ) += cpu.o 9obj-$(CONFIG_CPU_FREQ) += cpu.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c
index 6a60618a78ec..a8f947b72754 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c
@@ -35,7 +35,7 @@
35#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h> 36#include <linux/spi/flash.h>
37#include <linux/usb_isp1362.h> 37#include <linux/usb_isp1362.h>
38#include <asm/irq.h> 38#include <linux/irq.h>
39#include <asm/bfin5xx_spi.h> 39#include <asm/bfin5xx_spi.h>
40 40
41/* 41/*
@@ -53,11 +53,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
53 .size = 0x00020000, 53 .size = 0x00020000,
54 .offset = 0, 54 .offset = 0,
55 .mask_flags = MTD_CAP_ROM 55 .mask_flags = MTD_CAP_ROM
56 },{ 56 }, {
57 .name = "kernel", 57 .name = "kernel",
58 .size = 0xe0000, 58 .size = 0xe0000,
59 .offset = 0x20000 59 .offset = 0x20000
60 },{ 60 }, {
61 .name = "file system", 61 .name = "file system",
62 .size = 0x700000, 62 .size = 0x700000,
63 .offset = 0x00100000, 63 .offset = 0x00100000,
@@ -202,7 +202,7 @@ static struct resource smc91x_resources[] = {
202 .start = 0x20200300, 202 .start = 0x20200300,
203 .end = 0x20200300 + 16, 203 .end = 0x20200300 + 16,
204 .flags = IORESOURCE_MEM, 204 .flags = IORESOURCE_MEM,
205 },{ 205 }, {
206 .start = IRQ_PF14, 206 .start = IRQ_PF14,
207 .end = IRQ_PF14, 207 .end = IRQ_PF14,
208 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 208 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -223,11 +223,11 @@ static struct resource isp1362_hcd_resources[] = {
223 .start = 0x20308000, 223 .start = 0x20308000,
224 .end = 0x20308000, 224 .end = 0x20308000,
225 .flags = IORESOURCE_MEM, 225 .flags = IORESOURCE_MEM,
226 },{ 226 }, {
227 .start = 0x20308004, 227 .start = 0x20308004,
228 .end = 0x20308004, 228 .end = 0x20308004,
229 .flags = IORESOURCE_MEM, 229 .flags = IORESOURCE_MEM,
230 },{ 230 }, {
231 .start = IRQ_PG15, 231 .start = IRQ_PG15,
232 .end = IRQ_PG15, 232 .end = IRQ_PG15,
233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -262,7 +262,7 @@ static struct resource net2272_bfin_resources[] = {
262 .start = 0x20200000, 262 .start = 0x20200000,
263 .end = 0x20200000 + 0x100, 263 .end = 0x20200000 + 0x100,
264 .flags = IORESOURCE_MEM, 264 .flags = IORESOURCE_MEM,
265 },{ 265 }, {
266 .start = IRQ_PF7, 266 .start = IRQ_PF7,
267 .end = IRQ_PF7, 267 .end = IRQ_PF7,
268 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 268 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -283,7 +283,7 @@ static struct resource bfin_uart_resources[] = {
283 .start = 0xFFC00400, 283 .start = 0xFFC00400,
284 .end = 0xFFC004FF, 284 .end = 0xFFC004FF,
285 .flags = IORESOURCE_MEM, 285 .flags = IORESOURCE_MEM,
286 },{ 286 }, {
287 .start = 0xFFC02000, 287 .start = 0xFFC02000,
288 .end = 0xFFC020FF, 288 .end = 0xFFC020FF,
289 .flags = IORESOURCE_MEM, 289 .flags = IORESOURCE_MEM,
diff --git a/arch/blackfin/mach-bf537/boards/eth_mac.c b/arch/blackfin/mach-bf537/boards/eth_mac.c
index e129a08d63de..a725cc8a9290 100644
--- a/arch/blackfin/mach-bf537/boards/eth_mac.c
+++ b/arch/blackfin/mach-bf537/boards/eth_mac.c
@@ -20,8 +20,7 @@
20#include <linux/module.h> 20#include <linux/module.h>
21#include <asm/blackfin.h> 21#include <asm/blackfin.h>
22 22
23#if defined(CONFIG_GENERIC_BOARD) \ 23#if defined(CONFIG_GENERIC_BOARD) || defined(CONFIG_BFIN537_STAMP)
24 || defined(CONFIG_BFIN537_STAMP)
25 24
26/* 25/*
27 * Currently the MAC address is saved in Flash by U-Boot 26 * Currently the MAC address is saved in Flash by U-Boot
@@ -43,7 +42,7 @@ void get_bf537_ether_addr(char *addr)
43 */ 42 */
44void get_bf537_ether_addr(char *addr) 43void get_bf537_ether_addr(char *addr)
45{ 44{
46 printk(KERN_WARNING "%s: No valid Ethernet MAC address found\n",__FILE__); 45 printk(KERN_WARNING "%s: No valid Ethernet MAC address found\n", __FILE__);
47} 46}
48 47
49#endif 48#endif
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c
index fd57e7439e0f..648d984e98d6 100644
--- a/arch/blackfin/mach-bf537/boards/generic_board.c
+++ b/arch/blackfin/mach-bf537/boards/generic_board.c
@@ -35,9 +35,9 @@
35#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h> 36#include <linux/spi/flash.h>
37#include <linux/usb_isp1362.h> 37#include <linux/usb_isp1362.h>
38#include <asm/irq.h> 38#include <linux/irq.h>
39#include <asm/bfin5xx_spi.h>
40#include <linux/usb_sl811.h> 39#include <linux/usb_sl811.h>
40#include <asm/bfin5xx_spi.h>
41 41
42/* 42/*
43 * Name the Board for the /proc/cpuinfo 43 * Name the Board for the /proc/cpuinfo
@@ -54,19 +54,19 @@ static struct resource bfin_pcmcia_cf_resources[] = {
54 .start = 0x20310000, /* IO PORT */ 54 .start = 0x20310000, /* IO PORT */
55 .end = 0x20312000, 55 .end = 0x20312000,
56 .flags = IORESOURCE_MEM, 56 .flags = IORESOURCE_MEM,
57 },{ 57 }, {
58 .start = 0x20311000, /* Attribute Memory */ 58 .start = 0x20311000, /* Attribute Memory */
59 .end = 0x20311FFF, 59 .end = 0x20311FFF,
60 .flags = IORESOURCE_MEM, 60 .flags = IORESOURCE_MEM,
61 },{ 61 }, {
62 .start = IRQ_PROG_INTA, 62 .start = IRQ_PROG_INTA,
63 .end = IRQ_PROG_INTA, 63 .end = IRQ_PROG_INTA,
64 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 64 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
65 },{ 65 }, {
66 .start = IRQ_PF4, 66 .start = IRQ_PF4,
67 .end = IRQ_PF4, 67 .end = IRQ_PF4,
68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
69 },{ 69 }, {
70 .start = 6, /* Card Detect PF6 */ 70 .start = 6, /* Card Detect PF6 */
71 .end = 6, 71 .end = 6,
72 .flags = IORESOURCE_IRQ, 72 .flags = IORESOURCE_IRQ,
@@ -95,11 +95,11 @@ static struct resource smc91x_resources[] = {
95 .start = 0x20300300, 95 .start = 0x20300300,
96 .end = 0x20300300 + 16, 96 .end = 0x20300300 + 16,
97 .flags = IORESOURCE_MEM, 97 .flags = IORESOURCE_MEM,
98 },{ 98 }, {
99 .start = IRQ_PROG_INTB, 99 .start = IRQ_PROG_INTB,
100 .end = IRQ_PROG_INTB, 100 .end = IRQ_PROG_INTB,
101 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 101 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
102 },{ 102 }, {
103 /* 103 /*
104 * denotes the flag pin and is used directly if 104 * denotes the flag pin and is used directly if
105 * CONFIG_IRQCHIP_DEMUX_GPIO is defined. 105 * CONFIG_IRQCHIP_DEMUX_GPIO is defined.
@@ -123,15 +123,15 @@ static struct resource sl811_hcd_resources[] = {
123 .start = 0x20340000, 123 .start = 0x20340000,
124 .end = 0x20340000, 124 .end = 0x20340000,
125 .flags = IORESOURCE_MEM, 125 .flags = IORESOURCE_MEM,
126 },{ 126 }, {
127 .start = 0x20340004, 127 .start = 0x20340004,
128 .end = 0x20340004, 128 .end = 0x20340004,
129 .flags = IORESOURCE_MEM, 129 .flags = IORESOURCE_MEM,
130 },{ 130 }, {
131 .start = IRQ_PROG_INTA, 131 .start = IRQ_PROG_INTA,
132 .end = IRQ_PROG_INTA, 132 .end = IRQ_PROG_INTA,
133 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 133 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
134 },{ 134 }, {
135 .start = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO, 135 .start = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO,
136 .end = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO, 136 .end = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO,
137 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 137 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -179,15 +179,15 @@ static struct resource isp1362_hcd_resources[] = {
179 .start = 0x20360000, 179 .start = 0x20360000,
180 .end = 0x20360000, 180 .end = 0x20360000,
181 .flags = IORESOURCE_MEM, 181 .flags = IORESOURCE_MEM,
182 },{ 182 }, {
183 .start = 0x20360004, 183 .start = 0x20360004,
184 .end = 0x20360004, 184 .end = 0x20360004,
185 .flags = IORESOURCE_MEM, 185 .flags = IORESOURCE_MEM,
186 },{ 186 }, {
187 .start = IRQ_PROG_INTA, 187 .start = IRQ_PROG_INTA,
188 .end = IRQ_PROG_INTA, 188 .end = IRQ_PROG_INTA,
189 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 189 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
190 },{ 190 }, {
191 .start = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO, 191 .start = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO,
192 .end = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO, 192 .end = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO,
193 .flags = IORESOURCE_IRQ, 193 .flags = IORESOURCE_IRQ,
@@ -228,7 +228,7 @@ static struct resource net2272_bfin_resources[] = {
228 .start = 0x20300000, 228 .start = 0x20300000,
229 .end = 0x20300000 + 0x100, 229 .end = 0x20300000 + 0x100,
230 .flags = IORESOURCE_MEM, 230 .flags = IORESOURCE_MEM,
231 },{ 231 }, {
232 .start = IRQ_PF7, 232 .start = IRQ_PF7,
233 .end = IRQ_PF7, 233 .end = IRQ_PF7,
234 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 234 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -253,11 +253,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
253 .size = 0x00020000, 253 .size = 0x00020000,
254 .offset = 0, 254 .offset = 0,
255 .mask_flags = MTD_CAP_ROM 255 .mask_flags = MTD_CAP_ROM
256 },{ 256 }, {
257 .name = "kernel", 257 .name = "kernel",
258 .size = 0xe0000, 258 .size = 0xe0000,
259 .offset = 0x20000 259 .offset = 0x20000
260 },{ 260 }, {
261 .name = "file system", 261 .name = "file system",
262 .size = 0x700000, 262 .size = 0x700000,
263 .offset = 0x00100000, 263 .offset = 0x00100000,
@@ -375,7 +375,7 @@ static struct resource bfin_uart_resources[] = {
375 .start = 0xFFC00400, 375 .start = 0xFFC00400,
376 .end = 0xFFC004FF, 376 .end = 0xFFC004FF,
377 .flags = IORESOURCE_MEM, 377 .flags = IORESOURCE_MEM,
378 },{ 378 }, {
379 .start = 0xFFC02000, 379 .start = 0xFFC02000,
380 .end = 0xFFC020FF, 380 .end = 0xFFC020FF,
381 .flags = IORESOURCE_MEM, 381 .flags = IORESOURCE_MEM,
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 8aaf76dfce80..8806f1230f2d 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -37,7 +37,7 @@
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
38#include <linux/usb_isp1362.h> 38#include <linux/usb_isp1362.h>
39#endif 39#endif
40#include <asm/irq.h> 40#include <linux/irq.h>
41#include <asm/bfin5xx_spi.h> 41#include <asm/bfin5xx_spi.h>
42#include <linux/usb_sl811.h> 42#include <linux/usb_sl811.h>
43 43
@@ -58,15 +58,15 @@ static struct resource bfin_pcmcia_cf_resources[] = {
58 .start = 0x20310000, /* IO PORT */ 58 .start = 0x20310000, /* IO PORT */
59 .end = 0x20312000, 59 .end = 0x20312000,
60 .flags = IORESOURCE_MEM, 60 .flags = IORESOURCE_MEM,
61 },{ 61 }, {
62 .start = 0x20311000, /* Attribute Memory */ 62 .start = 0x20311000, /* Attribute Memory */
63 .end = 0x20311FFF, 63 .end = 0x20311FFF,
64 .flags = IORESOURCE_MEM, 64 .flags = IORESOURCE_MEM,
65 },{ 65 }, {
66 .start = IRQ_PF4, 66 .start = IRQ_PF4,
67 .end = IRQ_PF4, 67 .end = IRQ_PF4,
68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
69 },{ 69 }, {
70 .start = 6, /* Card Detect PF6 */ 70 .start = 6, /* Card Detect PF6 */
71 .end = 6, 71 .end = 6,
72 .flags = IORESOURCE_IRQ, 72 .flags = IORESOURCE_IRQ,
@@ -95,7 +95,7 @@ static struct resource smc91x_resources[] = {
95 .start = 0x20300300, 95 .start = 0x20300300,
96 .end = 0x20300300 + 16, 96 .end = 0x20300300 + 16,
97 .flags = IORESOURCE_MEM, 97 .flags = IORESOURCE_MEM,
98 },{ 98 }, {
99 99
100 .start = IRQ_PF7, 100 .start = IRQ_PF7,
101 .end = IRQ_PF7, 101 .end = IRQ_PF7,
@@ -116,11 +116,11 @@ static struct resource sl811_hcd_resources[] = {
116 .start = 0x20340000, 116 .start = 0x20340000,
117 .end = 0x20340000, 117 .end = 0x20340000,
118 .flags = IORESOURCE_MEM, 118 .flags = IORESOURCE_MEM,
119 },{ 119 }, {
120 .start = 0x20340004, 120 .start = 0x20340004,
121 .end = 0x20340004, 121 .end = 0x20340004,
122 .flags = IORESOURCE_MEM, 122 .flags = IORESOURCE_MEM,
123 },{ 123 }, {
124 .start = CONFIG_USB_SL811_BFIN_IRQ, 124 .start = CONFIG_USB_SL811_BFIN_IRQ,
125 .end = CONFIG_USB_SL811_BFIN_IRQ, 125 .end = CONFIG_USB_SL811_BFIN_IRQ,
126 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 126 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -167,11 +167,11 @@ static struct resource isp1362_hcd_resources[] = {
167 .start = 0x20360000, 167 .start = 0x20360000,
168 .end = 0x20360000, 168 .end = 0x20360000,
169 .flags = IORESOURCE_MEM, 169 .flags = IORESOURCE_MEM,
170 },{ 170 }, {
171 .start = 0x20360004, 171 .start = 0x20360004,
172 .end = 0x20360004, 172 .end = 0x20360004,
173 .flags = IORESOURCE_MEM, 173 .flags = IORESOURCE_MEM,
174 },{ 174 }, {
175 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, 175 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
176 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, 176 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
177 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 177 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -212,7 +212,7 @@ static struct resource net2272_bfin_resources[] = {
212 .start = 0x20300000, 212 .start = 0x20300000,
213 .end = 0x20300000 + 0x100, 213 .end = 0x20300000 + 0x100,
214 .flags = IORESOURCE_MEM, 214 .flags = IORESOURCE_MEM,
215 },{ 215 }, {
216 .start = IRQ_PF7, 216 .start = IRQ_PF7,
217 .end = IRQ_PF7, 217 .end = IRQ_PF7,
218 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 218 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -238,11 +238,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
238 .size = 0x00020000, 238 .size = 0x00020000,
239 .offset = 0, 239 .offset = 0,
240 .mask_flags = MTD_CAP_ROM 240 .mask_flags = MTD_CAP_ROM
241 },{ 241 }, {
242 .name = "kernel", 242 .name = "kernel",
243 .size = 0xe0000, 243 .size = 0xe0000,
244 .offset = 0x20000 244 .offset = 0x20000
245 },{ 245 }, {
246 .name = "file system", 246 .name = "file system",
247 .size = 0x700000, 247 .size = 0x700000,
248 .offset = 0x00100000, 248 .offset = 0x00100000,
@@ -294,16 +294,6 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = {
294}; 294};
295#endif 295#endif
296 296
297#if defined(CONFIG_PBX)
298static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
299 .ctl_reg = 0x4, /* send zero */
300 .enable_dma = 0,
301 .bits_per_word = 8,
302 .cs_change_per_word = 1,
303};
304#endif
305
306
307#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 297#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
308static struct bfin5xx_spi_chip spi_ad7877_chip_info = { 298static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
309 .cs_change_per_word = 1, 299 .cs_change_per_word = 1,
@@ -392,24 +382,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
392 .mode = SPI_MODE_3, 382 .mode = SPI_MODE_3,
393 }, 383 },
394#endif 384#endif
395#if defined(CONFIG_PBX)
396 {
397 .modalias = "fxs-spi",
398 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
399 .bus_num = 1,
400 .chip_select = 3,
401 .controller_data= &spi_si3xxx_chip_info,
402 .mode = SPI_MODE_3,
403 },
404 {
405 .modalias = "fxo-spi",
406 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
407 .bus_num = 1,
408 .chip_select = 2,
409 .controller_data= &spi_si3xxx_chip_info,
410 .mode = SPI_MODE_3,
411 },
412#endif
413#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 385#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
414{ 386{
415 .modalias = "ad7877", 387 .modalias = "ad7877",
@@ -451,7 +423,7 @@ static struct resource bfin_uart_resources[] = {
451 .start = 0xFFC00400, 423 .start = 0xFFC00400,
452 .end = 0xFFC004FF, 424 .end = 0xFFC004FF,
453 .flags = IORESOURCE_MEM, 425 .flags = IORESOURCE_MEM,
454 },{ 426 }, {
455 .start = 0xFFC02000, 427 .start = 0xFFC02000,
456 .end = 0xFFC020FF, 428 .end = 0xFFC020FF,
457 .flags = IORESOURCE_MEM, 429 .flags = IORESOURCE_MEM,
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 3a29b4d15f25..9c43d7756510 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -37,12 +37,10 @@
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
38#include <linux/usb_isp1362.h> 38#include <linux/usb_isp1362.h>
39#endif 39#endif
40#include <asm/irq.h>
41#include <linux/irq.h> 40#include <linux/irq.h>
42#include <linux/interrupt.h> 41#include <linux/interrupt.h>
43#include <asm/bfin5xx_spi.h>
44#include <linux/usb_sl811.h> 42#include <linux/usb_sl811.h>
45 43#include <asm/bfin5xx_spi.h>
46#include <linux/spi/ad7877.h> 44#include <linux/spi/ad7877.h>
47 45
48/* 46/*
@@ -85,7 +83,7 @@ static struct platform_device *bfin_isp1761_devices[] = {
85 83
86int __init bfin_isp1761_init(void) 84int __init bfin_isp1761_init(void)
87{ 85{
88 unsigned int num_devices=ARRAY_SIZE(bfin_isp1761_devices); 86 unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
89 87
90 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); 88 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
91 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); 89 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
@@ -107,15 +105,15 @@ static struct resource bfin_pcmcia_cf_resources[] = {
107 .start = 0x20310000, /* IO PORT */ 105 .start = 0x20310000, /* IO PORT */
108 .end = 0x20312000, 106 .end = 0x20312000,
109 .flags = IORESOURCE_MEM, 107 .flags = IORESOURCE_MEM,
110 },{ 108 }, {
111 .start = 0x20311000, /* Attribute Memory */ 109 .start = 0x20311000, /* Attribute Memory */
112 .end = 0x20311FFF, 110 .end = 0x20311FFF,
113 .flags = IORESOURCE_MEM, 111 .flags = IORESOURCE_MEM,
114 },{ 112 }, {
115 .start = IRQ_PF4, 113 .start = IRQ_PF4,
116 .end = IRQ_PF4, 114 .end = IRQ_PF4,
117 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 115 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
118 },{ 116 }, {
119 .start = 6, /* Card Detect PF6 */ 117 .start = 6, /* Card Detect PF6 */
120 .end = 6, 118 .end = 6,
121 .flags = IORESOURCE_IRQ, 119 .flags = IORESOURCE_IRQ,
@@ -144,7 +142,7 @@ static struct resource smc91x_resources[] = {
144 .start = 0x20300300, 142 .start = 0x20300300,
145 .end = 0x20300300 + 16, 143 .end = 0x20300300 + 16,
146 .flags = IORESOURCE_MEM, 144 .flags = IORESOURCE_MEM,
147 },{ 145 }, {
148 146
149 .start = IRQ_PF7, 147 .start = IRQ_PF7,
150 .end = IRQ_PF7, 148 .end = IRQ_PF7,
@@ -159,17 +157,39 @@ static struct platform_device smc91x_device = {
159}; 157};
160#endif 158#endif
161 159
160#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
161static struct resource dm9000_resources[] = {
162 [0] = {
163 .start = 0x203FB800,
164 .end = 0x203FB800 + 8,
165 .flags = IORESOURCE_MEM,
166 },
167 [1] = {
168 .start = IRQ_PF9,
169 .end = IRQ_PF9,
170 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
171 },
172};
173
174static struct platform_device dm9000_device = {
175 .name = "dm9000",
176 .id = -1,
177 .num_resources = ARRAY_SIZE(dm9000_resources),
178 .resource = dm9000_resources,
179};
180#endif
181
162#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) 182#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
163static struct resource sl811_hcd_resources[] = { 183static struct resource sl811_hcd_resources[] = {
164 { 184 {
165 .start = 0x20340000, 185 .start = 0x20340000,
166 .end = 0x20340000, 186 .end = 0x20340000,
167 .flags = IORESOURCE_MEM, 187 .flags = IORESOURCE_MEM,
168 },{ 188 }, {
169 .start = 0x20340004, 189 .start = 0x20340004,
170 .end = 0x20340004, 190 .end = 0x20340004,
171 .flags = IORESOURCE_MEM, 191 .flags = IORESOURCE_MEM,
172 },{ 192 }, {
173 .start = CONFIG_USB_SL811_BFIN_IRQ, 193 .start = CONFIG_USB_SL811_BFIN_IRQ,
174 .end = CONFIG_USB_SL811_BFIN_IRQ, 194 .end = CONFIG_USB_SL811_BFIN_IRQ,
175 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 195 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -216,11 +236,11 @@ static struct resource isp1362_hcd_resources[] = {
216 .start = 0x20360000, 236 .start = 0x20360000,
217 .end = 0x20360000, 237 .end = 0x20360000,
218 .flags = IORESOURCE_MEM, 238 .flags = IORESOURCE_MEM,
219 },{ 239 }, {
220 .start = 0x20360004, 240 .start = 0x20360004,
221 .end = 0x20360004, 241 .end = 0x20360004,
222 .flags = IORESOURCE_MEM, 242 .flags = IORESOURCE_MEM,
223 },{ 243 }, {
224 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, 244 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
225 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, 245 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
226 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 246 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -261,7 +281,7 @@ static struct resource net2272_bfin_resources[] = {
261 .start = 0x20300000, 281 .start = 0x20300000,
262 .end = 0x20300000 + 0x100, 282 .end = 0x20300000 + 0x100,
263 .flags = IORESOURCE_MEM, 283 .flags = IORESOURCE_MEM,
264 },{ 284 }, {
265 .start = IRQ_PF7, 285 .start = IRQ_PF7,
266 .end = IRQ_PF7, 286 .end = IRQ_PF7,
267 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 287 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -287,11 +307,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
287 .size = 0x00020000, 307 .size = 0x00020000,
288 .offset = 0, 308 .offset = 0,
289 .mask_flags = MTD_CAP_ROM 309 .mask_flags = MTD_CAP_ROM
290 },{ 310 }, {
291 .name = "kernel", 311 .name = "kernel",
292 .size = 0xe0000, 312 .size = 0xe0000,
293 .offset = 0x20000 313 .offset = 0x20000
294 },{ 314 }, {
295 .name = "file system", 315 .name = "file system",
296 .size = 0x700000, 316 .size = 0x700000,
297 .offset = 0x00100000, 317 .offset = 0x00100000,
@@ -361,7 +381,6 @@ static struct bfin5xx_spi_chip ad5304_chip_info = {
361 381
362#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 382#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
363static struct bfin5xx_spi_chip spi_ad7877_chip_info = { 383static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
364// .cs_change_per_word = 1,
365 .enable_dma = 0, 384 .enable_dma = 0,
366 .bits_per_word = 16, 385 .bits_per_word = 16,
367}; 386};
@@ -449,19 +468,19 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
449#endif 468#endif
450#if defined(CONFIG_PBX) 469#if defined(CONFIG_PBX)
451 { 470 {
452 .modalias = "fxs-spi", 471 .modalias = "fxs-spi",
453 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 472 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
454 .bus_num = 1, 473 .bus_num = 1,
455 .chip_select = 3, 474 .chip_select = 3,
456 .controller_data= &spi_si3xxx_chip_info, 475 .controller_data = &spi_si3xxx_chip_info,
457 .mode = SPI_MODE_3, 476 .mode = SPI_MODE_3,
458 }, 477 },
459 { 478 {
460 .modalias = "fxo-spi", 479 .modalias = "fxo-spi",
461 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 480 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
462 .bus_num = 1, 481 .bus_num = 1,
463 .chip_select = 2, 482 .chip_select = 2,
464 .controller_data= &spi_si3xxx_chip_info, 483 .controller_data = &spi_si3xxx_chip_info,
465 .mode = SPI_MODE_3, 484 .mode = SPI_MODE_3,
466 }, 485 },
467#endif 486#endif
@@ -516,7 +535,7 @@ static struct resource bfin_uart_resources[] = {
516 .start = 0xFFC00400, 535 .start = 0xFFC00400,
517 .end = 0xFFC004FF, 536 .end = 0xFFC004FF,
518 .flags = IORESOURCE_MEM, 537 .flags = IORESOURCE_MEM,
519 },{ 538 }, {
520 .start = 0xFFC02000, 539 .start = 0xFFC02000,
521 .end = 0xFFC020FF, 540 .end = 0xFFC020FF,
522 .flags = IORESOURCE_MEM, 541 .flags = IORESOURCE_MEM,
@@ -571,6 +590,10 @@ static struct platform_device *stamp_devices[] __initdata = {
571 &smc91x_device, 590 &smc91x_device,
572#endif 591#endif
573 592
593#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
594 &dm9000_device,
595#endif
596
574#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 597#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
575 &bfin_mac_device, 598 &bfin_mac_device,
576#endif 599#endif
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c
new file mode 100644
index 000000000000..706cb97b0265
--- /dev/null
+++ b/arch/blackfin/mach-bf537/dma.c
@@ -0,0 +1,115 @@
1/*
2 * File: arch/blackfin/mach-bf537/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#include <asm/blackfin.h>
30#include <asm/dma.h>
31
32struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
33 (struct dma_register *) DMA0_NEXT_DESC_PTR,
34 (struct dma_register *) DMA1_NEXT_DESC_PTR,
35 (struct dma_register *) DMA2_NEXT_DESC_PTR,
36 (struct dma_register *) DMA3_NEXT_DESC_PTR,
37 (struct dma_register *) DMA4_NEXT_DESC_PTR,
38 (struct dma_register *) DMA5_NEXT_DESC_PTR,
39 (struct dma_register *) DMA6_NEXT_DESC_PTR,
40 (struct dma_register *) DMA7_NEXT_DESC_PTR,
41 (struct dma_register *) DMA8_NEXT_DESC_PTR,
42 (struct dma_register *) DMA9_NEXT_DESC_PTR,
43 (struct dma_register *) DMA10_NEXT_DESC_PTR,
44 (struct dma_register *) DMA11_NEXT_DESC_PTR,
45 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
46 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
47 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
48 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
49};
50
51int channel2irq(unsigned int channel)
52{
53 int ret_irq = -1;
54
55 switch (channel) {
56 case CH_PPI:
57 ret_irq = IRQ_PPI;
58 break;
59
60 case CH_EMAC_RX:
61 ret_irq = IRQ_MAC_RX;
62 break;
63
64 case CH_EMAC_TX:
65 ret_irq = IRQ_MAC_TX;
66 break;
67
68 case CH_UART1_RX:
69 ret_irq = IRQ_UART1_RX;
70 break;
71
72 case CH_UART1_TX:
73 ret_irq = IRQ_UART1_TX;
74 break;
75
76 case CH_SPORT0_RX:
77 ret_irq = IRQ_SPORT0_RX;
78 break;
79
80 case CH_SPORT0_TX:
81 ret_irq = IRQ_SPORT0_TX;
82 break;
83
84 case CH_SPORT1_RX:
85 ret_irq = IRQ_SPORT1_RX;
86 break;
87
88 case CH_SPORT1_TX:
89 ret_irq = IRQ_SPORT1_TX;
90 break;
91
92 case CH_SPI:
93 ret_irq = IRQ_SPI;
94 break;
95
96 case CH_UART_RX:
97 ret_irq = IRQ_UART_RX;
98 break;
99
100 case CH_UART_TX:
101 ret_irq = IRQ_UART_TX;
102 break;
103
104 case CH_MEM_STREAM0_SRC:
105 case CH_MEM_STREAM0_DEST:
106 ret_irq = IRQ_MEM_DMA0;
107 break;
108
109 case CH_MEM_STREAM1_SRC:
110 case CH_MEM_STREAM1_DEST:
111 ret_irq = IRQ_MEM_DMA1;
112 break;
113 }
114 return ret_irq;
115}
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 7d902bbd860f..429c8a1019da 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -30,6 +30,8 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h>
34
33#if CONFIG_BFIN_KERNEL_CLOCK 35#if CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach/mem_init.h> 36#include <asm/mach/mem_init.h>
35#endif 37#endif
@@ -93,6 +95,10 @@ ENTRY(__start)
93 M2 = r0; 95 M2 = r0;
94 M3 = r0; 96 M3 = r0;
95 97
98 trace_buffer_start(p0,r0);
99 P0 = R1;
100 R0 = R1;
101
96 /* Turn off the icache */ 102 /* Turn off the icache */
97 p0.l = (IMEM_CONTROL & 0xFFFF); 103 p0.l = (IMEM_CONTROL & 0xFFFF);
98 p0.h = (IMEM_CONTROL >> 16); 104 p0.h = (IMEM_CONTROL >> 16);
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
index 2dbf3df465d1..a8b915f202ec 100644
--- a/arch/blackfin/mach-bf537/ints-priority.c
+++ b/arch/blackfin/mach-bf537/ints-priority.c
@@ -28,8 +28,8 @@
28 */ 28 */
29 29
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/irq.h>
31#include <asm/blackfin.h> 32#include <asm/blackfin.h>
32#include <asm/irq.h>
33 33
34void program_IAR(void) 34void program_IAR(void)
35{ 35{
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
new file mode 100644
index 000000000000..e78b03d56c7c
--- /dev/null
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -0,0 +1,316 @@
1if (BF54x)
2
3menu "BF548 Specific Configuration"
4
5comment "Interrupt Priority Assignment"
6menu "Priority"
7
8config IRQ_PLL_WAKEUP
9 int "IRQ_PLL_WAKEUP"
10 default 7
11config IRQ_DMAC0_ERR
12 int "IRQ_DMAC0_ERR"
13 default 7
14config IRQ_EPPI0_ERR
15 int "IRQ_EPPI0_ERR"
16 default 7
17config IRQ_SPORT0_ERR
18 int "IRQ_SPORT0_ERR"
19 default 7
20config IRQ_SPORT1_ERR
21 int "IRQ_SPORT1_ERR"
22 default 7
23config IRQ_SPI0_ERR
24 int "IRQ_SPI0_ERR"
25 default 7
26config IRQ_UART0_ERR
27 int "IRQ_UART0_ERR"
28 default 7
29config IRQ_RTC
30 int "IRQ_RTC"
31 default 8
32config IRQ_EPPI0
33 int "IRQ_EPPI0"
34 default 8
35config IRQ_SPORT0_RX
36 int "IRQ_SPORT0_RX"
37 default 9
38config IRQ_SPORT0_TX
39 int "IRQ_SPORT0_TX"
40 default 9
41config IRQ_SPORT1_RX
42 int "IRQ_SPORT1_RX"
43 default 9
44config IRQ_SPORT1_TX
45 int "IRQ_SPORT1_TX"
46 default 9
47config IRQ_SPI0
48 int "IRQ_SPI0"
49 default 10
50config IRQ_UART0_RX
51 int "IRQ_UART0_RX"
52 default 10
53config IRQ_UART0_TX
54 int "IRQ_UART0_TX"
55 default 10
56config IRQ_TIMER8
57 int "IRQ_TIMER8"
58 default 11
59config IRQ_TIMER9
60 int "IRQ_TIMER9"
61 default 11
62config IRQ_TIMER10
63 int "IRQ_TIMER10"
64 default 11
65config IRQ_PINT0
66 int "IRQ_PINT0"
67 default 12
68config IRQ_PINT1
69 int "IRQ_PINT0"
70 default 12
71config IRQ_MDMAS0
72 int "IRQ_MDMAS0"
73 default 13
74config IRQ_MDMAS1
75 int "IRQ_DMDMAS1"
76 default 13
77config IRQ_WATCHDOG
78 int "IRQ_WATCHDOG"
79 default 13
80config IRQ_DMAC1_ERR
81 int "IRQ_DMAC1_ERR"
82 default 7
83config IRQ_SPORT2_ERR
84 int "IRQ_SPORT2_ERR"
85 default 7
86config IRQ_SPORT3_ERR
87 int "IRQ_SPORT3_ERR"
88 default 7
89config IRQ_MXVR_DATA
90 int "IRQ MXVR Data"
91 default 7
92config IRQ_SPI1_ERR
93 int "IRQ_SPI1_ERR"
94 default 7
95config IRQ_SPI2_ERR
96 int "IRQ_SPI2_ERR"
97 default 7
98config IRQ_UART1_ERR
99 int "IRQ_UART1_ERR"
100 default 7
101config IRQ_UART2_ERR
102 int "IRQ_UART2_ERR"
103 default 7
104config IRQ_CAN0_ERR
105 int "IRQ_CAN0_ERR"
106 default 7
107config IRQ_SPORT2_RX
108 int "IRQ_SPORT2_RX"
109 default 9
110config IRQ_SPORT2_TX
111 int "IRQ_SPORT2_TX"
112 default 9
113config IRQ_SPORT3_RX
114 int "IRQ_SPORT3_RX"
115 default 9
116config IRQ_SPORT3_TX
117 int "IRQ_SPORT3_TX"
118 default 9
119config IRQ_EPPI1
120 int "IRQ_EPPI1"
121 default 9
122config IRQ_EPPI2
123 int "IRQ_EPPI2"
124 default 9
125config IRQ_SPI1
126 int "IRQ_SPI1"
127 default 10
128config IRQ_SPI2
129 int "IRQ_SPI2"
130 default 10
131config IRQ_UART1_RX
132 int "IRQ_UART1_RX"
133 default 10
134config IRQ_UART1_TX
135 int "IRQ_UART1_TX"
136 default 10
137config IRQ_ATAPI_RX
138 int "IRQ_ATAPI_RX"
139 default 10
140config IRQ_ATAPI_TX
141 int "IRQ_ATAPI_TX"
142 default 10
143config IRQ_TWI0
144 int "IRQ_TWI0"
145 default 11
146config IRQ_TWI1
147 int "IRQ_TWI1"
148 default 11
149config IRQ_CAN0_RX
150 int "IRQ_CAN_RX"
151 default 11
152config IRQ_CAN0_TX
153 int "IRQ_CAN_TX"
154 default 11
155config IRQ_MDMAS2
156 int "IRQ_MDMAS2"
157 default 13
158config IRQ_MDMAS3
159 int "IRQ_DMMAS3"
160 default 13
161config IRQ_MXVR_ERR
162 int "IRQ_MXVR_ERR"
163 default 11
164config IRQ_MXVR_MSG
165 int "IRQ_MXVR_MSG"
166 default 11
167config IRQ_MXVR_PKT
168 int "IRQ_MXVR_PKT"
169 default 11
170config IRQ_EPPI1_ERR
171 int "IRQ_EPPI1_ERR"
172 default 7
173config IRQ_EPPI2_ERR
174 int "IRQ_EPPI2_ERR"
175 default 7
176config IRQ_UART3_ERR
177 int "IRQ_UART3_ERR"
178 default 7
179config IRQ_HOST_ERR
180 int "IRQ_HOST_ERR"
181 default 7
182config IRQ_PIXC_ERR
183 int "IRQ_PIXC_ERR"
184 default 7
185config IRQ_NFC_ERR
186 int "IRQ_NFC_ERR"
187 default 7
188config IRQ_ATAPI_ERR
189 int "IRQ_ATAPI_ERR"
190 default 7
191config IRQ_CAN1_ERR
192 int "IRQ_CAN1_ERR"
193 default 7
194config IRQ_HS_DMA_ERR
195 int "IRQ Handshake DMA Status"
196 default 7
197config IRQ_PIXC_IN0
198 int "IRQ PIXC IN0"
199 default 8
200config IRQ_PIXC_IN1
201 int "IRQ PIXC IN1"
202 default 8
203config IRQ_PIXC_OUT
204 int "IRQ PIXC OUT"
205 default 8
206config IRQ_SDH
207 int "IRQ SDH"
208 default 8
209config IRQ_CNT
210 int "IRQ CNT"
211 default 8
212config IRQ_KEY
213 int "IRQ KEY"
214 default 8
215config IRQ_CAN1_RX
216 int "IRQ CAN1 RX"
217 default 11
218config IRQ_CAN1_TX
219 int "IRQ_CAN1_TX"
220 default 11
221config IRQ_SDH_MASK0
222 int "IRQ_SDH_MASK0"
223 default 11
224config IRQ_SDH_MASK1
225 int "IRQ_SDH_MASK1"
226 default 11
227config IRQ_USB_INT0
228 int "IRQ USB INT0"
229 default 11
230config IRQ_USB_INT1
231 int "IRQ USB INT1"
232 default 11
233config IRQ_USB_INT2
234 int "IRQ USB INT2"
235 default 11
236config IRQ_USB_DMA
237 int "IRQ USB DMA"
238 default 11
239config IRQ_OTPSEC
240 int "IRQ OPTSEC"
241 default 11
242config IRQ_TIMER0
243 int "IRQ_TIMER0"
244 default 11
245config IRQ_TIMER1
246 int "IRQ_TIMER1"
247 default 11
248config IRQ_TIMER2
249 int "IRQ_TIMER2"
250 default 11
251config IRQ_TIMER3
252 int "IRQ_TIMER3"
253 default 11
254config IRQ_TIMER4
255 int "IRQ_TIMER4"
256 default 11
257config IRQ_TIMER5
258 int "IRQ_TIMER5"
259 default 11
260config IRQ_TIMER6
261 int "IRQ_TIMER6"
262 default 11
263config IRQ_TIMER7
264 int "IRQ_TIMER7"
265 default 11
266config IRQ_PINT2
267 int "IRQ_PIN2"
268 default 11
269config IRQ_PINT3
270 int "IRQ_PIN3"
271 default 11
272
273 help
274 Enter the priority numbers between 7-13 ONLY. Others are Reserved.
275 This applies to all the above. It is not recommended to assign the
276 highest priority number 7 to UART or any other device.
277
278endmenu
279
280comment "Pin Interrupt to Port Assignment"
281menu "Assignment"
282
283config PINTx_REASSIGN
284 bool "Reprogram PINT Assignment"
285 default n
286 help
287 The interrupt assignment registers controls the pin-to-interrupt
288 assignment in a byte-wide manner. Each option allows you to select
289 a set of pins (High/Low Byte) of an specific Port being mapped
290 to one of the four PIN Interrupts IRQ_PINTx.
291
292 You shouldn't change any of these unless you know exactly what you're doing.
293 Please consult the Blackfin BF54x Processor Hardware Reference Manual.
294
295config PINT0_ASSIGN
296 hex "PINT0_ASSIGN"
297 depends on PINTx_REASSIGN
298 default 0x00000101
299config PINT1_ASSIGN
300 hex "PINT1_ASSIGN"
301 depends on PINTx_REASSIGN
302 default 0x01010000
303config PINT2_ASSIGN
304 hex "PINT2_ASSIGN"
305 depends on PINTx_REASSIGN
306 default 0x00000101
307config PINT3_ASSIGN
308 hex "PINT3_ASSIGN"
309 depends on PINTx_REASSIGN
310 default 0x02020303
311
312endmenu
313
314endmenu
315
316endif
diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile
new file mode 100644
index 000000000000..060ad78ebf1d
--- /dev/null
+++ b/arch/blackfin/mach-bf548/Makefile
@@ -0,0 +1,9 @@
1#
2# arch/blackfin/mach-bf537/Makefile
3#
4
5extra-y := head.o
6
7obj-y := ints-priority.o dma.o gpio.o
8
9obj-$(CONFIG_CPU_FREQ) += cpu.o
diff --git a/arch/blackfin/mach-bf548/boards/Makefile b/arch/blackfin/mach-bf548/boards/Makefile
new file mode 100644
index 000000000000..486e07c99a51
--- /dev/null
+++ b/arch/blackfin/mach-bf548/boards/Makefile
@@ -0,0 +1,5 @@
1#
2# arch/blackfin/mach-bf548/boards/Makefile
3#
4
5obj-$(CONFIG_BFIN548_EZKIT) += ezkit.o led.o
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
new file mode 100644
index 000000000000..96ad95fab1a8
--- /dev/null
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -0,0 +1,114 @@
1/*
2 * File: arch/blackfin/mach-bf548/boards/ezkit.c
3 * Based on: arch/blackfin/mach-bf537/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2007 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h>
37#include <linux/irq.h>
38#include <linux/irq.h>
39#include <linux/interrupt.h>
40#include <asm/bfin5xx_spi.h>
41
42/*
43 * Name the Board for the /proc/cpuinfo
44 */
45char *bfin_board_name = "ADSP-BF548-EZKIT";
46
47/*
48 * Driver needs to know address, irq and flag pin.
49 */
50
51#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
52static struct platform_device rtc_device = {
53 .name = "rtc-bfin",
54 .id = -1,
55};
56#endif
57
58#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
59static struct resource bfin_uart_resources[] = {
60#ifdef CONFIG_SERIAL_BFIN_UART0
61 {
62 .start = 0xFFC00400,
63 .end = 0xFFC004FF,
64 .flags = IORESOURCE_MEM,
65 },
66#endif
67#ifdef CONFIG_SERIAL_BFIN_UART1
68 {
69 .start = 0xFFC02000,
70 .end = 0xFFC020FF,
71 .flags = IORESOURCE_MEM,
72 },
73#endif
74#ifdef CONFIG_SERIAL_BFIN_UART2
75 {
76 .start = 0xFFC02100,
77 .end = 0xFFC021FF,
78 .flags = IORESOURCE_MEM,
79 },
80#endif
81#ifdef CONFIG_SERIAL_BFIN_UART3
82 {
83 .start = 0xFFC03100,
84 .end = 0xFFC031FF,
85 },
86#endif
87};
88
89static struct platform_device bfin_uart_device = {
90 .name = "bfin-uart",
91 .id = 1,
92 .num_resources = ARRAY_SIZE(bfin_uart_resources),
93 .resource = bfin_uart_resources,
94};
95#endif
96
97static struct platform_device *ezkit_devices[] __initdata = {
98#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
99 &rtc_device,
100#endif
101
102#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
103 &bfin_uart_device,
104#endif
105};
106
107static int __init stamp_init(void)
108{
109 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
110 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
111 return 0;
112}
113
114arch_initcall(stamp_init);
diff --git a/arch/blackfin/mach-bf548/boards/led.S b/arch/blackfin/mach-bf548/boards/led.S
new file mode 100644
index 000000000000..f47daf3770d0
--- /dev/null
+++ b/arch/blackfin/mach-bf548/boards/led.S
@@ -0,0 +1,172 @@
1/****************************************************
2 * LED1 ---- PG6 LED2 ---- PG7 *
3 * LED3 ---- PG8 LED4 ---- PG9 *
4 * LED5 ---- PG10 LED6 ---- PG11 *
5 ****************************************************/
6
7#include <linux/linkage.h>
8#include <asm/blackfin.h>
9
10/* All functions in this file save the registers they uses.
11 So there is no need to save any registers before calling them. */
12
13 .text;
14
15/* Initialize LEDs. */
16
17ENTRY(_led_init)
18 LINK 0;
19 [--SP] = P0;
20 [--SP] = R0;
21 [--SP] = R1;
22 [--SP] = R2;
23 R1 = (PG6|PG7|PG8|PG9|PG10|PG11)(Z);
24 R2 = ~R1;
25
26 P0.H = hi(PORTG_FER);
27 P0.L = lo(PORTG_FER);
28 R0 = W[P0](Z);
29 SSYNC;
30 R0 = R0 & R2;
31 W[P0] = R0.L;
32 SSYNC;
33
34 P0.H = hi(PORTG_DIR_SET);
35 P0.L = lo(PORTG_DIR_SET);
36 W[P0] = R1.L;
37 SSYNC;
38
39 P0.H = hi(PORTG_INEN);
40 P0.L = lo(PORTG_INEN);
41 R0 = W[P0](Z);
42 SSYNC;
43 R0 = R0 & R2;
44 W[P0] = R0.L;
45 SSYNC;
46
47 R2 = [SP++];
48 R1 = [SP++];
49 R0 = [SP++];
50 P0 = [SP++];
51 RTS;
52 .size _led_init, .-_led_init
53
54/* Set one LED on. Leave other LEDs unchanged.
55 It expects the LED number passed through R0. */
56
57ENTRY(_led_on)
58 LINK 0;
59 [--SP] = P0;
60 [--SP] = R1;
61 CALL _led_init;
62 R1 = 1;
63 R0 += 5;
64 R1 <<= R0;
65 P0.H = hi(PORTG_SET);
66 P0.L = lo(PORTG_SET);
67 W[P0] = R1.L;
68 SSYNC;
69 R1 = [SP++];
70 P0 = [SP++];
71 UNLINK;
72 RTS;
73 .size _led_on, .-_led_on
74
75/* Set one LED off. Leave other LEDs unchanged. */
76
77ENTRY(_led_off)
78 LINK 0;
79 [--SP] = P0;
80 [--SP] = R1;
81 CALL _led_init;
82 R1 = 1;
83 R0 += 5;
84 R1 <<= R0;
85 P0.H = hi(PORTG_CLEAR);
86 P0.L = lo(PORTG_CLEAR);
87 W[P0] = R1.L;
88 SSYNC;
89 R1 = [SP++];
90 P0 = [SP++];
91 UNLINK;
92 RTS;
93 .size _led_off, .-_led_off
94
95/* Toggle one LED. Leave other LEDs unchanged. */
96
97ENTRY(_led_toggle)
98 LINK 0;
99 [--SP] = P0;
100 [--SP] = R1;
101 CALL _led_init;
102 R1 = 1;
103 R0 += 5;
104 R1 <<= R0;
105 P0.H = hi(PORTG);
106 P0.L = lo(PORTG);
107 R0 = W[P0](Z);
108 SSYNC;
109 R0 = R0 ^ R1;
110 W[P0] = R0.L;
111 SSYNC;
112 R1 = [SP++];
113 P0 = [SP++];
114 UNLINK;
115 RTS;
116 .size _led_toggle, .-_led_toggle
117
118/* Display the number using LEDs in binary format. */
119
120ENTRY(_led_disp_num)
121 LINK 0;
122 [--SP] = P0;
123 [--SP] = R1;
124 [--SP] = R2;
125 CALL _led_init;
126 R1 = 0x3f(X);
127 R0 = R0 & R1;
128 R2 = 6(X);
129 R0 <<= R2;
130 R1 <<= R2;
131 P0.H = hi(PORTG);
132 P0.L = lo(PORTG);
133 R2 = W[P0](Z);
134 SSYNC;
135 R1 = ~R1;
136 R2 = R2 & R1;
137 R2 = R2 | R0;
138 W[P0] = R2.L;
139 SSYNC;
140 R2 = [SP++];
141 R1 = [SP++];
142 P0 = [SP++];
143 UNLINK;
144 RTS;
145 .size _led_disp_num, .-_led_disp_num
146
147/* Toggle the number using LEDs in binary format. */
148
149ENTRY(_led_toggle_num)
150 LINK 0;
151 [--SP] = P0;
152 [--SP] = R1;
153 [--SP] = R2;
154 CALL _led_init;
155 R1 = 0x3f(X);
156 R0 = R0 & R1;
157 R1 = 6(X);
158 R0 <<= R1;
159 P0.H = hi(PORTG);
160 P0.L = lo(PORTG);
161 R1 = W[P0](Z);
162 SSYNC;
163 R1 = R1 ^ R0;
164 W[P0] = R1.L;
165 SSYNC;
166 R2 = [SP++];
167 R1 = [SP++];
168 P0 = [SP++];
169 UNLINK;
170 RTS;
171 .size _led_toggle_num, .-_led_toggle_num
172
diff --git a/arch/blackfin/mach-bf548/cpu.c b/arch/blackfin/mach-bf548/cpu.c
new file mode 100644
index 000000000000..4298a3ccfbfc
--- /dev/null
+++ b/arch/blackfin/mach-bf548/cpu.c
@@ -0,0 +1,159 @@
1/*
2 * File: arch/blackfin/mach-bf548/cpu.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: clock scaling for the bf54x
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/init.h>
33#include <linux/cpufreq.h>
34#include <asm/dpmc.h>
35#include <linux/fs.h>
36#include <asm/bfin-global.h>
37
38/* CONFIG_CLKIN_HZ=25000000 */
39#define VCO5 (CONFIG_CLKIN_HZ*45)
40#define VCO4 (CONFIG_CLKIN_HZ*36)
41#define VCO3 (CONFIG_CLKIN_HZ*27)
42#define VCO2 (CONFIG_CLKIN_HZ*18)
43#define VCO1 (CONFIG_CLKIN_HZ*9)
44#define VCO(x) VCO##x
45
46#define MFREQ(x) {VCO(x),VCO(x)/4},{VCO(x),VCO(x)/2},{VCO(x),VCO(x)}
47/* frequency */
48static struct cpufreq_frequency_table bf548_freq_table[] = {
49 MFREQ(1),
50 MFREQ(3),
51 {VCO4, VCO4 / 2}, {VCO4, VCO4},
52 MFREQ(5),
53 {0, CPUFREQ_TABLE_END},
54};
55
56/*
57 * dpmc_fops->ioctl()
58 * static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
59 */
60static int bf548_getfreq(unsigned int cpu)
61{
62 unsigned long cclk_mhz;
63
64 /* The driver only support single cpu */
65 if (cpu == 0)
66 dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz);
67 else
68 cclk_mhz = -1;
69
70 return cclk_mhz;
71}
72
73static int bf548_target(struct cpufreq_policy *policy,
74 unsigned int target_freq, unsigned int relation)
75{
76 unsigned long cclk_mhz;
77 unsigned long vco_mhz;
78 unsigned long flags;
79 unsigned int index;
80 struct cpufreq_freqs freqs;
81
82 if (cpufreq_frequency_table_target(policy, bf548_freq_table, target_freq, relation, &index))
83 return -EINVAL;
84
85 cclk_mhz = bf548_freq_table[index].frequency;
86 vco_mhz = bf548_freq_table[index].index;
87
88 dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz);
89 freqs.old = bf548_getfreq(0);
90 freqs.new = cclk_mhz;
91 freqs.cpu = 0;
92
93 pr_debug("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n",
94 cclk_mhz, vco_mhz, index, target_freq, freqs.old);
95
96 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
97 local_irq_save(flags);
98 dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz);
99 local_irq_restore(flags);
100 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
101
102 vco_mhz = get_vco();
103 cclk_mhz = get_cclk();
104 return 0;
105}
106
107/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
108 * this platform, anyway.
109 */
110static int bf548_verify_speed(struct cpufreq_policy *policy)
111{
112 return cpufreq_frequency_table_verify(policy, &bf548_freq_table);
113}
114
115static int __init __bf548_cpu_init(struct cpufreq_policy *policy)
116{
117 if (policy->cpu != 0)
118 return -EINVAL;
119
120 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
121
122 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
123 /*Now ,only support one cpu */
124 policy->cur = bf548_getfreq(0);
125 cpufreq_frequency_table_get_attr(bf548_freq_table, policy->cpu);
126 return cpufreq_frequency_table_cpuinfo(policy, bf548_freq_table);
127}
128
129static struct freq_attr *bf548_freq_attr[] = {
130 &cpufreq_freq_attr_scaling_available_freqs,
131 NULL,
132};
133
134static struct cpufreq_driver bf548_driver = {
135 .verify = bf548_verify_speed,
136 .target = bf548_target,
137 .get = bf548_getfreq,
138 .init = __bf548_cpu_init,
139 .name = "bf548",
140 .owner = THIS_MODULE,
141 .attr = bf548_freq_attr,
142};
143
144static int __init bf548_cpu_init(void)
145{
146 return cpufreq_register_driver(&bf548_driver);
147}
148
149static void __exit bf548_cpu_exit(void)
150{
151 cpufreq_unregister_driver(&bf548_driver);
152}
153
154MODULE_AUTHOR("Mickael Kang");
155MODULE_DESCRIPTION("cpufreq driver for BF548 CPU");
156MODULE_LICENSE("GPL");
157
158module_init(bf548_cpu_init);
159module_exit(bf548_cpu_exit);
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
new file mode 100644
index 000000000000..a8184113be48
--- /dev/null
+++ b/arch/blackfin/mach-bf548/dma.c
@@ -0,0 +1,156 @@
1/*
2 * File: arch/blackfin/mach-bf561/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <asm/blackfin.h>
31#include <asm/dma.h>
32
33 struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
34 (struct dma_register *) DMA0_NEXT_DESC_PTR,
35 (struct dma_register *) DMA1_NEXT_DESC_PTR,
36 (struct dma_register *) DMA2_NEXT_DESC_PTR,
37 (struct dma_register *) DMA3_NEXT_DESC_PTR,
38 (struct dma_register *) DMA4_NEXT_DESC_PTR,
39 (struct dma_register *) DMA5_NEXT_DESC_PTR,
40 (struct dma_register *) DMA6_NEXT_DESC_PTR,
41 (struct dma_register *) DMA7_NEXT_DESC_PTR,
42 (struct dma_register *) DMA8_NEXT_DESC_PTR,
43 (struct dma_register *) DMA9_NEXT_DESC_PTR,
44 (struct dma_register *) DMA10_NEXT_DESC_PTR,
45 (struct dma_register *) DMA11_NEXT_DESC_PTR,
46 (struct dma_register *) DMA12_NEXT_DESC_PTR,
47 (struct dma_register *) DMA13_NEXT_DESC_PTR,
48 (struct dma_register *) DMA14_NEXT_DESC_PTR,
49 (struct dma_register *) DMA15_NEXT_DESC_PTR,
50 (struct dma_register *) DMA16_NEXT_DESC_PTR,
51 (struct dma_register *) DMA17_NEXT_DESC_PTR,
52 (struct dma_register *) DMA18_NEXT_DESC_PTR,
53 (struct dma_register *) DMA19_NEXT_DESC_PTR,
54 (struct dma_register *) DMA20_NEXT_DESC_PTR,
55 (struct dma_register *) DMA21_NEXT_DESC_PTR,
56 (struct dma_register *) DMA22_NEXT_DESC_PTR,
57 (struct dma_register *) DMA23_NEXT_DESC_PTR,
58 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
59 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
60 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
61 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
62 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
63 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
64 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
65 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
66};
67
68int channel2irq(unsigned int channel)
69{
70 int ret_irq = -1;
71
72 switch (channel) {
73 case CH_SPORT0_RX:
74 ret_irq = IRQ_SPORT0_RX;
75 break;
76 case CH_SPORT0_TX:
77 ret_irq = IRQ_SPORT0_TX;
78 break;
79 case CH_SPORT1_RX:
80 ret_irq = IRQ_SPORT1_RX;
81 break;
82 case CH_SPORT1_TX:
83 ret_irq = IRQ_SPORT1_TX;
84 case CH_SPI0:
85 ret_irq = IRQ_SPI0;
86 break;
87 case CH_SPI1:
88 ret_irq = IRQ_SPI1;
89 break;
90 case CH_UART0_RX:
91 ret_irq = IRQ_UART_RX;
92 break;
93 case CH_UART0_TX:
94 ret_irq = IRQ_UART_TX;
95 break;
96 case CH_UART1_RX:
97 ret_irq = IRQ_UART_RX;
98 break;
99 case CH_UART1_TX:
100 ret_irq = IRQ_UART_TX;
101 break;
102 case CH_EPPI0:
103 ret_irq = IRQ_EPPI0;
104 break;
105 case CH_EPPI1:
106 ret_irq = IRQ_EPPI1;
107 break;
108 case CH_EPPI2:
109 ret_irq = IRQ_EPPI2;
110 break;
111 case CH_PIXC_IMAGE:
112 ret_irq = IRQ_PIXC_IN0;
113 break;
114 case CH_PIXC_OVERLAY:
115 ret_irq = IRQ_PIXC_IN1;
116 break;
117 case CH_PIXC_OUTPUT:
118 ret_irq = IRQ_PIXC_OUT;
119 break;
120 case CH_SPORT2_RX:
121 ret_irq = IRQ_SPORT2_RX;
122 break;
123 case CH_SPORT2_TX:
124 ret_irq = IRQ_SPORT2_TX;
125 break;
126 case CH_SPORT3_RX:
127 ret_irq = IRQ_SPORT3_RX;
128 break;
129 case CH_SPORT3_TX:
130 ret_irq = IRQ_SPORT3_TX;
131 break;
132 case CH_SDH:
133 ret_irq = IRQ_SDH;
134 break;
135 case CH_SPI2:
136 ret_irq = IRQ_SPI2;
137 break;
138 case CH_MEM_STREAM0_SRC:
139 case CH_MEM_STREAM0_DEST:
140 ret_irq = IRQ_MDMAS0;
141 break;
142 case CH_MEM_STREAM1_SRC:
143 case CH_MEM_STREAM1_DEST:
144 ret_irq = IRQ_MDMAS1;
145 break;
146 case CH_MEM_STREAM2_SRC:
147 case CH_MEM_STREAM2_DEST:
148 ret_irq = IRQ_MDMAS2;
149 break;
150 case CH_MEM_STREAM3_SRC:
151 case CH_MEM_STREAM3_DEST:
152 ret_irq = IRQ_MDMAS3;
153 break;
154 }
155 return ret_irq;
156}
diff --git a/arch/blackfin/mach-bf548/gpio.c b/arch/blackfin/mach-bf548/gpio.c
new file mode 100644
index 000000000000..0da5f0003b8c
--- /dev/null
+++ b/arch/blackfin/mach-bf548/gpio.c
@@ -0,0 +1,323 @@
1/*
2 * File: arch/blackfin/mach-bf548/gpio.c
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description: GPIO Abstraction Layer
8 *
9 * Modified:
10 * Copyright 2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <linux/err.h>
32#include <asm/blackfin.h>
33#include <asm/gpio.h>
34#include <asm/portmux.h>
35#include <linux/irq.h>
36
37static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
38 (struct gpio_port_t *)PORTA_FER,
39 (struct gpio_port_t *)PORTB_FER,
40 (struct gpio_port_t *)PORTC_FER,
41 (struct gpio_port_t *)PORTD_FER,
42 (struct gpio_port_t *)PORTE_FER,
43 (struct gpio_port_t *)PORTF_FER,
44 (struct gpio_port_t *)PORTG_FER,
45 (struct gpio_port_t *)PORTH_FER,
46 (struct gpio_port_t *)PORTI_FER,
47 (struct gpio_port_t *)PORTJ_FER,
48};
49
50static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
51static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
52
53inline int check_gpio(unsigned short gpio)
54{
55 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
56 || gpio == GPIO_PH14 || gpio == GPIO_PH15
57 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15
58 || gpio > MAX_BLACKFIN_GPIOS)
59 return -EINVAL;
60 return 0;
61}
62
63inline void portmux_setup(unsigned short portno, unsigned short function)
64{
65 u32 pmux;
66
67 pmux = gpio_array[gpio_bank(portno)]->port_mux;
68
69 pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
70 pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
71
72 gpio_array[gpio_bank(portno)]->port_mux = pmux;
73
74}
75
76inline u16 get_portmux(unsigned short portno)
77{
78 u32 pmux;
79
80 pmux = gpio_array[gpio_bank(portno)]->port_mux;
81
82 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
83
84}
85
86static void port_setup(unsigned short gpio, unsigned short usage)
87{
88 if (usage == GPIO_USAGE) {
89 if (gpio_array[gpio_bank(gpio)]->port_fer & gpio_bit(gpio))
90 printk(KERN_WARNING
91 "bfin-gpio: Possible Conflict with Peripheral "
92 "usage and GPIO %d detected!\n", gpio);
93 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
94 } else
95 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
96 SSYNC();
97}
98
99static int __init bfin_gpio_init(void)
100{
101 printk(KERN_INFO "Blackfin GPIO Controller\n");
102
103 return 0;
104}
105
106arch_initcall(bfin_gpio_init);
107
108int peripheral_request(unsigned short per, const char *label)
109{
110 unsigned long flags;
111 unsigned short ident = P_IDENT(per);
112
113 if (!(per & P_DEFINED))
114 return -ENODEV;
115
116 if (check_gpio(ident) < 0)
117 return -EINVAL;
118
119 local_irq_save(flags);
120
121 if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
122 printk(KERN_ERR
123 "%s: Peripheral %d is already reserved as GPIO!\n",
124 __FUNCTION__, per);
125 dump_stack();
126 local_irq_restore(flags);
127 return -EBUSY;
128 }
129
130 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
131
132 u16 funct = get_portmux(ident);
133
134 if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
135 printk(KERN_ERR
136 "%s: Peripheral %d is already reserved!\n",
137 __FUNCTION__, per);
138 dump_stack();
139 local_irq_restore(flags);
140 return -EBUSY;
141 }
142 }
143
144 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
145
146 portmux_setup(ident, P_FUNCT2MUX(per));
147 port_setup(ident, PERIPHERAL_USAGE);
148
149 local_irq_restore(flags);
150
151 return 0;
152}
153EXPORT_SYMBOL(peripheral_request);
154
155int peripheral_request_list(unsigned short per[], const char *label)
156{
157
158 u16 cnt;
159 int ret;
160
161 for (cnt = 0; per[cnt] != 0; cnt++) {
162 ret = peripheral_request(per[cnt], label);
163 if (ret < 0)
164 return ret;
165 }
166
167 return 0;
168}
169EXPORT_SYMBOL(peripheral_request_list);
170
171void peripheral_free(unsigned short per)
172{
173 unsigned long flags;
174 unsigned short ident = P_IDENT(per);
175
176 if (!(per & P_DEFINED))
177 return;
178
179 if (check_gpio(ident) < 0)
180 return;
181
182 local_irq_save(flags);
183
184 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
185 printk(KERN_ERR "bfin-gpio: Peripheral %d wasn't reserved!\n", per);
186 dump_stack();
187 local_irq_restore(flags);
188 return;
189 }
190
191 if (!(per & P_MAYSHARE)) {
192 port_setup(ident, GPIO_USAGE);
193 }
194
195 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
196
197 local_irq_restore(flags);
198}
199EXPORT_SYMBOL(peripheral_free);
200
201void peripheral_free_list(unsigned short per[])
202{
203 u16 cnt;
204
205 for (cnt = 0; per[cnt] != 0; cnt++) {
206 peripheral_free(per[cnt]);
207 }
208
209}
210EXPORT_SYMBOL(peripheral_free_list);
211
212/***********************************************************
213*
214* FUNCTIONS: Blackfin GPIO Driver
215*
216* INPUTS/OUTPUTS:
217* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
218*
219*
220* DESCRIPTION: Blackfin GPIO Driver API
221*
222* CAUTION:
223*************************************************************
224* MODIFICATION HISTORY :
225**************************************************************/
226
227int gpio_request(unsigned short gpio, const char *label)
228{
229 unsigned long flags;
230
231 if (check_gpio(gpio) < 0)
232 return -EINVAL;
233
234 local_irq_save(flags);
235
236 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
237 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio);
238 dump_stack();
239 local_irq_restore(flags);
240 return -EBUSY;
241 }
242
243 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
244 printk(KERN_ERR
245 "bfin-gpio: GPIO %d is already reserved as Peripheral!\n", gpio);
246 dump_stack();
247 local_irq_restore(flags);
248 return -EBUSY;
249 }
250
251 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
252
253 local_irq_restore(flags);
254
255 port_setup(gpio, GPIO_USAGE);
256
257 return 0;
258}
259EXPORT_SYMBOL(gpio_request);
260
261void gpio_free(unsigned short gpio)
262{
263 unsigned long flags;
264
265 if (check_gpio(gpio) < 0)
266 return;
267
268 local_irq_save(flags);
269
270 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
271 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
272 dump_stack();
273 local_irq_restore(flags);
274 return;
275 }
276
277 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
278
279 local_irq_restore(flags);
280}
281EXPORT_SYMBOL(gpio_free);
282
283void gpio_direction_input(unsigned short gpio)
284{
285 unsigned long flags;
286
287 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
288
289 local_irq_save(flags);
290 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
291 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
292 local_irq_restore(flags);
293}
294EXPORT_SYMBOL(gpio_direction_input);
295
296void gpio_direction_output(unsigned short gpio)
297{
298 unsigned long flags;
299
300 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
301
302 local_irq_save(flags);
303 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
304 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
305 local_irq_restore(flags);
306}
307EXPORT_SYMBOL(gpio_direction_output);
308
309void gpio_set_value(unsigned short gpio, unsigned short arg)
310{
311 if (arg)
312 gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
313 else
314 gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
315
316}
317EXPORT_SYMBOL(gpio_set_value);
318
319unsigned short gpio_get_value(unsigned short gpio)
320{
321 return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
322}
323EXPORT_SYMBOL(gpio_get_value);
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
new file mode 100644
index 000000000000..06751ae8b857
--- /dev/null
+++ b/arch/blackfin/mach-bf548/head.S
@@ -0,0 +1,512 @@
1/*
2 * File: arch/blackfin/mach-bf548/head.S
3 * Based on: arch/blackfin/mach-bf537/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5 *
6 * Created: 1998
7 * Description: Startup code for Blackfin BF548
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <asm/blackfin.h>
32#include <asm/trace.h>
33#if CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach/mem_init.h>
35#endif
36
37.global __rambase
38.global __ramstart
39.global __ramend
40.extern ___bss_stop
41.extern ___bss_start
42.extern _bf53x_relocate_l1_mem
43
44#define INITIAL_STACK 0xFFB01000
45
46.text
47
48ENTRY(__start)
49ENTRY(__stext)
50 /* R0: argument of command line string, passed from uboot, save it */
51 R7 = R0;
52 /* Set the SYSCFG register */
53 R0 = 0x36;
54 SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
55 R0 = 0;
56
57 /* Clear Out All the data and pointer Registers*/
58 R1 = R0;
59 R2 = R0;
60 R3 = R0;
61 R4 = R0;
62 R5 = R0;
63 R6 = R0;
64
65 P0 = R0;
66 P1 = R0;
67 P2 = R0;
68 P3 = R0;
69 P4 = R0;
70 P5 = R0;
71
72 LC0 = r0;
73 LC1 = r0;
74 L0 = r0;
75 L1 = r0;
76 L2 = r0;
77 L3 = r0;
78
79 /* Clear Out All the DAG Registers*/
80 B0 = r0;
81 B1 = r0;
82 B2 = r0;
83 B3 = r0;
84
85 I0 = r0;
86 I1 = r0;
87 I2 = r0;
88 I3 = r0;
89
90 M0 = r0;
91 M1 = r0;
92 M2 = r0;
93 M3 = r0;
94
95 trace_buffer_start(p0,r0);
96 P0 = R1;
97 R0 = R1;
98
99 /* Turn off the icache */
100 p0.l = (IMEM_CONTROL & 0xFFFF);
101 p0.h = (IMEM_CONTROL >> 16);
102 R1 = [p0];
103 R0 = ~ENICPLB;
104 R0 = R0 & R1;
105 [p0] = R0;
106 SSYNC;
107
108 /* Turn off the dcache */
109 p0.l = (DMEM_CONTROL & 0xFFFF);
110 p0.h = (DMEM_CONTROL >> 16);
111 R1 = [p0];
112 R0 = ~ENDCPLB;
113 R0 = R0 & R1;
114 [p0] = R0;
115 SSYNC;
116
117 /* Initialize stack pointer */
118 SP.L = LO(INITIAL_STACK);
119 SP.H = HI(INITIAL_STACK);
120 FP = SP;
121 USP = SP;
122
123 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
124 call _bf53x_relocate_l1_mem;
125#if CONFIG_BFIN_KERNEL_CLOCK
126 call _start_dma_code;
127#endif
128 /* Code for initializing Async memory banks */
129
130 p2.h = hi(EBIU_AMBCTL1);
131 p2.l = lo(EBIU_AMBCTL1);
132 r0.h = hi(AMBCTL1VAL);
133 r0.l = lo(AMBCTL1VAL);
134 [p2] = r0;
135 ssync;
136
137 p2.h = hi(EBIU_AMBCTL0);
138 p2.l = lo(EBIU_AMBCTL0);
139 r0.h = hi(AMBCTL0VAL);
140 r0.l = lo(AMBCTL0VAL);
141 [p2] = r0;
142 ssync;
143
144 p2.h = hi(EBIU_AMGCTL);
145 p2.l = lo(EBIU_AMGCTL);
146 r0 = AMGCTLVAL;
147 w[p2] = r0;
148 ssync;
149
150 /* This section keeps the processor in supervisor mode
151 * during kernel boot. Switches to user mode at end of boot.
152 * See page 3-9 of Hardware Reference manual for documentation.
153 */
154
155 /* EVT15 = _real_start */
156
157 p0.l = lo(EVT15);
158 p0.h = hi(EVT15);
159 p1.l = _real_start;
160 p1.h = _real_start;
161 [p0] = p1;
162 csync;
163
164 p0.l = lo(IMASK);
165 p0.h = hi(IMASK);
166 p1.l = IMASK_IVG15;
167 p1.h = 0x0;
168 [p0] = p1;
169 csync;
170
171 raise 15;
172 p0.l = .LWAIT_HERE;
173 p0.h = .LWAIT_HERE;
174 reti = p0;
175#if defined (ANOMALY_05000281)
176 nop;
177 nop;
178 nop;
179#endif
180 rti;
181
182.LWAIT_HERE:
183 jump .LWAIT_HERE;
184
185ENTRY(_real_start)
186 [ -- sp ] = reti;
187 p0.l = lo(WDOG_CTL);
188 p0.h = hi(WDOG_CTL);
189 r0 = 0xAD6(z);
190 w[p0] = r0; /* watchdog off for now */
191 ssync;
192
193 /* Code update for BSS size == 0
194 * Zero out the bss region.
195 */
196
197 p1.l = ___bss_start;
198 p1.h = ___bss_start;
199 p2.l = ___bss_stop;
200 p2.h = ___bss_stop;
201 r0 = 0;
202 p2 -= p1;
203 lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
204.L_clear_bss:
205 B[p1++] = r0;
206
207 /* In case there is a NULL pointer reference
208 * Zero out region before stext
209 */
210
211 p1.l = 0x0;
212 p1.h = 0x0;
213 r0.l = __stext;
214 r0.h = __stext;
215 r0 = r0 >> 1;
216 p2 = r0;
217 r0 = 0;
218 lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
219.L_clear_zero:
220 W[p1++] = r0;
221
222 /* pass the uboot arguments to the global value command line */
223 R0 = R7;
224 call _cmdline_init;
225
226 p1.l = __rambase;
227 p1.h = __rambase;
228 r0.l = __sdata;
229 r0.h = __sdata;
230 [p1] = r0;
231
232 p1.l = __ramstart;
233 p1.h = __ramstart;
234 p3.l = ___bss_stop;
235 p3.h = ___bss_stop;
236
237 r1 = p3;
238 [p1] = r1;
239
240
241 /*
242 * load the current thread pointer and stack
243 */
244 r1.l = _init_thread_union;
245 r1.h = _init_thread_union;
246
247 r2.l = 0x2000;
248 r2.h = 0x0000;
249 r1 = r1 + r2;
250 sp = r1;
251 usp = sp;
252 fp = sp;
253 call _start_kernel;
254.L_exit:
255 jump.s .L_exit;
256
257.section .l1.text
258#if CONFIG_BFIN_KERNEL_CLOCK
259ENTRY(_start_dma_code)
260
261 /* Enable PHY CLK buffer output */
262 p0.h = hi(VR_CTL);
263 p0.l = lo(VR_CTL);
264 r0.l = w[p0];
265 bitset(r0, 14);
266 w[p0] = r0.l;
267 ssync;
268
269 p0.h = hi(SIC_IWR);
270 p0.l = lo(SIC_IWR);
271 r0.l = 0x1;
272 r0.h = 0x0;
273 [p0] = r0;
274 SSYNC;
275
276 /*
277 * Set PLL_CTL
278 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
279 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
280 * - [7] = output delay (add 200ps of delay to mem signals)
281 * - [6] = input delay (add 200ps of input delay to mem signals)
282 * - [5] = PDWN : 1=All Clocks off
283 * - [3] = STOPCK : 1=Core Clock off
284 * - [1] = PLL_OFF : 1=Disable Power to PLL
285 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
286 * all other bits set to zero
287 */
288
289 p0.h = hi(PLL_LOCKCNT);
290 p0.l = lo(PLL_LOCKCNT);
291 r0 = 0x300(Z);
292 w[p0] = r0.l;
293 ssync;
294
295 P2.H = hi(EBIU_SDGCTL);
296 P2.L = lo(EBIU_SDGCTL);
297 R0 = [P2];
298 BITSET (R0, 24);
299 [P2] = R0;
300 SSYNC;
301
302 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
303 r0 = r0 << 9; /* Shift it over, */
304 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
305 r0 = r1 | r0;
306 r1 = PLL_BYPASS; /* Bypass the PLL? */
307 r1 = r1 << 8; /* Shift it over */
308 r0 = r1 | r0; /* add them all together */
309
310 p0.h = hi(PLL_CTL);
311 p0.l = lo(PLL_CTL); /* Load the address */
312 cli r2; /* Disable interrupts */
313 ssync;
314 w[p0] = r0.l; /* Set the value */
315 idle; /* Wait for the PLL to stablize */
316 sti r2; /* Enable interrupts */
317
318.Lcheck_again:
319 p0.h = hi(PLL_STAT);
320 p0.l = lo(PLL_STAT);
321 R0 = W[P0](Z);
322 CC = BITTST(R0,5);
323 if ! CC jump .Lcheck_again;
324
325 /* Configure SCLK & CCLK Dividers */
326 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
327 p0.h = hi(PLL_DIV);
328 p0.l = lo(PLL_DIV);
329 w[p0] = r0.l;
330 ssync;
331
332 p0.l = lo(EBIU_SDRRC);
333 p0.h = hi(EBIU_SDRRC);
334 r0 = mem_SDRRC;
335 w[p0] = r0.l;
336 ssync;
337
338 p0.l = (EBIU_SDBCTL & 0xFFFF);
339 p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
340 r0 = mem_SDBCTL;
341 w[p0] = r0.l;
342 ssync;
343
344 P2.H = hi(EBIU_SDGCTL);
345 P2.L = lo(EBIU_SDGCTL);
346 R0 = [P2];
347 BITCLR (R0, 24);
348 p0.h = hi(EBIU_SDSTAT);
349 p0.l = lo(EBIU_SDSTAT);
350 r2.l = w[p0];
351 cc = bittst(r2,3);
352 if !cc jump .Lskip;
353 NOP;
354 BITSET (R0, 23);
355.Lskip:
356 [P2] = R0;
357 SSYNC;
358
359 R0.L = lo(mem_SDGCTL);
360 R0.H = hi(mem_SDGCTL);
361 R1 = [p2];
362 R1 = R1 | R0;
363 [P2] = R1;
364 SSYNC;
365
366 p0.h = hi(SIC_IWR);
367 p0.l = lo(SIC_IWR);
368 r0.l = lo(IWR_ENABLE_ALL);
369 r0.h = hi(IWR_ENABLE_ALL);
370 [p0] = r0;
371 SSYNC;
372
373 RTS;
374#endif /* CONFIG_BFIN_KERNEL_CLOCK */
375
376ENTRY(_bfin_reset)
377 /* No more interrupts to be handled*/
378 CLI R6;
379 SSYNC;
380
381#if defined(CONFIG_MTD_M25P80)
382/*
383 * The following code fix the SPI flash reboot issue,
384 * /CS signal of the chip which is using PF10 return to GPIO mode
385 */
386 p0.h = hi(PORTF_FER);
387 p0.l = lo(PORTF_FER);
388 r0.l = 0x0000;
389 w[p0] = r0.l;
390 SSYNC;
391
392/* /CS return to high */
393 p0.h = hi(PORTFIO);
394 p0.l = lo(PORTFIO);
395 r0.l = 0xFFFF;
396 w[p0] = r0.l;
397 SSYNC;
398
399/* Delay some time, This is necessary */
400 r1.h = 0;
401 r1.l = 0x400;
402 p1 = r1;
403 lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1;
404_delay_lab1:
405 r0.h = 0;
406 r0.l = 0x8000;
407 p0 = r0;
408 lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0;
409_delay_lab0:
410 nop;
411_delay_lab0_end:
412 nop;
413_delay_lab1_end:
414 nop;
415#endif
416
417 /* Clear the bits 13-15 in SWRST if they werent cleared */
418 p0.h = hi(SWRST);
419 p0.l = lo(SWRST);
420 csync;
421 r0.l = w[p0];
422
423 /* Clear the IMASK register */
424 p0.h = hi(IMASK);
425 p0.l = lo(IMASK);
426 r0 = 0x0;
427 [p0] = r0;
428
429 /* Clear the ILAT register */
430 p0.h = hi(ILAT);
431 p0.l = lo(ILAT);
432 r0 = [p0];
433 [p0] = r0;
434 SSYNC;
435
436 /* Disable the WDOG TIMER */
437 p0.h = hi(WDOG_CTL);
438 p0.l = lo(WDOG_CTL);
439 r0.l = 0xAD6;
440 w[p0] = r0.l;
441 SSYNC;
442
443 /* Clear the sticky bit incase it is already set */
444 p0.h = hi(WDOG_CTL);
445 p0.l = lo(WDOG_CTL);
446 r0.l = 0x8AD6;
447 w[p0] = r0.l;
448 SSYNC;
449
450 /* Program the count value */
451 R0.l = 0x100;
452 R0.h = 0x0;
453 P0.h = hi(WDOG_CNT);
454 P0.l = lo(WDOG_CNT);
455 [P0] = R0;
456 SSYNC;
457
458 /* Program WDOG_STAT if necessary */
459 P0.h = hi(WDOG_CTL);
460 P0.l = lo(WDOG_CTL);
461 R0 = W[P0](Z);
462 CC = BITTST(R0,1);
463 if !CC JUMP .LWRITESTAT;
464 CC = BITTST(R0,2);
465 if !CC JUMP .LWRITESTAT;
466 JUMP .LSKIP_WRITE;
467
468.LWRITESTAT:
469 /* When watch dog timer is enabled,
470 * a write to STAT will load the contents of CNT to STAT
471 */
472 R0 = 0x0000(z);
473 P0.h = hi(WDOG_STAT);
474 P0.l = lo(WDOG_STAT)
475 [P0] = R0;
476 SSYNC;
477
478.LSKIP_WRITE:
479 /* Enable the reset event */
480 P0.h = hi(WDOG_CTL);
481 P0.l = lo(WDOG_CTL);
482 R0 = W[P0](Z);
483 BITCLR(R0,1);
484 BITCLR(R0,2);
485 W[P0] = R0.L;
486 SSYNC;
487 NOP;
488
489 /* Enable the wdog counter */
490 R0 = W[P0](Z);
491 BITCLR(R0,4);
492 W[P0] = R0.L;
493 SSYNC;
494
495 IDLE;
496
497 RTS;
498
499.data
500
501/*
502 * Set up the usable of RAM stuff. Size of RAM is determined then
503 * an initial stack set up at the end.
504 */
505
506.align 4
507__rambase:
508.long 0
509__ramstart:
510.long 0
511__ramend:
512.long 0
diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c
new file mode 100644
index 000000000000..cb0ebac53c79
--- /dev/null
+++ b/arch/blackfin/mach-bf548/ints-priority.c
@@ -0,0 +1,137 @@
1/*
2 * File: arch/blackfin/mach-bf537/ints-priority.c
3 * Based on: arch/blackfin/mach-bf533/ints-priority.c
4 * Author: Michael Hennerich
5 *
6 * Created:
7 * Description: Set up the interupt priorities
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <linux/irq.h>
32#include <asm/blackfin.h>
33
34void program_IAR(void)
35{
36 /* Program the IAR0 Register with the configured priority */
37 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
38 ((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) |
39 ((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) |
40 ((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) |
41 ((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) |
42 ((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) |
43 ((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) |
44 ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
45
46 bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) |
47 ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
48 ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
49 ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
50 ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
51 ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
52 ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
53 ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
54
55 bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
56 ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
57 ((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) |
58 ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
59 ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
60 ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
61 ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS));
62
63 bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
64 ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
65 ((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) |
66 ((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) |
67 ((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) |
68 ((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) |
69 ((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) |
70 ((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS));
71
72 bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) |
73 ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
74 ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
75 ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
76 ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
77 ((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) |
78 ((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) |
79 ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
80
81 bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
82 ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
83 ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
84 ((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) |
85 ((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) |
86 ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
87 ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
88 ((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS));
89
90 bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) |
91 ((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) |
92 ((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) |
93 ((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) |
94 ((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) |
95 ((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) |
96 ((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) |
97 ((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS));
98
99 bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) |
100 ((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) |
101 ((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) |
102 ((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) |
103 ((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) |
104 ((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) |
105 ((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS));
106
107 bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) |
108 ((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) |
109 ((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) |
110 ((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) |
111 ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
112 ((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) |
113 ((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) |
114 ((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS));
115
116 bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) |
117 ((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) |
118 ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
119 ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
120 ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
121 ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) |
122 ((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS));
123
124 bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
125 ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS));
126
127 bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
128 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
129 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
130 ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
131 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
132 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
133 ((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) |
134 ((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS));
135
136 SSYNC();
137}
diff --git a/arch/blackfin/mach-bf561/Makefile b/arch/blackfin/mach-bf561/Makefile
index 57f475a55161..f39235a55783 100644
--- a/arch/blackfin/mach-bf561/Makefile
+++ b/arch/blackfin/mach-bf561/Makefile
@@ -4,6 +4,6 @@
4 4
5extra-y := head.o 5extra-y := head.o
6 6
7obj-y := ints-priority.o 7obj-y := ints-priority.o dma.o
8 8
9obj-$(CONFIG_BF561_COREB) += coreb.o 9obj-$(CONFIG_BF561_COREB) += coreb.o
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 3dc5c042048c..5b2b544529a1 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -34,7 +34,7 @@
34#include <linux/spi/spi.h> 34#include <linux/spi/spi.h>
35#include <linux/spi/flash.h> 35#include <linux/spi/flash.h>
36#include <linux/usb_isp1362.h> 36#include <linux/usb_isp1362.h>
37#include <asm/irq.h> 37#include <linux/irq.h>
38#include <asm/bfin5xx_spi.h> 38#include <asm/bfin5xx_spi.h>
39 39
40/* 40/*
@@ -52,11 +52,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
52 .size = 0x00020000, 52 .size = 0x00020000,
53 .offset = 0, 53 .offset = 0,
54 .mask_flags = MTD_CAP_ROM 54 .mask_flags = MTD_CAP_ROM
55 },{ 55 }, {
56 .name = "kernel", 56 .name = "kernel",
57 .size = 0xe0000, 57 .size = 0xe0000,
58 .offset = 0x20000 58 .offset = 0x20000
59 },{ 59 }, {
60 .name = "file system", 60 .name = "file system",
61 .size = 0x700000, 61 .size = 0x700000,
62 .offset = 0x00100000, 62 .offset = 0x00100000,
@@ -186,7 +186,7 @@ static struct resource smc91x_resources[] = {
186 .start = 0x28000300, 186 .start = 0x28000300,
187 .end = 0x28000300 + 16, 187 .end = 0x28000300 + 16,
188 .flags = IORESOURCE_MEM, 188 .flags = IORESOURCE_MEM,
189 },{ 189 }, {
190 .start = IRQ_PF0, 190 .start = IRQ_PF0,
191 .end = IRQ_PF0, 191 .end = IRQ_PF0,
192 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 192 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -206,11 +206,11 @@ static struct resource isp1362_hcd_resources[] = {
206 .start = 0x24008000, 206 .start = 0x24008000,
207 .end = 0x24008000, 207 .end = 0x24008000,
208 .flags = IORESOURCE_MEM, 208 .flags = IORESOURCE_MEM,
209 },{ 209 }, {
210 .start = 0x24008004, 210 .start = 0x24008004,
211 .end = 0x24008004, 211 .end = 0x24008004,
212 .flags = IORESOURCE_MEM, 212 .flags = IORESOURCE_MEM,
213 },{ 213 }, {
214 .start = IRQ_PF47, 214 .start = IRQ_PF47,
215 .end = IRQ_PF47, 215 .end = IRQ_PF47,
216 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 216 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -241,25 +241,25 @@ static struct platform_device isp1362_hcd_device = {
241 241
242#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 242#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
243static struct resource bfin_uart_resources[] = { 243static struct resource bfin_uart_resources[] = {
244 { 244 {
245 .start = 0xFFC00400, 245 .start = 0xFFC00400,
246 .end = 0xFFC004FF, 246 .end = 0xFFC004FF,
247 .flags = IORESOURCE_MEM, 247 .flags = IORESOURCE_MEM,
248 }, 248 },
249}; 249};
250 250
251static struct platform_device bfin_uart_device = { 251static struct platform_device bfin_uart_device = {
252 .name = "bfin-uart", 252 .name = "bfin-uart",
253 .id = 1, 253 .id = 1,
254 .num_resources = ARRAY_SIZE(bfin_uart_resources), 254 .num_resources = ARRAY_SIZE(bfin_uart_resources),
255 .resource = bfin_uart_resources, 255 .resource = bfin_uart_resources,
256}; 256};
257#endif 257#endif
258 258
259static struct platform_device *cm_bf561_devices[] __initdata = { 259static struct platform_device *cm_bf561_devices[] __initdata = {
260 260
261#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 261#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
262 &bfin_uart_device, 262 &bfin_uart_device,
263#endif 263#endif
264 264
265#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 265#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 9720b5c307ab..724191da20a2 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -30,10 +30,9 @@
30#include <linux/device.h> 30#include <linux/device.h>
31#include <linux/platform_device.h> 31#include <linux/platform_device.h>
32#include <linux/spi/spi.h> 32#include <linux/spi/spi.h>
33#include <asm/irq.h>
34#include <asm/bfin5xx_spi.h>
35#include <linux/interrupt.h>
36#include <linux/irq.h> 33#include <linux/irq.h>
34#include <linux/interrupt.h>
35#include <asm/bfin5xx_spi.h>
37 36
38/* 37/*
39 * Name the Board for the /proc/cpuinfo 38 * Name the Board for the /proc/cpuinfo
@@ -45,13 +44,13 @@ char *bfin_board_name = "ADDS-BF561-EZKIT";
45 44
46#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) 45#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
47static struct resource bfin_isp1761_resources[] = { 46static struct resource bfin_isp1761_resources[] = {
48 [0] = { 47 {
49 .name = "isp1761-regs", 48 .name = "isp1761-regs",
50 .start = ISP1761_BASE + 0x00000000, 49 .start = ISP1761_BASE + 0x00000000,
51 .end = ISP1761_BASE + 0x000fffff, 50 .end = ISP1761_BASE + 0x000fffff,
52 .flags = IORESOURCE_MEM, 51 .flags = IORESOURCE_MEM,
53 }, 52 },
54 [1] = { 53 {
55 .start = ISP1761_IRQ, 54 .start = ISP1761_IRQ,
56 .end = ISP1761_IRQ, 55 .end = ISP1761_IRQ,
57 .flags = IORESOURCE_IRQ, 56 .flags = IORESOURCE_IRQ,
@@ -71,7 +70,7 @@ static struct platform_device *bfin_isp1761_devices[] = {
71 70
72int __init bfin_isp1761_init(void) 71int __init bfin_isp1761_init(void)
73{ 72{
74 unsigned int num_devices=ARRAY_SIZE(bfin_isp1761_devices); 73 unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
75 74
76 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); 75 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
77 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); 76 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
@@ -98,7 +97,7 @@ static struct resource smc91x_resources[] = {
98 .start = 0x2C010300, 97 .start = 0x2C010300,
99 .end = 0x2C010300 + 16, 98 .end = 0x2C010300 + 16,
100 .flags = IORESOURCE_MEM, 99 .flags = IORESOURCE_MEM,
101 },{ 100 }, {
102 101
103 .start = IRQ_PF9, 102 .start = IRQ_PF9,
104 .end = IRQ_PF9, 103 .end = IRQ_PF9,
@@ -116,18 +115,18 @@ static struct platform_device smc91x_device = {
116 115
117#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 116#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
118static struct resource bfin_uart_resources[] = { 117static struct resource bfin_uart_resources[] = {
119 { 118 {
120 .start = 0xFFC00400, 119 .start = 0xFFC00400,
121 .end = 0xFFC004FF, 120 .end = 0xFFC004FF,
122 .flags = IORESOURCE_MEM, 121 .flags = IORESOURCE_MEM,
123 }, 122 },
124}; 123};
125 124
126static struct platform_device bfin_uart_device = { 125static struct platform_device bfin_uart_device = {
127 .name = "bfin-uart", 126 .name = "bfin-uart",
128 .id = 1, 127 .id = 1,
129 .num_resources = ARRAY_SIZE(bfin_uart_resources), 128 .num_resources = ARRAY_SIZE(bfin_uart_resources),
130 .resource = bfin_uart_resources, 129 .resource = bfin_uart_resources,
131}; 130};
132#endif 131#endif
133 132
@@ -176,7 +175,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
176 &spi_bfin_master_device, 175 &spi_bfin_master_device,
177#endif 176#endif
178#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 177#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
179 &bfin_uart_device, 178 &bfin_uart_device,
180#endif 179#endif
181}; 180};
182 181
diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c
index 585ecdd2f6a5..4dfea5da674c 100644
--- a/arch/blackfin/mach-bf561/boards/generic_board.c
+++ b/arch/blackfin/mach-bf561/boards/generic_board.c
@@ -30,7 +30,7 @@
30 30
31#include <linux/device.h> 31#include <linux/device.h>
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <asm/irq.h> 33#include <linux/irq.h>
34 34
35char *bfin_board_name = "UNKNOWN BOARD"; 35char *bfin_board_name = "UNKNOWN BOARD";
36 36
@@ -43,11 +43,11 @@ static struct resource smc91x_resources[] = {
43 .start = 0x2C010300, 43 .start = 0x2C010300,
44 .end = 0x2C010300 + 16, 44 .end = 0x2C010300 + 16,
45 .flags = IORESOURCE_MEM, 45 .flags = IORESOURCE_MEM,
46 },{ 46 }, {
47 .start = IRQ_PROG_INTB, 47 .start = IRQ_PROG_INTB,
48 .end = IRQ_PROG_INTB, 48 .end = IRQ_PROG_INTB,
49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
50 },{ 50 }, {
51 /* 51 /*
52 * denotes the flag pin and is used directly if 52 * denotes the flag pin and is used directly if
53 * CONFIG_IRQCHIP_DEMUX_GPIO is defined. 53 * CONFIG_IRQCHIP_DEMUX_GPIO is defined.
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
index db308c7ccabb..c442eb23db5e 100644
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ b/arch/blackfin/mach-bf561/boards/tepla.c
@@ -14,7 +14,7 @@
14 14
15#include <linux/device.h> 15#include <linux/device.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <asm/irq.h> 17#include <linux/irq.h>
18 18
19char *bfin_board_name = "Tepla-BF561"; 19char *bfin_board_name = "Tepla-BF561";
20 20
@@ -26,11 +26,11 @@ static struct resource smc91x_resources[] = {
26 .start = 0x2C000300, 26 .start = 0x2C000300,
27 .end = 0x2C000320, 27 .end = 0x2C000320,
28 .flags = IORESOURCE_MEM, 28 .flags = IORESOURCE_MEM,
29 },{ 29 }, {
30 .start = IRQ_PROG_INTB, 30 .start = IRQ_PROG_INTB,
31 .end = IRQ_PROG_INTB, 31 .end = IRQ_PROG_INTB,
32 .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL, 32 .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
33 },{ 33 }, {
34 /* 34 /*
35 * denotes the flag pin and is used directly if 35 * denotes the flag pin and is used directly if
36 * CONFIG_IRQCHIP_DEMUX_GPIO is defined. 36 * CONFIG_IRQCHIP_DEMUX_GPIO is defined.
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
index b28582fe083c..5d1d21b4c2a7 100644
--- a/arch/blackfin/mach-bf561/coreb.c
+++ b/arch/blackfin/mach-bf561/coreb.c
@@ -32,8 +32,8 @@
32#include <linux/device.h> 32#include <linux/device.h>
33#include <linux/ioport.h> 33#include <linux/ioport.h>
34#include <linux/module.h> 34#include <linux/module.h>
35#include <linux/uaccess.h>
35#include <asm/dma.h> 36#include <asm/dma.h>
36#include <asm/uaccess.h>
37 37
38#define MODULE_VER "v0.1" 38#define MODULE_VER "v0.1"
39 39
@@ -202,7 +202,7 @@ static int coreb_open(struct inode *inode, struct file *file)
202 spin_unlock_irq(&coreb_lock); 202 spin_unlock_irq(&coreb_lock);
203 return 0; 203 return 0;
204 204
205 out_busy: 205 out_busy:
206 spin_unlock_irq(&coreb_lock); 206 spin_unlock_irq(&coreb_lock);
207 return -EBUSY; 207 return -EBUSY;
208} 208}
@@ -365,19 +365,19 @@ int __init bf561_coreb_init(void)
365 printk(KERN_INFO "BF561 Core B driver %s initialized.\n", MODULE_VER); 365 printk(KERN_INFO "BF561 Core B driver %s initialized.\n", MODULE_VER);
366 return 0; 366 return 0;
367 367
368 release_dma_src: 368 release_dma_src:
369 free_dma(CH_MEM_STREAM2_SRC); 369 free_dma(CH_MEM_STREAM2_SRC);
370 release_dma_dest: 370 release_dma_dest:
371 free_dma(CH_MEM_STREAM2_DEST); 371 free_dma(CH_MEM_STREAM2_DEST);
372 release_data_a_sram: 372 release_data_a_sram:
373 release_mem_region(0xff400000, 0x8000); 373 release_mem_region(0xff400000, 0x8000);
374 release_data_b_sram: 374 release_data_b_sram:
375 release_mem_region(0xff500000, 0x8000); 375 release_mem_region(0xff500000, 0x8000);
376 release_instruction_b_sram: 376 release_instruction_b_sram:
377 release_mem_region(0xff610000, 0x4000); 377 release_mem_region(0xff610000, 0x4000);
378 release_instruction_a_sram: 378 release_instruction_a_sram:
379 release_mem_region(0xff600000, 0x4000); 379 release_mem_region(0xff600000, 0x4000);
380 exit: 380 exit:
381 return -ENOMEM; 381 return -ENOMEM;
382} 382}
383 383
diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c
new file mode 100644
index 000000000000..89c65bb0bed3
--- /dev/null
+++ b/arch/blackfin/mach-bf561/dma.c
@@ -0,0 +1,131 @@
1/*
2 * File: arch/blackfin/mach-bf561/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#include <asm/blackfin.h>
30#include <asm/dma.h>
31
32struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
33 (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
34 (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
35 (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
36 (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
37 (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
38 (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
39 (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
40 (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
41 (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
42 (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
43 (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
44 (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
45 (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
46 (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
47 (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
48 (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
49 (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
50 (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
51 (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
52 (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
53 (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
54 (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
55 (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
56 (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
57 (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
58 (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
59 (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
60 (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
61 (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
62 (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
63 (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
64 (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
65 (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
66 (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
67 (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
68 (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
69};
70
71int channel2irq(unsigned int channel)
72{
73 int ret_irq = -1;
74
75 switch (channel) {
76 case CH_PPI0:
77 ret_irq = IRQ_PPI0;
78 break;
79 case CH_PPI1:
80 ret_irq = IRQ_PPI1;
81 break;
82 case CH_SPORT0_RX:
83 ret_irq = IRQ_SPORT0_RX;
84 break;
85 case CH_SPORT0_TX:
86 ret_irq = IRQ_SPORT0_TX;
87 break;
88 case CH_SPORT1_RX:
89 ret_irq = IRQ_SPORT1_RX;
90 break;
91 case CH_SPORT1_TX:
92 ret_irq = IRQ_SPORT1_TX;
93 break;
94 case CH_SPI:
95 ret_irq = IRQ_SPI;
96 break;
97 case CH_UART_RX:
98 ret_irq = IRQ_UART_RX;
99 break;
100 case CH_UART_TX:
101 ret_irq = IRQ_UART_TX;
102 break;
103
104 case CH_MEM_STREAM0_SRC:
105 case CH_MEM_STREAM0_DEST:
106 ret_irq = IRQ_MEM_DMA0;
107 break;
108 case CH_MEM_STREAM1_SRC:
109 case CH_MEM_STREAM1_DEST:
110 ret_irq = IRQ_MEM_DMA1;
111 break;
112 case CH_MEM_STREAM2_SRC:
113 case CH_MEM_STREAM2_DEST:
114 ret_irq = IRQ_MEM_DMA2;
115 break;
116 case CH_MEM_STREAM3_SRC:
117 case CH_MEM_STREAM3_DEST:
118 ret_irq = IRQ_MEM_DMA3;
119 break;
120
121 case CH_IMEM_STREAM0_SRC:
122 case CH_IMEM_STREAM0_DEST:
123 ret_irq = IRQ_IMEM_DMA0;
124 break;
125 case CH_IMEM_STREAM1_SRC:
126 case CH_IMEM_STREAM1_DEST:
127 ret_irq = IRQ_IMEM_DMA1;
128 break;
129 }
130 return ret_irq;
131}
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 31cbc75c85cf..2f08bcb2dded 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -30,6 +30,8 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h>
34
33#if CONFIG_BFIN_KERNEL_CLOCK 35#if CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach/mem_init.h> 36#include <asm/mach/mem_init.h>
35#endif 37#endif
@@ -93,6 +95,10 @@ ENTRY(__start)
93 M2 = r0; 95 M2 = r0;
94 M3 = r0; 96 M3 = r0;
95 97
98 trace_buffer_start(p0,r0);
99 P0 = R1;
100 R0 = R1;
101
96 /* Turn off the icache */ 102 /* Turn off the icache */
97 p0.l = (IMEM_CONTROL & 0xFFFF); 103 p0.l = (IMEM_CONTROL & 0xFFFF);
98 p0.h = (IMEM_CONTROL >> 16); 104 p0.h = (IMEM_CONTROL >> 16);
diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c
index 86e3b0ee93f4..09b541b0f7c2 100644
--- a/arch/blackfin/mach-bf561/ints-priority.c
+++ b/arch/blackfin/mach-bf561/ints-priority.c
@@ -28,8 +28,8 @@
28 */ 28 */
29 29
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/irq.h>
31#include <asm/blackfin.h> 32#include <asm/blackfin.h>
32#include <asm/irq.h>
33 33
34void program_IAR(void) 34void program_IAR(void)
35{ 35{
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index d3a49073d196..0279ede70392 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -4,9 +4,9 @@
4 4
5obj-y := \ 5obj-y := \
6 cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \ 6 cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \
7 interrupt.o lock.o dpmc.o irqpanic.o 7 interrupt.o lock.o irqpanic.o
8 8
9obj-$(CONFIG_CPLB_INFO) += cplbinfo.o 9obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
10obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o 10obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
11obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o 11obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o
12obj-$(CONFIG_PM) += pm.o 12obj-$(CONFIG_PM) += pm.o dpmc.o
diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S
index 7924a90d9658..9d475623b724 100644
--- a/arch/blackfin/mach-common/cacheinit.S
+++ b/arch/blackfin/mach-common/cacheinit.S
@@ -38,104 +38,37 @@
38 38
39.text 39.text
40 40
41#ifdef ANOMALY_05000125
41#if defined(CONFIG_BLKFIN_CACHE) 42#if defined(CONFIG_BLKFIN_CACHE)
42ENTRY(_bfin_icache_init) 43ENTRY(_bfin_write_IMEM_CONTROL)
43 44
44 /* Initialize Instruction CPLBS */
45
46 I0.L = (ICPLB_ADDR0 & 0xFFFF);
47 I0.H = (ICPLB_ADDR0 >> 16);
48
49 I1.L = (ICPLB_DATA0 & 0xFFFF);
50 I1.H = (ICPLB_DATA0 >> 16);
51
52 I2.L = _icplb_table;
53 I2.H = _icplb_table;
54
55 r1 = -1; /* end point comparison */
56 r3 = 15; /* max counter */
57
58/* read entries from table */
59
60.Lread_iaddr:
61 R0 = [I2++];
62 CC = R0 == R1;
63 IF CC JUMP .Lidone;
64 [I0++] = R0;
65
66.Lread_idata:
67 R2 = [I2++];
68 [I1++] = R2;
69 R3 = R3 + R1;
70 CC = R3 == R1;
71 IF !CC JUMP .Lread_iaddr;
72
73.Lidone:
74 /* Enable Instruction Cache */ 45 /* Enable Instruction Cache */
75 P0.l = (IMEM_CONTROL & 0xFFFF); 46 P0.l = (IMEM_CONTROL & 0xFFFF);
76 P0.h = (IMEM_CONTROL >> 16); 47 P0.h = (IMEM_CONTROL >> 16);
77 R1 = [P0];
78 R0 = (IMC | ENICPLB);
79 R0 = R0 | R1;
80 48
81 /* Anomaly 05000125 */ 49 /* Anomaly 05000125 */
82 CLI R2; 50 CLI R1;
83 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ 51 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
84 .align 8; 52 .align 8;
85 [P0] = R0; 53 [P0] = R0;
86 SSYNC; 54 SSYNC;
87 STI R2; 55 STI R1;
88 RTS; 56 RTS;
89 57
90ENDPROC(_bfin_icache_init) 58ENDPROC(_bfin_write_IMEM_CONTROL)
91#endif 59#endif
92 60
93#if defined(CONFIG_BLKFIN_DCACHE) 61#if defined(CONFIG_BLKFIN_DCACHE)
94ENTRY(_bfin_dcache_init) 62ENTRY(_bfin_write_DMEM_CONTROL)
95 63 CLI R1;
96 /* Initialize Data CPLBS */
97
98 I0.L = (DCPLB_ADDR0 & 0xFFFF);
99 I0.H = (DCPLB_ADDR0 >> 16);
100
101 I1.L = (DCPLB_DATA0 & 0xFFFF);
102 I1.H = (DCPLB_DATA0 >> 16);
103
104 I2.L = _dcplb_table;
105 I2.H = _dcplb_table;
106
107 R1 = -1; /* end point comparison */
108 R3 = 15; /* max counter */
109
110 /* read entries from table */
111.Lread_daddr:
112 R0 = [I2++];
113 cc = R0 == R1;
114 IF CC JUMP .Lddone;
115 [I0++] = R0;
116
117.Lread_ddata:
118 R2 = [I2++];
119 [I1++] = R2;
120 R3 = R3 + R1;
121 CC = R3 == R1;
122 IF !CC JUMP .Lread_daddr;
123.Lddone:
124 P0.L = (DMEM_CONTROL & 0xFFFF);
125 P0.H = (DMEM_CONTROL >> 16);
126 R1 = [P0];
127
128 R0 = DMEM_CNTR;
129
130 R0 = R0 | R1;
131 /* Anomaly 05000125 */
132 CLI R2;
133 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ 64 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
134 .align 8; 65 .align 8;
135 [P0] = R0; 66 [P0] = R0;
136 SSYNC; 67 SSYNC;
137 STI R2; 68 STI R1;
138 RTS; 69 RTS;
139 70
140ENDPROC(_bfin_dcache_init) 71ENDPROC(_bfin_write_DMEM_CONTROL)
72#endif
73
141#endif 74#endif
diff --git a/arch/blackfin/mach-common/cplbinfo.c b/arch/blackfin/mach-common/cplbinfo.c
index caa9623e6bd6..785ca9816971 100644
--- a/arch/blackfin/mach-common/cplbinfo.c
+++ b/arch/blackfin/mach-common/cplbinfo.c
@@ -31,11 +31,10 @@
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/proc_fs.h> 33#include <linux/proc_fs.h>
34#include <linux/uaccess.h>
34 35
35#include <asm/current.h> 36#include <asm/current.h>
36#include <asm/uaccess.h>
37#include <asm/system.h> 37#include <asm/system.h>
38
39#include <asm/cplb.h> 38#include <asm/cplb.h>
40#include <asm/blackfin.h> 39#include <asm/blackfin.h>
41 40
@@ -92,8 +91,7 @@ static char *cplb_print_entry(char *buf, int type)
92 } else 91 } else
93 buf += sprintf(buf, "Data CPLB entry:\n"); 92 buf += sprintf(buf, "Data CPLB entry:\n");
94 93
95 buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\ 94 buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\n\tiCount\toCount\n");
96\tiCount\toCount\n");
97 95
98 while (*p_addr != 0xffffffff) { 96 while (*p_addr != 0xffffffff) {
99 entry = cplb_find_entry(cplb_addr, cplb_data, *p_addr, *p_data); 97 entry = cplb_find_entry(cplb_addr, cplb_data, *p_addr, *p_data);
@@ -144,8 +142,7 @@ static int cplbinfo_proc_output(char *buf)
144 142
145 p = buf; 143 p = buf;
146 144
147 p += sprintf(p, 145 p += sprintf(p, "------------------ CPLB Information ------------------\n\n");
148 "------------------ CPLB Information ------------------\n\n");
149 146
150 if (bfin_read_IMEM_CONTROL() & ENICPLB) 147 if (bfin_read_IMEM_CONTROL() & ENICPLB)
151 p = cplb_print_entry(p, CPLB_I); 148 p = cplb_print_entry(p, CPLB_I);
@@ -191,9 +188,9 @@ static int __init cplbinfo_init(void)
191{ 188{
192 struct proc_dir_entry *entry; 189 struct proc_dir_entry *entry;
193 190
194 if ((entry = create_proc_entry("cplbinfo", 0, NULL)) == NULL) { 191 entry = create_proc_entry("cplbinfo", 0, NULL);
192 if (!entry)
195 return -ENOMEM; 193 return -ENOMEM;
196 }
197 194
198 entry->read_proc = cplbinfo_read_proc; 195 entry->read_proc = cplbinfo_read_proc;
199 entry->write_proc = cplbinfo_write_proc; 196 entry->write_proc = cplbinfo_write_proc;
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 40045b1386ad..d61bba98fb54 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -49,34 +49,15 @@
49 49
50 50
51#include <linux/linkage.h> 51#include <linux/linkage.h>
52#include <linux/unistd.h>
52#include <asm/blackfin.h> 53#include <asm/blackfin.h>
53#include <asm/unistd.h>
54#include <asm/errno.h> 54#include <asm/errno.h>
55#include <asm/thread_info.h> /* TIF_NEED_RESCHED */ 55#include <asm/thread_info.h> /* TIF_NEED_RESCHED */
56#include <asm/asm-offsets.h> 56#include <asm/asm-offsets.h>
57#include <asm/trace.h>
57 58
58#include <asm/mach-common/context.S> 59#include <asm/mach-common/context.S>
59 60
60#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
61 /*
62 * TODO: this should be proper save/restore, but for now
63 * we'll just cheat and use 0x1/0x13
64 */
65# define DEBUG_START_HWTRACE \
66 P5.l = LO(TBUFCTL); \
67 P5.h = HI(TBUFCTL); \
68 R7 = 0x13; \
69 [P5] = R7;
70# define DEBUG_STOP_HWTRACE \
71 P5.l = LO(TBUFCTL); \
72 P5.h = HI(TBUFCTL); \
73 R7 = 0x01; \
74 [P5] = R7;
75#else
76# define DEBUG_START_HWTRACE
77# define DEBUG_STOP_HWTRACE
78#endif
79
80#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 61#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
81.section .l1.text 62.section .l1.text
82#else 63#else
@@ -110,25 +91,14 @@ ENTRY(_ex_icplb)
110 ASTAT = [sp++]; 91 ASTAT = [sp++];
111 SAVE_ALL_SYS 92 SAVE_ALL_SYS
112 call __cplb_hdr; 93 call __cplb_hdr;
113 DEBUG_START_HWTRACE 94 DEBUG_START_HWTRACE(p5, r7)
114 RESTORE_ALL_SYS 95 RESTORE_ALL_SYS
115 SP = RETN; 96 SP = RETN;
116 rtx; 97 rtx;
117ENDPROC(_ex_icplb) 98ENDPROC(_ex_icplb)
118 99
119ENTRY(_ex_spinlock)
120 /* Transform this into a syscall - twiddle the syscall vector. */
121 p5.l = lo(EVT15);
122 p5.h = hi(EVT15);
123 r7.l = _spinlock_bh;
124 r7.h = _spinlock_bh;
125 [p5] = r7;
126 csync;
127 /* Fall through. */
128ENDPROC(_ex_spinlock)
129
130ENTRY(_ex_syscall) 100ENTRY(_ex_syscall)
131 DEBUG_START_HWTRACE 101 DEBUG_START_HWTRACE(p5, r7)
132 (R7:6,P5:4) = [sp++]; 102 (R7:6,P5:4) = [sp++];
133 ASTAT = [sp++]; 103 ASTAT = [sp++];
134 raise 15; /* invoked by TRAP #0, for sys call */ 104 raise 15; /* invoked by TRAP #0, for sys call */
@@ -136,26 +106,6 @@ ENTRY(_ex_syscall)
136 rtx 106 rtx
137ENDPROC(_ex_syscall) 107ENDPROC(_ex_syscall)
138 108
139ENTRY(_spinlock_bh)
140 SAVE_ALL_SYS
141 /* To end up here, vector 15 was changed - so we have to change it
142 * back.
143 */
144 p0.l = lo(EVT15);
145 p0.h = hi(EVT15);
146 p1.l = _evt_system_call;
147 p1.h = _evt_system_call;
148 [p0] = p1;
149 csync;
150 r0 = [sp + PT_R0];
151 sp += -12;
152 call _sys_bfin_spinlock;
153 sp += 12;
154 [SP + PT_R0] = R0;
155 RESTORE_ALL_SYS
156 rti;
157ENDPROC(_spinlock_bh)
158
159ENTRY(_ex_soft_bp) 109ENTRY(_ex_soft_bp)
160 r7 = retx; 110 r7 = retx;
161 r7 += -2; 111 r7 += -2;
@@ -186,7 +136,7 @@ ENTRY(_ex_single_step)
186 if !cc jump _ex_trap_c; 136 if !cc jump _ex_trap_c;
187 137
188_return_from_exception: 138_return_from_exception:
189 DEBUG_START_HWTRACE 139 DEBUG_START_HWTRACE(p5, r7)
190#ifdef ANOMALY_05000257 140#ifdef ANOMALY_05000257
191 R7=LC0; 141 R7=LC0;
192 LC0=R7; 142 LC0=R7;
@@ -208,7 +158,7 @@ ENTRY(_handle_bad_cplb)
208 * need to make a CPLB exception look like a normal exception 158 * need to make a CPLB exception look like a normal exception
209 */ 159 */
210 160
211 DEBUG_START_HWTRACE 161 DEBUG_START_HWTRACE(p5, r7)
212 RESTORE_ALL_SYS 162 RESTORE_ALL_SYS
213 [--sp] = ASTAT; 163 [--sp] = ASTAT;
214 [--sp] = (R7:6, P5:4); 164 [--sp] = (R7:6, P5:4);
@@ -251,7 +201,7 @@ ENTRY(_ex_trap_c)
251 R6 = SEQSTAT; 201 R6 = SEQSTAT;
252 [P5] = R6; 202 [P5] = R6;
253 203
254 DEBUG_START_HWTRACE 204 DEBUG_START_HWTRACE(p5, r7)
255 (R7:6,P5:4) = [sp++]; 205 (R7:6,P5:4) = [sp++];
256 ASTAT = [sp++]; 206 ASTAT = [sp++];
257 SP = RETN; 207 SP = RETN;
@@ -335,7 +285,7 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
335 /* Try to deal with syscalls quickly. */ 285 /* Try to deal with syscalls quickly. */
336 [--sp] = ASTAT; 286 [--sp] = ASTAT;
337 [--sp] = (R7:6, P5:4); 287 [--sp] = (R7:6, P5:4);
338 DEBUG_STOP_HWTRACE 288 DEBUG_STOP_HWTRACE(p5, r7)
339 r7 = SEQSTAT; /* reason code is in bit 5:0 */ 289 r7 = SEQSTAT; /* reason code is in bit 5:0 */
340 r6.l = lo(SEQSTAT_EXCAUSE); 290 r6.l = lo(SEQSTAT_EXCAUSE);
341 r6.h = hi(SEQSTAT_EXCAUSE); 291 r6.h = hi(SEQSTAT_EXCAUSE);
@@ -741,6 +691,10 @@ _schedule_and_signal_from_int:
741 r0 = [p0]; 691 r0 = [p0];
742 sti r0; 692 sti r0;
743 693
694 r0 = sp;
695 sp += -12;
696 call _finish_atomic_sections;
697 sp += 12;
744 jump.s .Lresume_userspace; 698 jump.s .Lresume_userspace;
745 699
746_schedule_and_signal: 700_schedule_and_signal:
@@ -790,14 +744,14 @@ ENDPROC(_init_exception_buff)
790ALIGN 744ALIGN
791_extable: 745_extable:
792 /* entry for each EXCAUSE[5:0] 746 /* entry for each EXCAUSE[5:0]
793 * This table bmust be in sync with the table in ./kernel/traps.c 747 * This table must be in sync with the table in ./kernel/traps.c
794 * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined 748 * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined
795 */ 749 */
796 .long _ex_syscall; /* 0x00 - User Defined - Linux Syscall */ 750 .long _ex_syscall; /* 0x00 - User Defined - Linux Syscall */
797 .long _ex_soft_bp /* 0x01 - User Defined - Software breakpoint */ 751 .long _ex_soft_bp /* 0x01 - User Defined - Software breakpoint */
798 .long _ex_trap_c /* 0x02 - User Defined */ 752 .long _ex_trap_c /* 0x02 - User Defined */
799 .long _ex_trap_c /* 0x03 - User Defined - Atomic test and set service */ 753 .long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */
800 .long _ex_spinlock /* 0x04 - User Defined */ 754 .long _ex_trap_c /* 0x04 - User Defined */
801 .long _ex_trap_c /* 0x05 - User Defined */ 755 .long _ex_trap_c /* 0x05 - User Defined */
802 .long _ex_trap_c /* 0x06 - User Defined */ 756 .long _ex_trap_c /* 0x06 - User Defined */
803 .long _ex_trap_c /* 0x07 - User Defined */ 757 .long _ex_trap_c /* 0x07 - User Defined */
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 8be548e061bf..203e20709163 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -34,6 +34,7 @@
34#include <linux/linkage.h> 34#include <linux/linkage.h>
35#include <asm/entry.h> 35#include <asm/entry.h>
36#include <asm/asm-offsets.h> 36#include <asm/asm-offsets.h>
37#include <asm/trace.h>
37 38
38#include <asm/mach-common/context.S> 39#include <asm/mach-common/context.S>
39 40
@@ -170,10 +171,9 @@ ENTRY(_evt_ivhw)
170 r7.l = W[p5]; 171 r7.l = W[p5];
1711: 1721:
172#endif 173#endif
173 p0.l = lo(TBUFCTL); 174
174 p0.h = hi(TBUFCTL); 175 trace_buffer_stop(p0, r0);
175 r0 = 1; 176
176 [p0] = r0;
177 r0 = IRQ_HWERR; 177 r0 = IRQ_HWERR;
178 r1 = sp; 178 r1 = sp;
179 179
diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c
index 80943bbd37c2..6b9fd03ce835 100644
--- a/arch/blackfin/mach-common/ints-priority-dc.c
+++ b/arch/blackfin/mach-common/ints-priority-dc.c
@@ -183,7 +183,7 @@ static void bf561_gpio_ack_irq(unsigned int irq)
183{ 183{
184 u16 gpionr = irq - IRQ_PF0; 184 u16 gpionr = irq - IRQ_PF0;
185 185
186 if(gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { 186 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
187 set_gpio_data(gpionr, 0); 187 set_gpio_data(gpionr, 0);
188 SSYNC(); 188 SSYNC();
189 } 189 }
@@ -193,7 +193,7 @@ static void bf561_gpio_mask_ack_irq(unsigned int irq)
193{ 193{
194 u16 gpionr = irq - IRQ_PF0; 194 u16 gpionr = irq - IRQ_PF0;
195 195
196 if(gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { 196 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
197 set_gpio_data(gpionr, 0); 197 set_gpio_data(gpionr, 0);
198 SSYNC(); 198 SSYNC();
199 } 199 }
@@ -222,7 +222,7 @@ static unsigned int bf561_gpio_irq_startup(unsigned int irq)
222 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 222 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
223 223
224 ret = gpio_request(gpionr, NULL); 224 ret = gpio_request(gpionr, NULL);
225 if(ret) 225 if (ret)
226 return ret; 226 return ret;
227 227
228 } 228 }
@@ -262,7 +262,7 @@ static int bf561_gpio_irq_type(unsigned int irq, unsigned int type)
262 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 262 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
263 263
264 ret = gpio_request(gpionr, NULL); 264 ret = gpio_request(gpionr, NULL);
265 if(ret) 265 if (ret)
266 return ret; 266 return ret;
267 267
268 } 268 }
@@ -371,6 +371,9 @@ int __init init_arch_irq(void)
371 bfin_write_SICA_IMASK1(SIC_UNMASK_ALL); 371 bfin_write_SICA_IMASK1(SIC_UNMASK_ALL);
372 SSYNC(); 372 SSYNC();
373 373
374 bfin_write_SICA_IWR0(IWR_ENABLE_ALL);
375 bfin_write_SICA_IWR1(IWR_ENABLE_ALL);
376
374 local_irq_disable(); 377 local_irq_disable();
375 378
376 init_exception_buff(); 379 init_exception_buff();
@@ -393,7 +396,7 @@ int __init init_arch_irq(void)
393 bfin_write_EVT15(evt_system_call); 396 bfin_write_EVT15(evt_system_call);
394 CSYNC(); 397 CSYNC();
395 398
396 for (irq = 0; irq < SYS_IRQS; irq++) { 399 for (irq = 0; irq <= SYS_IRQS; irq++) {
397 if (irq <= IRQ_CORETMR) 400 if (irq <= IRQ_CORETMR)
398 set_irq_chip(irq, &bf561_core_irqchip); 401 set_irq_chip(irq, &bf561_core_irqchip);
399 else 402 else
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c
index 2cfc7d5aec5c..28a878c3577a 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority-sc.c
@@ -13,7 +13,7 @@
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> 13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola 14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl> 15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2006 Analog Devices Inc. 16 * Copyright 2004-2007 Analog Devices Inc.
17 * 17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 * 19 *
@@ -65,9 +65,9 @@ atomic_t num_spurious;
65 65
66struct ivgx { 66struct ivgx {
67 /* irq number for request_irq, available in mach-bf533/irq.h */ 67 /* irq number for request_irq, available in mach-bf533/irq.h */
68 int irqno; 68 unsigned int irqno;
69 /* corresponding bit in the SIC_ISR register */ 69 /* corresponding bit in the SIC_ISR register */
70 int isrflag; 70 unsigned int isrflag;
71} ivg_table[NR_PERI_INTS]; 71} ivg_table[NR_PERI_INTS];
72 72
73struct ivg_slice { 73struct ivg_slice {
@@ -88,17 +88,16 @@ static void __init search_IAR(void)
88 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { 88 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
89 int irqn; 89 int irqn;
90 90
91 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = 91 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
92 &ivg_table[irq_pos];
93 92
94 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { 93 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
95 int iar_shift = (irqn & 7) * 4; 94 int iar_shift = (irqn & 7) * 4;
96 if (ivg == 95 if (ivg ==
97 (0xf & 96 (0xf &
98 bfin_read32((unsigned long *) SIC_IAR0 + 97 bfin_read32((unsigned long *)SIC_IAR0 +
99 (irqn >> 3)) >> iar_shift)) { 98 (irqn >> 3)) >> iar_shift)) {
100 ivg_table[irq_pos].irqno = IVG7 + irqn; 99 ivg_table[irq_pos].irqno = IVG7 + irqn;
101 ivg_table[irq_pos].isrflag = 1 << irqn; 100 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
102 ivg7_13[ivg].istop++; 101 ivg7_13[ivg].istop++;
103 irq_pos++; 102 irq_pos++;
104 } 103 }
@@ -141,15 +140,31 @@ static void bfin_core_unmask_irq(unsigned int irq)
141 140
142static void bfin_internal_mask_irq(unsigned int irq) 141static void bfin_internal_mask_irq(unsigned int irq)
143{ 142{
143#ifndef CONFIG_BF54x
144 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 144 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
145 ~(1 << (irq - (IRQ_CORETMR + 1)))); 145 ~(1 << (irq - (IRQ_CORETMR + 1))));
146#else
147 unsigned mask_bank, mask_bit;
148 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
149 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
150 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
151 ~(1 << mask_bit));
152#endif
146 SSYNC(); 153 SSYNC();
147} 154}
148 155
149static void bfin_internal_unmask_irq(unsigned int irq) 156static void bfin_internal_unmask_irq(unsigned int irq)
150{ 157{
158#ifndef CONFIG_BF54x
151 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 159 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
152 (1 << (irq - (IRQ_CORETMR + 1)))); 160 (1 << (irq - (IRQ_CORETMR + 1))));
161#else
162 unsigned mask_bank, mask_bit;
163 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
164 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
165 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
166 (1 << mask_bit));
167#endif
153 SSYNC(); 168 SSYNC();
154} 169}
155 170
@@ -206,7 +221,7 @@ static struct irq_chip bfin_generic_error_irqchip = {
206}; 221};
207 222
208static void bfin_demux_error_irq(unsigned int int_err_irq, 223static void bfin_demux_error_irq(unsigned int int_err_irq,
209 struct irq_desc *intb_desc) 224 struct irq_desc *intb_desc)
210{ 225{
211 int irq = 0; 226 int irq = 0;
212 227
@@ -270,8 +285,8 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
270 } 285 }
271 286
272 pr_debug("IRQ %d:" 287 pr_debug("IRQ %d:"
273 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n", 288 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
274 irq); 289 irq);
275 } 290 }
276 } else 291 } else
277 printk(KERN_ERR 292 printk(KERN_ERR
@@ -279,11 +294,10 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
279 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", 294 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
280 __FUNCTION__, __FILE__, __LINE__); 295 __FUNCTION__, __FILE__, __LINE__);
281 296
282
283} 297}
284#endif /* BF537_GENERIC_ERROR_INT_DEMUX */ 298#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
285 299
286#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 300#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && !defined(CONFIG_BF54x)
287 301
288static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; 302static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
289static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; 303static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
@@ -361,8 +375,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
361 } 375 }
362 376
363 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | 377 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
364 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 378 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
365 {
366 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 379 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
367 ret = gpio_request(gpionr, NULL); 380 ret = gpio_request(gpionr, NULL);
368 if (ret) 381 if (ret)
@@ -407,7 +420,6 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
407 return 0; 420 return 0;
408} 421}
409 422
410
411static struct irq_chip bfin_gpio_irqchip = { 423static struct irq_chip bfin_gpio_irqchip = {
412 .ack = bfin_gpio_ack_irq, 424 .ack = bfin_gpio_ack_irq,
413 .mask = bfin_gpio_mask_irq, 425 .mask = bfin_gpio_mask_irq,
@@ -419,20 +431,20 @@ static struct irq_chip bfin_gpio_irqchip = {
419}; 431};
420 432
421static void bfin_demux_gpio_irq(unsigned int intb_irq, 433static void bfin_demux_gpio_irq(unsigned int intb_irq,
422 struct irq_desc *intb_desc) 434 struct irq_desc *intb_desc)
423{ 435{
424 u16 i; 436 u16 i;
437 struct irq_desc *desc;
425 438
426 for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=16) { 439 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
427 int irq = IRQ_PF0 + i; 440 int irq = IRQ_PF0 + i;
428 int flag_d = get_gpiop_data(i); 441 int flag_d = get_gpiop_data(i);
429 int mask = 442 int mask =
430 flag_d & (gpio_enabled[gpio_bank(i)] & 443 flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i));
431 get_gpiop_maska(i));
432 444
433 while (mask) { 445 while (mask) {
434 if (mask & 1) { 446 if (mask & 1) {
435 struct irq_desc *desc = irq_desc + irq; 447 desc = irq_desc + irq;
436 desc->handle_irq(irq, desc); 448 desc->handle_irq(irq, desc);
437 } 449 }
438 irq++; 450 irq++;
@@ -441,6 +453,264 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
441 } 453 }
442} 454}
443 455
456#else /* CONFIG_IRQCHIP_DEMUX_GPIO */
457
458#define NR_PINT_SYS_IRQS 4
459#define NR_PINT_BITS 32
460#define NR_PINTS 160
461#define IRQ_NOT_AVAIL 0xFF
462
463#define PINT_2_BANK(x) ((x) >> 5)
464#define PINT_2_BIT(x) ((x) & 0x1F)
465#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
466
467static unsigned char irq2pint_lut[NR_PINTS];
468static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
469
470struct pin_int_t {
471 unsigned int mask_set;
472 unsigned int mask_clear;
473 unsigned int request;
474 unsigned int assign;
475 unsigned int edge_set;
476 unsigned int edge_clear;
477 unsigned int invert_set;
478 unsigned int invert_clear;
479 unsigned int pinstate;
480 unsigned int latch;
481};
482
483static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
484 (struct pin_int_t *)PINT0_MASK_SET,
485 (struct pin_int_t *)PINT1_MASK_SET,
486 (struct pin_int_t *)PINT2_MASK_SET,
487 (struct pin_int_t *)PINT3_MASK_SET,
488};
489
490unsigned short get_irq_base(u8 bank, u8 bmap)
491{
492
493 u16 irq_base;
494
495 if (bank < 2) { /*PA-PB */
496 irq_base = IRQ_PA0 + bmap * 16;
497 } else { /*PC-PJ */
498 irq_base = IRQ_PC0 + bmap * 16;
499 }
500
501 return irq_base;
502
503}
504
505 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
506void init_pint_lut(void)
507{
508 u16 bank, bit, irq_base, bit_pos;
509 u32 pint_assign;
510 u8 bmap;
511
512 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
513
514 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
515
516 pint_assign = pint[bank]->assign;
517
518 for (bit = 0; bit < NR_PINT_BITS; bit++) {
519
520 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
521
522 irq_base = get_irq_base(bank, bmap);
523
524 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
525 bit_pos = bit + bank * NR_PINT_BITS;
526
527 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
528 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
529
530 }
531
532 }
533
534}
535
536static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
537
538static void bfin_gpio_ack_irq(unsigned int irq)
539{
540 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
541
542 pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
543 SSYNC();
544}
545
546static void bfin_gpio_mask_ack_irq(unsigned int irq)
547{
548 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
549 u32 pintbit = PINT_BIT(pint_val);
550 u8 bank = PINT_2_BANK(pint_val);
551
552 pint[bank]->request = pintbit;
553 pint[bank]->mask_clear = pintbit;
554 SSYNC();
555}
556
557static void bfin_gpio_mask_irq(unsigned int irq)
558{
559 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
560
561 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
562 SSYNC();
563}
564
565static void bfin_gpio_unmask_irq(unsigned int irq)
566{
567 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
568 u32 pintbit = PINT_BIT(pint_val);
569 u8 bank = PINT_2_BANK(pint_val);
570
571 pint[bank]->request = pintbit;
572 pint[bank]->mask_set = pintbit;
573 SSYNC();
574}
575
576static unsigned int bfin_gpio_irq_startup(unsigned int irq)
577{
578 unsigned int ret;
579 u16 gpionr = irq - IRQ_PA0;
580 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
581
582 if (pint_val == IRQ_NOT_AVAIL)
583 return -ENODEV;
584
585 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
586 ret = gpio_request(gpionr, NULL);
587 if (ret)
588 return ret;
589 }
590
591 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
592 bfin_gpio_unmask_irq(irq);
593
594 return ret;
595}
596
597static void bfin_gpio_irq_shutdown(unsigned int irq)
598{
599 bfin_gpio_mask_irq(irq);
600 gpio_free(irq - IRQ_PA0);
601 gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0);
602}
603
604static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
605{
606
607 unsigned int ret;
608 u16 gpionr = irq - IRQ_PA0;
609 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
610 u32 pintbit = PINT_BIT(pint_val);
611 u8 bank = PINT_2_BANK(pint_val);
612
613 if (pint_val == IRQ_NOT_AVAIL)
614 return -ENODEV;
615
616 if (type == IRQ_TYPE_PROBE) {
617 /* only probe unenabled GPIO interrupt lines */
618 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
619 return 0;
620 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
621 }
622
623 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
624 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
625 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
626 ret = gpio_request(gpionr, NULL);
627 if (ret)
628 return ret;
629 }
630
631 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
632 } else {
633 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
634 return 0;
635 }
636
637 gpio_direction_input(gpionr);
638
639 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
640 pint[bank]->edge_set = pintbit;
641 } else {
642 pint[bank]->edge_clear = pintbit;
643 }
644
645 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
646 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
647 else
648 pint[bank]->invert_set = pintbit; /* high or rising edge denoted by zero */
649
650 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
651 pint[bank]->invert_set = pintbit;
652 else
653 pint[bank]->invert_set = pintbit;
654
655 SSYNC();
656
657 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
658 set_irq_handler(irq, handle_edge_irq);
659 else
660 set_irq_handler(irq, handle_level_irq);
661
662 return 0;
663}
664
665static struct irq_chip bfin_gpio_irqchip = {
666 .ack = bfin_gpio_ack_irq,
667 .mask = bfin_gpio_mask_irq,
668 .mask_ack = bfin_gpio_mask_ack_irq,
669 .unmask = bfin_gpio_unmask_irq,
670 .set_type = bfin_gpio_irq_type,
671 .startup = bfin_gpio_irq_startup,
672 .shutdown = bfin_gpio_irq_shutdown
673};
674
675static void bfin_demux_gpio_irq(unsigned int intb_irq,
676 struct irq_desc *intb_desc)
677{
678 u8 bank, pint_val;
679 u32 request, irq;
680 struct irq_desc *desc;
681
682 switch (intb_irq) {
683 case IRQ_PINT0:
684 bank = 0;
685 break;
686 case IRQ_PINT2:
687 bank = 2;
688 break;
689 case IRQ_PINT3:
690 bank = 3;
691 break;
692 case IRQ_PINT1:
693 bank = 1;
694 break;
695 default:
696 return;
697 }
698
699 pint_val = bank * NR_PINT_BITS;
700
701 request = pint[bank]->request;
702
703 while (request) {
704 if (request & 1) {
705 irq = pint2irq_lut[pint_val] + SYS_IRQS;
706 desc = irq_desc + irq;
707 desc->handle_irq(irq, desc);
708 }
709 pint_val++;
710 request >>= 1;
711 }
712
713}
444#endif /* CONFIG_IRQCHIP_DEMUX_GPIO */ 714#endif /* CONFIG_IRQCHIP_DEMUX_GPIO */
445 715
446/* 716/*
@@ -452,7 +722,18 @@ int __init init_arch_irq(void)
452 int irq; 722 int irq;
453 unsigned long ilat = 0; 723 unsigned long ilat = 0;
454 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ 724 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
725#ifdef CONFIG_BF54x
726 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
727 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
728 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
729 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
730 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
731 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
732#else
455 bfin_write_SIC_IMASK(SIC_UNMASK_ALL); 733 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
734 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
735#endif
736
456 SSYNC(); 737 SSYNC();
457 738
458 local_irq_disable(); 739 local_irq_disable();
@@ -475,7 +756,18 @@ int __init init_arch_irq(void)
475 bfin_write_EVT15(evt_system_call); 756 bfin_write_EVT15(evt_system_call);
476 CSYNC(); 757 CSYNC();
477 758
478 for (irq = 0; irq < SYS_IRQS; irq++) { 759#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x)
760#ifdef CONFIG_PINTx_REASSIGN
761 pint[0]->assign = CONFIG_PINT0_ASSIGN;
762 pint[1]->assign = CONFIG_PINT1_ASSIGN;
763 pint[2]->assign = CONFIG_PINT2_ASSIGN;
764 pint[3]->assign = CONFIG_PINT3_ASSIGN;
765#endif
766 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
767 init_pint_lut();
768#endif
769
770 for (irq = 0; irq <= SYS_IRQS; irq++) {
479 if (irq <= IRQ_CORETMR) 771 if (irq <= IRQ_CORETMR)
480 set_irq_chip(irq, &bfin_core_irqchip); 772 set_irq_chip(irq, &bfin_core_irqchip);
481 else 773 else
@@ -484,20 +776,42 @@ int __init init_arch_irq(void)
484 if (irq != IRQ_GENERIC_ERROR) { 776 if (irq != IRQ_GENERIC_ERROR) {
485#endif 777#endif
486 778
779 switch (irq) {
487#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 780#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
488 if ((irq != IRQ_PROG_INTA) /*PORT F & G MASK_A Interrupt*/ 781#ifndef CONFIG_BF54x
489# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) 782 case IRQ_PROG_INTA:
490 && (irq != IRQ_MAC_RX) /*PORT H MASK_A Interrupt*/ 783 set_irq_chained_handler(irq,
491# endif 784 bfin_demux_gpio_irq);
492 ) { 785 break;
786#if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
787 case IRQ_MAC_RX:
788 set_irq_chained_handler(irq,
789 bfin_demux_gpio_irq);
790 break;
493#endif 791#endif
494 set_irq_handler(irq, handle_simple_irq); 792#else
495#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 793 case IRQ_PINT0:
496 } else {
497 set_irq_chained_handler(irq, 794 set_irq_chained_handler(irq,
498 bfin_demux_gpio_irq); 795 bfin_demux_gpio_irq);
499 } 796 break;
797 case IRQ_PINT1:
798 set_irq_chained_handler(irq,
799 bfin_demux_gpio_irq);
800 break;
801 case IRQ_PINT2:
802 set_irq_chained_handler(irq,
803 bfin_demux_gpio_irq);
804 break;
805 case IRQ_PINT3:
806 set_irq_chained_handler(irq,
807 bfin_demux_gpio_irq);
808 break;
809#endif /*CONFIG_BF54x */
500#endif 810#endif
811 default:
812 set_irq_handler(irq, handle_simple_irq);
813 break;
814 }
501 815
502#ifdef BF537_GENERIC_ERROR_INT_DEMUX 816#ifdef BF537_GENERIC_ERROR_INT_DEMUX
503 } else { 817 } else {
@@ -513,7 +827,11 @@ int __init init_arch_irq(void)
513#endif 827#endif
514 828
515#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 829#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
830#ifndef CONFIG_BF54x
516 for (irq = IRQ_PF0; irq < NR_IRQS; irq++) { 831 for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
832#else
833 for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
834#endif
517 set_irq_chip(irq, &bfin_gpio_irqchip); 835 set_irq_chip(irq, &bfin_gpio_irqchip);
518 /* if configured as edge, then will be changed to do_edge_IRQ */ 836 /* if configured as edge, then will be changed to do_edge_IRQ */
519 set_irq_handler(irq, handle_level_irq); 837 set_irq_handler(irq, handle_level_irq);
@@ -526,8 +844,7 @@ int __init init_arch_irq(void)
526 bfin_write_ILAT(ilat); 844 bfin_write_ILAT(ilat);
527 CSYNC(); 845 CSYNC();
528 846
529 printk(KERN_INFO 847 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
530 "Configuring Blackfin Priority Driven Interrupts\n");
531 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx, 848 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
532 * local_irq_enable() 849 * local_irq_enable()
533 */ 850 */
@@ -538,14 +855,13 @@ int __init init_arch_irq(void)
538 /* Enable interrupts IVG7-15 */ 855 /* Enable interrupts IVG7-15 */
539 irq_flags = irq_flags | IMASK_IVG15 | 856 irq_flags = irq_flags | IMASK_IVG15 |
540 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | 857 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
541 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | 858 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
542 IMASK_IVGHW;
543 859
544 return 0; 860 return 0;
545} 861}
546 862
547#ifdef CONFIG_DO_IRQ_L1 863#ifdef CONFIG_DO_IRQ_L1
548void do_irq(int vec, struct pt_regs *fp)__attribute__((l1_text)); 864void do_irq(int vec, struct pt_regs *fp) __attribute__((l1_text));
549#endif 865#endif
550 866
551void do_irq(int vec, struct pt_regs *fp) 867void do_irq(int vec, struct pt_regs *fp)
@@ -555,9 +871,25 @@ void do_irq(int vec, struct pt_regs *fp)
555 } else { 871 } else {
556 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; 872 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
557 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; 873 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
558 unsigned long sic_status; 874#ifdef CONFIG_BF54x
875 unsigned long sic_status[3];
559 876
560 SSYNC(); 877 SSYNC();
878 sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
879 sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
880 sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
881
882 for (;; ivg++) {
883 if (ivg >= ivg_stop) {
884 atomic_inc(&num_spurious);
885 return;
886 }
887 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
888 break;
889 }
890#else
891 unsigned long sic_status;
892 SSYNC();
561 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); 893 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
562 894
563 for (;; ivg++) { 895 for (;; ivg++) {
@@ -567,6 +899,7 @@ void do_irq(int vec, struct pt_regs *fp)
567 } else if (sic_status & ivg->isrflag) 899 } else if (sic_status & ivg->isrflag)
568 break; 900 break;
569 } 901 }
902#endif
570 vec = ivg->irqno; 903 vec = ivg->irqno;
571 } 904 }
572 asm_do_IRQ(vec, fp); 905 asm_do_IRQ(vec, fp);
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 150ef5d088dc..1772d8d2c1a7 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -35,10 +35,10 @@
35#include <linux/pm.h> 35#include <linux/pm.h>
36#include <linux/sched.h> 36#include <linux/sched.h>
37#include <linux/proc_fs.h> 37#include <linux/proc_fs.h>
38#include <linux/io.h>
39#include <linux/irq.h>
38 40
39#include <asm/io.h>
40#include <asm/dpmc.h> 41#include <asm/dpmc.h>
41#include <asm/irq.h>
42#include <asm/gpio.h> 42#include <asm/gpio.h>
43 43
44#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H 44#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
diff --git a/arch/blackfin/mm/blackfin_sram.c b/arch/blackfin/mm/blackfin_sram.c
index 68107924639e..16c6169ed01b 100644
--- a/arch/blackfin/mm/blackfin_sram.c
+++ b/arch/blackfin/mm/blackfin_sram.c
@@ -87,7 +87,7 @@ void __init l1sram_init(void)
87 L1_SCRATCH_LENGTH >> 10); 87 L1_SCRATCH_LENGTH >> 10);
88 88
89 memset(&l1_ssram, 0x00, sizeof(l1_ssram)); 89 memset(&l1_ssram, 0x00, sizeof(l1_ssram));
90 l1_ssram[0].paddr = (void*)L1_SCRATCH_START; 90 l1_ssram[0].paddr = (void *)L1_SCRATCH_START;
91 l1_ssram[0].size = L1_SCRATCH_LENGTH; 91 l1_ssram[0].size = L1_SCRATCH_LENGTH;
92 l1_ssram[0].flag = SRAM_SLT_FREE; 92 l1_ssram[0].flag = SRAM_SLT_FREE;
93 93
@@ -126,7 +126,7 @@ void __init l1_inst_sram_init(void)
126{ 126{
127#if L1_CODE_LENGTH != 0 127#if L1_CODE_LENGTH != 0
128 memset(&l1_inst_sram, 0x00, sizeof(l1_inst_sram)); 128 memset(&l1_inst_sram, 0x00, sizeof(l1_inst_sram));
129 l1_inst_sram[0].paddr = (void*)L1_CODE_START + (_etext_l1 - _stext_l1); 129 l1_inst_sram[0].paddr = (void *)L1_CODE_START + (_etext_l1 - _stext_l1);
130 l1_inst_sram[0].size = L1_CODE_LENGTH - (_etext_l1 - _stext_l1); 130 l1_inst_sram[0].size = L1_CODE_LENGTH - (_etext_l1 - _stext_l1);
131 l1_inst_sram[0].flag = SRAM_SLT_FREE; 131 l1_inst_sram[0].flag = SRAM_SLT_FREE;
132 132
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 570356dbe028..68459cc052a1 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -29,8 +29,8 @@
29 29
30#include <linux/swap.h> 30#include <linux/swap.h>
31#include <linux/bootmem.h> 31#include <linux/bootmem.h>
32#include <linux/uaccess.h>
32#include <asm/bfin-global.h> 33#include <asm/bfin-global.h>
33#include <asm/uaccess.h>
34#include <asm/l1layout.h> 34#include <asm/l1layout.h>
35#include "blackfin_sram.h" 35#include "blackfin_sram.h"
36 36
@@ -168,42 +168,31 @@ void __init mem_init(void)
168 } 168 }
169} 169}
170 170
171#ifdef CONFIG_BLK_DEV_INITRD 171static __init void free_init_pages(const char *what, unsigned long begin, unsigned long end)
172void __init free_initrd_mem(unsigned long start, unsigned long end)
173{ 172{
174 int pages = 0; 173 unsigned long addr;
175 for (; start < end; start += PAGE_SIZE) { 174 /* next to check that the page we free is not a partial page */
176 ClearPageReserved(virt_to_page(start)); 175 for (addr = begin; addr + PAGE_SIZE <= end; addr += PAGE_SIZE) {
177 init_page_count(virt_to_page(start)); 176 ClearPageReserved(virt_to_page(addr));
178 free_page(start); 177 init_page_count(virt_to_page(addr));
178 free_page(addr);
179 totalram_pages++; 179 totalram_pages++;
180 pages++;
181 } 180 }
182 printk(KERN_NOTICE "Freeing initrd memory: %dk freed\n", pages); 181 printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
182}
183
184#ifdef CONFIG_BLK_DEV_INITRD
185void __init free_initrd_mem(unsigned long start, unsigned long end)
186{
187 free_init_pages("initrd memory", start, end);
183} 188}
184#endif 189#endif
185 190
186void __init free_initmem(void) 191void __init free_initmem(void)
187{ 192{
188#ifdef CONFIG_RAMKERNEL 193#ifdef CONFIG_RAMKERNEL
189 unsigned long addr; 194 free_init_pages("unused kernel memory",
190 /* 195 (unsigned long)(&__init_begin),
191 * the following code should be cool even if these sections 196 (unsigned long)(&__init_end));
192 * are not page aligned.
193 */
194 addr = PAGE_ALIGN((unsigned long)(__init_begin));
195 /* next to check that the page we free is not a partial page */
196 for (; addr + PAGE_SIZE < (unsigned long)(__init_end);
197 addr += PAGE_SIZE) {
198 ClearPageReserved(virt_to_page(addr));
199 init_page_count(virt_to_page(addr));
200 free_page(addr);
201 totalram_pages++;
202 }
203 printk(KERN_NOTICE
204 "Freeing unused kernel memory: %ldk freed (0x%x - 0x%x)\n",
205 (addr - PAGE_ALIGN((long)__init_begin)) >> 10,
206 (int)(PAGE_ALIGN((unsigned long)(__init_begin))),
207 (int)(addr - PAGE_SIZE));
208#endif 197#endif
209} 198}
diff --git a/arch/blackfin/oprofile/common.c b/arch/blackfin/oprofile/common.c
index 009a1700c854..cb8b8d5af34f 100644
--- a/arch/blackfin/oprofile/common.c
+++ b/arch/blackfin/oprofile/common.c
@@ -33,12 +33,12 @@
33#include <linux/smp.h> 33#include <linux/smp.h>
34#include <linux/errno.h> 34#include <linux/errno.h>
35#include <linux/mutex.h> 35#include <linux/mutex.h>
36#include <linux/ptrace.h>
37#include <linux/irq.h>
38#include <linux/io.h>
36 39
37#include <asm/ptrace.h>
38#include <asm/system.h> 40#include <asm/system.h>
39#include <asm/blackfin.h> 41#include <asm/blackfin.h>
40#include <asm/irq.h>
41#include <asm/io.h>
42 42
43#include "op_blackfin.h" 43#include "op_blackfin.h"
44 44
diff --git a/arch/blackfin/oprofile/op_model_bf533.c b/arch/blackfin/oprofile/op_model_bf533.c
index b7a20a006b49..872dffe33623 100644
--- a/arch/blackfin/oprofile/op_model_bf533.c
+++ b/arch/blackfin/oprofile/op_model_bf533.c
@@ -32,12 +32,12 @@
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/smp.h> 33#include <linux/smp.h>
34#include <linux/interrupt.h> 34#include <linux/interrupt.h>
35#include <asm/ptrace.h> 35#include <linux/ptrace.h>
36#include <linux/irq.h>
37#include <linux/io.h>
36#include <asm/system.h> 38#include <asm/system.h>
37#include <asm/processor.h> 39#include <asm/processor.h>
38#include <asm/blackfin.h> 40#include <asm/blackfin.h>
39#include <asm/irq.h>
40#include <asm/io.h>
41 41
42#include "op_blackfin.h" 42#include "op_blackfin.h"
43 43
diff --git a/arch/blackfin/oprofile/timer_int.c b/arch/blackfin/oprofile/timer_int.c
index 8fba16c846c9..6c6f8606af4c 100644
--- a/arch/blackfin/oprofile/timer_int.c
+++ b/arch/blackfin/oprofile/timer_int.c
@@ -31,8 +31,7 @@
31#include <linux/smp.h> 31#include <linux/smp.h>
32#include <linux/irq.h> 32#include <linux/irq.h>
33#include <linux/oprofile.h> 33#include <linux/oprofile.h>
34 34#include <linux/ptrace.h>
35#include <asm/ptrace.h>
36 35
37static void enable_sys_timer0() 36static void enable_sys_timer0()
38{ 37{
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 08:34:59 -0500