diff options
Diffstat (limited to 'arch/blackfin')
39 files changed, 1299 insertions, 507 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index fef96f47876c..9b765107e15c 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig | |||
@@ -352,6 +352,11 @@ config MEM_MT48H32M16LFCJ_75 | |||
352 | depends on (BFIN526_EZBRD) | 352 | depends on (BFIN526_EZBRD) |
353 | default y | 353 | default y |
354 | 354 | ||
355 | config MEM_MT47H64M16 | ||
356 | bool | ||
357 | depends on (BFIN609_EZKIT) | ||
358 | default y | ||
359 | |||
355 | source "arch/blackfin/mach-bf518/Kconfig" | 360 | source "arch/blackfin/mach-bf518/Kconfig" |
356 | source "arch/blackfin/mach-bf527/Kconfig" | 361 | source "arch/blackfin/mach-bf527/Kconfig" |
357 | source "arch/blackfin/mach-bf533/Kconfig" | 362 | source "arch/blackfin/mach-bf533/Kconfig" |
@@ -399,8 +404,9 @@ config ROM_BASE | |||
399 | hex "Kernel ROM Base" | 404 | hex "Kernel ROM Base" |
400 | depends on ROMKERNEL | 405 | depends on ROMKERNEL |
401 | default "0x20040040" | 406 | default "0x20040040" |
402 | range 0x20000000 0x20400000 if !(BF54x || BF561) | 407 | range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x) |
403 | range 0x20000000 0x30000000 if (BF54x || BF561) | 408 | range 0x20000000 0x30000000 if (BF54x || BF561) |
409 | range 0xB0000000 0xC0000000 if (BF60x) | ||
404 | help | 410 | help |
405 | Make sure your ROM base does not include any file-header | 411 | Make sure your ROM base does not include any file-header |
406 | information that is prepended to the kernel. | 412 | information that is prepended to the kernel. |
@@ -1009,6 +1015,12 @@ config HAVE_PWM | |||
1009 | choice | 1015 | choice |
1010 | prompt "Uncached DMA region" | 1016 | prompt "Uncached DMA region" |
1011 | default DMA_UNCACHED_1M | 1017 | default DMA_UNCACHED_1M |
1018 | config DMA_UNCACHED_32M | ||
1019 | bool "Enable 32M DMA region" | ||
1020 | config DMA_UNCACHED_16M | ||
1021 | bool "Enable 16M DMA region" | ||
1022 | config DMA_UNCACHED_8M | ||
1023 | bool "Enable 8M DMA region" | ||
1012 | config DMA_UNCACHED_4M | 1024 | config DMA_UNCACHED_4M |
1013 | bool "Enable 4M DMA region" | 1025 | bool "Enable 4M DMA region" |
1014 | config DMA_UNCACHED_2M | 1026 | config DMA_UNCACHED_2M |
@@ -1038,7 +1050,7 @@ config BFIN_EXTMEM_ICACHEABLE | |||
1038 | config BFIN_L2_ICACHEABLE | 1050 | config BFIN_L2_ICACHEABLE |
1039 | bool "Enable ICACHE for L2 SRAM" | 1051 | bool "Enable ICACHE for L2 SRAM" |
1040 | depends on BFIN_ICACHE | 1052 | depends on BFIN_ICACHE |
1041 | depends on BF54x || BF561 | 1053 | depends on (BF54x || BF561 || BF60x) && !SMP |
1042 | default n | 1054 | default n |
1043 | 1055 | ||
1044 | config BFIN_DCACHE | 1056 | config BFIN_DCACHE |
diff --git a/arch/blackfin/configs/BF609-EZKIT_defconfig b/arch/blackfin/configs/BF609-EZKIT_defconfig index be9526bee4fb..f4b02350e415 100644 --- a/arch/blackfin/configs/BF609-EZKIT_defconfig +++ b/arch/blackfin/configs/BF609-EZKIT_defconfig | |||
@@ -90,6 +90,7 @@ CONFIG_INPUT_BFIN_ROTARY=y | |||
90 | # CONFIG_SERIO is not set | 90 | # CONFIG_SERIO is not set |
91 | # CONFIG_LEGACY_PTYS is not set | 91 | # CONFIG_LEGACY_PTYS is not set |
92 | CONFIG_BFIN_SIMPLE_TIMER=m | 92 | CONFIG_BFIN_SIMPLE_TIMER=m |
93 | # CONFIG_BFIN_CRC is not set | ||
93 | CONFIG_BFIN_LINKPORT=y | 94 | CONFIG_BFIN_LINKPORT=y |
94 | # CONFIG_DEVKMEM is not set | 95 | # CONFIG_DEVKMEM is not set |
95 | CONFIG_SERIAL_BFIN=y | 96 | CONFIG_SERIAL_BFIN=y |
@@ -153,3 +154,4 @@ CONFIG_CRYPTO_MD4=y | |||
153 | CONFIG_CRYPTO_MD5=y | 154 | CONFIG_CRYPTO_MD5=y |
154 | CONFIG_CRYPTO_ARC4=y | 155 | CONFIG_CRYPTO_ARC4=y |
155 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 156 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
157 | CONFIG_CRYPTO_DEV_BFIN_CRC=y | ||
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h index 608be5e6d25c..dc47d79287f9 100644 --- a/arch/blackfin/include/asm/bfin-global.h +++ b/arch/blackfin/include/asm/bfin-global.h | |||
@@ -14,7 +14,13 @@ | |||
14 | #include <linux/linkage.h> | 14 | #include <linux/linkage.h> |
15 | #include <linux/types.h> | 15 | #include <linux/types.h> |
16 | 16 | ||
17 | #if defined(CONFIG_DMA_UNCACHED_4M) | 17 | #if defined(CONFIG_DMA_UNCACHED_32M) |
18 | # define DMA_UNCACHED_REGION (32 * 1024 * 1024) | ||
19 | #elif defined(CONFIG_DMA_UNCACHED_16M) | ||
20 | # define DMA_UNCACHED_REGION (16 * 1024 * 1024) | ||
21 | #elif defined(CONFIG_DMA_UNCACHED_8M) | ||
22 | # define DMA_UNCACHED_REGION (8 * 1024 * 1024) | ||
23 | #elif defined(CONFIG_DMA_UNCACHED_4M) | ||
18 | # define DMA_UNCACHED_REGION (4 * 1024 * 1024) | 24 | # define DMA_UNCACHED_REGION (4 * 1024 * 1024) |
19 | #elif defined(CONFIG_DMA_UNCACHED_2M) | 25 | #elif defined(CONFIG_DMA_UNCACHED_2M) |
20 | # define DMA_UNCACHED_REGION (2 * 1024 * 1024) | 26 | # define DMA_UNCACHED_REGION (2 * 1024 * 1024) |
diff --git a/arch/blackfin/include/asm/bfin_crc.h b/arch/blackfin/include/asm/bfin_crc.h index 3deb4452ceed..75cef4dc85a1 100644 --- a/arch/blackfin/include/asm/bfin_crc.h +++ b/arch/blackfin/include/asm/bfin_crc.h | |||
@@ -79,20 +79,6 @@ struct crc_register { | |||
79 | u32 revid; | 79 | u32 revid; |
80 | }; | 80 | }; |
81 | 81 | ||
82 | struct bfin_crc { | ||
83 | struct miscdevice mdev; | ||
84 | struct list_head list; | ||
85 | int irq; | ||
86 | int dma_ch_src; | ||
87 | int dma_ch_dest; | ||
88 | volatile struct crc_register *regs; | ||
89 | struct crc_info *info; | ||
90 | struct mutex mutex; | ||
91 | struct completion c; | ||
92 | unsigned short opmode; | ||
93 | char name[20]; | ||
94 | }; | ||
95 | |||
96 | /* CRC_STATUS Masks */ | 82 | /* CRC_STATUS Masks */ |
97 | #define CMPERR 0x00000002 /* Compare error */ | 83 | #define CMPERR 0x00000002 /* Compare error */ |
98 | #define DCNTEXP 0x00000010 /* datacnt register expired */ | 84 | #define DCNTEXP 0x00000010 /* datacnt register expired */ |
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h index 8597158010b5..2d90d62edc97 100644 --- a/arch/blackfin/include/asm/bfin_serial.h +++ b/arch/blackfin/include/asm/bfin_serial.h | |||
@@ -282,7 +282,7 @@ struct bfin_uart_regs { | |||
282 | #define UART_GET_GCTL(p) UART_GET_CTL(p) | 282 | #define UART_GET_GCTL(p) UART_GET_CTL(p) |
283 | #define UART_GET_LCR(p) UART_GET_CTL(p) | 283 | #define UART_GET_LCR(p) UART_GET_CTL(p) |
284 | #define UART_GET_MCR(p) UART_GET_CTL(p) | 284 | #define UART_GET_MCR(p) UART_GET_CTL(p) |
285 | #if ANOMALY_05001001 | 285 | #if ANOMALY_16000030 |
286 | #define UART_GET_STAT(p) \ | 286 | #define UART_GET_STAT(p) \ |
287 | ({ \ | 287 | ({ \ |
288 | u32 __ret; \ | 288 | u32 __ret; \ |
diff --git a/arch/blackfin/include/asm/bfin_simple_timer.h b/arch/blackfin/include/asm/bfin_simple_timer.h index aadfb1ad1fac..b2d5e733079e 100644 --- a/arch/blackfin/include/asm/bfin_simple_timer.h +++ b/arch/blackfin/include/asm/bfin_simple_timer.h | |||
@@ -17,5 +17,11 @@ | |||
17 | #define BFIN_SIMPLE_TIMER_START _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6) | 17 | #define BFIN_SIMPLE_TIMER_START _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6) |
18 | #define BFIN_SIMPLE_TIMER_STOP _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8) | 18 | #define BFIN_SIMPLE_TIMER_STOP _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8) |
19 | #define BFIN_SIMPLE_TIMER_READ _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10) | 19 | #define BFIN_SIMPLE_TIMER_READ _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10) |
20 | #define BFIN_SIMPLE_TIMER_READ_COUNTER _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 11) | ||
21 | |||
22 | #define BFIN_SIMPLE_TIMER_MODE_PWM_ONESHOT 0 | ||
23 | #define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT 1 | ||
24 | #define BFIN_SIMPLE_TIMER_MODE_WDTH_CAP 2 | ||
25 | #define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT_NOIRQ 3 | ||
20 | 26 | ||
21 | #endif | 27 | #endif |
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h index 2f3339a47626..f4a072787436 100644 --- a/arch/blackfin/include/asm/bfin_twi.h +++ b/arch/blackfin/include/asm/bfin_twi.h | |||
@@ -66,9 +66,9 @@ struct bfin_twi_iface { | |||
66 | 66 | ||
67 | #define DEFINE_TWI_REG(reg_name, reg) \ | 67 | #define DEFINE_TWI_REG(reg_name, reg) \ |
68 | static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \ | 68 | static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \ |
69 | { return iface->regs_base->reg; } \ | 69 | { return bfin_read16(&iface->regs_base->reg); } \ |
70 | static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \ | 70 | static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \ |
71 | { iface->regs_base->reg = v; } | 71 | { bfin_write16(&iface->regs_base->reg, v); } |
72 | 72 | ||
73 | DEFINE_TWI_REG(CLKDIV, clkdiv) | 73 | DEFINE_TWI_REG(CLKDIV, clkdiv) |
74 | DEFINE_TWI_REG(CONTROL, control) | 74 | DEFINE_TWI_REG(CONTROL, control) |
@@ -84,7 +84,7 @@ DEFINE_TWI_REG(FIFO_CTL, fifo_ctl) | |||
84 | DEFINE_TWI_REG(FIFO_STAT, fifo_stat) | 84 | DEFINE_TWI_REG(FIFO_STAT, fifo_stat) |
85 | DEFINE_TWI_REG(XMT_DATA8, xmt_data8) | 85 | DEFINE_TWI_REG(XMT_DATA8, xmt_data8) |
86 | DEFINE_TWI_REG(XMT_DATA16, xmt_data16) | 86 | DEFINE_TWI_REG(XMT_DATA16, xmt_data16) |
87 | #if !ANOMALY_05001001 | 87 | #if !ANOMALY_16000030 |
88 | DEFINE_TWI_REG(RCV_DATA8, rcv_data8) | 88 | DEFINE_TWI_REG(RCV_DATA8, rcv_data8) |
89 | DEFINE_TWI_REG(RCV_DATA16, rcv_data16) | 89 | DEFINE_TWI_REG(RCV_DATA16, rcv_data16) |
90 | #else | 90 | #else |
@@ -94,7 +94,7 @@ static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface) | |||
94 | unsigned long flags; | 94 | unsigned long flags; |
95 | 95 | ||
96 | flags = hard_local_irq_save(); | 96 | flags = hard_local_irq_save(); |
97 | ret = iface->regs_base->rcv_data8; | 97 | ret = bfin_read16(&iface->regs_base->rcv_data8); |
98 | hard_local_irq_restore(flags); | 98 | hard_local_irq_restore(flags); |
99 | 99 | ||
100 | return ret; | 100 | return ret; |
@@ -106,7 +106,7 @@ static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface) | |||
106 | unsigned long flags; | 106 | unsigned long flags; |
107 | 107 | ||
108 | flags = hard_local_irq_save(); | 108 | flags = hard_local_irq_save(); |
109 | ret = iface->regs_base->rcv_data16; | 109 | ret = bfin_read16(&iface->regs_base->rcv_data16); |
110 | hard_local_irq_restore(flags); | 110 | hard_local_irq_restore(flags); |
111 | 111 | ||
112 | return ret; | 112 | return ret; |
diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S index 1f9060395a0a..507e7aa6a561 100644 --- a/arch/blackfin/include/asm/context.S +++ b/arch/blackfin/include/asm/context.S | |||
@@ -396,3 +396,12 @@ | |||
396 | call \func; | 396 | call \func; |
397 | #endif | 397 | #endif |
398 | .endm | 398 | .endm |
399 | |||
400 | #if defined(CONFIG_BFIN_SCRATCH_REG_RETN) | ||
401 | # define EX_SCRATCH_REG RETN | ||
402 | #elif defined(CONFIG_BFIN_SCRATCH_REG_RETE) | ||
403 | # define EX_SCRATCH_REG RETE | ||
404 | #else | ||
405 | # define EX_SCRATCH_REG CYCLES | ||
406 | #endif | ||
407 | |||
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h index e91eae8330a6..2673b11376f4 100644 --- a/arch/blackfin/include/asm/dpmc.h +++ b/arch/blackfin/include/asm/dpmc.h | |||
@@ -280,7 +280,7 @@ | |||
280 | PM_POP_SYNC(9) | 280 | PM_POP_SYNC(9) |
281 | #endif | 281 | #endif |
282 | 282 | ||
283 | #ifdef EBIU_AMBCTL | 283 | #ifdef EBIU_AMGCTL |
284 | PM_SYS_POP(9, EBIU_AMBCTL1) | 284 | PM_SYS_POP(9, EBIU_AMBCTL1) |
285 | PM_SYS_POP(8, EBIU_AMBCTL0) | 285 | PM_SYS_POP(8, EBIU_AMBCTL0) |
286 | PM_SYS_POP16(7, EBIU_AMGCTL) | 286 | PM_SYS_POP16(7, EBIU_AMGCTL) |
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index 3d84d96f7c2c..98d0133346b5 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h | |||
@@ -141,6 +141,8 @@ static inline void bfin_pm_standby_restore(void) | |||
141 | 141 | ||
142 | void bfin_gpio_pm_hibernate_restore(void); | 142 | void bfin_gpio_pm_hibernate_restore(void); |
143 | void bfin_gpio_pm_hibernate_suspend(void); | 143 | void bfin_gpio_pm_hibernate_suspend(void); |
144 | void bfin_pint_suspend(void); | ||
145 | void bfin_pint_resume(void); | ||
144 | 146 | ||
145 | # if !BFIN_GPIO_PINT | 147 | # if !BFIN_GPIO_PINT |
146 | int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl); | 148 | int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl); |
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h index 89de539ed010..4ae1144a4578 100644 --- a/arch/blackfin/include/asm/irq.h +++ b/arch/blackfin/include/asm/irq.h | |||
@@ -20,6 +20,16 @@ | |||
20 | /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */ | 20 | /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */ |
21 | #include <mach/irq.h> | 21 | #include <mach/irq.h> |
22 | 22 | ||
23 | /* | ||
24 | * pm save bfin pint registers | ||
25 | */ | ||
26 | struct bfin_pm_pint_save { | ||
27 | u32 mask_set; | ||
28 | u32 assign; | ||
29 | u32 edge_set; | ||
30 | u32 invert_set; | ||
31 | }; | ||
32 | |||
23 | #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) | 33 | #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) |
24 | # define NOP_PAD_ANOMALY_05000244 "nop; nop;" | 34 | # define NOP_PAD_ANOMALY_05000244 "nop; nop;" |
25 | #else | 35 | #else |
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h index 237579935e29..f019e9bcefe9 100644 --- a/arch/blackfin/include/asm/mem_init.h +++ b/arch/blackfin/include/asm/mem_init.h | |||
@@ -6,6 +6,9 @@ | |||
6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
7 | */ | 7 | */ |
8 | 8 | ||
9 | #ifndef __MEM_INIT_H__ | ||
10 | #define __MEM_INIT_H__ | ||
11 | |||
9 | #if defined(EBIU_SDGCTL) | 12 | #if defined(EBIU_SDGCTL) |
10 | #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ | 13 | #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ |
11 | defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ | 14 | defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ |
@@ -277,3 +280,212 @@ | |||
277 | #else | 280 | #else |
278 | #define PLL_BYPASS 0 | 281 | #define PLL_BYPASS 0 |
279 | #endif | 282 | #endif |
283 | |||
284 | #ifdef CONFIG_BF60x | ||
285 | |||
286 | /* DMC status bits */ | ||
287 | #define IDLE 0x1 | ||
288 | #define MEMINITDONE 0x4 | ||
289 | #define SRACK 0x8 | ||
290 | #define PDACK 0x10 | ||
291 | #define DPDACK 0x20 | ||
292 | #define DLLCALDONE 0x2000 | ||
293 | #define PENDREF 0xF0000 | ||
294 | #define PHYRDPHASE 0xF00000 | ||
295 | #define PHYRDPHASE_OFFSET 20 | ||
296 | |||
297 | /* DMC control bits */ | ||
298 | #define LPDDR 0x2 | ||
299 | #define INIT 0x4 | ||
300 | #define SRREQ 0x8 | ||
301 | #define PDREQ 0x10 | ||
302 | #define DPDREQ 0x20 | ||
303 | #define PREC 0x40 | ||
304 | #define ADDRMODE 0x100 | ||
305 | #define RDTOWR 0xE00 | ||
306 | #define PPREF 0x1000 | ||
307 | #define DLLCAL 0x2000 | ||
308 | |||
309 | /* DMC DLL control bits */ | ||
310 | #define DLLCALRDCNT 0xFF | ||
311 | #define DATACYC 0xF00 | ||
312 | #define DATACYC_OFFSET 8 | ||
313 | |||
314 | /* CGU Divisor bits */ | ||
315 | #define CSEL_OFFSET 0 | ||
316 | #define S0SEL_OFFSET 5 | ||
317 | #define SYSSEL_OFFSET 8 | ||
318 | #define S1SEL_OFFSET 13 | ||
319 | #define DSEL_OFFSET 16 | ||
320 | #define OSEL_OFFSET 22 | ||
321 | #define ALGN 0x20000000 | ||
322 | #define UPDT 0x40000000 | ||
323 | #define LOCK 0x80000000 | ||
324 | |||
325 | /* CGU Status bits */ | ||
326 | #define PLLEN 0x1 | ||
327 | #define PLLBP 0x2 | ||
328 | #define PLOCK 0x4 | ||
329 | #define CLKSALGN 0x8 | ||
330 | |||
331 | /* CGU Control bits */ | ||
332 | #define MSEL_MASK 0x7F00 | ||
333 | #define DF_MASK 0x1 | ||
334 | |||
335 | struct ddr_config { | ||
336 | u32 ddr_clk; | ||
337 | u32 dmc_ddrctl; | ||
338 | u32 dmc_ddrcfg; | ||
339 | u32 dmc_ddrtr0; | ||
340 | u32 dmc_ddrtr1; | ||
341 | u32 dmc_ddrtr2; | ||
342 | u32 dmc_ddrmr; | ||
343 | u32 dmc_ddrmr1; | ||
344 | }; | ||
345 | |||
346 | #if defined(CONFIG_MEM_MT47H64M16) | ||
347 | static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = { | ||
348 | [0] = { | ||
349 | .ddr_clk = 125, | ||
350 | .dmc_ddrctl = 0x00000904, | ||
351 | .dmc_ddrcfg = 0x00000422, | ||
352 | .dmc_ddrtr0 = 0x20705212, | ||
353 | .dmc_ddrtr1 = 0x201003CF, | ||
354 | .dmc_ddrtr2 = 0x00320107, | ||
355 | .dmc_ddrmr = 0x00000422, | ||
356 | .dmc_ddrmr1 = 0x4, | ||
357 | }, | ||
358 | [1] = { | ||
359 | .ddr_clk = 133, | ||
360 | .dmc_ddrctl = 0x00000904, | ||
361 | .dmc_ddrcfg = 0x00000422, | ||
362 | .dmc_ddrtr0 = 0x20806313, | ||
363 | .dmc_ddrtr1 = 0x2013040D, | ||
364 | .dmc_ddrtr2 = 0x00320108, | ||
365 | .dmc_ddrmr = 0x00000632, | ||
366 | .dmc_ddrmr1 = 0x4, | ||
367 | }, | ||
368 | [2] = { | ||
369 | .ddr_clk = 150, | ||
370 | .dmc_ddrctl = 0x00000904, | ||
371 | .dmc_ddrcfg = 0x00000422, | ||
372 | .dmc_ddrtr0 = 0x20A07323, | ||
373 | .dmc_ddrtr1 = 0x20160492, | ||
374 | .dmc_ddrtr2 = 0x00320209, | ||
375 | .dmc_ddrmr = 0x00000632, | ||
376 | .dmc_ddrmr1 = 0x4, | ||
377 | }, | ||
378 | [3] = { | ||
379 | .ddr_clk = 166, | ||
380 | .dmc_ddrctl = 0x00000904, | ||
381 | .dmc_ddrcfg = 0x00000422, | ||
382 | .dmc_ddrtr0 = 0x20A07323, | ||
383 | .dmc_ddrtr1 = 0x2016050E, | ||
384 | .dmc_ddrtr2 = 0x00320209, | ||
385 | .dmc_ddrmr = 0x00000632, | ||
386 | .dmc_ddrmr1 = 0x4, | ||
387 | }, | ||
388 | [4] = { | ||
389 | .ddr_clk = 200, | ||
390 | .dmc_ddrctl = 0x00000904, | ||
391 | .dmc_ddrcfg = 0x00000422, | ||
392 | .dmc_ddrtr0 = 0x20a07323, | ||
393 | .dmc_ddrtr1 = 0x2016050f, | ||
394 | .dmc_ddrtr2 = 0x00320509, | ||
395 | .dmc_ddrmr = 0x00000632, | ||
396 | .dmc_ddrmr1 = 0x4, | ||
397 | }, | ||
398 | [5] = { | ||
399 | .ddr_clk = 225, | ||
400 | .dmc_ddrctl = 0x00000904, | ||
401 | .dmc_ddrcfg = 0x00000422, | ||
402 | .dmc_ddrtr0 = 0x20E0A424, | ||
403 | .dmc_ddrtr1 = 0x302006DB, | ||
404 | .dmc_ddrtr2 = 0x0032020D, | ||
405 | .dmc_ddrmr = 0x00000842, | ||
406 | .dmc_ddrmr1 = 0x4, | ||
407 | }, | ||
408 | [6] = { | ||
409 | .ddr_clk = 250, | ||
410 | .dmc_ddrctl = 0x00000904, | ||
411 | .dmc_ddrcfg = 0x00000422, | ||
412 | .dmc_ddrtr0 = 0x20E0A424, | ||
413 | .dmc_ddrtr1 = 0x3020079E, | ||
414 | .dmc_ddrtr2 = 0x0032020D, | ||
415 | .dmc_ddrmr = 0x00000842, | ||
416 | .dmc_ddrmr1 = 0x4, | ||
417 | }, | ||
418 | }; | ||
419 | #endif | ||
420 | |||
421 | static inline void dmc_enter_self_refresh(void) | ||
422 | { | ||
423 | if (bfin_read_DMC0_STAT() & MEMINITDONE) { | ||
424 | bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ); | ||
425 | while (!(bfin_read_DMC0_STAT() & SRACK)) | ||
426 | continue; | ||
427 | } | ||
428 | } | ||
429 | |||
430 | static inline void dmc_exit_self_refresh(void) | ||
431 | { | ||
432 | if (bfin_read_DMC0_STAT() & MEMINITDONE) { | ||
433 | bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ); | ||
434 | while (bfin_read_DMC0_STAT() & SRACK) | ||
435 | continue; | ||
436 | } | ||
437 | } | ||
438 | |||
439 | static inline void init_cgu(u32 cgu_div, u32 cgu_ctl) | ||
440 | { | ||
441 | dmc_enter_self_refresh(); | ||
442 | |||
443 | /* Don't set the same value of MSEL and DF to CGU_CTL */ | ||
444 | if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK)) | ||
445 | != cgu_ctl) { | ||
446 | bfin_write32(CGU0_DIV, cgu_div); | ||
447 | bfin_write32(CGU0_CTL, cgu_ctl); | ||
448 | while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) || | ||
449 | !(bfin_read32(CGU0_STAT) & PLOCK)) | ||
450 | continue; | ||
451 | } | ||
452 | |||
453 | bfin_write32(CGU0_DIV, cgu_div | UPDT); | ||
454 | while (bfin_read32(CGU0_STAT) & CLKSALGN) | ||
455 | continue; | ||
456 | |||
457 | dmc_exit_self_refresh(); | ||
458 | } | ||
459 | |||
460 | static inline void init_dmc(u32 dmc_clk) | ||
461 | { | ||
462 | int i, dlldatacycle, dll_ctl; | ||
463 | |||
464 | for (i = 0; i < 7; i++) { | ||
465 | if (ddr_config_table[i].ddr_clk == dmc_clk) { | ||
466 | bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg); | ||
467 | bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0); | ||
468 | bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1); | ||
469 | bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2); | ||
470 | bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr); | ||
471 | bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1); | ||
472 | bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl); | ||
473 | break; | ||
474 | } | ||
475 | } | ||
476 | |||
477 | while (!(bfin_read_DMC0_STAT() & MEMINITDONE)) | ||
478 | continue; | ||
479 | |||
480 | dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET; | ||
481 | dll_ctl = bfin_read_DMC0_DLLCTL(); | ||
482 | dll_ctl &= ~DATACYC; | ||
483 | bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET)); | ||
484 | |||
485 | while (!(bfin_read_DMC0_STAT() & DLLCALDONE)) | ||
486 | continue; | ||
487 | } | ||
488 | #endif | ||
489 | |||
490 | #endif /*__MEM_INIT_H__*/ | ||
491 | |||
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h index 70c4e511cae6..cec771b8100c 100644 --- a/arch/blackfin/include/asm/traps.h +++ b/arch/blackfin/include/asm/traps.h | |||
@@ -125,5 +125,7 @@ | |||
125 | level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \ | 125 | level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \ |
126 | level " only instructions.\n" | 126 | level " only instructions.\n" |
127 | 127 | ||
128 | extern void double_fault_c(struct pt_regs *fp); | ||
129 | |||
128 | #endif /* __ASSEMBLY__ */ | 130 | #endif /* __ASSEMBLY__ */ |
129 | #endif /* _BFIN_TRAPS_H */ | 131 | #endif /* _BFIN_TRAPS_H */ |
diff --git a/arch/blackfin/kernel/bfin_dma.c b/arch/blackfin/kernel/bfin_dma.c index c166939ffb2b..4a32f2dd5ddc 100644 --- a/arch/blackfin/kernel/bfin_dma.c +++ b/arch/blackfin/kernel/bfin_dma.c | |||
@@ -45,7 +45,7 @@ static int __init blackfin_dma_init(void) | |||
45 | atomic_set(&dma_ch[i].chan_status, 0); | 45 | atomic_set(&dma_ch[i].chan_status, 0); |
46 | dma_ch[i].regs = dma_io_base_addr[i]; | 46 | dma_ch[i].regs = dma_io_base_addr[i]; |
47 | } | 47 | } |
48 | #ifdef CH_MEM_STREAM3_SRC | 48 | #if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x) |
49 | /* Mark MEMDMA Channel 3 as requested since we're using it internally */ | 49 | /* Mark MEMDMA Channel 3 as requested since we're using it internally */ |
50 | request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy"); | 50 | request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy"); |
51 | request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy"); | 51 | request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy"); |
@@ -361,7 +361,7 @@ void __init early_dma_memcpy_done(void) | |||
361 | __builtin_bfin_ssync(); | 361 | __builtin_bfin_ssync(); |
362 | } | 362 | } |
363 | 363 | ||
364 | #ifdef CH_MEM_STREAM3_SRC | 364 | #if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x) |
365 | #define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG | 365 | #define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG |
366 | #define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG | 366 | #define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG |
367 | #define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR | 367 | #define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR |
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 3e366dc2d6e1..34e96ce02aa9 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c | |||
@@ -58,12 +58,20 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) | |||
58 | 58 | ||
59 | #ifdef CONFIG_ROMKERNEL | 59 | #ifdef CONFIG_ROMKERNEL |
60 | /* Cover kernel XIP flash area */ | 60 | /* Cover kernel XIP flash area */ |
61 | #ifdef CONFIG_BF60x | ||
62 | addr = CONFIG_ROM_BASE & ~(16 * 1024 * 1024 - 1); | ||
63 | d_tbl[i_d].addr = addr; | ||
64 | d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_16MB; | ||
65 | i_tbl[i_i].addr = addr; | ||
66 | i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_16MB; | ||
67 | #else | ||
61 | addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1); | 68 | addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1); |
62 | d_tbl[i_d].addr = addr; | 69 | d_tbl[i_d].addr = addr; |
63 | d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB; | 70 | d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB; |
64 | i_tbl[i_i].addr = addr; | 71 | i_tbl[i_i].addr = addr; |
65 | i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB; | 72 | i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB; |
66 | #endif | 73 | #endif |
74 | #endif | ||
67 | 75 | ||
68 | /* Cover L1 memory. One 4M area for code and data each is enough. */ | 76 | /* Cover L1 memory. One 4M area for code and data each is enough. */ |
69 | if (cpu == 0) { | 77 | if (cpu == 0) { |
diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c index f0d1118f1825..e7be6532d6a0 100644 --- a/arch/blackfin/kernel/dma-mapping.c +++ b/arch/blackfin/kernel/dma-mapping.c | |||
@@ -122,12 +122,13 @@ void __dma_sync(dma_addr_t addr, size_t size, | |||
122 | EXPORT_SYMBOL(__dma_sync); | 122 | EXPORT_SYMBOL(__dma_sync); |
123 | 123 | ||
124 | int | 124 | int |
125 | dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | 125 | dma_map_sg(struct device *dev, struct scatterlist *sg_list, int nents, |
126 | enum dma_data_direction direction) | 126 | enum dma_data_direction direction) |
127 | { | 127 | { |
128 | struct scatterlist *sg; | ||
128 | int i; | 129 | int i; |
129 | 130 | ||
130 | for (i = 0; i < nents; i++, sg++) { | 131 | for_each_sg(sg_list, sg, nents, i) { |
131 | sg->dma_address = (dma_addr_t) sg_virt(sg); | 132 | sg->dma_address = (dma_addr_t) sg_virt(sg); |
132 | __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction); | 133 | __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction); |
133 | } | 134 | } |
@@ -136,12 +137,13 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |||
136 | } | 137 | } |
137 | EXPORT_SYMBOL(dma_map_sg); | 138 | EXPORT_SYMBOL(dma_map_sg); |
138 | 139 | ||
139 | void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | 140 | void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg_list, |
140 | int nelems, enum dma_data_direction direction) | 141 | int nelems, enum dma_data_direction direction) |
141 | { | 142 | { |
143 | struct scatterlist *sg; | ||
142 | int i; | 144 | int i; |
143 | 145 | ||
144 | for (i = 0; i < nelems; i++, sg++) { | 146 | for_each_sg(sg_list, sg, nelems, i) { |
145 | sg->dma_address = (dma_addr_t) sg_virt(sg); | 147 | sg->dma_address = (dma_addr_t) sg_virt(sg); |
146 | __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction); | 148 | __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction); |
147 | } | 149 | } |
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index af732eb3a687..fc179ca07799 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c | |||
@@ -114,9 +114,9 @@ static struct musb_hdrc_config musb_config = { | |||
114 | }; | 114 | }; |
115 | 115 | ||
116 | static struct musb_hdrc_platform_data musb_plat = { | 116 | static struct musb_hdrc_platform_data musb_plat = { |
117 | #if defined(CONFIG_USB_MUSB_OTG) | 117 | #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC) |
118 | .mode = MUSB_OTG, | 118 | .mode = MUSB_OTG, |
119 | #elif defined(CONFIG_USB_MUSB_HDRC_HCD) | 119 | #elif defined(CONFIG_USB_MUSB_HDRC) |
120 | .mode = MUSB_HOST, | 120 | .mode = MUSB_HOST, |
121 | #elif defined(CONFIG_USB_GADGET_MUSB_HDRC) | 121 | #elif defined(CONFIG_USB_GADGET_MUSB_HDRC) |
122 | .mode = MUSB_PERIPHERAL, | 122 | .mode = MUSB_PERIPHERAL, |
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index c9d9473a5ab2..5ed654ae66e1 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c | |||
@@ -873,7 +873,7 @@ static struct adf702x_platform_data adf7021_platform_data = { | |||
873 | }; | 873 | }; |
874 | static inline void adf702x_mac_init(void) | 874 | static inline void adf702x_mac_init(void) |
875 | { | 875 | { |
876 | random_ether_addr(adf7021_platform_data.mac_addr); | 876 | eth_random_addr(adf7021_platform_data.mac_addr); |
877 | } | 877 | } |
878 | #else | 878 | #else |
879 | static inline void adf702x_mac_init(void) {} | 879 | static inline void adf702x_mac_init(void) {} |
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 3bd75bae750d..c4d07f040947 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c | |||
@@ -635,9 +635,9 @@ static struct musb_hdrc_config musb_config = { | |||
635 | }; | 635 | }; |
636 | 636 | ||
637 | static struct musb_hdrc_platform_data musb_plat = { | 637 | static struct musb_hdrc_platform_data musb_plat = { |
638 | #if defined(CONFIG_USB_MUSB_OTG) | 638 | #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC) |
639 | .mode = MUSB_OTG, | 639 | .mode = MUSB_OTG, |
640 | #elif defined(CONFIG_USB_MUSB_HDRC_HCD) | 640 | #elif defined(CONFIG_USB_MUSB_HDRC) |
641 | .mode = MUSB_HOST, | 641 | .mode = MUSB_HOST, |
642 | #elif defined(CONFIG_USB_GADGET_MUSB_HDRC) | 642 | #elif defined(CONFIG_USB_GADGET_MUSB_HDRC) |
643 | .mode = MUSB_PERIPHERAL, | 643 | .mode = MUSB_PERIPHERAL, |
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h index 35c8ced46158..be9edb28f96b 100644 --- a/arch/blackfin/mach-bf548/include/mach/gpio.h +++ b/arch/blackfin/mach-bf548/include/mach/gpio.h | |||
@@ -171,6 +171,8 @@ | |||
171 | #define MAX_BLACKFIN_GPIOS 160 | 171 | #define MAX_BLACKFIN_GPIOS 160 |
172 | 172 | ||
173 | #define BFIN_GPIO_PINT 1 | 173 | #define BFIN_GPIO_PINT 1 |
174 | #define NR_PINT_SYS_IRQS 4 | ||
175 | #define NR_PINTS 160 | ||
174 | 176 | ||
175 | #ifndef __ASSEMBLY__ | 177 | #ifndef __ASSEMBLY__ |
176 | 178 | ||
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 838978808a15..7c36777c6455 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c | |||
@@ -452,18 +452,21 @@ static struct v4l2_input adv7183_inputs[] = { | |||
452 | .name = "Composite", | 452 | .name = "Composite", |
453 | .type = V4L2_INPUT_TYPE_CAMERA, | 453 | .type = V4L2_INPUT_TYPE_CAMERA, |
454 | .std = V4L2_STD_ALL, | 454 | .std = V4L2_STD_ALL, |
455 | .capabilities = V4L2_IN_CAP_STD, | ||
455 | }, | 456 | }, |
456 | { | 457 | { |
457 | .index = 1, | 458 | .index = 1, |
458 | .name = "S-Video", | 459 | .name = "S-Video", |
459 | .type = V4L2_INPUT_TYPE_CAMERA, | 460 | .type = V4L2_INPUT_TYPE_CAMERA, |
460 | .std = V4L2_STD_ALL, | 461 | .std = V4L2_STD_ALL, |
462 | .capabilities = V4L2_IN_CAP_STD, | ||
461 | }, | 463 | }, |
462 | { | 464 | { |
463 | .index = 2, | 465 | .index = 2, |
464 | .name = "Component", | 466 | .name = "Component", |
465 | .type = V4L2_INPUT_TYPE_CAMERA, | 467 | .type = V4L2_INPUT_TYPE_CAMERA, |
466 | .std = V4L2_STD_ALL, | 468 | .std = V4L2_STD_ALL, |
469 | .capabilities = V4L2_IN_CAP_STD, | ||
467 | }, | 470 | }, |
468 | }; | 471 | }; |
469 | 472 | ||
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig index 2cb727243778..101b33ee9bba 100644 --- a/arch/blackfin/mach-bf609/Kconfig +++ b/arch/blackfin/mach-bf609/Kconfig | |||
@@ -51,6 +51,14 @@ config PINT5_ASSIGN | |||
51 | 51 | ||
52 | endmenu | 52 | endmenu |
53 | 53 | ||
54 | config SEC_IRQ_PRIORITY_LEVELS | ||
55 | int "SEC interrupt priority levels" | ||
56 | default 7 | ||
57 | range 0 7 | ||
58 | help | ||
59 | Devide the total number of interrupt priority levels into sub-levels. | ||
60 | There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels. | ||
61 | |||
54 | endmenu | 62 | endmenu |
55 | 63 | ||
56 | endif | 64 | endif |
diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile index 2a27f8174543..234fe1b4bb0e 100644 --- a/arch/blackfin/mach-bf609/Makefile +++ b/arch/blackfin/mach-bf609/Makefile | |||
@@ -2,5 +2,5 @@ | |||
2 | # arch/blackfin/mach-bf609/Makefile | 2 | # arch/blackfin/mach-bf609/Makefile |
3 | # | 3 | # |
4 | 4 | ||
5 | obj-y := dma.o clock.o | 5 | obj-y := dma.o clock.o ints-priority.o |
6 | obj-$(CONFIG_PM) += pm.o hibernate.o | 6 | obj-$(CONFIG_PM) += pm.o dpm.o |
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c index ac64f47217c1..c2cf1ae31189 100644 --- a/arch/blackfin/mach-bf609/boards/ezkit.c +++ b/arch/blackfin/mach-bf609/boards/ezkit.c | |||
@@ -677,11 +677,28 @@ int bf609_nor_flash_init(struct platform_device *dev) | |||
677 | return 0; | 677 | return 0; |
678 | } | 678 | } |
679 | 679 | ||
680 | void bf609_nor_flash_exit(struct platform_device *dev) | ||
681 | { | ||
682 | const unsigned short pins[] = { | ||
683 | P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, | ||
684 | P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21, | ||
685 | P_A22, P_A23, P_A24, P_A25, P_NORCK, 0, | ||
686 | }; | ||
687 | |||
688 | peripheral_free_list(pins); | ||
689 | |||
690 | bfin_write32(SMC_GCTL, 0); | ||
691 | } | ||
692 | |||
680 | static struct physmap_flash_data ezkit_flash_data = { | 693 | static struct physmap_flash_data ezkit_flash_data = { |
681 | .width = 2, | 694 | .width = 2, |
682 | .parts = ezkit_partitions, | 695 | .parts = ezkit_partitions, |
683 | .init = bf609_nor_flash_init, | 696 | .init = bf609_nor_flash_init, |
697 | .exit = bf609_nor_flash_exit, | ||
684 | .nr_parts = ARRAY_SIZE(ezkit_partitions), | 698 | .nr_parts = ARRAY_SIZE(ezkit_partitions), |
699 | #ifdef CONFIG_ROMKERNEL | ||
700 | .probe_type = "map_rom", | ||
701 | #endif | ||
685 | }; | 702 | }; |
686 | 703 | ||
687 | static struct resource ezkit_flash_resource = { | 704 | static struct resource ezkit_flash_resource = { |
@@ -739,7 +756,7 @@ static struct bfin6xx_spi_chip spidev_chip_info = { | |||
739 | }; | 756 | }; |
740 | #endif | 757 | #endif |
741 | 758 | ||
742 | #if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE) | 759 | #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) |
743 | static struct platform_device bfin_i2s_pcm = { | 760 | static struct platform_device bfin_i2s_pcm = { |
744 | .name = "bfin-i2s-pcm-audio", | 761 | .name = "bfin-i2s-pcm-audio", |
745 | .id = -1, | 762 | .id = -1, |
@@ -825,6 +842,12 @@ static struct adau1761_platform_data adau1761_info = { | |||
825 | static const unsigned short ppi_req[] = { | 842 | static const unsigned short ppi_req[] = { |
826 | P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, | 843 | P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, |
827 | P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, | 844 | P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, |
845 | P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, | ||
846 | P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, | ||
847 | #if !defined(CONFIG_VIDEO_VS6624) && !defined(CONFIG_VIDEO_VS6624_MODULE) | ||
848 | P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19, | ||
849 | P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23, | ||
850 | #endif | ||
828 | P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, | 851 | P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, |
829 | 0, | 852 | 0, |
830 | }; | 853 | }; |
@@ -855,7 +878,7 @@ static struct bcap_route vs6624_routes[] = { | |||
855 | }, | 878 | }, |
856 | }; | 879 | }; |
857 | 880 | ||
858 | static const unsigned vs6624_ce_pin = GPIO_PD1; | 881 | static const unsigned vs6624_ce_pin = GPIO_PE4; |
859 | 882 | ||
860 | static struct bfin_capture_config bfin_capture_data = { | 883 | static struct bfin_capture_config bfin_capture_data = { |
861 | .card_name = "BF609", | 884 | .card_name = "BF609", |
@@ -871,7 +894,128 @@ static struct bfin_capture_config bfin_capture_data = { | |||
871 | .ppi_info = &ppi_info, | 894 | .ppi_info = &ppi_info, |
872 | .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI | 895 | .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI |
873 | | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656), | 896 | | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656), |
874 | .blank_clocks = 8, | 897 | .blank_pixels = 4, |
898 | }; | ||
899 | #endif | ||
900 | |||
901 | #if defined(CONFIG_VIDEO_ADV7842) \ | ||
902 | || defined(CONFIG_VIDEO_ADV7842_MODULE) | ||
903 | #include <media/adv7842.h> | ||
904 | |||
905 | static struct v4l2_input adv7842_inputs[] = { | ||
906 | { | ||
907 | .index = 0, | ||
908 | .name = "Composite", | ||
909 | .type = V4L2_INPUT_TYPE_CAMERA, | ||
910 | .std = V4L2_STD_ALL, | ||
911 | .capabilities = V4L2_IN_CAP_STD, | ||
912 | }, | ||
913 | { | ||
914 | .index = 1, | ||
915 | .name = "S-Video", | ||
916 | .type = V4L2_INPUT_TYPE_CAMERA, | ||
917 | .std = V4L2_STD_ALL, | ||
918 | .capabilities = V4L2_IN_CAP_STD, | ||
919 | }, | ||
920 | { | ||
921 | .index = 2, | ||
922 | .name = "Component", | ||
923 | .type = V4L2_INPUT_TYPE_CAMERA, | ||
924 | .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS, | ||
925 | }, | ||
926 | { | ||
927 | .index = 3, | ||
928 | .name = "VGA", | ||
929 | .type = V4L2_INPUT_TYPE_CAMERA, | ||
930 | .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS, | ||
931 | }, | ||
932 | { | ||
933 | .index = 4, | ||
934 | .name = "HDMI", | ||
935 | .type = V4L2_INPUT_TYPE_CAMERA, | ||
936 | .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS, | ||
937 | }, | ||
938 | }; | ||
939 | |||
940 | static struct bcap_route adv7842_routes[] = { | ||
941 | { | ||
942 | .input = 3, | ||
943 | .output = 0, | ||
944 | .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL | ||
945 | | EPPI_CTL_ACTIVE656), | ||
946 | }, | ||
947 | { | ||
948 | .input = 4, | ||
949 | .output = 0, | ||
950 | }, | ||
951 | { | ||
952 | .input = 2, | ||
953 | .output = 0, | ||
954 | }, | ||
955 | { | ||
956 | .input = 1, | ||
957 | .output = 0, | ||
958 | }, | ||
959 | { | ||
960 | .input = 0, | ||
961 | .output = 1, | ||
962 | .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16 | ||
963 | | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2 | ||
964 | | EPPI_CTL_SYNC2 | EPPI_CTL_NON656), | ||
965 | }, | ||
966 | }; | ||
967 | |||
968 | static struct adv7842_output_format adv7842_opf[] = { | ||
969 | { | ||
970 | .op_ch_sel = ADV7842_OP_CH_SEL_BRG, | ||
971 | .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8, | ||
972 | .op_656_range = 1, | ||
973 | .blank_data = 1, | ||
974 | .insert_av_codes = 1, | ||
975 | }, | ||
976 | { | ||
977 | .op_ch_sel = ADV7842_OP_CH_SEL_RGB, | ||
978 | .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16, | ||
979 | .op_656_range = 1, | ||
980 | .blank_data = 1, | ||
981 | }, | ||
982 | }; | ||
983 | |||
984 | static struct adv7842_platform_data adv7842_data = { | ||
985 | .opf = adv7842_opf, | ||
986 | .num_opf = ARRAY_SIZE(adv7842_opf), | ||
987 | .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1, | ||
988 | .prim_mode = ADV7842_PRIM_MODE_SDP, | ||
989 | .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1, | ||
990 | .inp_color_space = ADV7842_INP_COLOR_SPACE_AUTO, | ||
991 | .i2c_sdp_io = 0x40, | ||
992 | .i2c_sdp = 0x41, | ||
993 | .i2c_cp = 0x42, | ||
994 | .i2c_vdp = 0x43, | ||
995 | .i2c_afe = 0x44, | ||
996 | .i2c_hdmi = 0x45, | ||
997 | .i2c_repeater = 0x46, | ||
998 | .i2c_edid = 0x47, | ||
999 | .i2c_infoframe = 0x48, | ||
1000 | .i2c_cec = 0x49, | ||
1001 | .i2c_avlink = 0x4a, | ||
1002 | .i2c_ex = 0x26, | ||
1003 | }; | ||
1004 | |||
1005 | static struct bfin_capture_config bfin_capture_data = { | ||
1006 | .card_name = "BF609", | ||
1007 | .inputs = adv7842_inputs, | ||
1008 | .num_inputs = ARRAY_SIZE(adv7842_inputs), | ||
1009 | .routes = adv7842_routes, | ||
1010 | .i2c_adapter_id = 0, | ||
1011 | .board_info = { | ||
1012 | .type = "adv7842", | ||
1013 | .addr = 0x20, | ||
1014 | .platform_data = (void *)&adv7842_data, | ||
1015 | }, | ||
1016 | .ppi_info = &ppi_info, | ||
1017 | .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL | ||
1018 | | EPPI_CTL_ACTIVE656), | ||
875 | }; | 1019 | }; |
876 | #endif | 1020 | #endif |
877 | 1021 | ||
@@ -883,6 +1027,80 @@ static struct platform_device bfin_capture_device = { | |||
883 | }; | 1027 | }; |
884 | #endif | 1028 | #endif |
885 | 1029 | ||
1030 | #if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \ | ||
1031 | || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE) | ||
1032 | #include <linux/videodev2.h> | ||
1033 | #include <media/blackfin/bfin_display.h> | ||
1034 | #include <media/blackfin/ppi.h> | ||
1035 | |||
1036 | static const unsigned short ppi_req_disp[] = { | ||
1037 | P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, | ||
1038 | P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, | ||
1039 | P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, | ||
1040 | P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, | ||
1041 | P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, | ||
1042 | 0, | ||
1043 | }; | ||
1044 | |||
1045 | static const struct ppi_info ppi_info = { | ||
1046 | .type = PPI_TYPE_EPPI3, | ||
1047 | .dma_ch = CH_EPPI0_CH0, | ||
1048 | .irq_err = IRQ_EPPI0_STAT, | ||
1049 | .base = (void __iomem *)EPPI0_STAT, | ||
1050 | .pin_req = ppi_req_disp, | ||
1051 | }; | ||
1052 | |||
1053 | #if defined(CONFIG_VIDEO_ADV7511) \ | ||
1054 | || defined(CONFIG_VIDEO_ADV7511_MODULE) | ||
1055 | #include <media/adv7511.h> | ||
1056 | |||
1057 | static struct v4l2_output adv7511_outputs[] = { | ||
1058 | { | ||
1059 | .index = 0, | ||
1060 | .name = "HDMI", | ||
1061 | .type = V4L2_INPUT_TYPE_CAMERA, | ||
1062 | .capabilities = V4L2_OUT_CAP_CUSTOM_TIMINGS, | ||
1063 | }, | ||
1064 | }; | ||
1065 | |||
1066 | static struct disp_route adv7511_routes[] = { | ||
1067 | { | ||
1068 | .output = 0, | ||
1069 | }, | ||
1070 | }; | ||
1071 | |||
1072 | static struct adv7511_platform_data adv7511_data = { | ||
1073 | .edid_addr = 0x7e, | ||
1074 | .i2c_ex = 0x25, | ||
1075 | }; | ||
1076 | |||
1077 | static struct bfin_display_config bfin_display_data = { | ||
1078 | .card_name = "BF609", | ||
1079 | .outputs = adv7511_outputs, | ||
1080 | .num_outputs = ARRAY_SIZE(adv7511_outputs), | ||
1081 | .routes = adv7511_routes, | ||
1082 | .i2c_adapter_id = 0, | ||
1083 | .board_info = { | ||
1084 | .type = "adv7511", | ||
1085 | .addr = 0x39, | ||
1086 | .platform_data = (void *)&adv7511_data, | ||
1087 | }, | ||
1088 | .ppi_info = &ppi_info, | ||
1089 | .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16 | ||
1090 | | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3 | ||
1091 | | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2 | ||
1092 | | EPPI_CTL_NON656 | EPPI_CTL_DIR), | ||
1093 | }; | ||
1094 | #endif | ||
1095 | |||
1096 | static struct platform_device bfin_display_device = { | ||
1097 | .name = "bfin_display", | ||
1098 | .dev = { | ||
1099 | .platform_data = &bfin_display_data, | ||
1100 | }, | ||
1101 | }; | ||
1102 | #endif | ||
1103 | |||
886 | #if defined(CONFIG_BFIN_CRC) | 1104 | #if defined(CONFIG_BFIN_CRC) |
887 | #define BFIN_CRC_NAME "bfin-crc" | 1105 | #define BFIN_CRC_NAME "bfin-crc" |
888 | 1106 | ||
@@ -947,6 +1165,39 @@ static struct platform_device bfin_crc1_device = { | |||
947 | }; | 1165 | }; |
948 | #endif | 1166 | #endif |
949 | 1167 | ||
1168 | #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC) | ||
1169 | #define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc" | ||
1170 | #define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c | ||
1171 | |||
1172 | static struct resource bfin_crypto_crc_resources[] = { | ||
1173 | { | ||
1174 | .start = REG_CRC0_CTL, | ||
1175 | .end = REG_CRC0_REVID+4, | ||
1176 | .flags = IORESOURCE_MEM, | ||
1177 | }, | ||
1178 | { | ||
1179 | .start = IRQ_CRC0_DCNTEXP, | ||
1180 | .end = IRQ_CRC0_DCNTEXP, | ||
1181 | .flags = IORESOURCE_IRQ, | ||
1182 | }, | ||
1183 | { | ||
1184 | .start = CH_MEM_STREAM0_SRC_CRC0, | ||
1185 | .end = CH_MEM_STREAM0_SRC_CRC0, | ||
1186 | .flags = IORESOURCE_DMA, | ||
1187 | }, | ||
1188 | }; | ||
1189 | |||
1190 | static struct platform_device bfin_crypto_crc_device = { | ||
1191 | .name = BFIN_CRYPTO_CRC_NAME, | ||
1192 | .id = 0, | ||
1193 | .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources), | ||
1194 | .resource = bfin_crypto_crc_resources, | ||
1195 | .dev = { | ||
1196 | .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA, | ||
1197 | }, | ||
1198 | }; | ||
1199 | #endif | ||
1200 | |||
950 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | 1201 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
951 | static const struct ad7877_platform_data bfin_ad7877_ts_info = { | 1202 | static const struct ad7877_platform_data bfin_ad7877_ts_info = { |
952 | .model = 7877, | 1203 | .model = 7877, |
@@ -963,6 +1214,28 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = { | |||
963 | }; | 1214 | }; |
964 | #endif | 1215 | #endif |
965 | 1216 | ||
1217 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
1218 | #include <linux/input.h> | ||
1219 | #include <linux/gpio_keys.h> | ||
1220 | |||
1221 | static struct gpio_keys_button bfin_gpio_keys_table[] = { | ||
1222 | {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"}, | ||
1223 | {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"}, | ||
1224 | }; | ||
1225 | |||
1226 | static struct gpio_keys_platform_data bfin_gpio_keys_data = { | ||
1227 | .buttons = bfin_gpio_keys_table, | ||
1228 | .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), | ||
1229 | }; | ||
1230 | |||
1231 | static struct platform_device bfin_device_gpiokeys = { | ||
1232 | .name = "gpio-keys", | ||
1233 | .dev = { | ||
1234 | .platform_data = &bfin_gpio_keys_data, | ||
1235 | }, | ||
1236 | }; | ||
1237 | #endif | ||
1238 | |||
966 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | 1239 | static struct spi_board_info bfin_spi_board_info[] __initdata = { |
967 | #if defined(CONFIG_MTD_M25P80) \ | 1240 | #if defined(CONFIG_MTD_M25P80) \ |
968 | || defined(CONFIG_MTD_M25P80_MODULE) | 1241 | || defined(CONFIG_MTD_M25P80_MODULE) |
@@ -981,10 +1254,10 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
981 | { | 1254 | { |
982 | .modalias = "ad7877", | 1255 | .modalias = "ad7877", |
983 | .platform_data = &bfin_ad7877_ts_info, | 1256 | .platform_data = &bfin_ad7877_ts_info, |
984 | .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */ | 1257 | .irq = IRQ_PD9, |
985 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | 1258 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ |
986 | .bus_num = 0, | 1259 | .bus_num = 0, |
987 | .chip_select = 2, | 1260 | .chip_select = 4, |
988 | }, | 1261 | }, |
989 | #endif | 1262 | #endif |
990 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | 1263 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) |
@@ -1050,7 +1323,7 @@ static struct resource bfin_spi1_resource[] = { | |||
1050 | 1323 | ||
1051 | /* SPI controller data */ | 1324 | /* SPI controller data */ |
1052 | static struct bfin6xx_spi_master bf60x_spi_master_info0 = { | 1325 | static struct bfin6xx_spi_master bf60x_spi_master_info0 = { |
1053 | .num_chipselect = 4, | 1326 | .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, |
1054 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, | 1327 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, |
1055 | }; | 1328 | }; |
1056 | 1329 | ||
@@ -1065,7 +1338,7 @@ static struct platform_device bf60x_spi_master0 = { | |||
1065 | }; | 1338 | }; |
1066 | 1339 | ||
1067 | static struct bfin6xx_spi_master bf60x_spi_master_info1 = { | 1340 | static struct bfin6xx_spi_master bf60x_spi_master_info1 = { |
1068 | .num_chipselect = 4, | 1341 | .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, |
1069 | .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, | 1342 | .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, |
1070 | }; | 1343 | }; |
1071 | 1344 | ||
@@ -1146,6 +1419,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info0[] = { | |||
1146 | .platform_data = (void *)&adau1761_info | 1419 | .platform_data = (void *)&adau1761_info |
1147 | }, | 1420 | }, |
1148 | #endif | 1421 | #endif |
1422 | #if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE) | ||
1423 | { | ||
1424 | I2C_BOARD_INFO("ssm2602", 0x1b), | ||
1425 | }, | ||
1426 | #endif | ||
1149 | }; | 1427 | }; |
1150 | 1428 | ||
1151 | static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { | 1429 | static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { |
@@ -1261,6 +1539,9 @@ static struct platform_device *ezkit_devices[] __initdata = { | |||
1261 | &bfin_crc0_device, | 1539 | &bfin_crc0_device, |
1262 | &bfin_crc1_device, | 1540 | &bfin_crc1_device, |
1263 | #endif | 1541 | #endif |
1542 | #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC) | ||
1543 | &bfin_crypto_crc_device, | ||
1544 | #endif | ||
1264 | 1545 | ||
1265 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | 1546 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) |
1266 | &bfin_device_gpiokeys, | 1547 | &bfin_device_gpiokeys, |
@@ -1269,7 +1550,7 @@ static struct platform_device *ezkit_devices[] __initdata = { | |||
1269 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | 1550 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
1270 | &ezkit_flash_device, | 1551 | &ezkit_flash_device, |
1271 | #endif | 1552 | #endif |
1272 | #if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE) | 1553 | #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) |
1273 | &bfin_i2s_pcm, | 1554 | &bfin_i2s_pcm, |
1274 | #endif | 1555 | #endif |
1275 | #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \ | 1556 | #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \ |
@@ -1284,6 +1565,11 @@ static struct platform_device *ezkit_devices[] __initdata = { | |||
1284 | || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE) | 1565 | || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE) |
1285 | &bfin_capture_device, | 1566 | &bfin_capture_device, |
1286 | #endif | 1567 | #endif |
1568 | #if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \ | ||
1569 | || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE) | ||
1570 | &bfin_display_device, | ||
1571 | #endif | ||
1572 | |||
1287 | }; | 1573 | }; |
1288 | 1574 | ||
1289 | static int __init ezkit_init(void) | 1575 | static int __init ezkit_init(void) |
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c index 7f8f529693ae..437d56c82281 100644 --- a/arch/blackfin/mach-bf609/clock.c +++ b/arch/blackfin/mach-bf609/clock.c | |||
@@ -97,9 +97,10 @@ int wait_for_pll_align(void) | |||
97 | while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN)); | 97 | while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN)); |
98 | 98 | ||
99 | if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) { | 99 | if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) { |
100 | printk(KERN_DEBUG "fail to align clk\n"); | 100 | printk(KERN_CRIT "fail to align clk\n"); |
101 | return -1; | 101 | return -1; |
102 | } | 102 | } |
103 | |||
103 | return 0; | 104 | return 0; |
104 | } | 105 | } |
105 | 106 | ||
diff --git a/arch/blackfin/mach-bf609/dpm.S b/arch/blackfin/mach-bf609/dpm.S new file mode 100644 index 000000000000..54d50c689db1 --- /dev/null +++ b/arch/blackfin/mach-bf609/dpm.S | |||
@@ -0,0 +1,157 @@ | |||
1 | #include <linux/linkage.h> | ||
2 | #include <asm/blackfin.h> | ||
3 | #include <asm/dpmc.h> | ||
4 | |||
5 | #include <asm/context.S> | ||
6 | |||
7 | #define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) | ||
8 | |||
9 | .section .l1.text | ||
10 | ENTRY(_enter_hibernate) | ||
11 | /* switch stack to L1 scratch, prepare for ddr srfr */ | ||
12 | P0.H = HI(PM_STACK); | ||
13 | P0.L = LO(PM_STACK); | ||
14 | SP = P0; | ||
15 | |||
16 | call _bf609_ddr_sr; | ||
17 | call _bfin_hibernate_syscontrol; | ||
18 | |||
19 | P0.H = HI(DPM0_RESTORE4); | ||
20 | P0.L = LO(DPM0_RESTORE4); | ||
21 | P1.H = _bf609_pm_data; | ||
22 | P1.L = _bf609_pm_data; | ||
23 | [P0] = P1; | ||
24 | |||
25 | P0.H = HI(DPM0_CTL); | ||
26 | P0.L = LO(DPM0_CTL); | ||
27 | R3.H = HI(0x00000010); | ||
28 | R3.L = LO(0x00000010); | ||
29 | |||
30 | bfin_init_pm_bench_cycles; | ||
31 | |||
32 | [P0] = R3; | ||
33 | |||
34 | SSYNC; | ||
35 | ENDPROC(_enter_hibernate) | ||
36 | |||
37 | /* DPM wake up interrupt won't wake up core on bf60x if its core IMASK | ||
38 | * is disabled. This behavior differ from bf5xx serial processor. | ||
39 | */ | ||
40 | ENTRY(_dummy_deepsleep) | ||
41 | [--sp] = SYSCFG; | ||
42 | [--sp] = (R7:0,P5:0); | ||
43 | cli r0; | ||
44 | |||
45 | /* get wake up interrupt ID */ | ||
46 | P0.l = LO(SEC_SCI_BASE + SEC_CSID); | ||
47 | P0.h = HI(SEC_SCI_BASE + SEC_CSID); | ||
48 | R0 = [P0]; | ||
49 | |||
50 | /* ACK wake up interrupt in SEC */ | ||
51 | P1.l = LO(SEC_END); | ||
52 | P1.h = HI(SEC_END); | ||
53 | |||
54 | [P1] = R0; | ||
55 | SSYNC; | ||
56 | |||
57 | /* restore EVT 11 entry */ | ||
58 | p0.h = hi(EVT11); | ||
59 | p0.l = lo(EVT11); | ||
60 | p1.h = _evt_evt11; | ||
61 | p1.l = _evt_evt11; | ||
62 | |||
63 | [p0] = p1; | ||
64 | SSYNC; | ||
65 | |||
66 | (R7:0,P5:0) = [sp++]; | ||
67 | SYSCFG = [sp++]; | ||
68 | RTI; | ||
69 | ENDPROC(_dummy_deepsleep) | ||
70 | |||
71 | ENTRY(_enter_deepsleep) | ||
72 | LINK 0xC; | ||
73 | [--sp] = (R7:0,P5:0); | ||
74 | |||
75 | /* Change EVT 11 entry to dummy handler for wake up event */ | ||
76 | p0.h = hi(EVT11); | ||
77 | p0.l = lo(EVT11); | ||
78 | p1.h = _dummy_deepsleep; | ||
79 | p1.l = _dummy_deepsleep; | ||
80 | |||
81 | [p0] = p1; | ||
82 | |||
83 | P0.H = HI(PM_STACK); | ||
84 | P0.L = LO(PM_STACK); | ||
85 | |||
86 | EX_SCRATCH_REG = SP; | ||
87 | SP = P0; | ||
88 | |||
89 | SSYNC; | ||
90 | |||
91 | /* should put ddr to self refresh mode before sleep */ | ||
92 | call _bf609_ddr_sr; | ||
93 | |||
94 | /* Set DPM controller to deep sleep mode */ | ||
95 | P0.H = HI(DPM0_CTL); | ||
96 | P0.L = LO(DPM0_CTL); | ||
97 | R3.H = HI(0x00000008); | ||
98 | R3.L = LO(0x00000008); | ||
99 | [P0] = R3; | ||
100 | CSYNC; | ||
101 | |||
102 | /* Enable evt 11 in IMASK before idle, otherwise core doesn't wake up. */ | ||
103 | r0.l = 0x800; | ||
104 | r0.h = 0; | ||
105 | sti r0; | ||
106 | SSYNC; | ||
107 | |||
108 | bfin_init_pm_bench_cycles; | ||
109 | |||
110 | /* Fall into deep sleep in idle*/ | ||
111 | idle; | ||
112 | SSYNC; | ||
113 | |||
114 | /* Restore PLL after wake up from deep sleep */ | ||
115 | call _bf609_resume_ccbuf; | ||
116 | |||
117 | /* turn ddr out of self refresh mode */ | ||
118 | call _bf609_ddr_sr_exit; | ||
119 | |||
120 | SP = EX_SCRATCH_REG; | ||
121 | |||
122 | (R7:0,P5:0) = [SP++]; | ||
123 | UNLINK; | ||
124 | RTS; | ||
125 | ENDPROC(_enter_deepsleep) | ||
126 | |||
127 | .section .text | ||
128 | ENTRY(_bf609_hibernate) | ||
129 | bfin_cpu_reg_save; | ||
130 | bfin_core_mmr_save; | ||
131 | |||
132 | P0.H = _bf609_pm_data; | ||
133 | P0.L = _bf609_pm_data; | ||
134 | R1.H = 0xDEAD; | ||
135 | R1.L = 0xBEEF; | ||
136 | R2.H = .Lpm_resume_here; | ||
137 | R2.L = .Lpm_resume_here; | ||
138 | [P0++] = R1; | ||
139 | [P0++] = R2; | ||
140 | [P0++] = SP; | ||
141 | |||
142 | P1.H = _enter_hibernate; | ||
143 | P1.L = _enter_hibernate; | ||
144 | |||
145 | call (P1); | ||
146 | .Lpm_resume_here: | ||
147 | |||
148 | bfin_core_mmr_restore; | ||
149 | bfin_cpu_reg_restore; | ||
150 | |||
151 | [--sp] = RETI; /* Clear Global Interrupt Disable */ | ||
152 | SP += 4; | ||
153 | |||
154 | RTS; | ||
155 | |||
156 | ENDPROC(_bf609_hibernate) | ||
157 | |||
diff --git a/arch/blackfin/mach-bf609/hibernate.S b/arch/blackfin/mach-bf609/hibernate.S deleted file mode 100644 index d37a532519c8..000000000000 --- a/arch/blackfin/mach-bf609/hibernate.S +++ /dev/null | |||
@@ -1,65 +0,0 @@ | |||
1 | #include <linux/linkage.h> | ||
2 | #include <asm/blackfin.h> | ||
3 | #include <asm/dpmc.h> | ||
4 | |||
5 | #define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) | ||
6 | |||
7 | .section .l1.text | ||
8 | ENTRY(_enter_hibernate) | ||
9 | /* switch stack to L1 scratch, prepare for ddr srfr */ | ||
10 | P0.H = HI(PM_STACK); | ||
11 | P0.L = LO(PM_STACK); | ||
12 | SP = P0; | ||
13 | |||
14 | call _bf609_ddr_sr; | ||
15 | call _bfin_hibernate_syscontrol; | ||
16 | |||
17 | P0.H = HI(DPM0_RESTORE4); | ||
18 | P0.L = LO(DPM0_RESTORE4); | ||
19 | P1.H = _bf609_pm_data; | ||
20 | P1.L = _bf609_pm_data; | ||
21 | [P0] = P1; | ||
22 | |||
23 | P0.H = HI(DPM0_CTL); | ||
24 | P0.L = LO(DPM0_CTL); | ||
25 | R3.H = HI(0x00000010); | ||
26 | R3.L = LO(0x00000010); | ||
27 | |||
28 | bfin_init_pm_bench_cycles; | ||
29 | |||
30 | [P0] = R3; | ||
31 | |||
32 | SSYNC; | ||
33 | ENDPROC(_enter_hibernate_mode) | ||
34 | |||
35 | .section .text | ||
36 | ENTRY(_bf609_hibernate) | ||
37 | bfin_cpu_reg_save; | ||
38 | bfin_core_mmr_save; | ||
39 | |||
40 | P0.H = _bf609_pm_data; | ||
41 | P0.L = _bf609_pm_data; | ||
42 | R1.H = 0xDEAD; | ||
43 | R1.L = 0xBEEF; | ||
44 | R2.H = .Lpm_resume_here; | ||
45 | R2.L = .Lpm_resume_here; | ||
46 | [P0++] = R1; | ||
47 | [P0++] = R2; | ||
48 | [P0++] = SP; | ||
49 | |||
50 | P1.H = _enter_hibernate; | ||
51 | P1.L = _enter_hibernate; | ||
52 | |||
53 | call (P1); | ||
54 | .Lpm_resume_here: | ||
55 | |||
56 | bfin_core_mmr_restore; | ||
57 | bfin_cpu_reg_restore; | ||
58 | |||
59 | [--sp] = RETI; /* Clear Global Interrupt Disable */ | ||
60 | SP += 4; | ||
61 | |||
62 | RTS; | ||
63 | |||
64 | ENDPROC(_bf609_hibernate) | ||
65 | |||
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h index bdd39aefb565..7a07374308ac 100644 --- a/arch/blackfin/mach-bf609/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf609/include/mach/anomaly.h | |||
@@ -5,126 +5,99 @@ | |||
5 | * and can be replaced with that version at any time | 5 | * and can be replaced with that version at any time |
6 | * DO NOT EDIT THIS FILE | 6 | * DO NOT EDIT THIS FILE |
7 | * | 7 | * |
8 | * Copyright 2004-2011 Analog Devices Inc. | 8 | * Copyright 2004-2012 Analog Devices Inc. |
9 | * Licensed under the Clear BSD license. | 9 | * Licensed under the Clear BSD license. |
10 | */ | 10 | */ |
11 | 11 | ||
12 | /* This file should be up to date with: | 12 | /* This file should be up to date with: |
13 | * - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List | ||
13 | */ | 14 | */ |
14 | 15 | ||
15 | #if __SILICON_REVISION__ < 0 | 16 | #if __SILICON_REVISION__ < 0 |
16 | # error will not work on BF506 silicon version | 17 | # error will not work on BF609 silicon version |
17 | #endif | 18 | #endif |
18 | 19 | ||
19 | #ifndef _MACH_ANOMALY_H_ | 20 | #ifndef _MACH_ANOMALY_H_ |
20 | #define _MACH_ANOMALY_H_ | 21 | #define _MACH_ANOMALY_H_ |
21 | 22 | ||
22 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | 23 | /* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */ |
23 | #define ANOMALY_05000074 (1) | 24 | #define ANOMALY_16000003 (1) |
24 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | 25 | /* The EPPI Data Enable (DEN) Signal is Not Functional */ |
25 | #define ANOMALY_05000119 (1) | 26 | #define ANOMALY_16000004 (1) |
26 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 27 | /* Using L1 Instruction Cache with Parity Enabled is Unreliable */ |
27 | #define ANOMALY_05000122 (1) | 28 | #define ANOMALY_16000005 (1) |
28 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ | 29 | /* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */ |
29 | #define ANOMALY_05000245 (1) | 30 | #define ANOMALY_16000006 (1) |
30 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ | 31 | /* DDR2 Memory Reads May Fail Intermittently */ |
31 | #define ANOMALY_05000254 (1) | 32 | #define ANOMALY_16000007 (1) |
32 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | 33 | /* Instruction Memory Stalls Can Cause IFLUSH to Fail */ |
33 | #define ANOMALY_05000265 (1) | 34 | #define ANOMALY_16000008 (1) |
34 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | 35 | /* TestSET Instruction Cannot Be Interrupted */ |
35 | #define ANOMALY_05000310 (1) | 36 | #define ANOMALY_16000009 (1) |
36 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ | ||
37 | #define ANOMALY_05000366 (1) | ||
38 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | ||
39 | #define ANOMALY_05000416 (1) | ||
40 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ | ||
41 | #define ANOMALY_05000426 (1) | ||
42 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | 37 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
43 | #define ANOMALY_05000443 (1) | 38 | #define ANOMALY_16000010 (1) |
44 | /* UART IrDA Receiver Fails on Extended Bit Pulses */ | ||
45 | #define ANOMALY_05000447 (1) | ||
46 | /* False Hardware Error when RETI Points to Invalid Memory */ | 39 | /* False Hardware Error when RETI Points to Invalid Memory */ |
47 | #define ANOMALY_05000461 (1) | 40 | #define ANOMALY_16000011 (1) |
48 | /* PLL Latches Incorrect Settings During Reset */ | 41 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ |
49 | #define ANOMALY_05000469 (1) | 42 | #define ANOMALY_16000012 (1) |
50 | /* Incorrect Default MSEL Value in PLL_CTL */ | 43 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
51 | #define ANOMALY_05000472 (1) | 44 | #define ANOMALY_16000013 (1) |
52 | /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ | 45 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
53 | #define ANOMALY_05000473 (1) | 46 | #define ANOMALY_16000014 (1) |
54 | /* TESTSET Instruction Cannot Be Interrupted */ | 47 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
55 | #define ANOMALY_05000477 (1) | 48 | #define ANOMALY_16000015 (1) |
56 | /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ | 49 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ |
57 | #define ANOMALY_05000481 (1) | 50 | #define ANOMALY_16000017 (1) |
58 | /* IFLUSH sucks at life */ | 51 | /* RSI Boot Cleanup Routine Does Not Clear Registers */ |
59 | #define ANOMALY_05000491 (1) | 52 | #define ANOMALY_16000018 (1) |
60 | /* Tempopary anomaly ID for data loss in MMR read operation if interrupted */ | 53 | /* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */ |
61 | #define ANOMALY_05001001 (__SILICON_REVISION__ < 1) | 54 | #define ANOMALY_16000019 (1) |
55 | /* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */ | ||
56 | #define ANOMALY_16000020 (1) | ||
57 | /* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */ | ||
58 | #define ANOMALY_16000021 (1) | ||
59 | /* Boot Code Fails to Enable Parity Fault Detection */ | ||
60 | #define ANOMALY_16000022 (1) | ||
61 | /* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */ | ||
62 | #define ANOMALY_16000027 (1) | ||
63 | /* Interrupted Core Reads of MMRs May Cause Data Loss */ | ||
64 | #define ANOMALY_16000030 (1) | ||
62 | 65 | ||
63 | /* Anomalies that don't exist on this proc */ | 66 | /* Anomalies that don't exist on this proc */ |
64 | #define ANOMALY_05000099 (0) | ||
65 | #define ANOMALY_05000120 (0) | ||
66 | #define ANOMALY_05000125 (0) | ||
67 | #define ANOMALY_05000149 (0) | ||
68 | #define ANOMALY_05000158 (0) | 67 | #define ANOMALY_05000158 (0) |
69 | #define ANOMALY_05000171 (0) | ||
70 | #define ANOMALY_05000179 (0) | ||
71 | #define ANOMALY_05000182 (0) | ||
72 | #define ANOMALY_05000183 (0) | ||
73 | #define ANOMALY_05000189 (0) | 68 | #define ANOMALY_05000189 (0) |
74 | #define ANOMALY_05000198 (0) | 69 | #define ANOMALY_05000198 (0) |
75 | #define ANOMALY_05000202 (0) | ||
76 | #define ANOMALY_05000215 (0) | ||
77 | #define ANOMALY_05000219 (0) | ||
78 | #define ANOMALY_05000220 (0) | 70 | #define ANOMALY_05000220 (0) |
79 | #define ANOMALY_05000227 (0) | ||
80 | #define ANOMALY_05000230 (0) | 71 | #define ANOMALY_05000230 (0) |
81 | #define ANOMALY_05000231 (0) | 72 | #define ANOMALY_05000231 (0) |
82 | #define ANOMALY_05000233 (0) | ||
83 | #define ANOMALY_05000234 (0) | ||
84 | #define ANOMALY_05000242 (0) | ||
85 | #define ANOMALY_05000244 (0) | 73 | #define ANOMALY_05000244 (0) |
86 | #define ANOMALY_05000248 (0) | ||
87 | #define ANOMALY_05000250 (0) | ||
88 | #define ANOMALY_05000257 (0) | ||
89 | #define ANOMALY_05000261 (0) | ||
90 | #define ANOMALY_05000263 (0) | 74 | #define ANOMALY_05000263 (0) |
91 | #define ANOMALY_05000266 (0) | ||
92 | #define ANOMALY_05000273 (0) | 75 | #define ANOMALY_05000273 (0) |
93 | #define ANOMALY_05000274 (0) | 76 | #define ANOMALY_05000274 (0) |
94 | #define ANOMALY_05000278 (0) | 77 | #define ANOMALY_05000278 (0) |
95 | #define ANOMALY_05000281 (0) | 78 | #define ANOMALY_05000281 (0) |
96 | #define ANOMALY_05000283 (0) | ||
97 | #define ANOMALY_05000285 (0) | ||
98 | #define ANOMALY_05000287 (0) | 79 | #define ANOMALY_05000287 (0) |
99 | #define ANOMALY_05000301 (0) | ||
100 | #define ANOMALY_05000305 (0) | ||
101 | #define ANOMALY_05000307 (0) | ||
102 | #define ANOMALY_05000311 (0) | 80 | #define ANOMALY_05000311 (0) |
103 | #define ANOMALY_05000312 (0) | 81 | #define ANOMALY_05000312 (0) |
104 | #define ANOMALY_05000315 (0) | ||
105 | #define ANOMALY_05000323 (0) | 82 | #define ANOMALY_05000323 (0) |
106 | #define ANOMALY_05000353 (1) | ||
107 | #define ANOMALY_05000357 (0) | ||
108 | #define ANOMALY_05000362 (1) | ||
109 | #define ANOMALY_05000363 (0) | 83 | #define ANOMALY_05000363 (0) |
110 | #define ANOMALY_05000364 (0) | ||
111 | #define ANOMALY_05000371 (0) | ||
112 | #define ANOMALY_05000380 (0) | 84 | #define ANOMALY_05000380 (0) |
113 | #define ANOMALY_05000386 (0) | ||
114 | #define ANOMALY_05000389 (0) | ||
115 | #define ANOMALY_05000400 (0) | ||
116 | #define ANOMALY_05000402 (0) | ||
117 | #define ANOMALY_05000412 (0) | ||
118 | #define ANOMALY_05000432 (0) | ||
119 | #define ANOMALY_05000440 (0) | ||
120 | #define ANOMALY_05000448 (0) | 85 | #define ANOMALY_05000448 (0) |
121 | #define ANOMALY_05000456 (0) | ||
122 | #define ANOMALY_05000450 (0) | 86 | #define ANOMALY_05000450 (0) |
123 | #define ANOMALY_05000465 (0) | 87 | #define ANOMALY_05000456 (0) |
124 | #define ANOMALY_05000467 (0) | ||
125 | #define ANOMALY_05000474 (0) | ||
126 | #define ANOMALY_05000475 (0) | ||
127 | #define ANOMALY_05000480 (0) | 88 | #define ANOMALY_05000480 (0) |
128 | #define ANOMALY_05000485 (0) | 89 | #define ANOMALY_05000481 (1) |
90 | |||
91 | /* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */ | ||
92 | #define ANOMALY_05000491 ANOMALY_16000008 | ||
93 | #define ANOMALY_05000477 ANOMALY_16000009 | ||
94 | #define ANOMALY_05000443 ANOMALY_16000010 | ||
95 | #define ANOMALY_05000461 ANOMALY_16000011 | ||
96 | #define ANOMALY_05000426 ANOMALY_16000012 | ||
97 | #define ANOMALY_05000310 ANOMALY_16000013 | ||
98 | #define ANOMALY_05000245 ANOMALY_16000014 | ||
99 | #define ANOMALY_05000074 ANOMALY_16000015 | ||
100 | #define ANOMALY_05000416 ANOMALY_16000017 | ||
101 | |||
129 | 102 | ||
130 | #endif | 103 | #endif |
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h index 6aac38544cc9..f1a6afae1a71 100644 --- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h +++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h | |||
@@ -2665,7 +2665,6 @@ | |||
2665 | #define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */ | 2665 | #define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */ |
2666 | #define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */ | 2666 | #define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */ |
2667 | 2667 | ||
2668 | |||
2669 | /* ========================= | 2668 | /* ========================= |
2670 | L2CTL Registers | 2669 | L2CTL Registers |
2671 | ========================= */ | 2670 | ========================= */ |
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h index 127586b1e04a..c32c8cc8db2e 100644 --- a/arch/blackfin/mach-bf609/include/mach/gpio.h +++ b/arch/blackfin/mach-bf609/include/mach/gpio.h | |||
@@ -123,6 +123,8 @@ | |||
123 | 123 | ||
124 | 124 | ||
125 | #define BFIN_GPIO_PINT 1 | 125 | #define BFIN_GPIO_PINT 1 |
126 | #define NR_PINT_SYS_IRQS 6 | ||
127 | #define NR_PINTS 112 | ||
126 | 128 | ||
127 | 129 | ||
128 | #ifndef __ASSEMBLY__ | 130 | #ifndef __ASSEMBLY__ |
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h index 0004552433b2..23e74cdeeee8 100644 --- a/arch/blackfin/mach-bf609/include/mach/irq.h +++ b/arch/blackfin/mach-bf609/include/mach/irq.h | |||
@@ -293,9 +293,13 @@ | |||
293 | 293 | ||
294 | #define NR_MACH_IRQS (IRQ_PG15 + 1) | 294 | #define NR_MACH_IRQS (IRQ_PG15 + 1) |
295 | 295 | ||
296 | #define SEC_SCTL_PRIO_OFFSET 8 | ||
297 | |||
296 | #ifndef __ASSEMBLY__ | 298 | #ifndef __ASSEMBLY__ |
297 | #include <linux/types.h> | 299 | #include <linux/types.h> |
298 | 300 | ||
301 | extern u8 sec_int_priority[]; | ||
302 | |||
299 | /* | 303 | /* |
300 | * bfin pint registers layout | 304 | * bfin pint registers layout |
301 | */ | 305 | */ |
diff --git a/arch/blackfin/mach-bf609/include/mach/pm.h b/arch/blackfin/mach-bf609/include/mach/pm.h index 036d9bdc889e..3ca0fb965636 100644 --- a/arch/blackfin/mach-bf609/include/mach/pm.h +++ b/arch/blackfin/mach-bf609/include/mach/pm.h | |||
@@ -11,11 +11,14 @@ | |||
11 | 11 | ||
12 | #include <linux/suspend.h> | 12 | #include <linux/suspend.h> |
13 | 13 | ||
14 | int bfin609_pm_enter(suspend_state_t state); | 14 | extern int bfin609_pm_enter(suspend_state_t state); |
15 | int bf609_pm_prepare(void); | 15 | extern int bf609_pm_prepare(void); |
16 | void bf609_pm_finish(void); | 16 | extern void bf609_pm_finish(void); |
17 | 17 | ||
18 | void bf609_hibernate(void); | 18 | void bf609_hibernate(void); |
19 | void bfin_sec_raise_irq(unsigned int sid); | 19 | void bfin_sec_raise_irq(unsigned int sid); |
20 | void coreb_enable(void); | 20 | void coreb_enable(void); |
21 | |||
22 | int bf609_nor_flash_init(void); | ||
23 | void bf609_nor_flash_exit(void); | ||
21 | #endif | 24 | #endif |
diff --git a/arch/blackfin/mach-bf609/ints-priority.c b/arch/blackfin/mach-bf609/ints-priority.c new file mode 100644 index 000000000000..f68abb9aa79e --- /dev/null +++ b/arch/blackfin/mach-bf609/ints-priority.c | |||
@@ -0,0 +1,156 @@ | |||
1 | /* | ||
2 | * Copyright 2007-2008 Analog Devices Inc. | ||
3 | * | ||
4 | * Licensed under the GPL-2 or later. | ||
5 | * | ||
6 | * Set up the interrupt priorities | ||
7 | */ | ||
8 | |||
9 | #include <linux/module.h> | ||
10 | #include <linux/irq.h> | ||
11 | #include <asm/blackfin.h> | ||
12 | |||
13 | u8 sec_int_priority[] = { | ||
14 | 255, /* IRQ_SEC_ERR */ | ||
15 | 255, /* IRQ_CGU_EVT */ | ||
16 | 254, /* IRQ_WATCH0 */ | ||
17 | 254, /* IRQ_WATCH1 */ | ||
18 | 253, /* IRQ_L2CTL0_ECC_ERR */ | ||
19 | 253, /* IRQ_L2CTL0_ECC_WARN */ | ||
20 | 253, /* IRQ_C0_DBL_FAULT */ | ||
21 | 253, /* IRQ_C1_DBL_FAULT */ | ||
22 | 252, /* IRQ_C0_HW_ERR */ | ||
23 | 252, /* IRQ_C1_HW_ERR */ | ||
24 | 255, /* IRQ_C0_NMI_L1_PARITY_ERR */ | ||
25 | 255, /* IRQ_C1_NMI_L1_PARITY_ERR */ | ||
26 | |||
27 | 50, /* IRQ_TIMER0 */ | ||
28 | 50, /* IRQ_TIMER1 */ | ||
29 | 50, /* IRQ_TIMER2 */ | ||
30 | 50, /* IRQ_TIMER3 */ | ||
31 | 50, /* IRQ_TIMER4 */ | ||
32 | 50, /* IRQ_TIMER5 */ | ||
33 | 50, /* IRQ_TIMER6 */ | ||
34 | 50, /* IRQ_TIMER7 */ | ||
35 | 50, /* IRQ_TIMER_STAT */ | ||
36 | 0, /* IRQ_PINT0 */ | ||
37 | 0, /* IRQ_PINT1 */ | ||
38 | 0, /* IRQ_PINT2 */ | ||
39 | 0, /* IRQ_PINT3 */ | ||
40 | 0, /* IRQ_PINT4 */ | ||
41 | 0, /* IRQ_PINT5 */ | ||
42 | 0, /* IRQ_CNT */ | ||
43 | 50, /* RQ_PWM0_TRIP */ | ||
44 | 50, /* IRQ_PWM0_SYNC */ | ||
45 | 50, /* IRQ_PWM1_TRIP */ | ||
46 | 50, /* IRQ_PWM1_SYNC */ | ||
47 | 0, /* IRQ_TWI0 */ | ||
48 | 0, /* IRQ_TWI1 */ | ||
49 | 10, /* IRQ_SOFT0 */ | ||
50 | 10, /* IRQ_SOFT1 */ | ||
51 | 10, /* IRQ_SOFT2 */ | ||
52 | 10, /* IRQ_SOFT3 */ | ||
53 | 0, /* IRQ_ACM_EVT_MISS */ | ||
54 | 0, /* IRQ_ACM_EVT_COMPLETE */ | ||
55 | 0, /* IRQ_CAN0_RX */ | ||
56 | 0, /* IRQ_CAN0_TX */ | ||
57 | 0, /* IRQ_CAN0_STAT */ | ||
58 | 100, /* IRQ_SPORT0_TX */ | ||
59 | 100, /* IRQ_SPORT0_TX_STAT */ | ||
60 | 100, /* IRQ_SPORT0_RX */ | ||
61 | 100, /* IRQ_SPORT0_RX_STAT */ | ||
62 | 100, /* IRQ_SPORT1_TX */ | ||
63 | 100, /* IRQ_SPORT1_TX_STAT */ | ||
64 | 100, /* IRQ_SPORT1_RX */ | ||
65 | 100, /* IRQ_SPORT1_RX_STAT */ | ||
66 | 100, /* IRQ_SPORT2_TX */ | ||
67 | 100, /* IRQ_SPORT2_TX_STAT */ | ||
68 | 100, /* IRQ_SPORT2_RX */ | ||
69 | 100, /* IRQ_SPORT2_RX_STAT */ | ||
70 | 0, /* IRQ_SPI0_TX */ | ||
71 | 0, /* IRQ_SPI0_RX */ | ||
72 | 0, /* IRQ_SPI0_STAT */ | ||
73 | 0, /* IRQ_SPI1_TX */ | ||
74 | 0, /* IRQ_SPI1_RX */ | ||
75 | 0, /* IRQ_SPI1_STAT */ | ||
76 | 0, /* IRQ_RSI */ | ||
77 | 0, /* IRQ_RSI_INT0 */ | ||
78 | 0, /* IRQ_RSI_INT1 */ | ||
79 | 0, /* DMA11 Data (SDU) */ | ||
80 | 0, /* DMA12 Data (Reserved) */ | ||
81 | 0, /* Reserved */ | ||
82 | 0, /* Reserved */ | ||
83 | 30, /* IRQ_EMAC0_STAT */ | ||
84 | 0, /* EMAC0 Power (Reserved) */ | ||
85 | 30, /* IRQ_EMAC1_STAT */ | ||
86 | 0, /* EMAC1 Power (Reserved) */ | ||
87 | 0, /* IRQ_LP0 */ | ||
88 | 0, /* IRQ_LP0_STAT */ | ||
89 | 0, /* IRQ_LP1 */ | ||
90 | 0, /* IRQ_LP1_STAT */ | ||
91 | 0, /* IRQ_LP2 */ | ||
92 | 0, /* IRQ_LP2_STAT */ | ||
93 | 0, /* IRQ_LP3 */ | ||
94 | 0, /* IRQ_LP3_STAT */ | ||
95 | 0, /* IRQ_UART0_TX */ | ||
96 | 0, /* IRQ_UART0_RX */ | ||
97 | 0, /* IRQ_UART0_STAT */ | ||
98 | 0, /* IRQ_UART1_TX */ | ||
99 | 0, /* IRQ_UART1_RX */ | ||
100 | 0, /* IRQ_UART1_STAT */ | ||
101 | 0, /* IRQ_MDMA0_SRC_CRC0 */ | ||
102 | 0, /* IRQ_MDMA0_DEST_CRC0 */ | ||
103 | 0, /* IRQ_CRC0_DCNTEXP */ | ||
104 | 0, /* IRQ_CRC0_ERR */ | ||
105 | 0, /* IRQ_MDMA1_SRC_CRC1 */ | ||
106 | 0, /* IRQ_MDMA1_DEST_CRC1 */ | ||
107 | 0, /* IRQ_CRC1_DCNTEXP */ | ||
108 | 0, /* IRQ_CRC1_ERR */ | ||
109 | 0, /* IRQ_MDMA2_SRC */ | ||
110 | 0, /* IRQ_MDMA2_DEST */ | ||
111 | 0, /* IRQ_MDMA3_SRC */ | ||
112 | 0, /* IRQ_MDMA3_DEST */ | ||
113 | 120, /* IRQ_EPPI0_CH0 */ | ||
114 | 120, /* IRQ_EPPI0_CH1 */ | ||
115 | 120, /* IRQ_EPPI0_STAT */ | ||
116 | 120, /* IRQ_EPPI2_CH0 */ | ||
117 | 120, /* IRQ_EPPI2_CH1 */ | ||
118 | 120, /* IRQ_EPPI2_STAT */ | ||
119 | 120, /* IRQ_EPPI1_CH0 */ | ||
120 | 120, /* IRQ_EPPI1_CH1 */ | ||
121 | 120, /* IRQ_EPPI1_STAT */ | ||
122 | 120, /* IRQ_PIXC_CH0 */ | ||
123 | 120, /* IRQ_PIXC_CH1 */ | ||
124 | 120, /* IRQ_PIXC_CH2 */ | ||
125 | 120, /* IRQ_PIXC_STAT */ | ||
126 | 120, /* IRQ_PVP_CPDOB */ | ||
127 | 120, /* IRQ_PVP_CPDOC */ | ||
128 | 120, /* IRQ_PVP_CPSTAT */ | ||
129 | 120, /* IRQ_PVP_CPCI */ | ||
130 | 120, /* IRQ_PVP_STAT0 */ | ||
131 | 120, /* IRQ_PVP_MPDO */ | ||
132 | 120, /* IRQ_PVP_MPDI */ | ||
133 | 120, /* IRQ_PVP_MPSTAT */ | ||
134 | 120, /* IRQ_PVP_MPCI */ | ||
135 | 120, /* IRQ_PVP_CPDOA */ | ||
136 | 120, /* IRQ_PVP_STAT1 */ | ||
137 | 0, /* IRQ_USB_STAT */ | ||
138 | 0, /* IRQ_USB_DMA */ | ||
139 | 0, /* IRQ_TRU_INT0 */ | ||
140 | 0, /* IRQ_TRU_INT1 */ | ||
141 | 0, /* IRQ_TRU_INT2 */ | ||
142 | 0, /* IRQ_TRU_INT3 */ | ||
143 | 0, /* IRQ_DMAC0_ERROR */ | ||
144 | 0, /* IRQ_CGU0_ERROR */ | ||
145 | 0, /* Reserved */ | ||
146 | 0, /* IRQ_DPM */ | ||
147 | 0, /* Reserved */ | ||
148 | 0, /* IRQ_SWU0 */ | ||
149 | 0, /* IRQ_SWU1 */ | ||
150 | 0, /* IRQ_SWU2 */ | ||
151 | 0, /* IRQ_SWU3 */ | ||
152 | 0, /* IRQ_SWU4 */ | ||
153 | 0, /* IRQ_SWU4 */ | ||
154 | 0, /* IRQ_SWU6 */ | ||
155 | }; | ||
156 | |||
diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c index b76966eb16ad..dacafc163f76 100644 --- a/arch/blackfin/mach-bf609/pm.c +++ b/arch/blackfin/mach-bf609/pm.c | |||
@@ -11,13 +11,14 @@ | |||
11 | #include <linux/interrupt.h> | 11 | #include <linux/interrupt.h> |
12 | #include <linux/gpio.h> | 12 | #include <linux/gpio.h> |
13 | #include <linux/irq.h> | 13 | #include <linux/irq.h> |
14 | |||
15 | #include <linux/delay.h> | 14 | #include <linux/delay.h> |
15 | #include <linux/syscore_ops.h> | ||
16 | 16 | ||
17 | #include <asm/dpmc.h> | 17 | #include <asm/dpmc.h> |
18 | #include <asm/pm.h> | 18 | #include <asm/pm.h> |
19 | #include <mach/pm.h> | 19 | #include <mach/pm.h> |
20 | #include <asm/blackfin.h> | 20 | #include <asm/blackfin.h> |
21 | #include <asm/mem_init.h> | ||
21 | 22 | ||
22 | /***********************************************************/ | 23 | /***********************************************************/ |
23 | /* */ | 24 | /* */ |
@@ -132,60 +133,30 @@ void bfin_cpu_suspend(void) | |||
132 | } | 133 | } |
133 | 134 | ||
134 | __attribute__((l1_text)) | 135 | __attribute__((l1_text)) |
135 | void bfin_deepsleep(unsigned long mask) | 136 | void bf609_ddr_sr(void) |
136 | { | 137 | { |
137 | uint32_t dpm0_ctl; | 138 | dmc_enter_self_refresh(); |
138 | |||
139 | bfin_write32(DPM0_WAKE_EN, 0x10); | ||
140 | bfin_write32(DPM0_WAKE_POL, 0x10); | ||
141 | dpm0_ctl = 0x00000008; | ||
142 | bfin_write32(DPM0_CTL, dpm0_ctl); | ||
143 | SSYNC(); | ||
144 | __asm__ __volatile__( \ | ||
145 | ".align 8;" \ | ||
146 | "idle;" \ | ||
147 | : : \ | ||
148 | ); | ||
149 | #ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH | ||
150 | __asm__ __volatile__( | ||
151 | "R0 = 0;" | ||
152 | "CYCLES = R0;" | ||
153 | "CYCLES2 = R0;" | ||
154 | "R0 = SYSCFG;" | ||
155 | "BITSET(R0, 1);" | ||
156 | "SYSCFG = R0;" | ||
157 | : : : "R0" | ||
158 | ); | ||
159 | #endif | ||
160 | |||
161 | } | 139 | } |
162 | 140 | ||
163 | __attribute__((l1_text)) | 141 | __attribute__((l1_text)) |
164 | void bf609_ddr_sr(void) | 142 | void bf609_ddr_sr_exit(void) |
165 | { | 143 | { |
166 | uint32_t reg; | 144 | dmc_exit_self_refresh(); |
167 | |||
168 | reg = bfin_read_DMC0_CTL(); | ||
169 | reg |= 0x8; | ||
170 | bfin_write_DMC0_CTL(reg); | ||
171 | 145 | ||
172 | while (!(bfin_read_DMC0_STAT() & 0x8)) | 146 | /* After wake up from deep sleep and exit DDR from self refress mode, |
147 | * should wait till CGU PLL is locked. | ||
148 | */ | ||
149 | while (bfin_read32(CGU0_STAT) & CLKSALGN) | ||
173 | continue; | 150 | continue; |
174 | } | 151 | } |
175 | 152 | ||
176 | __attribute__((l1_text)) | 153 | __attribute__((l1_text)) |
177 | void bf609_ddr_sr_exit(void) | 154 | void bf609_resume_ccbuf(void) |
178 | { | 155 | { |
179 | uint32_t reg; | 156 | bfin_write32(DPM0_CCBF_EN, 3); |
180 | while (!(bfin_read_DMC0_STAT() & 0x1)) | 157 | bfin_write32(DPM0_CTL, 2); |
181 | continue; | ||
182 | 158 | ||
183 | reg = bfin_read_DMC0_CTL(); | 159 | while ((bfin_read32(DPM0_STAT) & 0xf) != 1); |
184 | reg &= ~0x8; | ||
185 | bfin_write_DMC0_CTL(reg); | ||
186 | |||
187 | while ((bfin_read_DMC0_STAT() & 0x8)) | ||
188 | continue; | ||
189 | } | 160 | } |
190 | 161 | ||
191 | __attribute__((l1_text)) | 162 | __attribute__((l1_text)) |
@@ -203,20 +174,25 @@ void bfin_hibernate_syscontrol(void) | |||
203 | bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4); | 174 | bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4); |
204 | } | 175 | } |
205 | 176 | ||
206 | #ifndef CONFIG_BF60x | 177 | #define IRQ_SID(irq) ((irq) - IVG15) |
207 | # define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) | 178 | asmlinkage void enter_deepsleep(void); |
208 | #else | 179 | |
209 | # define SIC_SYSIRQ(irq) ((irq) - IVG15) | 180 | __attribute__((l1_text)) |
210 | #endif | 181 | void bfin_deepsleep(unsigned long mask, unsigned long pol_mask) |
211 | void bfin_hibernate(unsigned long mask) | ||
212 | { | 182 | { |
213 | bfin_write32(DPM0_WAKE_EN, 0x10); | 183 | bfin_write32(DPM0_WAKE_EN, mask); |
214 | bfin_write32(DPM0_WAKE_POL, 0x10); | 184 | bfin_write32(DPM0_WAKE_POL, pol_mask); |
185 | SSYNC(); | ||
186 | enter_deepsleep(); | ||
187 | } | ||
188 | |||
189 | void bfin_hibernate(unsigned long mask, unsigned long pol_mask) | ||
190 | { | ||
191 | bfin_write32(DPM0_WAKE_EN, mask); | ||
192 | bfin_write32(DPM0_WAKE_POL, pol_mask); | ||
215 | bfin_write32(DPM0_PGCNTR, 0x0000FFFF); | 193 | bfin_write32(DPM0_PGCNTR, 0x0000FFFF); |
216 | bfin_write32(DPM0_HIB_DIS, 0xFFFF); | 194 | bfin_write32(DPM0_HIB_DIS, 0xFFFF); |
217 | 195 | ||
218 | printk(KERN_DEBUG "hibernate: restore %x pgcnt %x\n", bfin_read32(DPM0_RESTORE0), bfin_read32(DPM0_PGCNTR)); | ||
219 | |||
220 | bf609_hibernate(); | 196 | bf609_hibernate(); |
221 | } | 197 | } |
222 | 198 | ||
@@ -290,10 +266,11 @@ void bf609_cpu_pm_enter(suspend_state_t state) | |||
290 | printk(KERN_DEBUG "Unable to get irq wake\n"); | 266 | printk(KERN_DEBUG "Unable to get irq wake\n"); |
291 | 267 | ||
292 | if (state == PM_SUSPEND_STANDBY) | 268 | if (state == PM_SUSPEND_STANDBY) |
293 | bfin_deepsleep(wakeup); | 269 | bfin_deepsleep(wakeup, wakeup_pol); |
294 | else { | 270 | else { |
295 | bfin_hibernate(wakeup); | 271 | bfin_hibernate(wakeup, wakeup_pol); |
296 | } | 272 | } |
273 | |||
297 | } | 274 | } |
298 | 275 | ||
299 | int bf609_cpu_pm_prepare(void) | 276 | int bf609_cpu_pm_prepare(void) |
@@ -312,20 +289,36 @@ static struct bfin_cpu_pm_fns bf609_cpu_pm = { | |||
312 | .finish = bf609_cpu_pm_finish, | 289 | .finish = bf609_cpu_pm_finish, |
313 | }; | 290 | }; |
314 | 291 | ||
292 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
293 | static int smc_pm_syscore_suspend(void) | ||
294 | { | ||
295 | bf609_nor_flash_exit(); | ||
296 | return 0; | ||
297 | } | ||
298 | |||
299 | static void smc_pm_syscore_resume(void) | ||
300 | { | ||
301 | bf609_nor_flash_init(); | ||
302 | } | ||
303 | |||
304 | static struct syscore_ops smc_pm_syscore_ops = { | ||
305 | .suspend = smc_pm_syscore_suspend, | ||
306 | .resume = smc_pm_syscore_resume, | ||
307 | }; | ||
308 | #endif | ||
309 | |||
315 | static irqreturn_t test_isr(int irq, void *dev_id) | 310 | static irqreturn_t test_isr(int irq, void *dev_id) |
316 | { | 311 | { |
317 | printk(KERN_DEBUG "gpio irq %d\n", irq); | 312 | printk(KERN_DEBUG "gpio irq %d\n", irq); |
313 | if (irq == 231) | ||
314 | bfin_sec_raise_irq(IRQ_SID(IRQ_SOFT1)); | ||
318 | return IRQ_HANDLED; | 315 | return IRQ_HANDLED; |
319 | } | 316 | } |
320 | 317 | ||
321 | static irqreturn_t dpm0_isr(int irq, void *dev_id) | 318 | static irqreturn_t dpm0_isr(int irq, void *dev_id) |
322 | { | 319 | { |
323 | uint32_t wake_stat; | 320 | bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT)); |
324 | 321 | bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT)); | |
325 | wake_stat = bfin_read32(DPM0_WAKE_STAT); | ||
326 | printk(KERN_DEBUG "enter %s wake stat %08x\n", __func__, wake_stat); | ||
327 | |||
328 | bfin_write32(DPM0_WAKE_STAT, wake_stat); | ||
329 | return IRQ_HANDLED; | 322 | return IRQ_HANDLED; |
330 | } | 323 | } |
331 | 324 | ||
@@ -334,7 +327,11 @@ static int __init bf609_init_pm(void) | |||
334 | int irq; | 327 | int irq; |
335 | int error; | 328 | int error; |
336 | 329 | ||
337 | #if CONFIG_PM_BFIN_WAKE_PE12 | 330 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
331 | register_syscore_ops(&smc_pm_syscore_ops); | ||
332 | #endif | ||
333 | |||
334 | #ifdef CONFIG_PM_BFIN_WAKE_PE12 | ||
338 | irq = gpio_to_irq(GPIO_PE12); | 335 | irq = gpio_to_irq(GPIO_PE12); |
339 | if (irq < 0) { | 336 | if (irq < 0) { |
340 | error = irq; | 337 | error = irq; |
@@ -342,16 +339,19 @@ static int __init bf609_init_pm(void) | |||
342 | GPIO_PE12, error); | 339 | GPIO_PE12, error); |
343 | } | 340 | } |
344 | 341 | ||
345 | error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "gpiope12", NULL); | 342 | error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND |
343 | | IRQF_FORCE_RESUME, "gpiope12", NULL); | ||
346 | if(error < 0) | 344 | if(error < 0) |
347 | printk(KERN_DEBUG "Unable to get irq\n"); | 345 | printk(KERN_DEBUG "Unable to get irq\n"); |
348 | #endif | 346 | #endif |
349 | 347 | ||
350 | error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL); | 348 | error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND | |
349 | IRQF_FORCE_RESUME, "cgu0 event", NULL); | ||
351 | if(error < 0) | 350 | if(error < 0) |
352 | printk(KERN_DEBUG "Unable to get irq\n"); | 351 | printk(KERN_DEBUG "Unable to get irq\n"); |
353 | 352 | ||
354 | error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL); | 353 | error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND | |
354 | IRQF_FORCE_RESUME, "dpm0 event", NULL); | ||
355 | if (error < 0) | 355 | if (error < 0) |
356 | printk(KERN_DEBUG "Unable to get irq\n"); | 356 | printk(KERN_DEBUG "Unable to get irq\n"); |
357 | 357 | ||
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c index 7ad2407d1571..2308ce52f849 100644 --- a/arch/blackfin/mach-common/clocks-init.c +++ b/arch/blackfin/mach-common/clocks-init.c | |||
@@ -16,23 +16,14 @@ | |||
16 | #include <asm/dpmc.h> | 16 | #include <asm/dpmc.h> |
17 | 17 | ||
18 | #ifdef CONFIG_BF60x | 18 | #ifdef CONFIG_BF60x |
19 | #define CSEL_P 0 | ||
20 | #define S0SEL_P 5 | ||
21 | #define SYSSEL_P 8 | ||
22 | #define S1SEL_P 13 | ||
23 | #define DSEL_P 16 | ||
24 | #define OSEL_P 22 | ||
25 | #define ALGN_P 29 | ||
26 | #define UPDT_P 30 | ||
27 | #define LOCK_P 31 | ||
28 | 19 | ||
29 | #define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF) | 20 | #define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF) |
30 | #define CGU_DIV_VAL \ | 21 | #define CGU_DIV_VAL \ |
31 | ((CONFIG_CCLK_DIV << CSEL_P) | \ | 22 | ((CONFIG_CCLK_DIV << CSEL_OFFSET) | \ |
32 | (CONFIG_SCLK_DIV << SYSSEL_P) | \ | 23 | (CONFIG_SCLK_DIV << SYSSEL_OFFSET) | \ |
33 | (CONFIG_SCLK0_DIV << S0SEL_P) | \ | 24 | (CONFIG_SCLK0_DIV << S0SEL_OFFSET) | \ |
34 | (CONFIG_SCLK1_DIV << S1SEL_P) | \ | 25 | (CONFIG_SCLK1_DIV << S1SEL_OFFSET) | \ |
35 | (CONFIG_DCLK_DIV << DSEL_P)) | 26 | (CONFIG_DCLK_DIV << DSEL_OFFSET)) |
36 | 27 | ||
37 | #define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000) | 28 | #define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000) |
38 | #if ((CONFIG_BFIN_DCLK != 125) && \ | 29 | #if ((CONFIG_BFIN_DCLK != 125) && \ |
@@ -41,89 +32,7 @@ | |||
41 | (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250)) | 32 | (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250)) |
42 | #error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz" | 33 | #error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz" |
43 | #endif | 34 | #endif |
44 | struct ddr_config { | ||
45 | u32 ddr_clk; | ||
46 | u32 dmc_ddrctl; | ||
47 | u32 dmc_ddrcfg; | ||
48 | u32 dmc_ddrtr0; | ||
49 | u32 dmc_ddrtr1; | ||
50 | u32 dmc_ddrtr2; | ||
51 | u32 dmc_ddrmr; | ||
52 | u32 dmc_ddrmr1; | ||
53 | }; | ||
54 | 35 | ||
55 | struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = { | ||
56 | [0] = { | ||
57 | .ddr_clk = 125, | ||
58 | .dmc_ddrctl = 0x00000904, | ||
59 | .dmc_ddrcfg = 0x00000422, | ||
60 | .dmc_ddrtr0 = 0x20705212, | ||
61 | .dmc_ddrtr1 = 0x201003CF, | ||
62 | .dmc_ddrtr2 = 0x00320107, | ||
63 | .dmc_ddrmr = 0x00000422, | ||
64 | .dmc_ddrmr1 = 0x4, | ||
65 | }, | ||
66 | [1] = { | ||
67 | .ddr_clk = 133, | ||
68 | .dmc_ddrctl = 0x00000904, | ||
69 | .dmc_ddrcfg = 0x00000422, | ||
70 | .dmc_ddrtr0 = 0x20806313, | ||
71 | .dmc_ddrtr1 = 0x2013040D, | ||
72 | .dmc_ddrtr2 = 0x00320108, | ||
73 | .dmc_ddrmr = 0x00000632, | ||
74 | .dmc_ddrmr1 = 0x4, | ||
75 | }, | ||
76 | [2] = { | ||
77 | .ddr_clk = 150, | ||
78 | .dmc_ddrctl = 0x00000904, | ||
79 | .dmc_ddrcfg = 0x00000422, | ||
80 | .dmc_ddrtr0 = 0x20A07323, | ||
81 | .dmc_ddrtr1 = 0x20160492, | ||
82 | .dmc_ddrtr2 = 0x00320209, | ||
83 | .dmc_ddrmr = 0x00000632, | ||
84 | .dmc_ddrmr1 = 0x4, | ||
85 | }, | ||
86 | [3] = { | ||
87 | .ddr_clk = 166, | ||
88 | .dmc_ddrctl = 0x00000904, | ||
89 | .dmc_ddrcfg = 0x00000422, | ||
90 | .dmc_ddrtr0 = 0x20A07323, | ||
91 | .dmc_ddrtr1 = 0x2016050E, | ||
92 | .dmc_ddrtr2 = 0x00320209, | ||
93 | .dmc_ddrmr = 0x00000632, | ||
94 | .dmc_ddrmr1 = 0x4, | ||
95 | }, | ||
96 | [4] = { | ||
97 | .ddr_clk = 200, | ||
98 | .dmc_ddrctl = 0x00000904, | ||
99 | .dmc_ddrcfg = 0x00000422, | ||
100 | .dmc_ddrtr0 = 0x20a07323, | ||
101 | .dmc_ddrtr1 = 0x2016050f, | ||
102 | .dmc_ddrtr2 = 0x00320509, | ||
103 | .dmc_ddrmr = 0x00000632, | ||
104 | .dmc_ddrmr1 = 0x4, | ||
105 | }, | ||
106 | [5] = { | ||
107 | .ddr_clk = 225, | ||
108 | .dmc_ddrctl = 0x00000904, | ||
109 | .dmc_ddrcfg = 0x00000422, | ||
110 | .dmc_ddrtr0 = 0x20E0A424, | ||
111 | .dmc_ddrtr1 = 0x302006DB, | ||
112 | .dmc_ddrtr2 = 0x0032020D, | ||
113 | .dmc_ddrmr = 0x00000842, | ||
114 | .dmc_ddrmr1 = 0x4, | ||
115 | }, | ||
116 | [6] = { | ||
117 | .ddr_clk = 250, | ||
118 | .dmc_ddrctl = 0x00000904, | ||
119 | .dmc_ddrcfg = 0x00000422, | ||
120 | .dmc_ddrtr0 = 0x20E0A424, | ||
121 | .dmc_ddrtr1 = 0x3020079E, | ||
122 | .dmc_ddrtr2 = 0x0032020D, | ||
123 | .dmc_ddrmr = 0x00000842, | ||
124 | .dmc_ddrmr1 = 0x4, | ||
125 | }, | ||
126 | }; | ||
127 | #else | 36 | #else |
128 | #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ | 37 | #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ |
129 | #define PLL_CTL_VAL \ | 38 | #define PLL_CTL_VAL \ |
@@ -144,43 +53,9 @@ void init_clocks(void) | |||
144 | * in the middle of reprogramming things, and that'll screw us up. | 53 | * in the middle of reprogramming things, and that'll screw us up. |
145 | * For example, any automatic DMAs left by U-Boot for splash screens. | 54 | * For example, any automatic DMAs left by U-Boot for splash screens. |
146 | */ | 55 | */ |
147 | |||
148 | #ifdef CONFIG_BF60x | 56 | #ifdef CONFIG_BF60x |
149 | int i, dlldatacycle, dll_ctl; | 57 | init_cgu(CGU_DIV_VAL, CGU_CTL_VAL); |
150 | bfin_write32(CGU0_DIV, CGU_DIV_VAL); | 58 | init_dmc(CONFIG_BFIN_DCLK); |
151 | bfin_write32(CGU0_CTL, CGU_CTL_VAL); | ||
152 | while ((bfin_read32(CGU0_STAT) & 0x8) || !(bfin_read32(CGU0_STAT) & 0x4)) | ||
153 | continue; | ||
154 | |||
155 | bfin_write32(CGU0_DIV, CGU_DIV_VAL | (1 << UPDT_P)); | ||
156 | while (bfin_read32(CGU0_STAT) & (1 << 3)) | ||
157 | continue; | ||
158 | |||
159 | for (i = 0; i < 7; i++) { | ||
160 | if (ddr_config_table[i].ddr_clk == CONFIG_BFIN_DCLK) { | ||
161 | bfin_write_DDR0_CFG(ddr_config_table[i].dmc_ddrcfg); | ||
162 | bfin_write_DDR0_TR0(ddr_config_table[i].dmc_ddrtr0); | ||
163 | bfin_write_DDR0_TR1(ddr_config_table[i].dmc_ddrtr1); | ||
164 | bfin_write_DDR0_TR2(ddr_config_table[i].dmc_ddrtr2); | ||
165 | bfin_write_DDR0_MR(ddr_config_table[i].dmc_ddrmr); | ||
166 | bfin_write_DDR0_EMR1(ddr_config_table[i].dmc_ddrmr1); | ||
167 | bfin_write_DDR0_CTL(ddr_config_table[i].dmc_ddrctl); | ||
168 | break; | ||
169 | } | ||
170 | } | ||
171 | |||
172 | do_sync(); | ||
173 | while (!(bfin_read_DDR0_STAT() & 0x4)) | ||
174 | continue; | ||
175 | |||
176 | dlldatacycle = (bfin_read_DDR0_STAT() & 0x00f00000) >> 20; | ||
177 | dll_ctl = bfin_read_DDR0_DLLCTL(); | ||
178 | dll_ctl &= 0x0ff; | ||
179 | bfin_write_DDR0_DLLCTL(dll_ctl | (dlldatacycle << 8)); | ||
180 | |||
181 | do_sync(); | ||
182 | while (!(bfin_read_DDR0_STAT() & 0x2000)) | ||
183 | continue; | ||
184 | #else | 59 | #else |
185 | size_t i; | 60 | size_t i; |
186 | for (i = 0; i < MAX_DMA_CHANNELS; ++i) { | 61 | for (i = 0; i < MAX_DMA_CHANNELS; ++i) { |
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c index 6e87dc13f6bf..c854a27cbeab 100644 --- a/arch/blackfin/mach-common/cpufreq.c +++ b/arch/blackfin/mach-common/cpufreq.c | |||
@@ -64,7 +64,8 @@ static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk) | |||
64 | 64 | ||
65 | /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */ | 65 | /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */ |
66 | #if ANOMALY_05000273 || ANOMALY_05000274 || \ | 66 | #if ANOMALY_05000273 || ANOMALY_05000274 || \ |
67 | (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE)) | 67 | (!(defined(CONFIG_BF54x) || defined(CONFIG_BF60x)) \ |
68 | && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE)) | ||
68 | min_cclk = sclk * 2; | 69 | min_cclk = sclk * 2; |
69 | #else | 70 | #else |
70 | min_cclk = sclk; | 71 | min_cclk = sclk; |
@@ -173,7 +174,7 @@ static int bfin_target(struct cpufreq_policy *poli, | |||
173 | #else | 174 | #else |
174 | ret = cpu_set_cclk(cpu, freqs.new * 1000); | 175 | ret = cpu_set_cclk(cpu, freqs.new * 1000); |
175 | if (ret != 0) { | 176 | if (ret != 0) { |
176 | pr_debug("cpufreq set freq failed %d\n", ret); | 177 | WARN_ONCE(ret, "cpufreq set freq failed %d\n", ret); |
177 | break; | 178 | break; |
178 | } | 179 | } |
179 | #endif | 180 | #endif |
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 04c2fbe41a7f..1c3d2c5bb0bb 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S | |||
@@ -25,13 +25,6 @@ | |||
25 | 25 | ||
26 | #include <asm/context.S> | 26 | #include <asm/context.S> |
27 | 27 | ||
28 | #if defined(CONFIG_BFIN_SCRATCH_REG_RETN) | ||
29 | # define EX_SCRATCH_REG RETN | ||
30 | #elif defined(CONFIG_BFIN_SCRATCH_REG_RETE) | ||
31 | # define EX_SCRATCH_REG RETE | ||
32 | #else | ||
33 | # define EX_SCRATCH_REG CYCLES | ||
34 | #endif | ||
35 | 28 | ||
36 | #ifdef CONFIG_EXCPT_IRQ_SYSC_L1 | 29 | #ifdef CONFIG_EXCPT_IRQ_SYSC_L1 |
37 | .section .l1.text | 30 | .section .l1.text |
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 2729cba715b0..7ca09ec2ca53 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c | |||
@@ -26,8 +26,9 @@ | |||
26 | #include <asm/gpio.h> | 26 | #include <asm/gpio.h> |
27 | #include <asm/irq_handler.h> | 27 | #include <asm/irq_handler.h> |
28 | #include <asm/dpmc.h> | 28 | #include <asm/dpmc.h> |
29 | #include <asm/traps.h> | ||
29 | 30 | ||
30 | #ifndef CONFIG_BF60x | 31 | #ifndef SEC_GCTL |
31 | # define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) | 32 | # define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) |
32 | #else | 33 | #else |
33 | # define SIC_SYSIRQ(irq) ((irq) - IVG15) | 34 | # define SIC_SYSIRQ(irq) ((irq) - IVG15) |
@@ -56,7 +57,7 @@ unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */ | |||
56 | unsigned vr_wakeup; | 57 | unsigned vr_wakeup; |
57 | #endif | 58 | #endif |
58 | 59 | ||
59 | #ifndef CONFIG_BF60x | 60 | #ifndef SEC_GCTL |
60 | static struct ivgx { | 61 | static struct ivgx { |
61 | /* irq number for request_irq, available in mach-bf5xx/irq.h */ | 62 | /* irq number for request_irq, available in mach-bf5xx/irq.h */ |
62 | unsigned int irqno; | 63 | unsigned int irqno; |
@@ -143,7 +144,7 @@ static void bfin_core_unmask_irq(struct irq_data *d) | |||
143 | void bfin_internal_mask_irq(unsigned int irq) | 144 | void bfin_internal_mask_irq(unsigned int irq) |
144 | { | 145 | { |
145 | unsigned long flags = hard_local_irq_save(); | 146 | unsigned long flags = hard_local_irq_save(); |
146 | #ifndef CONFIG_BF60x | 147 | #ifndef SEC_GCTL |
147 | #ifdef SIC_IMASK0 | 148 | #ifdef SIC_IMASK0 |
148 | unsigned mask_bank = SIC_SYSIRQ(irq) / 32; | 149 | unsigned mask_bank = SIC_SYSIRQ(irq) / 32; |
149 | unsigned mask_bit = SIC_SYSIRQ(irq) % 32; | 150 | unsigned mask_bit = SIC_SYSIRQ(irq) % 32; |
@@ -175,7 +176,7 @@ void bfin_internal_unmask_irq(unsigned int irq) | |||
175 | { | 176 | { |
176 | unsigned long flags = hard_local_irq_save(); | 177 | unsigned long flags = hard_local_irq_save(); |
177 | 178 | ||
178 | #ifndef CONFIG_BF60x | 179 | #ifndef SEC_GCTL |
179 | #ifdef SIC_IMASK0 | 180 | #ifdef SIC_IMASK0 |
180 | unsigned mask_bank = SIC_SYSIRQ(irq) / 32; | 181 | unsigned mask_bank = SIC_SYSIRQ(irq) / 32; |
181 | unsigned mask_bit = SIC_SYSIRQ(irq) % 32; | 182 | unsigned mask_bit = SIC_SYSIRQ(irq) % 32; |
@@ -199,7 +200,7 @@ void bfin_internal_unmask_irq(unsigned int irq) | |||
199 | hard_local_irq_restore(flags); | 200 | hard_local_irq_restore(flags); |
200 | } | 201 | } |
201 | 202 | ||
202 | #ifdef CONFIG_BF60x | 203 | #ifdef SEC_GCTL |
203 | static void bfin_sec_preflow_handler(struct irq_data *d) | 204 | static void bfin_sec_preflow_handler(struct irq_data *d) |
204 | { | 205 | { |
205 | unsigned long flags = hard_local_irq_save(); | 206 | unsigned long flags = hard_local_irq_save(); |
@@ -310,7 +311,24 @@ static void bfin_sec_disable(struct irq_data *d) | |||
310 | hard_local_irq_restore(flags); | 311 | hard_local_irq_restore(flags); |
311 | } | 312 | } |
312 | 313 | ||
313 | static void bfin_sec_raise_irq(unsigned int sid) | 314 | static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority) |
315 | { | ||
316 | unsigned long flags = hard_local_irq_save(); | ||
317 | uint32_t reg_sctl; | ||
318 | int i; | ||
319 | |||
320 | bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels); | ||
321 | |||
322 | for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) { | ||
323 | reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO; | ||
324 | reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET; | ||
325 | bfin_write_SEC_SCTL(i, reg_sctl); | ||
326 | } | ||
327 | |||
328 | hard_local_irq_restore(flags); | ||
329 | } | ||
330 | |||
331 | void bfin_sec_raise_irq(unsigned int sid) | ||
314 | { | 332 | { |
315 | unsigned long flags = hard_local_irq_save(); | 333 | unsigned long flags = hard_local_irq_save(); |
316 | 334 | ||
@@ -396,24 +414,34 @@ void handle_sec_fault(unsigned int irq, struct irq_desc *desc) | |||
396 | raw_spin_unlock(&desc->lock); | 414 | raw_spin_unlock(&desc->lock); |
397 | } | 415 | } |
398 | 416 | ||
399 | static int sec_suspend(void) | 417 | void handle_core_fault(unsigned int irq, struct irq_desc *desc) |
400 | { | 418 | { |
401 | return 0; | 419 | struct pt_regs *fp = get_irq_regs(); |
402 | } | ||
403 | 420 | ||
404 | static void sec_resume(void) | 421 | raw_spin_lock(&desc->lock); |
405 | { | ||
406 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); | ||
407 | udelay(100); | ||
408 | bfin_write_SEC_GCTL(SEC_GCTL_EN); | ||
409 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); | ||
410 | } | ||
411 | 422 | ||
412 | static struct syscore_ops sec_pm_syscore_ops = { | 423 | switch (irq) { |
413 | .suspend = sec_suspend, | 424 | case IRQ_C0_DBL_FAULT: |
414 | .resume = sec_resume, | 425 | double_fault_c(fp); |
415 | }; | 426 | break; |
427 | case IRQ_C0_HW_ERR: | ||
428 | dump_bfin_process(fp); | ||
429 | dump_bfin_mem(fp); | ||
430 | show_regs(fp); | ||
431 | printk(KERN_NOTICE "Kernel Stack\n"); | ||
432 | show_stack(current, NULL); | ||
433 | print_modules(); | ||
434 | panic("Kernel core hardware error"); | ||
435 | break; | ||
436 | case IRQ_C0_NMI_L1_PARITY_ERR: | ||
437 | panic("NMI occurs unexpectedly"); | ||
438 | break; | ||
439 | default: | ||
440 | panic("Core 1 fault occurs unexpectedly"); | ||
441 | } | ||
416 | 442 | ||
443 | raw_spin_unlock(&desc->lock); | ||
444 | } | ||
417 | #endif | 445 | #endif |
418 | 446 | ||
419 | #ifdef CONFIG_SMP | 447 | #ifdef CONFIG_SMP |
@@ -437,7 +465,7 @@ static void bfin_internal_unmask_irq_chip(struct irq_data *d) | |||
437 | } | 465 | } |
438 | #endif | 466 | #endif |
439 | 467 | ||
440 | #if defined(CONFIG_PM) && !defined(CONFIG_BF60x) | 468 | #if defined(CONFIG_PM) && !defined(SEC_GCTL) |
441 | int bfin_internal_set_wake(unsigned int irq, unsigned int state) | 469 | int bfin_internal_set_wake(unsigned int irq, unsigned int state) |
442 | { | 470 | { |
443 | u32 bank, bit, wakeup = 0; | 471 | u32 bank, bit, wakeup = 0; |
@@ -496,7 +524,10 @@ static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state) | |||
496 | return bfin_internal_set_wake(d->irq, state); | 524 | return bfin_internal_set_wake(d->irq, state); |
497 | } | 525 | } |
498 | #else | 526 | #else |
499 | # define bfin_internal_set_wake(irq, state) | 527 | inline int bfin_internal_set_wake(unsigned int irq, unsigned int state) |
528 | { | ||
529 | return 0; | ||
530 | } | ||
500 | # define bfin_internal_set_wake_chip NULL | 531 | # define bfin_internal_set_wake_chip NULL |
501 | #endif | 532 | #endif |
502 | 533 | ||
@@ -518,7 +549,7 @@ static struct irq_chip bfin_internal_irqchip = { | |||
518 | .irq_set_wake = bfin_internal_set_wake_chip, | 549 | .irq_set_wake = bfin_internal_set_wake_chip, |
519 | }; | 550 | }; |
520 | 551 | ||
521 | #ifdef CONFIG_BF60x | 552 | #ifdef SEC_GCTL |
522 | static struct irq_chip bfin_sec_irqchip = { | 553 | static struct irq_chip bfin_sec_irqchip = { |
523 | .name = "SEC", | 554 | .name = "SEC", |
524 | .irq_mask_ack = bfin_sec_mask_ack_irq, | 555 | .irq_mask_ack = bfin_sec_mask_ack_irq, |
@@ -868,14 +899,6 @@ void bfin_demux_gpio_irq(unsigned int inta_irq, | |||
868 | 899 | ||
869 | #else | 900 | #else |
870 | 901 | ||
871 | # ifndef CONFIG_BF60x | ||
872 | #define NR_PINT_SYS_IRQS 4 | ||
873 | #define NR_PINTS 160 | ||
874 | # else | ||
875 | #define NR_PINT_SYS_IRQS 6 | ||
876 | #define NR_PINTS 112 | ||
877 | #endif | ||
878 | |||
879 | #define NR_PINT_BITS 32 | 902 | #define NR_PINT_BITS 32 |
880 | #define IRQ_NOT_AVAIL 0xFF | 903 | #define IRQ_NOT_AVAIL 0xFF |
881 | 904 | ||
@@ -897,29 +920,21 @@ static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = { | |||
897 | #endif | 920 | #endif |
898 | }; | 921 | }; |
899 | 922 | ||
900 | #ifndef CONFIG_BF60x | ||
901 | inline unsigned int get_irq_base(u32 bank, u8 bmap) | 923 | inline unsigned int get_irq_base(u32 bank, u8 bmap) |
902 | { | 924 | { |
903 | unsigned int irq_base; | 925 | unsigned int irq_base; |
904 | 926 | ||
927 | #ifndef CONFIG_BF60x | ||
905 | if (bank < 2) { /*PA-PB */ | 928 | if (bank < 2) { /*PA-PB */ |
906 | irq_base = IRQ_PA0 + bmap * 16; | 929 | irq_base = IRQ_PA0 + bmap * 16; |
907 | } else { /*PC-PJ */ | 930 | } else { /*PC-PJ */ |
908 | irq_base = IRQ_PC0 + bmap * 16; | 931 | irq_base = IRQ_PC0 + bmap * 16; |
909 | } | 932 | } |
910 | |||
911 | return irq_base; | ||
912 | } | ||
913 | #else | 933 | #else |
914 | inline unsigned int get_irq_base(u32 bank, u8 bmap) | ||
915 | { | ||
916 | unsigned int irq_base; | ||
917 | |||
918 | irq_base = IRQ_PA0 + bank * 16 + bmap * 16; | 934 | irq_base = IRQ_PA0 + bank * 16 + bmap * 16; |
919 | 935 | #endif | |
920 | return irq_base; | 936 | return irq_base; |
921 | } | 937 | } |
922 | #endif | ||
923 | 938 | ||
924 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ | 939 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
925 | void init_pint_lut(void) | 940 | void init_pint_lut(void) |
@@ -1089,6 +1104,9 @@ static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type) | |||
1089 | } | 1104 | } |
1090 | 1105 | ||
1091 | #ifdef CONFIG_PM | 1106 | #ifdef CONFIG_PM |
1107 | static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS]; | ||
1108 | static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS]; | ||
1109 | |||
1092 | static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) | 1110 | static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) |
1093 | { | 1111 | { |
1094 | u32 pint_irq; | 1112 | u32 pint_irq; |
@@ -1124,6 +1142,59 @@ static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) | |||
1124 | 1142 | ||
1125 | return 0; | 1143 | return 0; |
1126 | } | 1144 | } |
1145 | |||
1146 | void bfin_pint_suspend(void) | ||
1147 | { | ||
1148 | u32 bank; | ||
1149 | |||
1150 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { | ||
1151 | save_pint_reg[bank].mask_set = pint[bank]->mask_set; | ||
1152 | save_pint_reg[bank].assign = pint[bank]->assign; | ||
1153 | save_pint_reg[bank].edge_set = pint[bank]->edge_set; | ||
1154 | save_pint_reg[bank].invert_set = pint[bank]->invert_set; | ||
1155 | } | ||
1156 | } | ||
1157 | |||
1158 | void bfin_pint_resume(void) | ||
1159 | { | ||
1160 | u32 bank; | ||
1161 | |||
1162 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { | ||
1163 | pint[bank]->mask_set = save_pint_reg[bank].mask_set; | ||
1164 | pint[bank]->assign = save_pint_reg[bank].assign; | ||
1165 | pint[bank]->edge_set = save_pint_reg[bank].edge_set; | ||
1166 | pint[bank]->invert_set = save_pint_reg[bank].invert_set; | ||
1167 | } | ||
1168 | } | ||
1169 | |||
1170 | #ifdef SEC_GCTL | ||
1171 | static int sec_suspend(void) | ||
1172 | { | ||
1173 | u32 bank; | ||
1174 | |||
1175 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) | ||
1176 | save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0)); | ||
1177 | return 0; | ||
1178 | } | ||
1179 | |||
1180 | static void sec_resume(void) | ||
1181 | { | ||
1182 | u32 bank; | ||
1183 | |||
1184 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); | ||
1185 | udelay(100); | ||
1186 | bfin_write_SEC_GCTL(SEC_GCTL_EN); | ||
1187 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); | ||
1188 | |||
1189 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) | ||
1190 | bfin_write_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]); | ||
1191 | } | ||
1192 | |||
1193 | static struct syscore_ops sec_pm_syscore_ops = { | ||
1194 | .suspend = sec_suspend, | ||
1195 | .resume = sec_resume, | ||
1196 | }; | ||
1197 | #endif | ||
1127 | #else | 1198 | #else |
1128 | # define bfin_gpio_set_wake NULL | 1199 | # define bfin_gpio_set_wake NULL |
1129 | #endif | 1200 | #endif |
@@ -1230,6 +1301,7 @@ void __cpuinit init_exception_vectors(void) | |||
1230 | CSYNC(); | 1301 | CSYNC(); |
1231 | } | 1302 | } |
1232 | 1303 | ||
1304 | #ifndef SEC_GCTL | ||
1233 | /* | 1305 | /* |
1234 | * This function should be called during kernel startup to initialize | 1306 | * This function should be called during kernel startup to initialize |
1235 | * the BFin IRQ handling routines. | 1307 | * the BFin IRQ handling routines. |
@@ -1240,7 +1312,6 @@ int __init init_arch_irq(void) | |||
1240 | int irq; | 1312 | int irq; |
1241 | unsigned long ilat = 0; | 1313 | unsigned long ilat = 0; |
1242 | 1314 | ||
1243 | #ifndef CONFIG_BF60x | ||
1244 | /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ | 1315 | /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ |
1245 | #ifdef SIC_IMASK0 | 1316 | #ifdef SIC_IMASK0 |
1246 | bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); | 1317 | bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); |
@@ -1255,9 +1326,6 @@ int __init init_arch_irq(void) | |||
1255 | #else | 1326 | #else |
1256 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); | 1327 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); |
1257 | #endif | 1328 | #endif |
1258 | #else /* CONFIG_BF60x */ | ||
1259 | bfin_write_SEC_GCTL(SEC_GCTL_RESET); | ||
1260 | #endif | ||
1261 | 1329 | ||
1262 | local_irq_disable(); | 1330 | local_irq_disable(); |
1263 | 1331 | ||
@@ -1267,10 +1335,6 @@ int __init init_arch_irq(void) | |||
1267 | pint[1]->assign = CONFIG_PINT1_ASSIGN; | 1335 | pint[1]->assign = CONFIG_PINT1_ASSIGN; |
1268 | pint[2]->assign = CONFIG_PINT2_ASSIGN; | 1336 | pint[2]->assign = CONFIG_PINT2_ASSIGN; |
1269 | pint[3]->assign = CONFIG_PINT3_ASSIGN; | 1337 | pint[3]->assign = CONFIG_PINT3_ASSIGN; |
1270 | # ifdef CONFIG_BF60x | ||
1271 | pint[4]->assign = CONFIG_PINT4_ASSIGN; | ||
1272 | pint[5]->assign = CONFIG_PINT5_ASSIGN; | ||
1273 | # endif | ||
1274 | # endif | 1338 | # endif |
1275 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ | 1339 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
1276 | init_pint_lut(); | 1340 | init_pint_lut(); |
@@ -1283,7 +1347,6 @@ int __init init_arch_irq(void) | |||
1283 | irq_set_chip(irq, &bfin_internal_irqchip); | 1347 | irq_set_chip(irq, &bfin_internal_irqchip); |
1284 | 1348 | ||
1285 | switch (irq) { | 1349 | switch (irq) { |
1286 | #ifndef CONFIG_BF60x | ||
1287 | #if BFIN_GPIO_PINT | 1350 | #if BFIN_GPIO_PINT |
1288 | case IRQ_PINT0: | 1351 | case IRQ_PINT0: |
1289 | case IRQ_PINT1: | 1352 | case IRQ_PINT1: |
@@ -1319,7 +1382,6 @@ int __init init_arch_irq(void) | |||
1319 | irq_set_handler(irq, handle_percpu_irq); | 1382 | irq_set_handler(irq, handle_percpu_irq); |
1320 | break; | 1383 | break; |
1321 | #endif | 1384 | #endif |
1322 | #endif | ||
1323 | 1385 | ||
1324 | #ifdef CONFIG_TICKSOURCE_CORETMR | 1386 | #ifdef CONFIG_TICKSOURCE_CORETMR |
1325 | case IRQ_CORETMR: | 1387 | case IRQ_CORETMR: |
@@ -1349,8 +1411,7 @@ int __init init_arch_irq(void) | |||
1349 | 1411 | ||
1350 | init_mach_irq(); | 1412 | init_mach_irq(); |
1351 | 1413 | ||
1352 | #ifndef CONFIG_BF60x | 1414 | #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) |
1353 | #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) && !defined(CONFIG_BF60x) | ||
1354 | for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) | 1415 | for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) |
1355 | irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip, | 1416 | irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip, |
1356 | handle_level_irq); | 1417 | handle_level_irq); |
@@ -1360,28 +1421,6 @@ int __init init_arch_irq(void) | |||
1360 | irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) | 1421 | irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) |
1361 | irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, | 1422 | irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, |
1362 | handle_level_irq); | 1423 | handle_level_irq); |
1363 | #else | ||
1364 | for (irq = BFIN_IRQ(0); irq <= SYS_IRQS; irq++) { | ||
1365 | if (irq < CORE_IRQS) { | ||
1366 | irq_set_chip(irq, &bfin_sec_irqchip); | ||
1367 | __irq_set_handler(irq, handle_sec_fault, 0, NULL); | ||
1368 | } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) { | ||
1369 | irq_set_chip(irq, &bfin_sec_irqchip); | ||
1370 | irq_set_chained_handler(irq, bfin_demux_gpio_irq); | ||
1371 | } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) { | ||
1372 | irq_set_chip(irq, &bfin_sec_irqchip); | ||
1373 | irq_set_handler(irq, handle_percpu_irq); | ||
1374 | } else { | ||
1375 | irq_set_chip_and_handler(irq, &bfin_sec_irqchip, | ||
1376 | handle_fasteoi_irq); | ||
1377 | __irq_set_preflow_handler(irq, bfin_sec_preflow_handler); | ||
1378 | } | ||
1379 | } | ||
1380 | for (irq = GPIO_IRQ_BASE; | ||
1381 | irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) | ||
1382 | irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, | ||
1383 | handle_level_irq); | ||
1384 | #endif | ||
1385 | bfin_write_IMASK(0); | 1424 | bfin_write_IMASK(0); |
1386 | CSYNC(); | 1425 | CSYNC(); |
1387 | ilat = bfin_read_ILAT(); | 1426 | ilat = bfin_read_ILAT(); |
@@ -1393,7 +1432,6 @@ int __init init_arch_irq(void) | |||
1393 | /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx, | 1432 | /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx, |
1394 | * local_irq_enable() | 1433 | * local_irq_enable() |
1395 | */ | 1434 | */ |
1396 | #ifndef CONFIG_BF60x | ||
1397 | program_IAR(); | 1435 | program_IAR(); |
1398 | /* Therefore it's better to setup IARs before interrupts enabled */ | 1436 | /* Therefore it's better to setup IARs before interrupts enabled */ |
1399 | search_IAR(); | 1437 | search_IAR(); |
@@ -1427,23 +1465,6 @@ int __init init_arch_irq(void) | |||
1427 | #else | 1465 | #else |
1428 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); | 1466 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
1429 | #endif | 1467 | #endif |
1430 | #else /* CONFIG_BF60x */ | ||
1431 | /* Enable interrupts IVG7-15 */ | ||
1432 | bfin_irq_flags |= IMASK_IVG15 | | ||
1433 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | | ||
1434 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; | ||
1435 | |||
1436 | |||
1437 | bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN); | ||
1438 | bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0)); | ||
1439 | bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0)); | ||
1440 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); | ||
1441 | udelay(100); | ||
1442 | bfin_write_SEC_GCTL(SEC_GCTL_EN); | ||
1443 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); | ||
1444 | init_software_driven_irq(); | ||
1445 | register_syscore_ops(&sec_pm_syscore_ops); | ||
1446 | #endif | ||
1447 | return 0; | 1468 | return 0; |
1448 | } | 1469 | } |
1449 | 1470 | ||
@@ -1452,14 +1473,11 @@ __attribute__((l1_text)) | |||
1452 | #endif | 1473 | #endif |
1453 | static int vec_to_irq(int vec) | 1474 | static int vec_to_irq(int vec) |
1454 | { | 1475 | { |
1455 | #ifndef CONFIG_BF60x | ||
1456 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; | 1476 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; |
1457 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; | 1477 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; |
1458 | unsigned long sic_status[3]; | 1478 | unsigned long sic_status[3]; |
1459 | #endif | ||
1460 | if (likely(vec == EVT_IVTMR_P)) | 1479 | if (likely(vec == EVT_IVTMR_P)) |
1461 | return IRQ_CORETMR; | 1480 | return IRQ_CORETMR; |
1462 | #ifndef CONFIG_BF60x | ||
1463 | #ifdef SIC_ISR | 1481 | #ifdef SIC_ISR |
1464 | sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); | 1482 | sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); |
1465 | #else | 1483 | #else |
@@ -1488,11 +1506,119 @@ static int vec_to_irq(int vec) | |||
1488 | #endif | 1506 | #endif |
1489 | return ivg->irqno; | 1507 | return ivg->irqno; |
1490 | } | 1508 | } |
1491 | #else | 1509 | } |
1492 | /* for bf60x read */ | 1510 | |
1511 | #else /* SEC_GCTL */ | ||
1512 | |||
1513 | /* | ||
1514 | * This function should be called during kernel startup to initialize | ||
1515 | * the BFin IRQ handling routines. | ||
1516 | */ | ||
1517 | |||
1518 | int __init init_arch_irq(void) | ||
1519 | { | ||
1520 | int irq; | ||
1521 | unsigned long ilat = 0; | ||
1522 | |||
1523 | bfin_write_SEC_GCTL(SEC_GCTL_RESET); | ||
1524 | |||
1525 | local_irq_disable(); | ||
1526 | |||
1527 | #if BFIN_GPIO_PINT | ||
1528 | # ifdef CONFIG_PINTx_REASSIGN | ||
1529 | pint[0]->assign = CONFIG_PINT0_ASSIGN; | ||
1530 | pint[1]->assign = CONFIG_PINT1_ASSIGN; | ||
1531 | pint[2]->assign = CONFIG_PINT2_ASSIGN; | ||
1532 | pint[3]->assign = CONFIG_PINT3_ASSIGN; | ||
1533 | pint[4]->assign = CONFIG_PINT4_ASSIGN; | ||
1534 | pint[5]->assign = CONFIG_PINT5_ASSIGN; | ||
1535 | # endif | ||
1536 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ | ||
1537 | init_pint_lut(); | ||
1538 | #endif | ||
1539 | |||
1540 | for (irq = 0; irq <= SYS_IRQS; irq++) { | ||
1541 | if (irq <= IRQ_CORETMR) { | ||
1542 | irq_set_chip(irq, &bfin_core_irqchip); | ||
1543 | #ifdef CONFIG_TICKSOURCE_CORETMR | ||
1544 | if (irq == IRQ_CORETMR) | ||
1545 | # ifdef CONFIG_SMP | ||
1546 | irq_set_handler(irq, handle_percpu_irq); | ||
1547 | # else | ||
1548 | irq_set_handler(irq, handle_simple_irq); | ||
1549 | # endif | ||
1550 | #endif | ||
1551 | } else if (irq < BFIN_IRQ(0)) { | ||
1552 | irq_set_chip_and_handler(irq, &bfin_internal_irqchip, | ||
1553 | handle_simple_irq); | ||
1554 | } else if (irq == IRQ_SEC_ERR) { | ||
1555 | irq_set_chip_and_handler(irq, &bfin_sec_irqchip, | ||
1556 | handle_sec_fault); | ||
1557 | } else if (irq < CORE_IRQS && irq >= IRQ_C0_DBL_FAULT) { | ||
1558 | irq_set_chip_and_handler(irq, &bfin_sec_irqchip, | ||
1559 | handle_core_fault); | ||
1560 | } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) { | ||
1561 | irq_set_chip(irq, &bfin_sec_irqchip); | ||
1562 | irq_set_chained_handler(irq, bfin_demux_gpio_irq); | ||
1563 | } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) { | ||
1564 | irq_set_chip(irq, &bfin_sec_irqchip); | ||
1565 | irq_set_handler(irq, handle_percpu_irq); | ||
1566 | } else { | ||
1567 | irq_set_chip_and_handler(irq, &bfin_sec_irqchip, | ||
1568 | handle_fasteoi_irq); | ||
1569 | __irq_set_preflow_handler(irq, bfin_sec_preflow_handler); | ||
1570 | } | ||
1571 | } | ||
1572 | for (irq = GPIO_IRQ_BASE; | ||
1573 | irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) | ||
1574 | irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, | ||
1575 | handle_level_irq); | ||
1576 | |||
1577 | bfin_write_IMASK(0); | ||
1578 | CSYNC(); | ||
1579 | ilat = bfin_read_ILAT(); | ||
1580 | CSYNC(); | ||
1581 | bfin_write_ILAT(ilat); | ||
1582 | CSYNC(); | ||
1583 | |||
1584 | printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); | ||
1585 | |||
1586 | bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority); | ||
1587 | |||
1588 | bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority); | ||
1589 | |||
1590 | /* Enable interrupts IVG7-15 */ | ||
1591 | bfin_irq_flags |= IMASK_IVG15 | | ||
1592 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | | ||
1593 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; | ||
1594 | |||
1595 | |||
1596 | bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN); | ||
1597 | bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0)); | ||
1598 | bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0)); | ||
1599 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); | ||
1600 | udelay(100); | ||
1601 | bfin_write_SEC_GCTL(SEC_GCTL_EN); | ||
1602 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); | ||
1603 | bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); | ||
1604 | |||
1605 | init_software_driven_irq(); | ||
1606 | register_syscore_ops(&sec_pm_syscore_ops); | ||
1607 | |||
1608 | return 0; | ||
1609 | } | ||
1610 | |||
1611 | #ifdef CONFIG_DO_IRQ_L1 | ||
1612 | __attribute__((l1_text)) | ||
1613 | #endif | ||
1614 | static int vec_to_irq(int vec) | ||
1615 | { | ||
1616 | if (likely(vec == EVT_IVTMR_P)) | ||
1617 | return IRQ_CORETMR; | ||
1618 | |||
1493 | return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID)); | 1619 | return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID)); |
1494 | #endif /* end of CONFIG_BF60x */ | ||
1495 | } | 1620 | } |
1621 | #endif /* SEC_GCTL */ | ||
1496 | 1622 | ||
1497 | #ifdef CONFIG_DO_IRQ_L1 | 1623 | #ifdef CONFIG_DO_IRQ_L1 |
1498 | __attribute__((l1_text)) | 1624 | __attribute__((l1_text)) |
@@ -1514,6 +1640,10 @@ int __ipipe_get_irq_priority(unsigned irq) | |||
1514 | if (irq <= IRQ_CORETMR) | 1640 | if (irq <= IRQ_CORETMR) |
1515 | return irq; | 1641 | return irq; |
1516 | 1642 | ||
1643 | #ifdef SEC_GCTL | ||
1644 | if (irq >= BFIN_IRQ(0)) | ||
1645 | return IVG11; | ||
1646 | #else | ||
1517 | for (ient = 0; ient < NR_PERI_INTS; ient++) { | 1647 | for (ient = 0; ient < NR_PERI_INTS; ient++) { |
1518 | struct ivgx *ivg = ivg_table + ient; | 1648 | struct ivgx *ivg = ivg_table + ient; |
1519 | if (ivg->irqno == irq) { | 1649 | if (ivg->irqno == irq) { |
@@ -1524,6 +1654,7 @@ int __ipipe_get_irq_priority(unsigned irq) | |||
1524 | } | 1654 | } |
1525 | } | 1655 | } |
1526 | } | 1656 | } |
1657 | #endif | ||
1527 | 1658 | ||
1528 | return IVG15; | 1659 | return IVG15; |
1529 | } | 1660 | } |
@@ -1536,8 +1667,6 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | |||
1536 | { | 1667 | { |
1537 | struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); | 1668 | struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); |
1538 | struct ipipe_domain *this_domain = __ipipe_current_domain; | 1669 | struct ipipe_domain *this_domain = __ipipe_current_domain; |
1539 | struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; | ||
1540 | struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; | ||
1541 | int irq, s = 0; | 1670 | int irq, s = 0; |
1542 | 1671 | ||
1543 | irq = vec_to_irq(vec); | 1672 | irq = vec_to_irq(vec); |
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index ca6655e0d653..87bfe549ad3f 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c | |||
@@ -172,6 +172,10 @@ int bfin_pm_suspend_mem_enter(void) | |||
172 | 172 | ||
173 | bfin_gpio_pm_hibernate_suspend(); | 173 | bfin_gpio_pm_hibernate_suspend(); |
174 | 174 | ||
175 | #if BFIN_GPIO_PINT | ||
176 | bfin_pint_suspend(); | ||
177 | #endif | ||
178 | |||
175 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) | 179 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
176 | flushinv_all_dcache(); | 180 | flushinv_all_dcache(); |
177 | #endif | 181 | #endif |
@@ -190,6 +194,10 @@ int bfin_pm_suspend_mem_enter(void) | |||
190 | _enable_icplb(); | 194 | _enable_icplb(); |
191 | _enable_dcplb(); | 195 | _enable_dcplb(); |
192 | 196 | ||
197 | #if BFIN_GPIO_PINT | ||
198 | bfin_pint_resume(); | ||
199 | #endif | ||
200 | |||
193 | bfin_gpio_pm_hibernate_restore(); | 201 | bfin_gpio_pm_hibernate_restore(); |
194 | blackfin_dma_resume(); | 202 | blackfin_dma_resume(); |
195 | 203 | ||