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-rw-r--r--arch/blackfin/mach-common/Makefile1
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S50
-rw-r--r--arch/blackfin/mach-common/entry.S113
-rw-r--r--arch/blackfin/mach-common/interrupt.S17
-rw-r--r--arch/blackfin/mach-common/ints-priority.c11
-rw-r--r--arch/blackfin/mach-common/irqpanic.c106
6 files changed, 135 insertions, 163 deletions
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index 814cb483853b..ff299f24aba0 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -11,4 +11,3 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq.o
11obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o 11obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
12obj-$(CONFIG_SMP) += smp.o 12obj-$(CONFIG_SMP) += smp.o
13obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o 13obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o
14obj-$(CONFIG_DEBUG_ICACHE_CHECK) += irqpanic.o
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 5969d86836a5..9cfdd49a3127 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -292,13 +292,7 @@ ENTRY(_do_hibernate)
292#ifdef SIC_IMASK 292#ifdef SIC_IMASK
293 PM_SYS_PUSH(SIC_IMASK) 293 PM_SYS_PUSH(SIC_IMASK)
294#endif 294#endif
295#ifdef SICA_IMASK0 295#ifdef SIC_IAR0
296 PM_SYS_PUSH(SICA_IMASK0)
297#endif
298#ifdef SICA_IMASK1
299 PM_SYS_PUSH(SICA_IMASK1)
300#endif
301#ifdef SIC_IAR2
302 PM_SYS_PUSH(SIC_IAR0) 296 PM_SYS_PUSH(SIC_IAR0)
303 PM_SYS_PUSH(SIC_IAR1) 297 PM_SYS_PUSH(SIC_IAR1)
304 PM_SYS_PUSH(SIC_IAR2) 298 PM_SYS_PUSH(SIC_IAR2)
@@ -321,17 +315,6 @@ ENTRY(_do_hibernate)
321 PM_SYS_PUSH(SIC_IAR11) 315 PM_SYS_PUSH(SIC_IAR11)
322#endif 316#endif
323 317
324#ifdef SICA_IAR0
325 PM_SYS_PUSH(SICA_IAR0)
326 PM_SYS_PUSH(SICA_IAR1)
327 PM_SYS_PUSH(SICA_IAR2)
328 PM_SYS_PUSH(SICA_IAR3)
329 PM_SYS_PUSH(SICA_IAR4)
330 PM_SYS_PUSH(SICA_IAR5)
331 PM_SYS_PUSH(SICA_IAR6)
332 PM_SYS_PUSH(SICA_IAR7)
333#endif
334
335#ifdef SIC_IWR 318#ifdef SIC_IWR
336 PM_SYS_PUSH(SIC_IWR) 319 PM_SYS_PUSH(SIC_IWR)
337#endif 320#endif
@@ -344,12 +327,6 @@ ENTRY(_do_hibernate)
344#ifdef SIC_IWR2 327#ifdef SIC_IWR2
345 PM_SYS_PUSH(SIC_IWR2) 328 PM_SYS_PUSH(SIC_IWR2)
346#endif 329#endif
347#ifdef SICA_IWR0
348 PM_SYS_PUSH(SICA_IWR0)
349#endif
350#ifdef SICA_IWR1
351 PM_SYS_PUSH(SICA_IWR1)
352#endif
353 330
354#ifdef PINT0_ASSIGN 331#ifdef PINT0_ASSIGN
355 PM_SYS_PUSH(PINT0_MASK_SET) 332 PM_SYS_PUSH(PINT0_MASK_SET)
@@ -750,12 +727,6 @@ ENTRY(_do_hibernate)
750 PM_SYS_POP(PINT0_MASK_SET) 727 PM_SYS_POP(PINT0_MASK_SET)
751#endif 728#endif
752 729
753#ifdef SICA_IWR1
754 PM_SYS_POP(SICA_IWR1)
755#endif
756#ifdef SICA_IWR0
757 PM_SYS_POP(SICA_IWR0)
758#endif
759#ifdef SIC_IWR2 730#ifdef SIC_IWR2
760 PM_SYS_POP(SIC_IWR2) 731 PM_SYS_POP(SIC_IWR2)
761#endif 732#endif
@@ -769,17 +740,6 @@ ENTRY(_do_hibernate)
769 PM_SYS_POP(SIC_IWR) 740 PM_SYS_POP(SIC_IWR)
770#endif 741#endif
771 742
772#ifdef SICA_IAR0
773 PM_SYS_POP(SICA_IAR7)
774 PM_SYS_POP(SICA_IAR6)
775 PM_SYS_POP(SICA_IAR5)
776 PM_SYS_POP(SICA_IAR4)
777 PM_SYS_POP(SICA_IAR3)
778 PM_SYS_POP(SICA_IAR2)
779 PM_SYS_POP(SICA_IAR1)
780 PM_SYS_POP(SICA_IAR0)
781#endif
782
783#ifdef SIC_IAR8 743#ifdef SIC_IAR8
784 PM_SYS_POP(SIC_IAR11) 744 PM_SYS_POP(SIC_IAR11)
785 PM_SYS_POP(SIC_IAR10) 745 PM_SYS_POP(SIC_IAR10)
@@ -797,17 +757,11 @@ ENTRY(_do_hibernate)
797#ifdef SIC_IAR3 757#ifdef SIC_IAR3
798 PM_SYS_POP(SIC_IAR3) 758 PM_SYS_POP(SIC_IAR3)
799#endif 759#endif
800#ifdef SIC_IAR2 760#ifdef SIC_IAR0
801 PM_SYS_POP(SIC_IAR2) 761 PM_SYS_POP(SIC_IAR2)
802 PM_SYS_POP(SIC_IAR1) 762 PM_SYS_POP(SIC_IAR1)
803 PM_SYS_POP(SIC_IAR0) 763 PM_SYS_POP(SIC_IAR0)
804#endif 764#endif
805#ifdef SICA_IMASK1
806 PM_SYS_POP(SICA_IMASK1)
807#endif
808#ifdef SICA_IMASK0
809 PM_SYS_POP(SICA_IMASK0)
810#endif
811#ifdef SIC_IMASK 765#ifdef SIC_IMASK
812 PM_SYS_POP(SIC_IMASK) 766 PM_SYS_POP(SIC_IMASK)
813#endif 767#endif
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index af1bffa21dc1..2ca915ee181f 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -889,6 +889,66 @@ ENTRY(_ret_from_exception)
889 rts; 889 rts;
890ENDPROC(_ret_from_exception) 890ENDPROC(_ret_from_exception)
891 891
892#if defined(CONFIG_PREEMPT)
893
894ENTRY(_up_to_irq14)
895#if ANOMALY_05000281 || ANOMALY_05000461
896 r0.l = lo(SAFE_USER_INSTRUCTION);
897 r0.h = hi(SAFE_USER_INSTRUCTION);
898 reti = r0;
899#endif
900
901#ifdef CONFIG_DEBUG_HWERR
902 /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
903 r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
904#else
905 /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
906 r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
907#endif
908 sti r0;
909
910 p0.l = lo(EVT14);
911 p0.h = hi(EVT14);
912 p1.l = _evt_up_evt14;
913 p1.h = _evt_up_evt14;
914 [p0] = p1;
915 csync;
916
917 raise 14;
9181:
919 jump 1b;
920ENDPROC(_up_to_irq14)
921
922ENTRY(_evt_up_evt14)
923#ifdef CONFIG_DEBUG_HWERR
924 r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
925 sti r0;
926#else
927 cli r0;
928#endif
929#ifdef CONFIG_TRACE_IRQFLAGS
930 [--sp] = rets;
931 sp += -12;
932 call _trace_hardirqs_off;
933 sp += 12;
934 rets = [sp++];
935#endif
936 [--sp] = RETI;
937 SP += 4;
938
939 /* restore normal evt14 */
940 p0.l = lo(EVT14);
941 p0.h = hi(EVT14);
942 p1.l = _evt_evt14;
943 p1.h = _evt_evt14;
944 [p0] = p1;
945 csync;
946
947 rts;
948ENDPROC(_evt_up_evt14)
949
950#endif
951
892#ifdef CONFIG_IPIPE 952#ifdef CONFIG_IPIPE
893 953
894_resume_kernel_from_int: 954_resume_kernel_from_int:
@@ -902,8 +962,54 @@ _resume_kernel_from_int:
902 ( r7:4, p5:3 ) = [sp++]; 962 ( r7:4, p5:3 ) = [sp++];
903 rets = [sp++]; 963 rets = [sp++];
904 rts 964 rts
965#elif defined(CONFIG_PREEMPT)
966
967_resume_kernel_from_int:
968 /* check preempt_count */
969 r7 = sp;
970 r4.l = lo(ALIGN_PAGE_MASK);
971 r4.h = hi(ALIGN_PAGE_MASK);
972 r7 = r7 & r4;
973 p5 = r7;
974 r7 = [p5 + TI_PREEMPT];
975 cc = r7 == 0x0;
976 if !cc jump .Lreturn_to_kernel;
977.Lneed_schedule:
978 r7 = [p5 + TI_FLAGS];
979 r4.l = lo(_TIF_WORK_MASK);
980 r4.h = hi(_TIF_WORK_MASK);
981 r7 = r7 & r4;
982 cc = BITTST(r7, TIF_NEED_RESCHED);
983 if !cc jump .Lreturn_to_kernel;
984 /*
985 * let schedule done at level 15, otherwise sheduled process will run
986 * at high level and block low level interrupt
987 */
988 r6 = reti; /* save reti */
989 r5.l = .Lkernel_schedule;
990 r5.h = .Lkernel_schedule;
991 reti = r5;
992 rti;
993.Lkernel_schedule:
994 [--sp] = rets;
995 sp += -12;
996 pseudo_long_call _preempt_schedule_irq, p4;
997 sp += 12;
998 rets = [sp++];
999
1000 [--sp] = rets;
1001 sp += -12;
1002 /* up to irq14 so that reti after restore_all can return to irq15(kernel) */
1003 pseudo_long_call _up_to_irq14, p4;
1004 sp += 12;
1005 rets = [sp++];
1006
1007 reti = r6; /* restore reti so that origin process can return to interrupted point */
1008
1009 jump .Lneed_schedule;
905#else 1010#else
906#define _resume_kernel_from_int 2f 1011
1012#define _resume_kernel_from_int .Lreturn_to_kernel
907#endif 1013#endif
908 1014
909ENTRY(_return_from_int) 1015ENTRY(_return_from_int)
@@ -913,7 +1019,7 @@ ENTRY(_return_from_int)
913 p2.h = hi(ILAT); 1019 p2.h = hi(ILAT);
914 r0 = [p2]; 1020 r0 = [p2];
915 cc = bittst (r0, EVT_IVG15_P); 1021 cc = bittst (r0, EVT_IVG15_P);
916 if cc jump 2f; 1022 if cc jump .Lreturn_to_kernel;
917 1023
918 /* if not return to user mode, get out */ 1024 /* if not return to user mode, get out */
919 p2.l = lo(IPEND); 1025 p2.l = lo(IPEND);
@@ -945,7 +1051,7 @@ ENTRY(_return_from_int)
945 STI r0; 1051 STI r0;
946 raise 15; /* raise evt15 to do signal or reschedule */ 1052 raise 15; /* raise evt15 to do signal or reschedule */
947 rti; 1053 rti;
9482: 1054.Lreturn_to_kernel:
949 rts; 1055 rts;
950ENDPROC(_return_from_int) 1056ENDPROC(_return_from_int)
951 1057
@@ -1631,6 +1737,7 @@ ENTRY(_sys_call_table)
1631 .long _sys_fanotify_init 1737 .long _sys_fanotify_init
1632 .long _sys_fanotify_mark 1738 .long _sys_fanotify_mark
1633 .long _sys_prlimit64 1739 .long _sys_prlimit64
1740 .long _sys_cacheflush
1634 1741
1635 .rept NR_syscalls-(.-_sys_call_table)/4 1742 .rept NR_syscalls-(.-_sys_call_table)/4
1636 .long _sys_ni_syscall 1743 .long _sys_ni_syscall
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index cee62cf4acd4..2df37db3b49b 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -116,7 +116,24 @@ __common_int_entry:
116 cc = r0 == 0; 116 cc = r0 == 0;
117 if cc jump .Lcommon_restore_context; 117 if cc jump .Lcommon_restore_context;
118#else /* CONFIG_IPIPE */ 118#else /* CONFIG_IPIPE */
119
120#ifdef CONFIG_PREEMPT
121 r7 = sp;
122 r4.l = lo(ALIGN_PAGE_MASK);
123 r4.h = hi(ALIGN_PAGE_MASK);
124 r7 = r7 & r4;
125 p5 = r7;
126 r7 = [p5 + TI_PREEMPT]; /* get preempt count */
127 r7 += 1; /* increment it */
128 [p5 + TI_PREEMPT] = r7;
129#endif
119 pseudo_long_call _do_irq, p2; 130 pseudo_long_call _do_irq, p2;
131
132#ifdef CONFIG_PREEMPT
133 r7 += -1;
134 [p5 + TI_PREEMPT] = r7; /* restore preempt count */
135#endif
136
120 SP += 12; 137 SP += 12;
121#endif /* CONFIG_IPIPE */ 138#endif /* CONFIG_IPIPE */
122 pseudo_long_call _return_from_int, p2; 139 pseudo_long_call _return_from_int, p2;
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index eaece5f84e42..da7e3c63746b 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -511,7 +511,7 @@ static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
511 int i, irq = 0; 511 int i, irq = 0;
512 u32 status = bfin_read_EMAC_SYSTAT(); 512 u32 status = bfin_read_EMAC_SYSTAT();
513 513
514 for (i = 0; i < (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++) 514 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
515 if (status & (1L << i)) { 515 if (status & (1L << i)) {
516 irq = IRQ_MAC_PHYINT + i; 516 irq = IRQ_MAC_PHYINT + i;
517 break; 517 break;
@@ -529,8 +529,9 @@ static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
529 } else 529 } else
530 printk(KERN_ERR 530 printk(KERN_ERR
531 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR" 531 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
532 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", 532 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
533 __func__, __FILE__, __LINE__); 533 "(EMAC_SYSTAT=0x%X)\n",
534 __func__, __FILE__, __LINE__, status);
534} 535}
535#endif 536#endif
536 537
@@ -1298,7 +1299,7 @@ void do_irq(int vec, struct pt_regs *fp)
1298 } else { 1299 } else {
1299 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; 1300 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1300 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; 1301 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1301#if defined(SIC_ISR0) || defined(SICA_ISR0) 1302#if defined(SIC_ISR0)
1302 unsigned long sic_status[3]; 1303 unsigned long sic_status[3];
1303 1304
1304 if (smp_processor_id()) { 1305 if (smp_processor_id()) {
@@ -1378,7 +1379,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1378 if (likely(vec == EVT_IVTMR_P)) 1379 if (likely(vec == EVT_IVTMR_P))
1379 irq = IRQ_CORETMR; 1380 irq = IRQ_CORETMR;
1380 else { 1381 else {
1381#if defined(SIC_ISR0) || defined(SICA_ISR0) 1382#if defined(SIC_ISR0)
1382 unsigned long sic_status[3]; 1383 unsigned long sic_status[3];
1383 1384
1384 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); 1385 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
diff --git a/arch/blackfin/mach-common/irqpanic.c b/arch/blackfin/mach-common/irqpanic.c
deleted file mode 100644
index c6496249e2bc..000000000000
--- a/arch/blackfin/mach-common/irqpanic.c
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * panic kernel with dump information
3 *
4 * Copyright 2005-2009 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/kernel_stat.h>
11#include <linux/sched.h>
12#include <asm/blackfin.h>
13
14#define L1_ICACHE_START 0xffa10000
15#define L1_ICACHE_END 0xffa13fff
16
17/*
18 * irq_panic - calls panic with string setup
19 */
20__attribute__ ((l1_text))
21asmlinkage void irq_panic(int reason, struct pt_regs *regs)
22{
23 unsigned int cmd, tag, ca, cache_hi, cache_lo, *pa;
24 unsigned short i, j, die;
25 unsigned int bad[10][6];
26
27 /* check entire cache for coherency
28 * Since printk is in cacheable memory,
29 * don't call it until you have checked everything
30 */
31
32 die = 0;
33 i = 0;
34
35 /* check icache */
36
37 for (ca = L1_ICACHE_START; ca <= L1_ICACHE_END && i < 10; ca += 32) {
38
39 /* Grab various address bits for the itest_cmd fields */
40 cmd = (((ca & 0x3000) << 4) | /* ca[13:12] for SBNK[1:0] */
41 ((ca & 0x0c00) << 16) | /* ca[11:10] for WAYSEL[1:0] */
42 ((ca & 0x3f8)) | /* ca[09:03] for SET[4:0] and DW[1:0] */
43 0); /* Access Tag, Read access */
44
45 SSYNC();
46 bfin_write_ITEST_COMMAND(cmd);
47 SSYNC();
48 tag = bfin_read_ITEST_DATA0();
49 SSYNC();
50
51 /* if tag is marked as valid, check it */
52 if (tag & 1) {
53 /* The icache is arranged in 4 groups of 64-bits */
54 for (j = 0; j < 32; j += 8) {
55 cmd = ((((ca + j) & 0x3000) << 4) | /* ca[13:12] for SBNK[1:0] */
56 (((ca + j) & 0x0c00) << 16) | /* ca[11:10] for WAYSEL[1:0] */
57 (((ca + j) & 0x3f8)) | /* ca[09:03] for SET[4:0] and DW[1:0] */
58 4); /* Access Data, Read access */
59
60 SSYNC();
61 bfin_write_ITEST_COMMAND(cmd);
62 SSYNC();
63
64 cache_hi = bfin_read_ITEST_DATA1();
65 cache_lo = bfin_read_ITEST_DATA0();
66
67 pa = ((unsigned int *)((tag & 0xffffcc00) |
68 ((ca + j) & ~(0xffffcc00))));
69
70 /*
71 * Debugging this, enable
72 *
73 * printk("addr: %08x %08x%08x | %08x%08x\n",
74 * ((unsigned int *)((tag & 0xffffcc00) | ((ca+j) & ~(0xffffcc00)))),
75 * cache_hi, cache_lo, *(pa+1), *pa);
76 */
77
78 if (cache_hi != *(pa + 1) || cache_lo != *pa) {
79 /* Since icache is not working, stay out of it, by not printing */
80 die = 1;
81 bad[i][0] = (ca + j);
82 bad[i][1] = cache_hi;
83 bad[i][2] = cache_lo;
84 bad[i][3] = ((tag & 0xffffcc00) |
85 ((ca + j) & ~(0xffffcc00)));
86 bad[i][4] = *(pa + 1);
87 bad[i][5] = *(pa);
88 i++;
89 }
90 }
91 }
92 }
93 if (die) {
94 printk(KERN_EMERG "icache coherency error\n");
95 for (j = 0; j <= i; j++) {
96 printk(KERN_EMERG
97 "cache address : %08x cache value : %08x%08x\n",
98 bad[j][0], bad[j][1], bad[j][2]);
99 printk(KERN_EMERG
100 "physical address: %08x SDRAM value : %08x%08x\n",
101 bad[j][3], bad[j][4], bad[j][5]);
102 }
103 panic("icache coherency error");
104 } else
105 printk(KERN_EMERG "icache checked, and OK\n");
106}